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retroSoC
SystemVerilog 0 0 0
A Customized ASIC framework for Retro Stuff!
Updated 2026-11-02 10:09:07 +00:00
pdfding
Python 0 0 0
Updated 2026-09-23 06:25:16 +00:00
common
SystemVerilog 0 0 0
A SystemVerilog Components Library
Updated 2026-08-27 05:13:10 +00:00
timer
SystemVerilog 0 0 0
An APB4-based Timer Controller
Updated 2026-08-03 16:02:04 +00:00
spi
SystemVerilog 0 0 0
An APB4-based SPI Controller
Updated 2026-03-21 02:13:25 +00:00
i2c
SystemVerilog 0 0 0
An APB4-based I2C Controller
Updated 2026-03-14 07:49:10 +00:00
uart
SystemVerilog 0 0 0
An APB4-based UART Controller
Updated 2026-03-14 07:36:46 +00:00
vga
SystemVerilog 0 0 0
An AXI4-based VGA Controller
Updated 2025-10-08 17:20:11 +00:00
excel2ralf
Python 0 0 0
Excel file to UVM register model ralf file conversion tool
Updated 2025-05-10 07:13:12 +00:00
psram
SystemVerilog 0 0 0
An AXI4-based PSRAM Controller
Updated 2024-12-14 13:21:41 +00:00