From 85f21f01f32b7a2ec87ccf71019f19382fbe408c Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 9 Aug 2025 14:24:23 +0800 Subject: [PATCH 1/2] fix: add spi if to filelist and fix display info in right format --- rtl/mini/filelist/ip.fl | 1 + rtl/mini/tb/retrosoc_tb.sv | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/rtl/mini/filelist/ip.fl b/rtl/mini/filelist/ip.fl index c891e528..8453ee2a 100644 --- a/rtl/mini/filelist/ip.fl +++ b/rtl/mini/filelist/ip.fl @@ -23,6 +23,7 @@ ../../clusterip/i2c/rtl/i2c_master_byte_ctrl.sv ../../clusterip/i2c/rtl/apb4_i2c.sv ../../clusterip/spi/rtl/apb4_spi.sv +../../clusterip/spi/rtl/spi_if.sv ../../clusterip/spi/rtl/spi_clkgen.sv ../../clusterip/spi/rtl/spi_apb_if.sv ../../clusterip/spi/rtl/spi_ctrl.sv diff --git a/rtl/mini/tb/retrosoc_tb.sv b/rtl/mini/tb/retrosoc_tb.sv index 3a2b19d2..cae6e07e 100644 --- a/rtl/mini/tb/retrosoc_tb.sv +++ b/rtl/mini/tb/retrosoc_tb.sv @@ -249,11 +249,11 @@ module retrosoc_tb; else r_pll_cfg = 3'd0; // 24M if (r_pll_en == 1'b0) begin - $display("pll_en: %d pll_cfg: %d clk_freq: %dMHz", r_pll_en, r_pll_cfg, EXT_CPU_FREQ); + $display("pll_en: %0d pll_cfg: %0d clk_freq: %0dMHz", r_pll_en, r_pll_cfg, EXT_CPU_FREQ); end else if (r_pll_cfg == 3'd0 || r_pll_cfg == 3'd1) begin - $display("pll_en: %d pll_cfg: %d clk_freq: %dMHz", r_pll_en, r_pll_cfg, XTAL_CPU_FREQ); + $display("pll_en: %0d pll_cfg: %0d clk_freq: %0dMHz", r_pll_en, r_pll_cfg, XTAL_CPU_FREQ); end else begin - $display("pll_en: %d pll_cfg: %d clk_freq: %dMHz", r_pll_en, r_pll_cfg, (r_pll_cfg + 1) * 24); + $display("pll_en: %0d pll_cfg: %0d clk_freq: %0dMHz", r_pll_en, r_pll_cfg, (r_pll_cfg + 1) * 24); end end endmodule From 61849398c1caf228fea06e97d7a7e7a6d8602f31 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 9 Aug 2025 14:25:27 +0800 Subject: [PATCH 2/2] feat: add sram ctrl macro in behv env --- rtl/tech/tc_sram.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/rtl/tech/tc_sram.sv b/rtl/tech/tc_sram.sv index 76e4e161..e89a8982 100644 --- a/rtl/tech/tc_sram.sv +++ b/rtl/tech/tc_sram.sv @@ -9,6 +9,7 @@ module tc_sram_1024x32 ( ); `ifdef PDK_BEHAV +`ifdef HAVE_SRAM logic [31:0] r_data; logic [31:0] mem [0:1023]; @@ -26,6 +27,7 @@ module tc_sram_1024x32 ( end end end +`endif `elsif PDK_IHP130 `ifdef HAVE_SRAM logic [63:0] s_rd_data_mem;