From 23c80da792d6be9e8a8a801909b0f031aaac56c4 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Mon, 24 Aug 2026 07:39:09 +0800 Subject: [PATCH] fix: fix the wrong timing para for commercial flow --- physical/commercial/tcl/syn/main.tcl | 8 ++++---- tests/test_commercial_flow.py | 10 ++++++++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/physical/commercial/tcl/syn/main.tcl b/physical/commercial/tcl/syn/main.tcl index a7e3ffcb..662e0ce6 100644 --- a/physical/commercial/tcl/syn/main.tcl +++ b/physical/commercial/tcl/syn/main.tcl @@ -66,12 +66,12 @@ proc run_synthesis {} { flow::apply_constraints redirect [file join $report_dir check_design.pre.rpt] { check_design } redirect [file join $report_dir check_timing.pre.rpt] { - check_timing -verbose + check_timing } if {![check_design]} { flow::fail "pre-compile Design Compiler check_design failed" } - if {![check_timing -include {no_clock unconstrained_endpoints}]} { + if {![check_timing -include {unconstrained_endpoints}]} { flow::fail "pre-compile timing constraints are incomplete" } set_fix_multiple_port_nets -all -buffer_constants @@ -89,7 +89,7 @@ proc run_synthesis {} { check_design -summary } redirect [file join $report_dir check_timing.rpt] { - check_timing -verbose + check_timing } redirect [file join $report_dir timing.setup.rpt] { report_timing -delay_type max -max_paths 1000 -input_pins -nets @@ -119,7 +119,7 @@ proc run_synthesis {} { if {![check_design]} { flow::fail "Design Compiler check_design failed" } - if {![check_timing -include {no_clock unconstrained_endpoints}]} { + if {![check_timing -include {unconstrained_endpoints}]} { flow::fail "Design Compiler timing constraints are incomplete" } if {[flow::report_has_failure [file join $report_dir check_design.rpt] \ diff --git a/tests/test_commercial_flow.py b/tests/test_commercial_flow.py index a968b098..c402209b 100644 --- a/tests/test_commercial_flow.py +++ b/tests/test_commercial_flow.py @@ -287,6 +287,16 @@ def test_dc_analyze_receives_one_source_list_argument() -> None: assert "concat $analyze_command [dict get $rtl sources]" not in synthesis +def test_dc_check_timing_uses_supported_options() -> None: + synthesis = (FLOW / "tcl/syn/main.tcl").read_text(encoding="utf-8") + assert synthesis.count("check_timing\n") == 2 + assert "check_timing -verbose" not in synthesis + assert synthesis.count( + "check_timing -include {unconstrained_endpoints}" + ) == 2 + assert "no_clock" not in synthesis + + def test_commercial_timing_contract_covers_canonical_domains(tmp_path: Path) -> None: output = tmp_path / "commercial_timing_contract.tcl" subprocess.run(