diff --git a/crt/src/service/booter.c b/crt/src/service/booter.c
index 03feb9eb..23d60797 100644
--- a/crt/src/service/booter.c
+++ b/crt/src/service/booter.c
@@ -12,6 +12,28 @@
 #include <retrosoc/service/booter.h>
 #include <user_design_info.h>
 
+static void rs_print_hazard3_spec(void) {
+    printf("\nManagement-Core Specification:\n");
+    printf("  Identity\n");
+    printf("    Core: Hazard3(single hart), 3-stage pipeline\n");
+    printf("    Role: trusted management, boot, lifecycle control\n");
+    printf("    Source: https://github.com/Wren6991/Hazard3\n");
+    printf("  Hardware ISA\n");
+    printf("    Base: RV32IMAC_Zicsr\n");
+    printf("    Bit manipulation: Zba_Zbb_Zbc_Zbkb_Zbkx_Zbs\n");
+    printf("    Other: Zifencei_Zilsd_Xh3BextM_Xh3IRQ\n");
+    printf("    Not present: U-mode PMP Zcb_Zclsd_Zcmp_Xh3PMPM_Xh3Power\n");
+    printf("  Privilege and interrupts\n");
+    printf("    Mode: M-mode only; mandatory, trap, and counter CSRs enabled\n");
+    printf("    IRQ: 30 external + software + timer; Xh3IRQ, 4 priority levels\n");
+    printf("  Memory bus\n");
+    printf("    AHB5 manager -> AHB-Lite/AXI4 fabric\n");
+    printf("    Single-beat access; no burst or exclusive transactions\n");
+    printf("  Debug\n");
+    printf("    RISC-V JTAG DTM/DM, IDCODE 0x%08x\n", RS_SOC_MGMT_JTAG_IDCODE);
+    printf("    One hart: halt/resume, 2 breakpoints; no system-bus access\n");
+}
+
 void rs_app_info(void) {
     uint8_t selected_core;
     uint8_t selected_ip;
@@ -78,10 +100,7 @@ void rs_app_info(void) {
     printf("  | SRAM / Ext |    | Peripherals|    | User IP    |\n");
     printf("  +------------+    +------------+    +------------+\n");
 
-    printf("\nManagement Processor:\n");
-    printf("       %-15s %-12s %-12s %s\n", "[name]", "[isa]", "[maintainer]", "[repo]");
-    printf("=>[0]: %-15s %-12s %-12s %s\n", "Hazard3", "rv32imac", "Wren6991",
-           "https://github.com/Wren6991/Hazard3");
+    rs_print_hazard3_spec();
 
     printf("\nUser Processors:\n");
     uint32_t core_size = sizeof(user_core_info) / sizeof(user_core_info[0]);
diff --git a/rtl/mini/mk/software.mk b/rtl/mini/mk/software.mk
index 66fd140c..6ded66f9 100644
--- a/rtl/mini/mk/software.mk
+++ b/rtl/mini/mk/software.mk
@@ -44,6 +44,7 @@ DEF_VAL += -DAPP_$(APP)
 DEF_VAL += -DCOMPILER_NAME='"$(CC)"'
 DEF_VAL += -DCOMPILER_CFLAGS='"$(GCC_FLAGS) $(SW_WARN_FLAGS)"'
 DEF_VAL += -DCOMPILER_ISA='"$(ISA_FLAGS)"'
+DEF_VAL += -DRS_SOC_MGMT_JTAG_IDCODE=0x$(JTAG_IDCODE)U
 DEF_VAL += -DRS_CLINT_TIMEBASE_HZ=$(CLINT_TIMEBASE_HZ)U
 DEF_VAL += -DRS_RTC_CLOCK_HZ=$(AUD_CLK_HZ)U
 ifeq ($(HAVE_CSR),YES)
diff --git a/tests/test_mgmt_core_spec.py b/tests/test_mgmt_core_spec.py
new file mode 100644
index 00000000..9b2b87b7
--- /dev/null
+++ b/tests/test_mgmt_core_spec.py
@@ -0,0 +1,65 @@
+"""Keep the boot display aligned with the fixed Hazard3 management-core integration."""
+
+from pathlib import Path
+
+
+ROOT = Path(__file__).resolve().parents[1]
+BOOTER = ROOT / "crt/src/service/booter.c"
+SOFTWARE_MAKE = ROOT / "rtl/mini/mk/software.mk"
+MGMT_CORE = ROOT / "rtl/mini/top/mgmt_core_wrapper.sv"
+MGMT_DEBUG = ROOT / "rtl/mini/top/mgmt_debug_wrapper.sv"
+AHBL_TO_AXI4 = ROOT / "rtl/mini/top/ahbl2axi4.sv"
+
+
+def test_booter_prints_the_fixed_hazard3_specification() -> None:
+    booter = BOOTER.read_text(encoding="utf-8")
+    software_make = SOFTWARE_MAKE.read_text(encoding="utf-8")
+    management_core = MGMT_CORE.read_text(encoding="utf-8")
+    management_debug = MGMT_DEBUG.read_text(encoding="utf-8")
+    ahbl_to_axi4 = AHBL_TO_AXI4.read_text(encoding="utf-8")
+
+    assert "DEF_VAL += -DRS_SOC_MGMT_JTAG_IDCODE=0x$(JTAG_IDCODE)U" in software_make
+    assert "Management-Core Specification:" in booter
+    assert "Management Processor:" not in booter
+    assert "User Processors:" in booter
+    assert "Core: Hazard3(single hart), 3-stage pipeline" in booter
+    assert "Base: RV32IMAC_Zicsr" in booter
+    assert "Bit manipulation: Zba_Zbb_Zbc_Zbkb_Zbkx_Zbs" in booter
+    assert "Other: Zifencei_Zilsd_Xh3BextM_Xh3IRQ" in booter
+    assert "Not present: U-mode PMP Zcb_Zclsd_Zcmp_Xh3PMPM_Xh3Power" in booter
+    assert "IRQ: 30 external + software + timer; Xh3IRQ, 4 priority levels" in booter
+    assert "one shared instruction/data AHB5 manager port" in booter
+    assert "single-beat AXI4 normal access" in booter
+    assert "no burst, lock, or global-exclusive forwarding; no system A atomics" in booter
+    assert "RS_SOC_MGMT_JTAG_IDCODE" in booter
+    assert "halted-hart memory commands; system bus access disabled" in booter
+    assert "2 exact execute-address hardware breakpoints; no watchpoints" in booter
+
+    for parameter in (
+        ".EXTENSION_A        (1)",
+        ".EXTENSION_C        (1)",
+        ".EXTENSION_M        (1)",
+        ".EXTENSION_ZBA      (1)",
+        ".EXTENSION_ZBB      (1)",
+        ".EXTENSION_ZBC      (1)",
+        ".EXTENSION_ZBKB     (1)",
+        ".EXTENSION_ZBKX     (1)",
+        ".EXTENSION_ZBS      (1)",
+        ".EXTENSION_ZIFENCEI (1)",
+        ".EXTENSION_ZILSD    (1)",
+        ".EXTENSION_XH3BEXTM (1)",
+        ".EXTENSION_XH3IRQ   (1)",
+        ".U_MODE             (0)",
+        ".PMP_REGIONS        (0)",
+        ".BREAKPOINT_TRIGGERS(2)",
+        ".NUM_IRQS           (30)",
+        ".IRQ_PRIORITY_BITS  (2)",
+    ):
+        assert parameter in management_core
+
+    assert ".HAVE_SBA(0)" in management_debug
+    assert "ahbl.htrans == AHBL_TRANS_NSEQ" in ahbl_to_axi4
+    assert "axi4.awlen    = 8'd0;" in ahbl_to_axi4
+    assert "axi4.arlen    = 8'd0;" in ahbl_to_axi4
+    assert "axi4.awlock   = `AXI4_LOCK_NORM;" in ahbl_to_axi4
+    assert "axi4.arlock   = `AXI4_LOCK_NORM;" in ahbl_to_axi4