From 3b85b07cb542cfd3d79356d52541740a1febf4f4 Mon Sep 17 00:00:00 2001
From: maksyuki <maksyuki@126.com>
Date: Fri, 31 Jan 2025 21:19:23 +0800
Subject: [PATCH] chore: modify rtl files macros

---
 rtl/Makefile | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/rtl/Makefile b/rtl/Makefile
index aecb9c5b..38831be8 100644
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -4,7 +4,7 @@ CFLAGS=
 
 WAVE := NONE
 
-IP := ./ip/spram_model.v \
+RTL_IP := ./ip/spram_model.v \
       ./ip/spimemio.v \
       ./ip/simpleuart.v \
 	  ./ip/i2c_master_bit_ctrl.v \
@@ -13,9 +13,19 @@ IP := ./ip/spram_model.v \
       ./ip/simple_spi_master.v \
       ./ip/counter_timer.v \
 	  ./ip/spi_slave.v \
-      ./ip/ravenna_spi.v
+      ./ip/ravenna_spi.v \
+	  ./ip/spiflash.v
 
-INC := -I./ip
+RTL_TECH := ../tech/tc_io.v \
+            ../tech/tc_clk.v \
+            ../tech/tc_sram.v
+
+RTL_PDK := ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v \
+           ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v \
+           ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v \
+           ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v
+
+RTL_INC := -I./ip
 # +behv_wave
 retrosim: retrosoc_tb.vvp retrosoc_fw.hex retrosoc_fw.bin retrosoc_fw.txt
 	vvp -N $< +firmware=retrosoc_fw.hex +behv_$(WAVE) -fst
@@ -25,13 +35,13 @@ retrosynsim: retrosoc_syn_tb.vvp retrosoc_fw.hex
 	vvp -N $< +firmware=retrosoc_fw.hex +syn_$(WAVE) -fst
 
 
-retrosoc_tb.vvp: retrosoc_tb.v retrosoc_asic.v  retrosoc.v picorv32.v $(IP) ./ip/spiflash.v ../tech/tc_io.v ../tech/tc_clk.v ../tech/tc_sram.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v
-	iverilog $(INC) -s retrosoc_tb -o $@ $^
+retrosoc_tb.vvp: retrosoc_tb.v retrosoc_asic.v  retrosoc.v picorv32.v $(RTL_IP) $(RTL_TECH) $(RTL_PDK)
+	iverilog $(RTL_INC) -s retrosoc_tb -o $@ $^
 
-retrosoc_syn_tb.vvp: retrosoc_tb.v ../syn/yosys/out/retrosoc_yosys.v spiflash.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v
+retrosoc_syn_tb.vvp: retrosoc_tb.v ../syn/yosys/out/retrosoc_asic_yosys.v ./ip/spiflash.v $(RTL_PDK)
 	iverilog -s retrosoc_tb -o $@ $^
 
-../syn/yosys/out/retrosoc_yosys.v:
+../syn/yosys/out/retrosoc_asic_yosys.v:
 	$(MAKE) -C ../syn/yosys -f yosys.mk
 
 retrosoc_syn.v:
@@ -41,7 +51,7 @@ retrosoc_sections.lds: sections.lds
 	$(CROSS)cpp -P -DRETROSOC -o $@ $^
 
 retrosoc_fw.elf: retrosoc_sections.lds start.s firmware.c
-	$(CROSS)gcc $(CFLAGS) -DRETROSOC -mabi=ilp32 -march=rv32i -Wl,-Bstatic,-T,retrosoc_sections.lds,--strip-debug -ffreestanding -nostdlib -o retrosoc_fw.elf start.s firmware.c
+	$(CROSS)gcc $(CFLAGS) -DRETROSOC -mabi=ilp32 -march=rv32im -Wl,-Bstatic,-T,retrosoc_sections.lds,--strip-debug -ffreestanding -nostdlib -o retrosoc_fw.elf start.s firmware.c
 
 retrosoc_fw.hex: retrosoc_fw.elf
 	$(CROSS)objcopy -O verilog retrosoc_fw.elf retrosoc_fw.hex