From 3d2f685a9a26888bb3205cdc4a3c431388b83725 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 15:55:19 +0800 Subject: [PATCH] docs: record the GF180 SRAM macro path and its evidence Extend the chapter 3 memory-swap documentation to GF180: hp-platform.md adds the tiling table (8-bit macro stacking with registered read muxes), notes the repo-owned functional models versus the vendor collateral in the locked PDK, and documents the SKY130 byte-mask blocker as the reason that PDK stays behavioral; hp-rv64-validation.md records the directed-TB, MEM_INTF, boot-testbench, and SoC macro-sim evidence; the two READMEs generalize the override wording to IHP130/ICS55/GF180. Physical qualification (Liberty registration, STA, LEC) stays explicitly deferred. --- docs/hp-rv64-validation.md | 22 ++++++++++++++++++---- docs/ip/hp-platform.md | 26 ++++++++++++++++++++++++++ rtl/README.md | 5 +++-- scripts/README.md | 6 ++++-- 4 files changed, 51 insertions(+), 8 deletions(-) diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index 7208424a..30d11b90 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -134,6 +134,18 @@ qualification. Current evidence requires, at minimum: to Icarus) passes on the ICS55 path as well, and the `ics55.mk` CI profile smoke simulation (`APP=ci_smoke`, Verilator) passes with the macro path compiled into the SoC. +- The wrappers also have a GF180 macro path: under `PDK_GF180`+ + `HAVE_SRAM_MACRO` without `PDK_BEHAV` each wrapper is tiled from the GF180 + 8-bit bit-write macros `gf180mcu_fd_ip_sram__sram{64,128,256,512}x8m8wm1` + (identical active-low polarity; depth/width tiling with registered read + muxes where stacked). The vendor verilog views are timing-only, so the + simulation models are repo-owned in `rtl/tech/gf180_sram_sim_cells.sv`. + The directed eight-wrapper equivalence bench and the MEM_INTF suite both + pass on the GF180 path, and the focused boot testbench variant + `test_c906_boots_smoke_payload_with_gf180_macros` passes with the SRAM + tiles and the `icgtp_1` ICG active together. SKY130 stays behavioral: the + locked OpenRAM SRAM has only a byte-granular write mask while the wrappers + need per-bit write enable. - The chapter 3 ICG swap is validated in simulation on all four PDKs: the `gated_clk_cell.v`/`tdt_gated_clk_cell.v`/`BUFGCE.v` overrides select `sg13g2_slgcp_1` (IHP130), `ICGX1H7R` (ICS55, scan enable ORed into `E`), @@ -167,10 +179,12 @@ hp-smoke-sim` builds the whole SoC (C906 `aq_spsram_*` wrappers and `HP_GA2D_CACHE_CLEAN` markers; with the ICG overrides the same run also exercises the real `sg13g2_slgcp_1` clock gates. The same SoC smoke passes on the ICS55 macro+ICG path (`PDK=ICS55 PDK_BEHAV=NO`, 3.64M cycles, -`SIM_TEST_PASS code=0` with the full GA2D cache-lifecycle marker sequence), -and the `sky130.mk` and `gf180.mk` CI profile smokes (`APP=ci_smoke`, -Verilator) pass with the `sky130_fd_sc_hd__sdlclkp_1` / -`gf180mcu_fd_sc_mcu7t5v0__icgtp_1` ICG compiled in. The default 300 s +`SIM_TEST_PASS code=0` with the full GA2D cache-lifecycle marker sequence) +and on the GF180 macro+ICG path (`PDK=GF180 PDK_BEHAV=NO`, identical cycle +count), and the `sky130.mk` and `gf180.mk` CI profile smokes (`APP=ci_smoke`, +Verilator) pass with the SRAM tiles and the `sky130_fd_sc_hd__sdlclkp_1` / +`gf180mcu_fd_sc_mcu7t5v0__icgtp_1` ICG compiled in (the GF180 C906 SRAMs run +as macro tiles there too). The default 300 s `HP_SMOKE_SIM_TIME` is only enough when the run is uncontended, and the bare `ics55.mk` profile-default `sim` (no fast-flash) exceeds its 180 s default budget in this environment, so these were run with CI-sized time budgets. diff --git a/docs/ip/hp-platform.md b/docs/ip/hp-platform.md index f59f2755..4cd6e284 100644 --- a/docs/ip/hp-platform.md +++ b/docs/ip/hp-platform.md @@ -79,6 +79,32 @@ are active-low at identical widths), so the replacement is a direct connection with no inversion, padding, or stacking; `MARE`/`MAR` are tied off as in `tc_sram.sv`. +With `PDK_GF180` + `HAVE_SRAM_MACRO` and without `PDK_BEHAV`, each wrapper is +tiled from the GF180 8-bit bit-write macros +(`gf180mcu_fd_ip_sram__sram{64,128,256,512}x8m8wm1`; active-low +`CEN`/`GWEN`/per-bit `WEN` match the wrapper polarity). The vendor verilog +views are timing-only, so the simulation models are repo-owned in +`rtl/tech/gf180_sram_sim_cells.sv` (the 512x8 SoC model plus the +64/128/256x8 tiles): + +| Wrapper | Tile | Tiling | +| --- | --- | --- | +| `aq_spsram_1024x16` (BHT) | 512x8 | depth 2 (`A[9]`) x width 2 | +| `aq_spsram_2048x32` (ICache data) | 512x8 | depth 4 (`A[10:9]`) x width 4 | +| `aq_spsram_256x59` (ICache tag) | 256x8 | width 8; top tile's upper 5 bits tied inactive | +| `aq_spsram_1024x64` (DCache data) | 512x8 | depth 2 (`A[9]`) x width 8 | +| `aq_spsram_128x8` (DCache dirty) | 128x8 | exact, single tile | +| `aq_spsram_64x58` (DCache tag) | 64x8 | width 8; top tile's upper 6 bits tied inactive | +| `aq_spsram_64x88` (JTLB data) | 64x8 | width 11, exact | +| `aq_spsram_64x98` (JTLB tag) | 64x8 | width 13; top tile's upper 6 bits tied inactive | + +Depth stacks register the bank select on read transactions and mux the tile +outputs, like the IHP130 stacks. SKY130 stays on the behavioral path: the +locked OpenRAM SRAM (`sky130_sram_4kbyte_1rw_32x1024_8`) offers only a +byte-granular write mask (`wmask0[3:0]` per 32-bit word) while the C906 +wrappers require per-bit write enable, so no SKY130 SRAM macro can serve +them. + Every other configuration — including the committed `PDK_BEHAV=YES` CI profiles — compiles the upstream behavioral `aq_f_spsram_*` instance byte-identically. diff --git a/rtl/README.md b/rtl/README.md index 8ee06b5a..0ba89006 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -22,8 +22,9 @@ sources are an external lint boundary. The reviewed hart-ID, sysmap address-attribute, SRAM wrapper, and clock-gate (ICG) overrides live in `rtl/mini/ip_overrides/` (the `aq_spsram_*.v` overrides implement the integration manual chapter 3 -memory swap and select IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 -`ics55_ecos_sram_*` macros only under `PDK_IHP130`/`PDK_ICS55` + +memory swap and select IHP130 `RM_IHPSG13_1P_*`, exact-geometry ICS55 +`ics55_ecos_sram_*`, or tiled GF180 `gf180mcu_fd_ip_sram__sram*x8m8wm1` +macros only under `PDK_IHP130`/`PDK_ICS55`/`PDK_GF180` + `HAVE_SRAM_MACRO` without `PDK_BEHAV`; the `gated_clk_cell.v`, `tdt_gated_clk_cell.v`, and `BUFGCE.v` overrides implement the chapter 3 ICG swap and select the process clock-gating cell under a `PDK_*` define without diff --git a/scripts/README.md b/scripts/README.md index 08b23619..893b10bf 100644 --- a/scripts/README.md +++ b/scripts/README.md @@ -132,8 +132,10 @@ upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1 `aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, the eight `aq_spsram_*.v` SRAM wrappers whose PDK-selectable macro path — stacked -IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 `ics55_ecos_sram_*` — is -gated on `PDK_IHP130`/`PDK_ICS55`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, and +IHP130 `RM_IHPSG13_1P_*`, exact-geometry ICS55 `ics55_ecos_sram_*`, or tiled +GF180 `gf180mcu_fd_ip_sram__sram*x8m8wm1` — is +gated on `PDK_IHP130`/`PDK_ICS55`/`PDK_GF180`+`HAVE_SRAM_MACRO` without +`PDK_BEHAV`, and the `gated_clk_cell.v`/`tdt_gated_clk_cell.v`/`BUFGCE.v` clock-gate overrides that select the process ICG cell under a `PDK_*` define without `PDK_BEHAV`), each pinned to