From 41a21b6881b5abf996744bf2a75fe3152705bed1 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 1 Feb 2025 00:10:07 +0800 Subject: [PATCH] fix: fix a error tim value reg wr bit width bug --- rtl/ip/apb_wrapper.v | 2 ++ rtl/ip/counter_timer.v | 8 ++++---- rtl/ip/i2c_slave.v | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) create mode 100644 rtl/ip/apb_wrapper.v diff --git a/rtl/ip/apb_wrapper.v b/rtl/ip/apb_wrapper.v new file mode 100644 index 00000000..6547a1e4 --- /dev/null +++ b/rtl/ip/apb_wrapper.v @@ -0,0 +1,2 @@ +module apb_wrapper (); +endmodule diff --git a/rtl/ip/counter_timer.v b/rtl/ip/counter_timer.v index 8d7b7f51..f3501fa6 100644 --- a/rtl/ip/counter_timer.v +++ b/rtl/ip/counter_timer.v @@ -48,10 +48,10 @@ module counter_timer ( if (resetn == 1'b0) begin value_reset <= 32'd0; end else begin - if (reg_val_we[3]) value_reset <= reg_val_di[31:24]; - if (reg_val_we[2]) value_reset <= reg_val_di[23:16]; - if (reg_val_we[1]) value_reset <= reg_val_di[15:8]; - if (reg_val_we[0]) value_reset <= reg_val_di[7:0]; + if (reg_val_we[3]) value_reset[31:24] <= reg_val_di[31:24]; + if (reg_val_we[2]) value_reset[23:16] <= reg_val_di[23:16]; + if (reg_val_we[1]) value_reset[15:8] <= reg_val_di[15:8]; + if (reg_val_we[0]) value_reset[7:0] <= reg_val_di[7:0]; end end diff --git a/rtl/ip/i2c_slave.v b/rtl/ip/i2c_slave.v index ae877206..65a1ce87 100644 --- a/rtl/ip/i2c_slave.v +++ b/rtl/ip/i2c_slave.v @@ -55,7 +55,7 @@ module i2c_slave ( if (cntr == 8) state = SDATA; else if ((state == SDATA) && (cntr == 17)) begin state <= SIDLE; - $display("i2c Slave has received 0x%X - Address: 0x%X", data, addr); + $display("[HARDWARE] i2c Slave has received 0x%X - Address: 0x%X", data, addr); end initial begin