diff --git a/.gitignore b/.gitignore
index c6a015fb..b86695d1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -41,4 +41,5 @@ kianV
 !get_pdk.py
 def.fl
 yosys.fl
-dc.fl
\ No newline at end of file
+dc.fl
+minirv.sv
\ No newline at end of file
diff --git a/Makefile b/Makefile
index 660c0d18..7b0cf601 100644
--- a/Makefile
+++ b/Makefile
@@ -35,8 +35,8 @@ $(info MAKE APP:      $(MAKE))
 $(info MAKE CMDGOAL:  $(MAKECMDGOALS))
 $(info MAKE FILELIST: $(MAKEFILE_LIST))
 $(info ============== HW CONFIG INFO =============================)
-$(info SOC       [MINI, STD]:                  $(SOC))
-$(info CORE      [PICORV32, KIANV]:            $(CORE))
+$(info SOC       [TINY, MINI]:                 $(SOC))
+$(info CORE      [MINIRV PICORV32, KIANV]:     $(CORE))
 $(info SIMU      [VCS, VERILATOR]:             $(SIMU))
 $(info SYNTH     [YOSYS, DC]:                  $(SYNTH))
 $(info TIMI      [OPENSTA, ISTA]:              $(TIMI))
@@ -82,6 +82,9 @@ ifeq ($(SOC), TINY)
 endif
 
 ifeq ($(SYNTH), YOSYS)
+    DEF_LIST += +define+SYNTHESIS #HACK: for some core
+    $(info SYNTH DEF_LIST: $(DEF_LIST))
+    $(file > $(RTL_PATH)/filelist/def.fl, $(DEF_LIST))
     demo := $(shell python3 $(RTL_PATH)/filelist/comb.py $(RTL_FLIST))
     include syn/yosys/yosys.mk
 else ifeq ($(SYNTH), DC)
diff --git a/syn/yosys/synth_config.mk b/syn/yosys/synth_config.mk
index e7941e51..4a8d9727 100644
--- a/syn/yosys/synth_config.mk
+++ b/syn/yosys/synth_config.mk
@@ -17,23 +17,12 @@ export YOSYS_FLATTEN_HIER := 1
 # a list of yosys selection strings, all selected instances will be 
 # kept as a seperate hierarchical element, all others will be flattened
 # https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/select.html
-export YOSYS_KEEP_HIER_INST :=  "t:croc_soc$$*" \
-								"t:croc_domain$$*" \
-								"t:core_wrap$$*" \
-								"t:cve2_register_file_ff$$*" \
-								"t:cve2_cs_registers$$*" \
-								"t:dmi_jtag$$*" \
-								"t:dm_top$$*" \
-								"t:gpio$$*" \
-								"t:timer_unit$$*" \
-								"t:reg_uart_wrap$$*" \
-								"t:tc_clk*$$*" \
-								"t:tc_sram$$*" \
-								"t:soc_ctrl_reg_top$$*" \
-								"t:user_domain$$*" \
+export YOSYS_KEEP_HIER_INST :=  "t:tc_clk*$$*" \
+								"t:tc_sram*$$*" \
 								"t:cdc_*$$*" \
-								"t:sync$$*" \
+								"t:core_*$$*" \
+								"t:sync*$$*" \
 
 # the paths (full names) of all instances matching these strings is reported
 # for floorplaning or writing constraints
-export YOSYS_REPORT_INSTS :=	"t:*RM_IHPSG13_*"
+export YOSYS_REPORT_INSTS :=	"t:*core_wrapper*"
diff --git a/syn/yosys/yosys.mk b/syn/yosys/yosys.mk
index 64d0fd24..689b4a83 100644
--- a/syn/yosys/yosys.mk
+++ b/syn/yosys/yosys.mk
@@ -29,7 +29,7 @@ include $(YOSYS_DIR)/synth_config.mk
 
 TOP_DESIGN    ?= retrosoc_asic
 RTL_NAME      ?= retrosoc_asic
-SV_FLIST      := $(YOSYS_DIR)/../../rtl/mini/filelist/yosys.fl
+SV_FLIST      := $(YOSYS_DIR)/../../rtl/$(shell echo $(SOC) | tr A-Z a-z )/filelist/yosys.fl
 
 $(info SV_FLIST: $(SV_FLIST))