From 8d735aafbd1010fe0824522476bbe2a4254262a6 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 10 Oct 2026 15:15:21 +0800 Subject: [PATCH 01/31] feat: refactor tests and update configurations for OpenC906 migration - Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator. --- ATTRIBUTIONS.md | 10 + Makefile | 49 +- README.md | 4 +- app/benchmark/npu/npu_p6_runner.c | 6 +- app/ports/hp-apu/main.c | 30 +- app/ports/linux/README.md | 2 +- app/ports/linux/linux/retrosoc_hp.dts | 35 +- app/ports/linux/opensbi/retrosoc_hp/Kconfig | 1 - .../linux/opensbi/retrosoc_hp/platform.c | 61 +- app/ports/linux/smoke/npu_acceptance.c | 3 +- app/ports/linux/smoke/start.S | 24 +- app/ports/rtthread/README.md | 5 +- app/ports/rtthread/board.c | 39 +- app/ports/rtthread/rtconfig.py | 2 +- .../ihp130-hazard3-coremark-standard.mk | 1 - configs/benchmark/ihp130-hazard3-coremark.mk | 1 - configs/benchmark/ihp130-hazard3.mk | 1 - configs/ci/gf180.mk | 1 - configs/ci/ics55.mk | 1 - configs/ci/ihp130-apu.mk | 1 - configs/ci/ihp130-debug.mk | 1 - configs/ci/ihp130-hp.mk | 1 - configs/ci/ihp130-rtthread.mk | 1 - configs/ci/ihp130-shell.mk | 1 - configs/ci/ihp130-xpi-flash-loader.mk | 1 - configs/ci/ihp130.mk | 1 - configs/ci/sky130.mk | 1 - configs/cluster/ics55.mk | 1 - crt/src/service/booter.c | 32 +- dependencies/README.md | 20 +- dependencies/dependencies.lock.json | 10 +- docs/README.md | 5 +- docs/axi4-interconnect.md | 22 +- docs/commercial-soc-alignment.md | 5 +- docs/hazard3-debug.md | 4 +- docs/hp-rv64-validation.md | 71 +- docs/ip/apu.md | 4 +- docs/ip/clint.md | 17 +- docs/ip/crypto-verification.md | 2 +- docs/ip/crypto.md | 5 +- docs/ip/ga2d.md | 3 +- docs/ip/hp-platform.md | 141 +- docs/ip/npu-verification.md | 9 +- docs/ip/npu.md | 4 +- docs/ip/resource-controller.md | 11 +- docs/lp-hp-architecture.md | 37 +- docs/mini-high-performance-traceability.md | 12 +- docs/mini-soc-block-diagram.dot | 13 +- docs/mini-soc-block-diagram.svg | 355 +- docs/soc-family-positioning.md | 51 +- publications/README.md | 9 +- publications/build_datasheet.py | 4 +- publications/datasheets/diagram-circuits.json | 482 +- publications/datasheets/diagram-packages.typ | 8 +- publications/datasheets/features.json | 12 +- publications/datasheets/figures.typ | 2 +- publications/datasheets/ip-catalog.json | 5 +- publications/datasheets/ip-content.json | 54 +- publications/datasheets/ips/hp-aclint.typ | 34 +- publications/datasheets/ips/hp-mailbox.typ | 2 +- publications/datasheets/ips/hp-plic.typ | 31 +- publications/datasheets/ips/resource.typ | 2 +- publications/datasheets/ips/uart1.typ | 2 +- publications/datasheets/overview-groups.json | 4 +- .../datasheets/register-annotations.json | 70 - .../datasheets/register-profiles.json | 245 - .../datasheets/sections/architecture.typ | 36 +- .../datasheets/sections/clock-programming.typ | 2 +- .../datasheets/sections/linux-runtime.typ | 20 +- .../datasheets/sections/memory-use.typ | 17 +- publications/datasheets/sections/overview.typ | 4 +- .../datasheets/sections/processor-details.typ | 71 +- .../datasheets/sections/routing-reference.typ | 7 +- .../datasheets/sections/software-runtime.typ | 4 +- publications/datasheets/sections/software.typ | 4 +- .../datasheets/sections/system-management.typ | 2 +- .../datasheets/sections/usage-appendices.typ | 2 +- publications/datasheets/soc-architecture.json | 79 +- publications/datasheets/style.md | 3 +- publications/datasheets/system-reference.json | 92 +- publications/datasheets/waveforms.json | 144 - publications/diagram_reference.py | 8 +- publications/implementation_reference.py | 76 +- publications/register_reference.py | 1 - publications/software_reference.py | 7 +- quality/warnings/ihp130/rtl-lint.json | 4888 ++++++++++++++++- rtl/README.md | 15 +- rtl/mini/Makefile | 2 +- rtl/mini/address_map/memory_map.json | 21 +- rtl/mini/filelist/top.fl | 2 + rtl/mini/integration/generate_soc_topology.py | 4 +- rtl/mini/integration/soc_topology.json | 30 +- rtl/mini/ip_overrides/aq_sysio_kid.v | 203 + rtl/mini/ip_overrides/sysmap.h | 72 + rtl/mini/top/apb4_periph.sv | 34 +- rtl/mini/top/axi4_data_crossbar.sv | 4 +- rtl/mini/top/axi4_downsizer_128to64.sv | 327 ++ rtl/mini/top/axi4_mmio_demux.sv | 203 + rtl/mini/top/hp_core_wrapper.sv | 378 +- rtl/mini/top/hp_subsystem.sv | 38 +- rtl/mini/top/retrosoc.sv | 222 +- rtl/mini/top/soc_data_plane.sv | 37 +- rtl/rtl_style_audit.json | 2 + scripts/README.md | 5 +- scripts/build_hp_apu.py | 2 +- scripts/build_hp_linux.py | 2 +- scripts/build_hp_smoke.py | 2 +- scripts/check_format.py | 8 +- scripts/generate_openc906.py | 174 + scripts/generate_vexiiriscv.py | 15 +- scripts/npu_compiler.py | 16 + scripts/run_npu_p6_verilator.py | 3 +- scripts/setup_openc906.py | 33 + ...oSocHp.scala => GenerateRetroSocStd.scala} | 10 +- tests/rtl/apb4_topology_tb.sv | 8 +- tests/rtl/axi4_downsizer_128to64_tb.sv | 420 ++ tests/rtl/axi4_mmio_demux_tb.sv | 370 ++ tests/rtl/ga2d_platform_tb.sv | 185 +- tests/rtl/hp_c906_boot_tb.sv | 356 ++ tests/test_axi4.py | 84 + tests/test_ga2d_platform.py | 4 +- tests/test_hp_platform.py | 208 +- tests/test_mgmt_core_spec.py | 38 +- tests/test_npu_p6.py | 6 +- tests/test_publication_dev_snapshot.py | 4 +- tests/test_publication_diagrams.py | 2 +- tests/test_publication_implementation.py | 15 +- tests/test_publication_programming.py | 4 +- tests/test_publication_registers.py | 6 +- tests/test_publication_retrieval.py | 6 +- tests/test_publication_software.py | 4 +- tests/test_soc_topology.py | 30 +- tests/test_std_vexiiriscv.py | 52 + 133 files changed, 8797 insertions(+), 2420 deletions(-) create mode 100644 rtl/mini/ip_overrides/aq_sysio_kid.v create mode 100644 rtl/mini/ip_overrides/sysmap.h create mode 100644 rtl/mini/top/axi4_downsizer_128to64.sv create mode 100644 rtl/mini/top/axi4_mmio_demux.sv create mode 100644 scripts/generate_openc906.py create mode 100644 scripts/setup_openc906.py rename scripts/vexiiriscv/{GenerateRetroSocHp.scala => GenerateRetroSocStd.scala} (91%) create mode 100644 tests/rtl/axi4_downsizer_128to64_tb.sv create mode 100644 tests/rtl/axi4_mmio_demux_tb.sv create mode 100644 tests/rtl/hp_c906_boot_tb.sv create mode 100644 tests/test_std_vexiiriscv.py diff --git a/ATTRIBUTIONS.md b/ATTRIBUTIONS.md index c19ccfee..0e7ea534 100644 --- a/ATTRIBUTIONS.md +++ b/ATTRIBUTIONS.md @@ -1,5 +1,15 @@ # Third-party attribution +The Mini high-performance (HP) core is the pre-generated T-Head OpenC906 RTL +from [XUANTIE-RV/openc906](https://github.com/XUANTIE-RV/openc906), locked at +commit `b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f` in +`dependencies/dependencies.lock.json` and installed below +`.cache/retrosoc/sources/openc906`. OpenC906 is licensed under Apache-2.0; its +copyright and license files remain in the locked checkout and are not copied +into this repository. The single retroSoC-controlled substitution is the +reviewed hart-ID override `rtl/mini/ip_overrides/aq_sysio_kid.v`, which +retains the upstream Apache-2.0 header. + The optional HP RT-Thread kernel is official RT-Thread v5.3.0, commit `99428a1e7f7447955aa860f7c969273a12095b8f`, from [RT-Thread/rt-thread](https://github.com/RT-Thread/rt-thread). It is licensed diff --git a/Makefile b/Makefile index c3a9dd3c..72d1ab2b 100644 --- a/Makefile +++ b/Makefile @@ -51,7 +51,6 @@ PDK_BEHAV ?= NO HAVE_SVA ?= NO APU_ENABLE_P7 ?= NO HAVE_HP ?= $(if $(filter TINY,$(SOC)),NO,YES) -HP_CONFIG ?= rv64imafdc_zicbom_max BUILD_RELEASE ?= NO JTAG_IDCODE ?= DEADBEEF EXT_CLK_HZ ?= 72000000 @@ -97,6 +96,7 @@ HP_COREMARK_REPORT ?= BUILD_ROOT ?= $(ROOT_PATH)/build CACHE_ROOT ?= $(ROOT_PATH)/.cache/retrosoc VEXIIRISCV_ROOT ?= $(ROOT_PATH)/.cache/retrosoc/sources/vexiiriscv +OPENC906_ROOT ?= $(ROOT_PATH)/.cache/retrosoc/sources/openc906 SBT ?= sbt BUILD_TIMESTAMP ?= $(shell date '+%Y-%m-%d-%H-%M') BUILD_TIMESTAMP := $(BUILD_TIMESTAMP) @@ -117,7 +117,7 @@ JOBS ?= $(shell count=$$(nproc 2>/dev/null || printf '1'); \ else printf '%s' "$$count"; fi) LOCAL_RTL_FILES ?= CONFIG_KEY_VARS := SOC MINI_MODE PDK HAVE_PLL HAVE_SRAM_IF HAVE_SRAM_MACRO SRAM_SIZE_KIB PDK_BEHAV HAVE_SVA APU_ENABLE_P7 \ - HAVE_HP HP_CONFIG BUILD_RELEASE JTAG_IDCODE EXT_CLK_HZ AUD_CLK_HZ CLINT_TIMEBASE_HZ MGMT_CPU_CLK_HZ \ + HAVE_HP BUILD_RELEASE JTAG_IDCODE EXT_CLK_HZ AUD_CLK_HZ CLINT_TIMEBASE_HZ MGMT_CPU_CLK_HZ \ ISA HAVE_CSR APP LINK_TYPE COREMARK_MODE RTL_TOP FIRMWARE_NAME CONFIG_KEY_VARS += NPU_P5_ACCEPTANCE NPU_P6_ACCEPTANCE NPU_P6_WORKLOAD # Preserve existing baseline keys; experimental software inputs have distinct variants. @@ -142,8 +142,8 @@ SW_BUILD_DIR := $(VARIANT_ROOT)/sw SIM_TOOL_NAME := $(shell printf '%s' '$(SIMU)' | tr '[:upper:]' '[:lower:]') SIM_BUILD_ROOT := $(VARIANT_ROOT)/sim/$(SIM_TOOL_NAME) META_DIR := $(VARIANT_ROOT)/meta -HP_GENERATED_DIR := $(VARIANT_ROOT)/generated/vexiiriscv -HP_GENERATED_RTL := $(HP_GENERATED_DIR)/vexii_riscv_hp_generated.v +HP_GENERATED_DIR := $(VARIANT_ROOT)/generated/openc906 +HP_GENERATED_FL := $(HP_GENERATED_DIR)/openc906.fl HP_GENERATED_MANIFEST := $(HP_GENERATED_DIR)/manifest.json HP_GENERATED_STAMP := $(HP_GENERATED_DIR)/.stamp APU_P5_DIR := $(VARIANT_ROOT)/apu/p5 @@ -243,7 +243,6 @@ VALID_SYNTH_RECIPE := balanced area speed VALID_STA := NONE OPENSTA VALID_PDK := ICS55 IHP130 SKY130 GF180 VALID_BOOL := YES NO -VALID_HP_CONFIG := rv64imafdc_zicbom_max VALID_ISA := RV32E RV32I RV32IM VALID_APP := benchmark bringup ci_smoke coremark debug hp_boot shell xpi_flash_loader apu_release VALID_LINK_TYPE := xip jtag_sram ld2_all_sram ld2_sram ld2_psram ld2_sdram ld2_tiny_banked @@ -269,7 +268,6 @@ $(call validate_value,PDK_BEHAV,$(VALID_BOOL)) $(call validate_value,HAVE_SVA,$(VALID_BOOL)) $(call validate_value,APU_ENABLE_P7,$(VALID_BOOL)) $(call validate_value,HAVE_HP,$(VALID_BOOL)) -$(call validate_value,HP_CONFIG,$(VALID_HP_CONFIG)) $(call validate_value,BUILD_RELEASE,$(VALID_BOOL)) $(call validate_value,WAVE,$(VALID_BOOL)) $(call validate_value,FORMAL,$(VALID_BOOL)) @@ -522,7 +520,7 @@ crypto-p2-report: manifest --netlist-root $(CRYPTO_P2_NETLIST_ROOT) --sta-root $(CRYPTO_P2_STA_ROOT) \ --physical-root $(CRYPTO_P2_PHYSICAL_ROOT) -.PHONY: help config doctor setup setup-regression setup-mpw setup-vexiiriscv setup-clusterip setup-ip setup-pdk setup-app setup-apu-reference setup-apu-kws-reference apu-p5-bundle apu-p5-corpus apu-p7-model apu-p9-coefficients apu-p9-evidence apu-p9-memory-ab setup-hp-linux hp-linux hp-bundle hp-linux-sim hp-smoke-bundle hp-smoke-sim hp-apu-bundle hp-apu-sim \ +.PHONY: help config doctor setup setup-regression setup-mpw setup-vexiiriscv setup-openc906 setup-clusterip setup-ip setup-pdk setup-app setup-apu-reference setup-apu-kws-reference apu-p5-bundle apu-p5-corpus apu-p7-model apu-p9-coefficients apu-p9-evidence apu-p9-memory-ab setup-hp-linux hp-linux hp-bundle hp-linux-sim hp-smoke-bundle hp-smoke-sim hp-apu-bundle hp-apu-sim \ clean-all purge-cache manifest check-warnings metrics check-metrics package commercial-package \ regress-smoke regress-rtl regress-pr regress-nightly sim-asm format format-check sw-format sw-format-check mk-format \ mk-format-check rtl-format rtl-format-check rtl-style-check rtl-migrate-connections rtl-migrate-names sw-policy-check sw-host-test \ @@ -532,7 +530,7 @@ crypto-p2-report: manifest pin-map check-pin-map soc-topology check-soc-topology user-extensions check-user-extensions \ check-clock-reset-domains tech-cell-test rtl-lint check-rtl-lint \ formal formal-bus formal-rib-adapter formal-rib2apb formal-gpio formal-ws2812 formal-uart formal-i2c formal-timer formal-dvp formal-i2s formal-onchip-ram formal-opipsram formal-dma formal-apu formal-apu-kws formal-apu-p9 formal-gateway-a formal-sdio formal-clean formal-doctor \ - rtl-style-check-all rtl-readiness-check rtl-readiness-check-all vexii-generate + rtl-style-check-all rtl-readiness-check rtl-readiness-check-all openc906-prepare std-vexii-generate .NOTPARALLEL: setup help: @@ -607,7 +605,8 @@ help: ' soc-topology generate the selected internal SoC integration artifacts' \ ' check-soc-topology validate the canonical internal SoC integration map' \ ' user-extensions generate the selected scalar user-extension bindings' \ - ' vexii-generate generate the locked HP VexiiRiscv RTL below build/' \ + ' openc906-prepare emit the locked HP OpenC906 filelist below build/' \ + ' std-vexii-generate generate the Std-series VexiiRiscv RTL below build/ (Std asset)' \ ' check-user-extensions validate the canonical user-extension map' \ ' check-clock-reset-domains validate the root clock/reset and CDC inventory' \ ' rtl-lint | check-rtl-lint run/check strict Verilator RTL lint warnings' \ @@ -655,7 +654,7 @@ config: HAVE_PLL '$(HAVE_PLL)' HAVE_SRAM_IF '$(HAVE_SRAM_IF)' \ HAVE_SRAM_MACRO '$(HAVE_SRAM_MACRO)' SRAM_SIZE_KIB '$(SRAM_SIZE_KIB)' \ PDK_BEHAV '$(PDK_BEHAV)' HAVE_SVA '$(HAVE_SVA)' APU_ENABLE_P7 '$(APU_ENABLE_P7)' \ - HAVE_HP '$(HAVE_HP)' HP_CONFIG '$(HP_CONFIG)' BUILD_RELEASE '$(BUILD_RELEASE)' \ + HAVE_HP '$(HAVE_HP)' BUILD_RELEASE '$(BUILD_RELEASE)' \ JTAG_IDCODE '$(JTAG_IDCODE)' EXT_CLK_HZ '$(EXT_CLK_HZ)' AUD_CLK_HZ '$(AUD_CLK_HZ)' \ CLINT_TIMEBASE_HZ '$(CLINT_TIMEBASE_HZ)' MGMT_CPU_CLK_HZ '$(MGMT_CPU_CLK_HZ)' \ ISA '$(ISA)' HAVE_CSR '$(HAVE_CSR)' APP '$(APP)' \ @@ -691,7 +690,7 @@ setup: setup-tiny setup-tiny: python3 $(ROOT_PATH)/scripts/setup_tiny.py --pdk $(PDK) else -setup: setup-mpw setup-vexiiriscv setup-clusterip setup-ip setup-pdk setup-app +setup: setup-mpw setup-openc906 setup-clusterip setup-ip setup-pdk setup-app endif setup-regression: @@ -710,6 +709,9 @@ setup-mpw: setup-vexiiriscv: python3 $(ROOT_PATH)/scripts/setup_vexiiriscv.py +setup-openc906: + python3 $(ROOT_PATH)/scripts/setup_openc906.py + setup-clusterip: python3 $(ROOT_PATH)/rtl/managed/clusterip/setup.py @@ -1102,19 +1104,28 @@ npu-p5-lp-sim: firmware sim --require 'NPU_P5_LP model=kws' --require 'SIM_TEST_PASS code=0' ifeq ($(HAVE_HP),YES) -$(HP_GENERATED_STAMP): $(ROOT_PATH)/scripts/generate_vexiiriscv.py \ - $(ROOT_PATH)/scripts/vexiiriscv/GenerateRetroSocHp.scala $(LOCK_FILE) - python3 $(ROOT_PATH)/scripts/generate_vexiiriscv.py \ - --root $(ROOT_PATH) --source $(VEXIIRISCV_ROOT) --output $(HP_GENERATED_DIR) \ - --manifest $(HP_GENERATED_MANIFEST) --lock $(LOCK_FILE) --sbt $(SBT) +$(HP_GENERATED_STAMP): $(ROOT_PATH)/scripts/generate_openc906.py \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_sysio_kid.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/sysmap.h $(LOCK_FILE) + python3 $(ROOT_PATH)/scripts/generate_openc906.py \ + --root $(ROOT_PATH) --source $(OPENC906_ROOT) --output $(HP_GENERATED_DIR) \ + --manifest $(HP_GENERATED_MANIFEST) --lock $(LOCK_FILE) @touch $@ -vexii-generate: $(HP_GENERATED_STAMP) +openc906-prepare: $(HP_GENERATED_STAMP) else -vexii-generate: - @printf '%s\n' 'HAVE_HP=NO; no VexiiRiscv RTL is required' +openc906-prepare: + @printf '%s\n' 'HAVE_HP=NO; no OpenC906 RTL is required' endif +# Std-series asset: the VexiiRiscv generator no longer participates in the +# Mini build; it is preserved here for the future Std performance core. +STD_VEXII_DIR := $(VARIANT_ROOT)/generated/vexiiriscv +std-vexii-generate: + python3 $(ROOT_PATH)/scripts/generate_vexiiriscv.py \ + --root $(ROOT_PATH) --source $(VEXIIRISCV_ROOT) --output $(STD_VEXII_DIR) \ + --manifest $(STD_VEXII_DIR)/manifest.json --lock $(LOCK_FILE) --sbt $(SBT) + clean-all: python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(abspath $(BUILD_ROOT)) diff --git a/README.md b/README.md index dfab1cbb..41a07c2c 100644 --- a/README.md +++ b/README.md @@ -19,7 +19,7 @@ An open-source RISC-V SoC platform, from SystemVerilog RTL and firmware to repro ## Platform overview **Mini and Tiny have independent integration flows.** Mini combines a -low-power Hazard3 management hart and a VexiiRiscv application hart; its separate +low-power Hazard3 management hart and a T-Head OpenC906 application hart; its separate MPW profile retains selectable-core compatibility. [Tiny](docs/ip/tiny-soc.md) is a wired MCU with one Hazard3 RV32IMC hart, 128 KiB SRAM, AXI4/APB4 and no wireless IP. Tiny defaults to ICS55 SAFE24 with a parked PLL and retains @@ -34,7 +34,7 @@ multimedia inputs. | Area | Mini platform | | --- | --- | -| Compute | Hazard3 LP management hart; generated dual-issue VexiiRiscv HP application hart. Baseline profiles compile LP firmware for RV32IM and select an RV64IMAFDC HP core with Zicbom cache maintenance. | +| Compute | Hazard3 LP management hart; locked pre-generated T-Head OpenC906 HP application hart. Baseline profiles compile LP firmware for RV32IM and use the OpenC906 DEFAULT RV64GC configuration with T-Head custom cache-maintenance instructions. | | Memory and interconnect | Native AXI4 data plane, APB4 control, configurable on-chip SRAM, SDRAM, PSRAM/OPI-PSRAM, and XPI flash integration. | | Control and I/O | GPIO, timers, UART, I2C, I2S, PWM, RTC, watchdog, storage interfaces, DMA, interrupt routing, and fixed EXT-L/EXT-H extension slots. | | Software | Freestanding C runtime and HAL, board support, diagnostic and shell applications, CoreMark, and HP boot/bundle tooling. | diff --git a/app/benchmark/npu/npu_p6_runner.c b/app/benchmark/npu/npu_p6_runner.c index 46ff64f9..f47f5015 100644 --- a/app/benchmark/npu/npu_p6_runner.c +++ b/app/benchmark/npu/npu_p6_runner.c @@ -503,7 +503,8 @@ static void rs_npu_p6_clean_range(const void *pointer, uint32_t bytes) { uintptr_t end = ((uintptr_t)pointer + bytes + UINT32_C(63)) & ~(uintptr_t)UINT32_C(63); while (cursor < end) { - __asm__ volatile("cbo.clean 0(%0)" : : "r"(cursor) : "memory"); + /* OpenC906 dcache.cva: clean the 64-byte D-cache line at cursor. */ + __asm__ volatile(".insn r 0x0b, 0x0, 0x01, x0, %0, x5" : : "r"(cursor) : "memory"); cursor += UINT32_C(64); } } @@ -513,7 +514,8 @@ static void rs_npu_p6_invalidate_range(const void *pointer, uint32_t bytes) { uintptr_t end = ((uintptr_t)pointer + bytes + UINT32_C(63)) & ~(uintptr_t)UINT32_C(63); while (cursor < end) { - __asm__ volatile("cbo.inval 0(%0)" : : "r"(cursor) : "memory"); + /* OpenC906 dcache.iva: invalidate the 64-byte D-cache line at cursor. */ + __asm__ volatile(".insn r 0x0b, 0x0, 0x01, x0, %0, x6" : : "r"(cursor) : "memory"); cursor += UINT32_C(64); } __asm__ volatile("fence r, r" : : : "memory"); diff --git a/app/ports/hp-apu/main.c b/app/ports/hp-apu/main.c index f8ebb8c4..920dfc90 100644 --- a/app/ports/hp-apu/main.c +++ b/app/ports/hp-apu/main.c @@ -25,7 +25,7 @@ #define HP_MAILBOX_HP_DOORBELL UINT32_C(0x2C) #define HP_MAILBOX_HP_INTR_STATE UINT32_C(0x40) -#define HP_CBO_LINE_BYTES UINT32_C(64) +#define HP_CACHE_LINE_BYTES UINT32_C(64) #define HP_MAILBOX_BUDGET UINT32_C(0x08000000) #define HP_JOB_BUDGET UINT32_C(0x08000000) #define HP_JOB_TERMINAL \ @@ -77,24 +77,26 @@ static void hp_uart_puthex(uint32_t value) { } } -static void hp_cbo_clean(uint32_t address, uint32_t bytes) { - uint32_t cursor = address & ~(HP_CBO_LINE_BYTES - 1U); +static void hp_dcache_clean(uint32_t address, uint32_t bytes) { + uint32_t cursor = address & ~(HP_CACHE_LINE_BYTES - 1U); const uint32_t end = address + bytes; while (cursor < end) { - __asm__ volatile("cbo.clean 0(%0)" ::"r"(cursor) : "memory"); - cursor += HP_CBO_LINE_BYTES; + /* OpenC906 dcache.cva: clean the 64-byte D-cache line at cursor. */ + __asm__ volatile(".insn r 0x0b, 0x0, 0x01, x0, %0, x5" ::"r"(cursor) : "memory"); + cursor += HP_CACHE_LINE_BYTES; } __asm__ volatile("fence rw, rw" ::: "memory"); } -static void hp_cbo_inval(uint32_t address, uint32_t bytes) { - uint32_t cursor = address & ~(HP_CBO_LINE_BYTES - 1U); +static void hp_dcache_inval(uint32_t address, uint32_t bytes) { + uint32_t cursor = address & ~(HP_CACHE_LINE_BYTES - 1U); const uint32_t end = address + bytes; while (cursor < end) { - __asm__ volatile("cbo.inval 0(%0)" ::"r"(cursor) : "memory"); - cursor += HP_CBO_LINE_BYTES; + /* OpenC906 dcache.iva: invalidate the 64-byte D-cache line at cursor. */ + __asm__ volatile(".insn r 0x0b, 0x0, 0x01, x0, %0, x6" ::"r"(cursor) : "memory"); + cursor += HP_CACHE_LINE_BYTES; } __asm__ volatile("fence rw, rw" ::: "memory"); } @@ -200,7 +202,7 @@ static bool hp_submit_wav(volatile rs_apu_release_page_t *page) { !hp_range_in(page->output_address, page->output_capacity, write_base, write_limit)) { return false; } - hp_cbo_clean(page->wav_address, page->wav_bytes); + hp_dcache_clean(page->wav_address, page->wav_bytes); *hp_reg(apu + RS_APU_ABI_JOB_CONTROL) = 0U; *hp_reg(apu + RS_APU_ABI_JOB_INPUT_ADDRESS) = page->wav_address; *hp_reg(apu + RS_APU_ABI_JOB_INPUT_LENGTH) = page->wav_bytes; @@ -221,7 +223,7 @@ static bool hp_submit_wav(volatile rs_apu_release_page_t *page) { if ((page->wav_status & (UINT32_C(1) << RS_APU_ABI_JOB_STATUS_DONE)) == 0U) { return false; } - hp_cbo_inval(page->output_address, page->wav_output_bytes); + hp_dcache_inval(page->output_address, page->wav_output_bytes); page->wav_output_crc = hp_crc32((volatile const uint8_t *)(uintptr_t)page->output_address, page->wav_output_bytes); page->hp_steps |= RS_APU_RELEASE_STEP_WAV_DONE; @@ -240,7 +242,7 @@ static bool hp_submit_kws(volatile rs_apu_release_page_t *page) { } *hp_reg(apu + RS_APU_ABI_KWS_CONTROL) = UINT32_C(3); page->hp_steps |= RS_APU_RELEASE_STEP_KWS_ARM; - hp_cbo_clean(page->kws_address, page->kws_bytes); + hp_dcache_clean(page->kws_address, page->kws_bytes); *hp_reg(apu + RS_APU_ABI_JOB_CONTROL) = UINT32_C(1); *hp_reg(apu + RS_APU_ABI_JOB_INPUT_ADDRESS) = page->kws_address; *hp_reg(apu + RS_APU_ABI_JOB_INPUT_LENGTH) = page->kws_bytes; @@ -295,7 +297,7 @@ static void hp_publish(volatile rs_apu_release_page_t *page, uint32_t summary) { page->hp_steps |= RS_APU_RELEASE_STEP_PUBLISH; page->result_magic = RS_APU_RELEASE_RESULT_MAGIC; - hp_cbo_clean(RS_APU_RELEASE_PAGE_ADDRESS, RS_APU_RELEASE_PAGE_BYTES); + hp_dcache_clean(RS_APU_RELEASE_PAGE_ADDRESS, RS_APU_RELEASE_PAGE_BYTES); mailbox[HP_MAILBOX_HP_EVENT / 4U] = RS_APU_RELEASE_EVENT_DONE; mailbox[HP_MAILBOX_HP_ARG0 / 4U] = summary; mailbox[HP_MAILBOX_HP_SEQUENCE / 4U] = RS_APU_RELEASE_MAILBOX_SEQUENCE; @@ -340,7 +342,7 @@ void main(void) { } } hp_milestone("MAILBOX"); - hp_cbo_inval(RS_APU_RELEASE_PAGE_ADDRESS, RS_APU_RELEASE_PAGE_BYTES); + hp_dcache_inval(RS_APU_RELEASE_PAGE_ADDRESS, RS_APU_RELEASE_PAGE_BYTES); page->hp_steps = RS_APU_RELEASE_STEP_MAILBOX; if ((code != RS_APU_RELEASE_JOB_RUN) || (argument != RS_APU_RELEASE_PAGE_ADDRESS) || (page->magic != RS_APU_RELEASE_PAGE_MAGIC) || diff --git a/app/ports/linux/README.md b/app/ports/linux/README.md index 777a6a47..e5c3276e 100644 --- a/app/ports/linux/README.md +++ b/app/ports/linux/README.md @@ -1,7 +1,7 @@ # HP Linux Port This directory owns the Buildroot external tree, device tree, kernel config, -and integration metadata for the fixed RV64 VexiiRiscv HP core. Linux, +and integration metadata for the fixed RV64GC T-Head OpenC906 HP core. Linux, OpenSBI, Buildroot, toolchains, and all generated images remain below `.cache/` or `build/` and are not tracked. diff --git a/app/ports/linux/linux/retrosoc_hp.dts b/app/ports/linux/linux/retrosoc_hp.dts index 77896549..344ac54c 100644 --- a/app/ports/linux/linux/retrosoc_hp.dts +++ b/app/ports/linux/linux/retrosoc_hp.dts @@ -18,15 +18,14 @@ timebase-frequency = <1000000>; cpu@1 { - compatible = "spinal,vexiiriscv", "riscv"; + compatible = "thead,c906", "riscv"; device_type = "cpu"; reg = <1>; clock-frequency = <72000000>; mmu-type = "riscv,sv39"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicsr", "zifencei"; - riscv,cbom-block-size = <64>; hp_cpu_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -60,15 +59,27 @@ #size-cells = <1>; ranges; - hp_aclint: timer@2000000 { - compatible = "sifive,clint0"; - reg = <0x02000000 0x00010000>; - interrupts-extended = <&hp_cpu_intc 3>, <&hp_cpu_intc 7>; + /* + * Internal C906 CLINT (thead,c900-clint): decoded by the core + * BIU, not a SoC fabric slave. No memory-mapped mtime; software + * reads the time CSR. Interrupt order per hart: M-SW, M-timer, + * S-SW, S-timer. + */ + hp_clint: timer@c000000 { + compatible = "thead,c900-clint"; + reg = <0x0c000000 0x00010000>; + interrupts-extended = <&hp_cpu_intc 3>, <&hp_cpu_intc 7>, + <&hp_cpu_intc 1>, <&hp_cpu_intc 5>; }; - hp_plic: interrupt-controller@c000000 { - compatible = "sifive,plic-1.0.0"; - reg = <0x0c000000 0x04000000>; + /* + * Internal C906 PLIC (thead,c900-plic): decoded by the core + * BIU. SoC external source n is PLIC ID n+16; IDs 0-15 are + * reserved/internal. + */ + hp_plic: interrupt-controller@8000000 { + compatible = "thead,c900-plic"; + reg = <0x08000000 0x04000000>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; @@ -80,7 +91,7 @@ compatible = "retrosoc,uart-v3"; reg = <0x10018000 0x1000>; interrupt-parent = <&hp_plic>; - interrupts = <1>; + interrupts = <17>; clock-frequency = <72000000>; status = "okay"; }; @@ -89,7 +100,7 @@ compatible = "retrosoc,hp-mailbox-v1"; reg = <0x10019000 0x1000>; interrupt-parent = <&hp_plic>; - interrupts = <2>; + interrupts = <18>; #mbox-cells = <1>; }; }; diff --git a/app/ports/linux/opensbi/retrosoc_hp/Kconfig b/app/ports/linux/opensbi/retrosoc_hp/Kconfig index 4f294b16..b6261b9b 100644 --- a/app/ports/linux/opensbi/retrosoc_hp/Kconfig +++ b/app/ports/linux/opensbi/retrosoc_hp/Kconfig @@ -3,5 +3,4 @@ config PLATFORM_RETROSOC_HP bool select IPI_MSWI - select TIMER_MTIMER default y diff --git a/app/ports/linux/opensbi/retrosoc_hp/platform.c b/app/ports/linux/opensbi/retrosoc_hp/platform.c index 88ee80fc..43640474 100644 --- a/app/ports/linux/opensbi/retrosoc_hp/platform.c +++ b/app/ports/linux/opensbi/retrosoc_hp/platform.c @@ -1,13 +1,18 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* Copyright (c) 2026 Yuchi Miao */ +#include +#include #include #include #include +#include #include -#include -#define RETROSOC_HP_ACLINT_BASE 0x02000000UL +/* Internal C906 CLINT (thead,c900-clint), decoded by the core BIU. */ +#define RETROSOC_HP_CLINT_BASE 0x0C000000UL +#define RETROSOC_HP_CLINT_MTIMECMP_LO 0x4000UL +#define RETROSOC_HP_CLINT_MTIMECMP_HI 0x4004UL #define RETROSOC_HP_UART_BASE 0x10018000UL #define RETROSOC_HP_UART_BAUD_INT 78U #define RETROSOC_HP_UART_BAUD_FRAC 32U @@ -30,21 +35,44 @@ static const u32 s_hart_index_to_id[] = {1U}; static struct aclint_mswi_data s_mswi = { - .addr = RETROSOC_HP_ACLINT_BASE, + .addr = RETROSOC_HP_CLINT_BASE, .size = ACLINT_MSWI_SIZE, - .first_hartid = 0U, - .hart_count = 2U, + .first_hartid = 1U, + .hart_count = 1U, }; -static struct aclint_mtimer_data s_mtimer = { - .mtime_freq = 1000000UL, - .mtime_addr = RETROSOC_HP_ACLINT_BASE + 0xBFF8UL, - .mtime_size = ACLINT_DEFAULT_MTIME_SIZE, - .mtimecmp_addr = RETROSOC_HP_ACLINT_BASE + 0x4000UL, - .mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE, - .first_hartid = 0U, - .hart_count = 2U, - .has_64bit_mmio = false, +/* No memory-mapped mtime: the SoC drives mtime into the core. */ +static u64 retrosoc_hp_timer_value(void) { + return csr_read(CSR_TIME); +} + +static void retrosoc_hp_mtimecmp_write(u64 value) { + writel_relaxed((u32)-1, (void *)(RETROSOC_HP_CLINT_BASE + RETROSOC_HP_CLINT_MTIMECMP_LO)); + writel_relaxed((u32)(value >> 32U), + (void *)(RETROSOC_HP_CLINT_BASE + RETROSOC_HP_CLINT_MTIMECMP_HI)); + writel_relaxed((u32)value, (void *)(RETROSOC_HP_CLINT_BASE + RETROSOC_HP_CLINT_MTIMECMP_LO)); +} + +static void retrosoc_hp_timer_event_start(u64 next_event) { + retrosoc_hp_mtimecmp_write(next_event); +} + +static void retrosoc_hp_timer_event_stop(void) { + retrosoc_hp_mtimecmp_write(~0ULL); +} + +static int retrosoc_hp_timer_warm_init(void) { + retrosoc_hp_timer_event_stop(); + return 0; +} + +static struct sbi_timer_device s_timer = { + .name = "retrosoc-hp-c906-clint", + .timer_freq = 1000000UL, + .timer_value = retrosoc_hp_timer_value, + .timer_event_start = retrosoc_hp_timer_event_start, + .timer_event_stop = retrosoc_hp_timer_event_stop, + .warm_init = retrosoc_hp_timer_warm_init, }; static void retrosoc_hp_uart_write(u32 offset, u32 value) { @@ -93,7 +121,8 @@ static int retrosoc_hp_early_init(bool cold_boot) { } static int retrosoc_hp_timer_init(void) { - return aclint_mtimer_cold_init(&s_mtimer, NULL); + sbi_timer_set_device(&s_timer); + return 0; } static const struct sbi_platform_operations s_platform_operations = { @@ -104,7 +133,7 @@ static const struct sbi_platform_operations s_platform_operations = { const struct sbi_platform platform = { .opensbi_version = OPENSBI_VERSION, .platform_version = SBI_PLATFORM_VERSION(1U, 0U), - .name = "retroSoC RV64 HP", + .name = "retroSoC OpenC906 HP", .features = SBI_PLATFORM_DEFAULT_FEATURES, .hart_count = 1U, .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE, diff --git a/app/ports/linux/smoke/npu_acceptance.c b/app/ports/linux/smoke/npu_acceptance.c index ac7e4d29..0e4cd8f3 100644 --- a/app/ports/linux/smoke/npu_acceptance.c +++ b/app/ports/linux/smoke/npu_acceptance.c @@ -17,7 +17,8 @@ static void rs_hp_npu_clean_range(const void *pointer, uint32_t bytes) { uintptr_t end = ((uintptr_t)pointer + bytes + UINT32_C(63)) & ~(uintptr_t)UINT32_C(63); while (cursor < end) { - __asm__ volatile("cbo.clean 0(%0)" : : "r"(cursor) : "memory"); + /* OpenC906 dcache.cva: clean the 64-byte D-cache line at cursor. */ + __asm__ volatile(".insn r 0x0b, 0x0, 0x01, x0, %0, x5" : : "r"(cursor) : "memory"); cursor += UINT32_C(64); } } diff --git a/app/ports/linux/smoke/start.S b/app/ports/linux/smoke/start.S index 0f432285..42f8626e 100644 --- a/app/ports/linux/smoke/start.S +++ b/app/ports/linux/smoke/start.S @@ -58,6 +58,10 @@ .equ GA2D_WAIT_POLLS, 0x00100000 _start: + # Enable the T-Head extended instruction set (mxstatus.theadisaee) so the + # C906 custom-0 cache maintenance instructions below decode legally. + li t0, 0x400000 + csrs 0x7c0, t0 la sp, _stack_top la t0, _bss_start la t1, _bss_end @@ -257,27 +261,31 @@ prepare_source_data: mv ra, s0 ret +# C906 cache maintenance replaces the VexiiRiscv Zicbom ops: custom-0 +# encodings dcache.cva (0x0250000b | rs1<<15, clean by VA) and dcache.iva +# (0x0260000b | rs1<<15, invalidate by VA) per the OpenC906 ID decoder and +# the XTheadCmo specification. Each shared buffer remains one 64-byte line. clean_shared_lines: la a0, hp_source_guard - cbo.clean 0(a0) + .insn r 0x0b, 0x0, 0x01, x0, a0, x5 la a0, hp_source_line - cbo.clean 0(a0) + .insn r 0x0b, 0x0, 0x01, x0, a0, x5 la a0, hp_destination_line - cbo.clean 0(a0) + .insn r 0x0b, 0x0, 0x01, x0, a0, x5 la a0, hp_destination_guard - cbo.clean 0(a0) + .insn r 0x0b, 0x0, 0x01, x0, a0, x5 fence rw, rw ret invalidate_shared_lines: la a0, hp_source_guard - cbo.inval 0(a0) + .insn r 0x0b, 0x0, 0x01, x0, a0, x6 la a0, hp_source_line - cbo.inval 0(a0) + .insn r 0x0b, 0x0, 0x01, x0, a0, x6 la a0, hp_destination_line - cbo.inval 0(a0) + .insn r 0x0b, 0x0, 0x01, x0, a0, x6 la a0, hp_destination_guard - cbo.inval 0(a0) + .insn r 0x0b, 0x0, 0x01, x0, a0, x6 fence r, r ret diff --git a/app/ports/rtthread/README.md b/app/ports/rtthread/README.md index be405dad..d7ba32e3 100644 --- a/app/ports/rtthread/README.md +++ b/app/ports/rtthread/README.md @@ -6,8 +6,9 @@ dependency lock under `.cache/`; it is not edited or copied into project source. SCons runs on a staged BSP below `build//hp-rtthread/`. Run `make setup-hp-rtthread`, then `make CONFIG=configs/ci/ihp130-rtthread.mk -SIMU=VERILATOR hp-rtthread-sim`. The test uses UART1, hart-1 CLINT and PLIC -machine context 0/source 2. Peripheral accesses remain 32 bits. Static threads +SIMU=VERILATOR hp-rtthread-sim`. The test uses UART1 and the internal C906 +CLINT (time CSR plus MTIMECMP at 0x0C004000) and PLIC machine context 0 with +the mailbox doorbell at source 18. Peripheral accesses remain 32 bits. Static threads exercise RV64 integer state, timer preemption, semaphore/message queue behavior, timeouts, and an LP-to-HP mailbox interrupt. LP validates the final mailbox response and owns SYSCTRL TEST_STATUS. A banner alone is not a pass. diff --git a/app/ports/rtthread/board.c b/app/ports/rtthread/board.c index 5f9f54ce..eff873b6 100644 --- a/app/ports/rtthread/board.c +++ b/app/ports/rtthread/board.c @@ -3,10 +3,12 @@ #include -#define RS_RTT_UART UINT32_C(0x10018000) -#define RS_RTT_CLINT UINT32_C(0x02000000) -#define RS_RTT_PLIC UINT32_C(0x0C000000) -#define RS_RTT_MAILBOX UINT32_C(0x10019000) +#define RS_RTT_UART UINT32_C(0x10018000) +/* Internal C906 CLINT (MSIP@0x0, MTIMECMP@0x4000) and PLIC (ID n+16). */ +#define RS_RTT_CLINT UINT32_C(0x0C000000) +#define RS_RTT_PLIC UINT32_C(0x08000000) +#define RS_RTT_MAILBOX UINT32_C(0x10019000) +#define RS_RTT_MAILBOX_PLIC_ID UINT32_C(18) static struct rt_semaphore s_mailbox_sem; static volatile uint32_t s_irq_command; @@ -23,19 +25,16 @@ static void rs_write32(uint32_t address, uint32_t value) { } static uint64_t rs_time(void) { - uint32_t high; - uint32_t low; - do { - high = rs_read32(RS_RTT_CLINT + UINT32_C(0xBFFC)); - low = rs_read32(RS_RTT_CLINT + UINT32_C(0xBFF8)); - } while (high != rs_read32(RS_RTT_CLINT + UINT32_C(0xBFFC))); - return ((uint64_t)high << 32U) | low; + uint64_t value; + /* No memory-mapped mtime: the SoC drives mtime into the core. */ + __asm__ volatile("csrr %0, time" : "=r"(value)); + return value; } static void rs_set_timer(uint64_t value) { - rs_write32(RS_RTT_CLINT + UINT32_C(0x4008), UINT32_MAX); - rs_write32(RS_RTT_CLINT + UINT32_C(0x400C), (uint32_t)(value >> 32U)); - rs_write32(RS_RTT_CLINT + UINT32_C(0x4008), (uint32_t)value); + rs_write32(RS_RTT_CLINT + UINT32_C(0x4000), UINT32_MAX); + rs_write32(RS_RTT_CLINT + UINT32_C(0x4004), (uint32_t)(value >> 32U)); + rs_write32(RS_RTT_CLINT + UINT32_C(0x4000), (uint32_t)value); __asm__ volatile("fence iorw, iorw" ::: "memory"); } @@ -82,11 +81,11 @@ static void rs_assert(const char *expression, const char *function, rt_size_t li } void rt_trigger_software_interrupt(void) { - rs_write32(RS_RTT_CLINT + UINT32_C(4), 1U); + rs_write32(RS_RTT_CLINT, 1U); } void rt_hw_do_after_save_above(void) { - rs_write32(RS_RTT_CLINT + UINT32_C(4), 0U); + rs_write32(RS_RTT_CLINT, 0U); } void handle_trap(rt_ubase_t cause, rt_ubase_t epc, void *frame) { @@ -109,7 +108,7 @@ void handle_trap(rt_ubase_t cause, rt_ubase_t epc, void *frame) { break; case 11U: { uint32_t claim = rs_read32(RS_RTT_PLIC + UINT32_C(0x200004)); - if (claim != 2U) { + if (claim != RS_RTT_MAILBOX_PLIC_ID) { rs_rtt_fail(93U); } s_irq_command = rs_read32(RS_RTT_MAILBOX + UINT32_C(0x10)); @@ -149,11 +148,11 @@ void rt_hw_board_init(void) { rs_write32(RS_RTT_UART + UINT32_C(4), 32U); rs_write32(RS_RTT_UART + UINT32_C(8), 3U); rs_write32(RS_RTT_UART + UINT32_C(0x0C), 3U); - rs_write32(RS_RTT_CLINT + UINT32_C(4), 0U); + rs_write32(RS_RTT_CLINT, 0U); rs_write32(RS_RTT_MAILBOX + UINT32_C(0x40), 1U); rs_write32(RS_RTT_MAILBOX + UINT32_C(0x44), 1U); - rs_write32(RS_RTT_PLIC + UINT32_C(8), 1U); - rs_write32(RS_RTT_PLIC + UINT32_C(0x2000), 4U); + rs_write32(RS_RTT_PLIC + (UINT32_C(4) * RS_RTT_MAILBOX_PLIC_ID), 1U); + rs_write32(RS_RTT_PLIC + UINT32_C(0x2000), UINT32_C(1) << RS_RTT_MAILBOX_PLIC_ID); rs_write32(RS_RTT_PLIC + UINT32_C(0x200000), 0U); s_next_tick = rs_time() + UINT64_C(1000); rs_set_timer(s_next_tick); diff --git a/app/ports/rtthread/rtconfig.py b/app/ports/rtthread/rtconfig.py index 7f65faff..ff490bf4 100644 --- a/app/ports/rtthread/rtconfig.py +++ b/app/ports/rtthread/rtconfig.py @@ -10,7 +10,7 @@ CC = AS = LINK = PREFIX + 'gcc' CXX = PREFIX + 'g++' AR = PREFIX + 'ar' TARGET_EXT = 'elf' -DEVICE = '-march=rv64imafdc_zicbom_zicsr_zifencei -mabi=lp64d -mcmodel=medany' +DEVICE = '-march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany' CFLAGS = DEVICE + ' -O2 -g -ffreestanding -fno-builtin -ffunction-sections -fdata-sections -Wall' AFLAGS = DEVICE + ' -g -x assembler-with-cpp' LFLAGS = DEVICE + ' -nostdlib -nostartfiles -Wl,--gc-sections,-Map=rtthread.map -T linker.ld' diff --git a/configs/benchmark/ihp130-hazard3-coremark-standard.mk b/configs/benchmark/ihp130-hazard3-coremark-standard.mk index 35771224..bdeb775c 100644 --- a/configs/benchmark/ihp130-hazard3-coremark-standard.mk +++ b/configs/benchmark/ihp130-hazard3-coremark-standard.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max PDK_BEHAV := YES HAVE_SVA := NO EXT_CLK_HZ := 72000000 diff --git a/configs/benchmark/ihp130-hazard3-coremark.mk b/configs/benchmark/ihp130-hazard3-coremark.mk index 21b7f4ff..9d590cbc 100644 --- a/configs/benchmark/ihp130-hazard3-coremark.mk +++ b/configs/benchmark/ihp130-hazard3-coremark.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max PDK_BEHAV := YES HAVE_SVA := NO EXT_CLK_HZ := 72000000 diff --git a/configs/benchmark/ihp130-hazard3.mk b/configs/benchmark/ihp130-hazard3.mk index a695fa14..46c52bd5 100644 --- a/configs/benchmark/ihp130-hazard3.mk +++ b/configs/benchmark/ihp130-hazard3.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max PDK_BEHAV := YES HAVE_SVA := NO EXT_CLK_HZ := 72000000 diff --git a/configs/ci/gf180.mk b/configs/ci/gf180.mk index 4bb3d339..0af0c986 100644 --- a/configs/ci/gf180.mk +++ b/configs/ci/gf180.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max HAVE_SVA := NO EXT_CLK_HZ := 72000000 AUD_CLK_HZ := 18432000 diff --git a/configs/ci/ics55.mk b/configs/ci/ics55.mk index d35e5a75..82470577 100644 --- a/configs/ci/ics55.mk +++ b/configs/ci/ics55.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max HAVE_SVA := NO EXT_CLK_HZ := 72000000 AUD_CLK_HZ := 18432000 diff --git a/configs/ci/ihp130-apu.mk b/configs/ci/ihp130-apu.mk index 07775a30..257bf09f 100644 --- a/configs/ci/ihp130-apu.mk +++ b/configs/ci/ihp130-apu.mk @@ -4,7 +4,6 @@ PDK := IHP130 HAVE_PLL := NO HAVE_HP := YES APU_ENABLE_P7 := YES -HP_CONFIG := rv64imafdc_zicbom_max HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 diff --git a/configs/ci/ihp130-debug.mk b/configs/ci/ihp130-debug.mk index 2e8682ab..0b16f4d3 100644 --- a/configs/ci/ihp130-debug.mk +++ b/configs/ci/ihp130-debug.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max PDK_BEHAV := YES HAVE_SVA := NO EXT_CLK_HZ := 72000000 diff --git a/configs/ci/ihp130-hp.mk b/configs/ci/ihp130-hp.mk index 146f2291..7ad152ce 100644 --- a/configs/ci/ihp130-hp.mk +++ b/configs/ci/ihp130-hp.mk @@ -3,7 +3,6 @@ MINI_MODE := PRODUCT PDK := IHP130 HAVE_PLL := NO HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 diff --git a/configs/ci/ihp130-rtthread.mk b/configs/ci/ihp130-rtthread.mk index dbb2719a..018d8a13 100644 --- a/configs/ci/ihp130-rtthread.mk +++ b/configs/ci/ihp130-rtthread.mk @@ -4,7 +4,6 @@ MINI_MODE := PRODUCT PDK := IHP130 HAVE_PLL := NO HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 diff --git a/configs/ci/ihp130-shell.mk b/configs/ci/ihp130-shell.mk index 729d1162..5fed5fec 100644 --- a/configs/ci/ihp130-shell.mk +++ b/configs/ci/ihp130-shell.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max HAVE_SVA := NO EXT_CLK_HZ := 72000000 AUD_CLK_HZ := 18432000 diff --git a/configs/ci/ihp130-xpi-flash-loader.mk b/configs/ci/ihp130-xpi-flash-loader.mk index aed60288..5b7cbb3c 100644 --- a/configs/ci/ihp130-xpi-flash-loader.mk +++ b/configs/ci/ihp130-xpi-flash-loader.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max PDK_BEHAV := YES HAVE_SVA := NO EXT_CLK_HZ := 72000000 diff --git a/configs/ci/ihp130.mk b/configs/ci/ihp130.mk index 4224e991..7d84e990 100644 --- a/configs/ci/ihp130.mk +++ b/configs/ci/ihp130.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max HAVE_SVA := NO EXT_CLK_HZ := 72000000 AUD_CLK_HZ := 18432000 diff --git a/configs/ci/sky130.mk b/configs/ci/sky130.mk index e2dceb51..39de55b2 100644 --- a/configs/ci/sky130.mk +++ b/configs/ci/sky130.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max HAVE_SVA := NO EXT_CLK_HZ := 72000000 AUD_CLK_HZ := 18432000 diff --git a/configs/cluster/ics55.mk b/configs/cluster/ics55.mk index d35e5a75..82470577 100644 --- a/configs/cluster/ics55.mk +++ b/configs/cluster/ics55.mk @@ -6,7 +6,6 @@ HAVE_SRAM_IF := YES HAVE_SRAM_MACRO := YES SRAM_SIZE_KIB := 32 HAVE_HP := YES -HP_CONFIG := rv64imafdc_zicbom_max HAVE_SVA := NO EXT_CLK_HZ := 72000000 AUD_CLK_HZ := 18432000 diff --git a/crt/src/service/booter.c b/crt/src/service/booter.c index c73457a4..159fa559 100644 --- a/crt/src/service/booter.c +++ b/crt/src/service/booter.c @@ -49,23 +49,21 @@ static void rs_print_hp_core_spec(void) { printf("\nHigh-Performance-Core Specification:\n"); printf(" Identity\n"); - printf(" Core: VexiiRiscv(hart 1), dual-issue in-order\n"); + printf(" Core: T-Head OpenC906(hart 1), dual-issue in-order\n"); printf(" Role: application, RT-Thread and Linux\n"); - printf(" Source: https://github.com/SpinalHDL/VexiiRiscv\n"); + printf(" Source: https://github.com/XUANTIE-RV/openc906\n"); printf(" Hardware ISA and privilege\n"); - printf(" Base: RV64IMAFDC_Zicbom_Zicntr_Zihpm\n"); - printf(" Mode: M/S/U; Sv39 MMU, 9-bit ASID\n"); - printf(" Protection: 16 PMP regions, 4 KiB granularity\n"); - printf(" IRQ: machine software/timer/external + supervisor external\n"); - printf(" Microarchitecture\n"); - printf(" Execution: 2 decoders/lanes, late ALU, full bypassing\n"); - printf(" Prediction: BTB + GShare + RAS\n"); + printf(" Base: RV64IMAFDC_Zicsr_Zifencei (RV64GC)\n"); + printf(" Mode: M/S/U; Sv39 MMU\n"); + printf(" IRQ: internal CLINT/PLIC (T-Head c900 layout)\n"); + printf(" Interrupt and timer windows\n"); + printf(" PLIC: 0x08000000; SoC external source n -> ID n+16\n"); + printf(" CLINT: 0x0c000000; MSIP/MTIMECMP/SSIP/STIMECMP\n"); + printf(" No MMIO mtime; software reads the time CSR\n"); + printf(" LP->HP notification: mailbox doorbell (PLIC ID 18)\n"); printf(" Cache and memory\n"); - printf(" L1: separate 16 KiB, 4-way instruction and data caches\n"); - printf(" Maintenance: 64-byte Zicbom CBO; no hardware coherency\n"); - printf(" Bus: native AXI64 I/D/MMIO; MMIO downsized to AXI32\n"); - printf(" Debug\n"); - printf(" Embedded RISC-V JTAG, 4 triggers\n"); + printf(" L1: separate instruction and data caches; no hardware coherency\n"); + printf(" Bus: AXI4 via core BIU; MMIO downsized to AXI32\n"); printf(" Runtime\n"); printf(" Released: %s; actual: %s; reset asserted: %s\n", rs_boolean_name(status.released), rs_boolean_name(status.actual_released), rs_boolean_name(status.reset_asserted)); @@ -75,10 +73,8 @@ static void rs_print_hp_core_spec(void) { static void rs_print_mmio_map(void) { printf("Memory-Mapped I/O Devices:\n"); - printf(" 1 x HP ACLINT @%p\n", - (void *)(uintptr_t)RS_SOC_HP_ACLINT_BASE); - printf(" 1 x HP PLIC @%p\n", - (void *)(uintptr_t)RS_SOC_HP_PLIC_BASE); + printf(" 1 x GLOBAL CLINT @%p\n", + (void *)(uintptr_t)RS_SOC_APB4_CLINT_BASE); printf(" 1 x GPIO(32PIN) @%p\n", (void *)(uintptr_t)RS_SOC_APB4_GPIO_BASE); printf(" 1 x UART0 @%p\n", diff --git a/dependencies/README.md b/dependencies/README.md index 8bdec376..bdd5791f 100644 --- a/dependencies/README.md +++ b/dependencies/README.md @@ -40,14 +40,18 @@ manifest, geometry, source revisions, generated-file hashes, and TT/SS views before materializing it below `.cache/retrosoc/pdk/sky130/openram/`. Generated Verilog, Liberty, LEF, GDS, and SPICE views are never committed here. -The HP profile additionally locks VexiiRiscv, OpenSBI, Linux stable, and -Buildroot source revisions and the SBT launcher used by VexiiRiscv generation. -`make setup-hp-linux` installs the software sources below -`.cache/retrosoc/sources/`; VexiiRiscv may be supplied through -`VEXIIRISCV_ROOT`, but its revision is still checked before generated RTL is -accepted. Java 17 is a host runtime supplied by Docker, Nix, or the documented -Ubuntu prerequisites. No generated CPU RTL or Linux build output belongs in -Git. +The HP profile locks the OpenC906 source (`sources.openc906`, Apache-2.0) below +`.cache/retrosoc/sources/openc906`; `make setup-openc906` installs it and +`make openc906-prepare` emits the build-variant `openc906.fl` filelist with the +reviewed hart-ID override substituted (the locked checkout is never modified). +OpenSBI, Linux stable, and Buildroot source revisions are locked for HP payload +builds. `make setup-hp-linux` installs the software sources below +`.cache/retrosoc/sources/`. VexiiRiscv remains locked as a Std-series asset: it +may be supplied through `VEXIIRISCV_ROOT`, its revision is still checked before +generated RTL is accepted, and `make std-vexii-generate` invokes the SBT +launcher for `GenerateRetroSocStd.scala`. Java 17 is a host runtime supplied +by Docker, Nix, or the documented Ubuntu prerequisites. No generated CPU RTL or +Linux build output belongs in Git. `rtthread_hp` pins official RT-Thread v5.3.0 at `99428a1e7f7447955aa860f7c969273a12095b8f`. `make setup-hp-rtthread` installs diff --git a/dependencies/dependencies.lock.json b/dependencies/dependencies.lock.json index 0997b658..29b7957f 100644 --- a/dependencies/dependencies.lock.json +++ b/dependencies/dependencies.lock.json @@ -25,7 +25,15 @@ "revision": "ef7da4134ff11ec6a681d0632123b232b853b046", "destination": ".cache/retrosoc/sources/vexiiriscv", "recursive": true, - "license": "MIT" + "license": "MIT", + "purpose": "Std series performance-core generator source (Std asset; no longer consumed by Mini)" + }, + "openc906": { + "url": "https://github.com/XUANTIE-RV/openc906.git", + "revision": "b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f", + "destination": ".cache/retrosoc/sources/openc906", + "license": "Apache-2.0", + "purpose": "Mini HP core: pre-generated openC906 RTL (C906_RTL_FACTORY/gen_rtl), default configuration" }, "rtthread_hp": { "url": "https://github.com/RT-Thread/rt-thread.git", diff --git a/docs/README.md b/docs/README.md index 599ffaec..e8ba994a 100644 --- a/docs/README.md +++ b/docs/README.md @@ -120,8 +120,9 @@ the root README and subsystem guides. counting modes, interrupt, debug-freeze, HAL, and verification contracts. - [ip/sysctrl.md](ip/sysctrl.md) defines the SystemCtrl compatibility, clock/pad/fault/performance/RTC/test contracts, HAL, and verification. -- [ip/hp-platform.md](ip/hp-platform.md) defines the experimental HP PLIC and - LP/HP mailbox register, interrupt, software, and verification contracts. +- [ip/hp-platform.md](ip/hp-platform.md) defines the HP OpenC906 platform, the + C906 internal CLINT/PLIC interrupt architecture, and the LP/HP mailbox + register, software, and verification contracts. - [hp-rv64-validation.md](hp-rv64-validation.md) records RV64 core, V2 bundle, RT-Thread/Linux acceptance evidence and deferred gates. - [ip/onchip-sram.md](ip/onchip-sram.md) defines the configurable native-AXI4 diff --git a/docs/axi4-interconnect.md b/docs/axi4-interconnect.md index 903fe866..63ad2b82 100644 --- a/docs/axi4-interconnect.md +++ b/docs/axi4-interconnect.md @@ -30,19 +30,24 @@ master. Requests to one target use Common round-robin arbitration and retain ownership through `B` or `RLAST`. Misaligned, unsupported, cross-page, and cross-target transactions return `SLVERR`; unmapped addresses return `DECERR`. -Hazard3 accesses APB4 registers through LP-to-PCLK async-safe bridges. HP MMIO -is downsized and crosses HP-to-LP. Product access policy prevents the HP MMIO -master from writing SYSCTRL/RCU, watchdog, and GPIO administration windows. +Hazard3 accesses APB4 registers through LP-to-PCLK async-safe bridges. The HP +core's single 128-bit AXI4 master is serialized by `axi4_downsizer_128to64` +and split by `axi4_mmio_demux`: the `0x02000000-0x2FFFFFFF` window enters the +MMIO chain, where it is downsized and crosses HP-to-LP, while every other +address reaches HP data-plane master slot 0. Product access policy prevents +the HP MMIO master from writing SYSCTRL/RCU, watchdog, and GPIO +administration windows. ## HP data plane The native payload fabric is AXI64 with 32-bit addresses and seven-bit global -IDs. It has nine masters: +IDs. It has nine active masters over ten fixed slots (slot 1 is retired and +tied idle; the ID-prefix map is preserved): | Index | Master | Adaptation | | ---: | --- | --- | -| 0 | Vexii I-cache | native AXI64, source ID preserved | -| 1 | Vexii D-cache | native AXI64, source ID preserved | +| 0 | HP core (OpenC906) | single 128-bit AXI4 master serialized by `axi4_downsizer_128to64`, source ID preserved; four read credits and two write credits (the retired data port's write credits) | +| 1 | retired HP D-cache slot | tied idle | | 2 | central DMA | PCLK-to-HP CDC, AXI32-to-64 | | 3 | I/O gateway A | USB2 and SDIO0, PCLK-to-HP CDC, AXI32-to-64 | | 4 | I/O gateway B | SDIO1 and SPI-SD, PCLK-to-HP CDC, AXI32-to-64 | @@ -73,8 +78,7 @@ the integration RTL: | Master | Read targets | Write targets | Instruction | Attribute rule | | --- | --- | --- | --- | --- | -| HP I-cache | all five memories | none | allowed | cache attributes preserved | -| HP D-cache | all five memories | SRAM, SDRAM, QPI, OPI | denied | cache attributes preserved | +| HP core | all five memories | SRAM, SDRAM, QPI, OPI | allowed | cache attributes preserved | | DMA, I/O A/B, LP gateway | all five memories | SRAM, SDRAM, QPI, OPI | denied | `AxCACHE=0` required | | GA2D | all five memories | SRAM, SDRAM, QPI, OPI | denied | `AxCACHE=0` required; direct FILL/COPY/CONVERT/BLEND 2D engine, no hardware coherency | | JPEG | all five memories | SRAM, SDRAM, QPI, OPI | denied | `AxCACHE=0` required; one normal read and one normal write credit | @@ -86,7 +90,7 @@ and records the immutable master identity and original decoded target. Per-target arbitration first selects the highest effective five-bit priority and then uses the Common round-robin arbiter among equal requesters. Normal -classes are HP I/D 12, I/O gateways 10, DMA/JPEG/EXT-H/GA2D 8, and LP gateway 2, with +classes are HP core 12, I/O gateways 10, DMA/JPEG/EXT-H/GA2D 8, and LP gateway 2, with incoming AXI QoS able to raise a normal request up to 15. A continuously eligible request is promoted to 16 after 256 cycles. During recovery, the LP gateway is promoted to 31. Target backpressure is outside the service bound; diff --git a/docs/commercial-soc-alignment.md b/docs/commercial-soc-alignment.md index 2ea8020b..95421c5d 100644 --- a/docs/commercial-soc-alignment.md +++ b/docs/commercial-soc-alignment.md @@ -20,8 +20,9 @@ ecosystem of the referenced devices. Official sources were rechecked on ## Technical Selection Mini remains a small, non-coherent, performance-first SoC. Hazard3 is the -only root-management master. Vexii I/D, DMA, I/O gateways, the LP data gateway, EXT-H, and GA2D use a -nine-master native AXI64 data plane with seven-bit global IDs. GA2D is a +only root-management master. The OpenC906 HP core master, DMA, I/O gateways, +the LP data gateway, JPEG, EXT-H, and GA2D share a +nine-active-master native AXI64 data plane with seven-bit global IDs. GA2D is a dedicated PCLK-to-HP AXI64/ID3 bridge carrying direct, single-job private-AXI64 2D FILL/COPY/CONVERT/BLEND traffic; `APB4_GA2D` remains its separate PCLK control plane and resource-owned IRQ route. It supports RGB565, RGB888, diff --git a/docs/hazard3-debug.md b/docs/hazard3-debug.md index fea36d36..e9653390 100644 --- a/docs/hazard3-debug.md +++ b/docs/hazard3-debug.md @@ -13,7 +13,9 @@ a second SoC bus master. Debugger memory operations execute through the halted hart and remain subject to the AXI4 interconnect access policy. MPW user cores, peripherals, clocks, and pad control stay outside the debug-reset scope. -The product Vexii HP hart can own shared JTAG only while held in reset. C0-C3 +The product OpenC906 HP hart can own shared JTAG only while held in reset; HP +debug uses the C906 internal Debug Module behind the external JTAG DTM +(`tdt_dmi_top`). C0-C3 are software-selected only in the mini-ver-mpw compatibility profile; they are not management-core options and do not have a management Debug Module. diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index b809cb1b..bfb41ab2 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -1,10 +1,65 @@ # HP RV64 Migration Validation -The active contract is [HP platform](ip/hp-platform.md), phases 2–5. LP remains -RV32 Hazard3. All PRODUCT profiles select RV64IMAFDC with Zicbom, Sv39 and -32-bit physical addresses. No upstream CPU or RT-Thread source is modified. +The active contract is [HP platform](ip/hp-platform.md). LP remains RV32 +Hazard3 (hart 0); HP is the locked, pre-generated T-Head OpenC906 (hart 1, +RV64GC with Zicsr/Zifencei, M/S/U modes, Sv39, 32-bit SoC physical +addresses). No upstream CPU or RT-Thread source is modified. -## Reproduction +## Current status after the OpenC906 core swap + +All simulation evidence below was gathered with the previous generated +VexiiRiscv HP core and is historical: it must not be presented as OpenC906 +qualification. Current evidence requires, at minimum: + +- `make setup-openc906` (part of `make setup`) restoring the locked + [openc906](https://github.com/XUANTIE-RV/openc906) checkout, and + `make openc906-prepare` emitting + `build//generated/openc906/openc906.fl` and its manifest under the + pinned upstream sha256 guard, with the reviewed + `rtl/mini/ip_overrides/aq_sysio_kid.v` hart-ID override applied by filelist + generation rather than by editing the vendored checkout. +- Verilator compile of the OpenC906 HP subsystem, including the serializing + `axi4_downsizer_128to64` and `axi4_mmio_demux` path. +- Fresh `hp-smoke-sim`, `hp-rtthread-sim`, and `hp-linux-sim` runs from their + committed IHP130 profiles with all contract markers and + `SIM_TEST_PASS code=0`, exercising the internal C906 CLINT/PLIC and the + `time`-CSR mtime delivery. +- The IHP130 behavioral PR regression on the swapped design. + +### OpenC906 evidence gathered (2026-10-10) + +- `hp-smoke-sim` on `configs/ci/ihp130-hp.mk` (Verilator): `HP_LINUX_READY`, + `HP_GA2D_PASS`, `HP_GA2D_CACHE_CLEAN`, `SIM_TEST_PASS code=0`; + 3,629,906 cycles in 285 s. This exercises C906 boot at 0x38000000, the + 128-to-64 downsizer and MMIO demux, the mailbox protocol, the GA2D engine + through the HP data path, and the T-Head `dcache.cva`/`dcache.iva` cache + lifecycle handshake. +- Focused `hp_c906_boot_tb` (pytest `test_hp_platform.py`): the real smoke + payload runs on `hp_core_wrapper` plus the production MMIO chain + (64-to-32 downsizer, address gate, HP-to-LP CDC bridge) and completes the + full mailbox/GA2D-phase protocol. +- The swap exposed and fixed a latent integration bug: the merged HP port + initially inherited the read-only I-cache slot's zero write credits in the + data crossbar; `axi4_data_crossbar.sv` now grants the HP slot two write + credits, locked by a new write/readback case in `ga2d_platform_tb`. +- The sysmap override is required for correctness: the upstream default marks + the Mini MMIO window cacheable/bufferable, which absorbs device writes in + the C906 store buffer; `rtl/mini/ip_overrides/sysmap.h` marks the MMIO and + core-internal CLINT/PLIC windows strong-order non-cacheable per the user + manual. + +`hp-rtthread-sim`, `hp-linux-sim`, and the synthesis-dependent gates remain +unrun this round (synthesis waits for the SRAM macro swap); they stay required +evidence for qualification. + +Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT +(scan/mbist tied off), the debug SBA AXI master (unconnected), ASIC +memory-macro replacement for the behavioral FPGA SRAM models, and HP Linux +re-qualification timing/performance evidence. + +## Historical VexiiRiscv evidence (pre-swap) + +### Reproduction (VexiiRiscv) ```sh make setup-vexiiriscv setup-hp-rtthread setup-hp-linux @@ -38,7 +93,7 @@ The `ihp130-apu` evidence profile likewise uses workload 1 only as the existing four-entry transport. Its application-specific `apu_release` LP loader owns the APU acceptance semantics; that bundle label does not claim a Linux boot result. -## Measured runs +### Measured runs (VexiiRiscv) Initial RV64 validation uses `configs/ci/ihp130-hp.mk` and `BUILD_TIMESTAMP=2026-09-25-11-42`, producing @@ -86,7 +141,7 @@ The IHP130 behavioral PR regression completed successfully with new/increased signatures as non-blocking observations; baselines were not modified. No synthesis or STA result is implied by this regression. -## RT-Thread first-schedule failure and correction +### RT-Thread first-schedule failure and correction The first BSP run reached `HP_RTTHREAD_BOOT` and then reported `RTTHREAD_TRAP cause=1 epc=deadbeee`, failure 92, followed by LP failure 18. @@ -106,7 +161,7 @@ the initial variant. This was a BSP integration error: bound. The same integrated test then passed scheduling, RV64 context, IPC, timer timeout, and mailbox IRQ checks. Vendor source stayed unchanged. -## Linux firmware reservation correction +### Linux firmware reservation correction The first RV64 run reached Linux 6.12.105 and memory initialization. Its log reported no `/reserved-memory` node and included the full SDRAM range beginning @@ -146,7 +201,7 @@ RISC-V `pt_regs` layout. UART subsequently reported the 9-bit ASID allocator. These observations avoid treating an IRQ-handler PC or stale raw SDRAM as evidence of main-thread progress. -## Coverage limits +### Coverage limits The repository's mechanical C format/policy checks are partial MISRA evidence; no complete MISRA certification or new approved Required-rule deviation is diff --git a/docs/ip/apu.md b/docs/ip/apu.md index 1f432187..ed82525b 100644 --- a/docs/ip/apu.md +++ b/docs/ip/apu.md @@ -39,7 +39,7 @@ This refreeze is a future implementation contract, not a synthesis/PPA result. The APU is deliberately coreless. LP loads one validated codec-microcode bundle at startup and HP or LP later submits jobs. The APU contains a bounded codec -sequencer and fixed processing engines; it does not contain Hazard3, VexiiRiscv, +sequencer and fixed processing engines; it does not contain Hazard3, OpenC906, a DSP CPU, a general-purpose instruction set, or a C runtime. The design was frozen on 2026-09-02 from these repository sources of truth: @@ -2673,7 +2673,7 @@ measured evidence. Inferred memories may be padded/duplicated by elaboration; the 462208 logical table bits above are not interchangeable with that tool statistic. Removing the two reported groups would arithmetically leave 568626 bits (about 70.1 percent lower), but that is a projection, not a synthesis -speed, RSS or measured memory claim. Vexii and other IP memories are outside +speed, RSS or measured memory claim. OpenC906 and other IP memories are outside P9 scope. Fresh like-for-like reports below are required. Stable requirements: diff --git a/docs/ip/clint.md b/docs/ip/clint.md index fb359f7b..09f888fe 100644 --- a/docs/ip/clint.md +++ b/docs/ip/clint.md @@ -1,12 +1,17 @@ # Core-Local Interruptor The baseline Mini SoC CLINT provides machine software and machine timer -interrupts for the management hart. The HP profile adds an independent -two-slot instance at `0x02000000` and connects slot 1 to HP hart 1. Its register -layout follows the conventional SiFive +interrupts for the management hart and owns the global `mtime` source. Its +register layout follows the conventional SiFive CLINT and RISC-V ACLINT-compatible offsets, while its bus-facing logic uses the retroSoC APB4 target protocol. +With the OpenC906 HP core, the former HP ACLINT instance at `0x02000000` is +removed: the C906 uses its internal CLINT/PLIC (T-Head c900 layouts, decoded +inside the core BIU below `0x08000000`), and this CLINT's `mtime` is delivered +to the C906 through `pad_cpu_sys_cnt` and read by HP software through the +`time` CSR. There is no HP memory-mapped `mtime`. + ## Integration | Property | Value | @@ -20,9 +25,9 @@ retroSoC APB4 target protocol. | User-core access | denied by the AXI4 interconnect access policy | | User-core interrupt visibility | masked | -The HP instance uses the same 1 MHz reference timebase. OpenSBI programs hart -1 `MSIP` at `0x02000004`, `MTIMECMP` at `0x02004008`, and shared `MTIME` at -`0x0200BFF8`. The baseline management CLINT remains at `0x10020000`. +The CLINT drives the global 1 MHz reference timebase. Its `mtime` is exported +to the HP subsystem (`pad_cpu_sys_cnt`) so the OpenC906 `time` CSR tracks the +same counter. The baseline management CLINT remains at `0x10020000`. The timebase divider runs from the buffered external reference clock, not the PLL-selected system clock. A toggle crosses into the system domain through the diff --git a/docs/ip/crypto-verification.md b/docs/ip/crypto-verification.md index b7c08693..c52db7a2 100644 --- a/docs/ip/crypto-verification.md +++ b/docs/ip/crypto-verification.md @@ -25,7 +25,7 @@ response after retirement, a stale response after an epoch change, and a missing response. Engine transactions carry both an operation epoch and a per-bank transaction token; write retirements are never consumed as read responses. The default product store remains fixed-latency with no fault -injection. Generated VexiiRiscv output, its manifest, and the selected +injection. The generated OpenC906 filelist, its manifest, and the selected IHP SRAM behavioral models are included in each firmware run's source hash. The interruption argument combines universal control properties with bounded diff --git a/docs/ip/crypto.md b/docs/ip/crypto.md index 523ca2f4..7b22b165 100644 --- a/docs/ip/crypto.md +++ b/docs/ip/crypto.md @@ -257,7 +257,7 @@ are permitted and are not hardware ROM implementations. AEAD/HMAC, new key sizes, CRT, masking/blinding, HUK/key ladders, Linux crypto drivers, private DMA, ECC/MBIST/secure scan and side-channel certification remain -deferred. Vexii and APU storage are outside this refreeze. +deferred. OpenC906 and APU storage are outside this refreeze. ### Physical layout and implementation boundary @@ -818,7 +818,8 @@ python3 scripts/crypto_p1.py quality --variant-root build/ For the CI manifest use `APP=ci_smoke HAVE_CSR=YES`, the existing `ld2_all_sram`, `SIMU=VERILATOR` and `HAVE_SVA=YES` overrides. The firmware runner records its complete build/simulation command, per-run manifest, input -hashes including generated VexiiRiscv and selected PDK model inputs, ELF/log/ +hashes including the generated OpenC906 filelist/manifest and selected PDK +model inputs, ELF/log/ result hashes and command exit status. The report rejects missing, changed or unsuccessful runs. These helpers do not invoke Pytest. diff --git a/docs/ip/ga2d.md b/docs/ip/ga2d.md index 4fbc7c63..b62b48bc 100644 --- a/docs/ip/ga2d.md +++ b/docs/ip/ga2d.md @@ -65,7 +65,8 @@ Confirmed baseline facts: 4. Central DMA implements a 32-bit, one-dimensional transfer contract. GA2D does not add channels or request selectors to that controller. 5. Mini has no hardware cache coherency. Ownership, fences, and the HP - 64-byte Zicbom cache-maintenance contract remain software obligations. + 64-byte cache-maintenance contract (OpenC906 custom-0 + `dcache.cva`/`dcache.iva` instructions) remain software obligations. Phase 1 approves expansion of the LP interrupt platform. Phase 2 approves the ninth data master, wider global IDs, and resource/observability changes. diff --git a/docs/ip/hp-platform.md b/docs/ip/hp-platform.md index 2c9b011d..fa6fe41a 100644 --- a/docs/ip/hp-platform.md +++ b/docs/ip/hp-platform.md @@ -4,16 +4,52 @@ The RV64 migration approved on 2026-09-25 extends the existing HP platform in the phases below. These are requirements, not claims of completed validation. -LP remains the RV32 Hazard3 management hart (hart 0). HP is VexiiRiscv hart 1, -RV64IMAFDC_Zicbom_Zicntr_Zihpm, with M/S/U modes and Sv39. Physical addresses -remain 32 bits; the reset vector remains `0x38000000`. The existing 16 KiB -four-way I/D caches, 64-byte lines, 9-bit ASIDs, PMP, and clocks remain fixed. -I/D and cacheless MMIO use AXI64 at HP; MMIO is downsized to the existing -AXI32/APB32 control plane. Software accesses peripheral registers as 32-bit -words, including the two halves of CLINT timer registers. No new CDC or +LP remains the RV32 Hazard3 management hart (hart 0). HP is hart 1, a T-Head +OpenC906 core from [XUANTIE-RV/openc906](https://github.com/XUANTIE-RV/openc906) +(Apache-2.0), locked in `dependencies/dependencies.lock.json` and integrated +from its pre-generated `C906_RTL_FACTORY/gen_rtl` DEFAULT configuration: +RV64GC (RV64IMAFDC plus Zicsr and Zifencei) with M/S/U modes and Sv39, +32 KiB instruction and data caches with 64-byte lines, an eight-region PMP, +and a 16K-entry BHT. The earlier VexiiRiscv-based RV64 integration is +superseded; its validation evidence is retained only as historical in +[HP RV64 validation](../hp-rv64-validation.md). VexiiRiscv remains in the +repository solely as the frozen Std-series generator asset +(`scripts/vexiiriscv/GenerateRetroSocStd.scala`, driven by +`make std-vexii-generate`); Mini no longer consumes it and Mini profiles have +no `HP_CONFIG` selector. + +The C906 drives 40-bit addresses; Mini physical addresses remain 32 bits and +the reset vector remains `0x38000000`. The core exposes a single 128-bit AXI4 +master (8-bit IDs, `axim_clk_en` tied high for 1:1 clocking) that a +serializing `axi4_downsizer_128to64` and `axi4_mmio_demux` split into HP +data-fabric master slot 0 and the MMIO window `0x02000000-0x2FFFFFFF`; the +former separate I-cache/D-cache/MMIO port structure and crossbar master slot 1 +are retired (slot 1 is tied idle, ID-prefix map preserved). MMIO continues +through the existing 64-to-32 downsizer/gate/CDC chain into the AXI32/APB32 +control plane. Software accesses peripheral registers as 32-bit words, +including the two halves of CLINT timer registers. No new CDC or hardware coherency is introduced. LP retains SYSCTRL and terminal-status ownership, DMA channel 6, SDRAM initialization, and HP release control. +OpenC906 implements no Zicbom, Zicntr, or Zihpm; cache maintenance uses the +T-Head custom-0 `dcache.cva`/`dcache.iva` instructions. Debug uses the C906 +internal Debug Module behind the external JTAG DTM (`tdt_dmi_top`). +OpenC906 hardwires `mhartid=0` upstream; retroSoC substitutes the reviewed +override `rtl/mini/ip_overrides/aq_sysio_kid.v` (only change: +`sysio_core_hartid = 3'd1`) during build-time filelist generation through +`scripts/generate_openc906.py`, which guards the pinned upstream sha256. A +second reviewed override, `rtl/mini/ip_overrides/sysmap.h`, replaces the +upstream default sysmap region table (which targets a 40-bit reference map +and would mark the Mini peripheral window cacheable/bufferable) with the Mini +address map: the MMIO window `0x02000000`-`0x2FFFFFFF` — including the +core-internal CLINT/PLIC window — is strong-order/non-cacheable device memory +as the OpenC906 user manual requires; SRAM/SDRAM/PSRAM/OPI and the flash/XIP +windows stay cacheable. The vendored checkout is never modified. Deferred +this phase: low-power support +(`core0_pad_lpmd_b` unconnected), DFT (scan/mbist tied off), the debug SBA AXI +master (unconnected), ASIC memory-macro replacement for the behavioral FPGA +SRAM models, and HP Linux re-qualification timing/performance evidence. + ### Boot bundle V2 The little-endian header remains 128 bytes at flash offset `0x00100000`, with @@ -35,7 +71,8 @@ with a nonzero error code. LP prints `HP_LINUX_READY` and terminates on Linux success without entering the GA2D protocol. RT-Thread publishes ready event 1, argument `0x52545401`, sequence 1 after -enabling PLIC source 2 in machine context 0. LP sends command `0x52545402`, +enabling the mailbox-doorbell PLIC ID (18) in the machine context. LP sends +command `0x52545402`, argument `0x12345678`, sequence 1. Its ISR clears the HP mailbox source and completes the PLIC claim; the test thread verifies the received message. Once all tests pass, HP publishes event 2, argument `0x52545401`, sequence 2. @@ -48,7 +85,8 @@ handshake documented by its existing payload. RT-Thread uses the official v5.3.0 commit `99428a1e7f7447955aa860f7c969273a12095b8f` without vendor source modifications. The BSP uses the common RISC-V M-mode port, static threads and IPC objects, -1000 Hz ticks, UART1, hart-1 MSIP/MTIMECMP, and the existing PLIC/mailbox. +1000 Hz ticks, UART1, the internal CLINT MSIP/MTIMECMP pair, and the internal +PLIC plus the mailbox. The first test image covers integer RV64 computation/context, preemption, semaphore and message queue behavior, timeouts, and external mailbox IRQ. RT-Smart, networking, filesystems, and floating-point task qualification are @@ -68,10 +106,13 @@ uncompressed and does not run the full Buildroot services sequence. #### Phase 2 - RV64 HP core and platform migration -Migrate the fixed generator, all PRODUCT profiles, manifests and core reports; -retain the locked VexiiRiscv revision. Use separate RV32 LP and RV64 HP tools. -Validate generated port widths, narrow MMIO lanes, 64-bit memory accesses, -and the migrated GA2D/cache-lifecycle smoke in IHP130 Verilator. +Originally executed against a generated VexiiRiscv core; that integration is +superseded by the OpenC906 swap and its evidence is historical. The current +phase integrates the locked OpenC906 DEFAULT configuration, all PRODUCT +profiles, manifests and core reports. Use separate RV32 LP and RV64 HP tools. +Validate the 128-to-64 serializing downsizer, the MMIO demux, narrow MMIO +lanes, 64-bit memory accesses, and the migrated GA2D/cache-lifecycle smoke in +IHP130 Verilator. #### Phase 3 - RT-Thread dependency, BSP and acceptance @@ -90,7 +131,8 @@ Unexpected console corruption remains a failure requiring diagnosis. #### Phase 5 - Documentation and delivery evidence Update architecture, guides and publication source bindings. Preserve prior -RV32 evidence as historical. Each workload writes separate run logs and +RV32 and pre-swap VexiiRiscv evidence as historical. Each workload writes +separate run logs and structured results; an interrupted or ongoing run cannot reuse an old pass. Run affected host/Python/C/RTL checks and IHP130 behavioral regressions. Synthesis, netlist simulation, STA, and synthesis-dependent metrics are @@ -98,39 +140,43 @@ explicitly deferred by user instruction, as are SRAM macro replacement, CDC/RDC/physical signoff and commercial qualification. No PPA claim is made. Reference boundaries: [RT-Thread v5.3.0](https://github.com/RT-Thread/rt-thread/releases/tag/v5.3.0) -supplies the OS/CPU port; the repository owns board integration. The existing -CLINT/PLIC architecture and locked OpenSBI platform supply the interrupt and -supervisor boot patterns; no third-party board register map is imported. +supplies the OS/CPU port; the repository owns board integration. The C906 +internal CLINT/PLIC (the `thead,c900-clint`/`thead,c900-plic` device-tree +bindings) and the locked OpenSBI platform supply the interrupt and supervisor +boot patterns; no third-party board register map is imported. -The experimental LP/HP profile adds a 32-source, two-context PLIC at -`0x0C000000` and a bidirectional mailbox at `0x10019000`. Both are self-owned -APB4 peripherals. Their role in boot and lifecycle control is defined by -[LP/HP Architecture](../lp-hp-architecture.md). +The LP/HP profile adds a bidirectional mailbox at `0x10019000` as a +self-owned APB4 peripheral. Its role in boot and lifecycle control is defined +by [LP/HP Architecture](../lp-hp-architecture.md). -## PLIC +## Interrupt and timer architecture -Source 0 is permanently reserved. Source 1 is UART1, source 2 is the HP-side -mailbox doorbell, source 3 is EXT-H, and sources 4 through 10 are central DMA, -USB2, SDIO0, SDIO1, SPI-SD, JPEG, and APU respectively. Source 11 is GA2D and -source 12 is the NPU shell. Sources 13 through 31 -are reserved and tied low. Resource-owned sources are suppressed unless HP is -the exclusive owner. Each source has a three-bit priority. Context 0 drives HP -machine external interrupt and context 1 drives HP supervisor external interrupt. +The former SoC-level HP ACLINT at `0x02000000` and HP PLIC at `0x0C000000` +are removed from the HP path; their self-owned RTL sources remain in the +repository but are no longer instantiated. Interrupt and timer delivery now +uses the CLINT and PLIC internal to the C906, which follow the T-Head c900 +register layouts and are decoded inside the core BIU at the 128 MiB-aligned +window base `0x08000000`. That window never reaches the SoC fabric; +`rtl/mini/address_map/memory_map.json` reserves it as `HP_C906_SYS`: -| Address offset | Register | Access | -| --- | --- | --- | -| `0x000000 + 4 * source` | source priority | RW | -| `0x001000` | pending bits 31:0 | RO | -| `0x002000 + 0x80 * context` | enable bits 31:0 | RW | -| `0x200000 + 0x1000 * context` | threshold | RW | -| `0x200004 + 0x1000 * context` | claim/complete | RO/RW | +| Address | Function | +| --- | --- | +| `0x08000000` | internal PLIC (`thead,c900-plic`) | +| `0x0C000000` | internal CLINT (`thead,c900-clint`): MSIP at +`0x0`, MTIMECMP at +`0x4000`, SSIP at +`0xC000`, STIMECMP at +`0xD000` | -Claim returns the lowest source ID at the greatest priority strictly above the -context threshold, clears its pending bit, and marks it claimed. Writing that -nonzero ID to the same context's claim/complete register completes it. A level -source that remains asserted becomes pending again after completion. Priority -zero disables delivery. The MVP implements one 32-bit pending/enable word and -does not implement MSI, AIA, virtualization, or affinity routing. +The CLINT at `0x10020000` remains the LP/global CLINT and the mtime source. +Its mtime is delivered to the C906 through `pad_cpu_sys_cnt`; HP software +reads the `time` CSR and has no memory-mapped mtime. + +SoC interrupt source numbers are unchanged at the boundary: source 1 is +UART1, source 2 is the HP-side mailbox doorbell, source 3 is EXT-H, and +sources 4 through 12 are central DMA, USB2, SDIO0, SDIO1, SPI-SD, JPEG, APU, +GA2D, and the NPU shell respectively. Sources 13 and above are reserved and +tied low. Resource-owned sources are suppressed unless HP is the exclusive +owner. The C906 maps external input *i* to PLIC ID *i*+16, so software claims +these sources as PLIC IDs 17 through 28; IDs 0-15 are reserved/internal. +LP-to-HP notification is exclusively the mailbox doorbell (PLIC ID 18); the +former LP-writes-HP-MSIP path no longer exists. ## Mailbox @@ -160,8 +206,9 @@ Linux userspace acceptance script reports event 1, argument `0x4C4E5801`, and sequence 1 after init; this is a bring-up verdict, not a general Linux mailbox driver ABI. -`tests/rtl/plic_tb.sv` and `tests/rtl/hp_mailbox_tb.sv` cover register and -interrupt behavior. `tests/test_hp_boot_bundle.py` enforces the handwritten -mailbox RTL/C offset parity. Production work still requires a Linux mailbox -driver, concurrent sequence/wrap policy, malformed-message tests, lifecycle -timeouts, and fault-injection coverage. +`tests/rtl/hp_mailbox_tb.sv` covers mailbox register and interrupt behavior. +`tests/rtl/plic_tb.sv` covers the retained self-owned PLIC RTL, which is no +longer part of the HP interrupt path. `tests/test_hp_boot_bundle.py` enforces +the handwritten mailbox RTL/C offset parity. Production work still requires a +Linux mailbox driver, concurrent sequence/wrap policy, malformed-message +tests, lifecycle timeouts, and fault-injection coverage. diff --git a/docs/ip/npu-verification.md b/docs/ip/npu-verification.md index fe23599c..6cf8de6b 100644 --- a/docs/ip/npu-verification.md +++ b/docs/ip/npu-verification.md @@ -154,7 +154,8 @@ simulation and the applicable bounded formal harness: The reference is the pinned portable-C INT8 implementation running beside the NPU path on the same complete PRODUCT Verilator model of the 72 MHz HP -VexiiRiscv configuration, with the same model, corpus, memory placement and +core configuration (OpenC906 after the 2026-10-09 core swap), with the same +model, corpus, memory placement and declared cache policy. Both paths include the inference result through CPU softmax; the NPU path additionally includes command submission, DMA transfers, synchronization and wait. Preprocessing and corpus transport are measured @@ -173,7 +174,8 @@ replacement would change the measured denominator and requires an explicit verification-contract refreeze before implementation. The stage-instrumented Mini IHP130 diagnostic run at root revision -`d084002bfe99`, using `configs/ci/ihp130.mk` and the locked VexiiRiscv revision, +`d084002bfe99`, using `configs/ci/ihp130.mk` and the then-current locked +VexiiRiscv revision (pre-OpenC906-swap evidence), entered `reference-start` for both a contention KWS shard and a non-contention KWS shard, but did not reach `reference-compute-done` within the bounded host run. This establishes a portable-C reference runtime/evidence gap, not an NPU @@ -347,7 +349,8 @@ The LP `ci_smoke` run used real external-interrupt entry and acknowledgement, completed the KWS job and terminal CPU Softmax, and ended with `SIM_TEST_PASS code=0`. Its retained counters were 5765715 active cycles, 320326 DMA read bytes, 72076 DMA write bytes and 59530 CPU Softmax cycles. The -HP run used polling plus Zicbom maintenance, completed the same KWS deployment, +HP run (pre-OpenC906-swap, VexiiRiscv evidence) used polling plus Zicbom +maintenance, completed the same KWS deployment, passed the concurrent GA2D/resource hand-off checks and ended with `HP_NPU_PASS` and `SIM_TEST_PASS code=0`. diff --git a/docs/ip/npu.md b/docs/ip/npu.md index 719389b7..548df7c4 100644 --- a/docs/ip/npu.md +++ b/docs/ip/npu.md @@ -291,7 +291,7 @@ integration advertises no execution readiness, DMA, or operator capability. | HP IRQ | PLIC source 12 | The peripheral IRQ group expands 25 to 26 bits; the existing 64-bit LP vector -and 32-source PLIC container need no width increase. Preserve the separate +and the HP PLIC input container need no width increase. Preserve the separate MPW compatibility path and all existing harts, resources and interrupts. Phase 2 MUST update topology generator names/policies, hardcoded master credit/priority functions, 9x6 assertions, resource vectors, monitor banks, @@ -649,7 +649,7 @@ Software serializes one submitter and acquires resource ownership before use. Before START it cleans input/constants/descriptors and cleans/invalidates output lines as applicable, then fences. After terminal successful output completion it invalidates output and fences before CPU access. Use the -existing 64-byte HP Zicbom boundary and avoid sharing cache lines with +existing 64-byte HP cache-line boundary and avoid sharing cache lines with unrelated allocations. LP still executes ordering fences despite no D-cache. Cache ownership of an active NPU job remains the application's responsibility during HP lifecycle operations; automatic coherence is not implied. diff --git a/docs/ip/resource-controller.md b/docs/ip/resource-controller.md index fa51c2f3..617099e5 100644 --- a/docs/ip/resource-controller.md +++ b/docs/ip/resource-controller.md @@ -87,17 +87,20 @@ resource-8 idle and ACK with the live source-safe-idle signal. ## Cache Maintenance -VexiiRiscv implements `Zicbom` with a 64-byte CBO block. On HP shutdown the AON +VexiiRiscv-era note: the pre-swap HP core implemented `Zicbom` with a 64-byte +CBO block; OpenC906 instead uses 64-byte cache lines with the T-Head custom-0 +`dcache.cva`/`dcache.iva` maintenance instructions. On HP shutdown the AON lifecycle controller first asserts the Resource Controller cache request while HP remains released and its MMIO path remains open. Software cleans and -invalidates shared ranges with CBO operations, reports completion to LP, and LP +invalidates shared ranges with those instructions, reports completion to LP, +and LP writes `CACHE_CONTROL.CLEAN`. AON then blocks new addresses and drains the data plane. Missing acknowledgement is bounded by the lifecycle timeout and records a forced fault before reset proceeds. This handshake provides an execution window and explicit evidence point; it -does not create hardware coherency. Buffer ownership, fences, CBO range policy, -and a Linux platform driver remain software responsibilities. +does not create hardware coherency. Buffer ownership, fences, maintenance +range policy, and a Linux platform driver remain software responsibilities. ## Delivery Boundary diff --git a/docs/lp-hp-architecture.md b/docs/lp-hp-architecture.md index 4585bfec..e01c0968 100644 --- a/docs/lp-hp-architecture.md +++ b/docs/lp-hp-architecture.md @@ -19,9 +19,9 @@ Every committed `MINI_MODE=PRODUCT` profile instantiates two fixed harts: | Property | LP management | HP application | | --- | --- | --- | -| Core | Hazard3 | generated VexiiRiscv | +| Core | Hazard3 | T-Head OpenC906 (locked pre-generated DEFAULT configuration) | | Hart ID | 0 | 1 | -| ISA | profile RV32I/RV32IM | RV64IMAFDC + Zicbom, S/U mode, Sv39 | +| ISA | profile RV32I/RV32IM | RV64GC (RV64IMAFDC + Zicsr/Zifencei), S/U mode, Sv39 | | Reset clock | REF24 at 24 MHz | external 72 MHz safe clock | | Role | boot, control, diagnostics, recovery | high-throughput application/Linux | | JTAG | reset owner | selectable while HP is held in reset | @@ -34,6 +34,19 @@ product address, interrupt, or lifecycle ABI. There is no hardware cache coherency. Firmware and operating systems must use explicit ownership, fences, and cache maintenance for shared buffers. +HP interrupt and timer delivery uses the CLINT and PLIC internal to the C906 +(T-Head c900 register layouts), decoded inside the core BIU below the +128 MiB-aligned base `0x08000000`; that window never reaches the SoC fabric +and is reserved as `HP_C906_SYS` in the address map. The former SoC-level HP +ACLINT (`0x02000000`) and HP PLIC (`0x0C000000`) are removed. SoC interrupt +source numbers are unchanged at the boundary (1 UART1, 2 mailbox doorbell, +3 EXT-H, 4-12 DMA/USB2/SDIO0/SDIO1/SPI-SD/JPEG/APU/GA2D/NPU); the C906 maps +external input *i* to PLIC ID *i*+16, so software sees IDs 17-28. The CLINT +at `0x10020000` remains the LP/global CLINT and mtime source; mtime reaches +the C906 through `pad_cpu_sys_cnt` and is read through the `time` CSR. +LP-to-HP notification is exclusively the mailbox doorbell (PLIC ID 18). See +[HP platform](ip/hp-platform.md). + ## Clock and reset domains `soc_clock_reset_subsystem` is the product clock/reset implementation behind @@ -74,10 +87,11 @@ Hazard3 -> AHB-Lite adapter -> LP AXI32 control fabric -> LP/PCLK bridge -> APB4 peripheral and system register banks ``` -HP uncached MMIO is downsized to AXI32 and crosses HP to LP through -`axi4_async_bridge`. Product access control rejects HP writes to root SYSCTRL, -watchdog, and GPIO administration windows with `SLVERR`; Hazard3 retains full -management access. +HP uncached MMIO is demuxed from the HP core's single AXI4 master by +`axi4_mmio_demux` (window `0x02000000-0x2FFFFFFF`), downsized to AXI32, and +crosses HP to LP through `axi4_async_bridge`. Product access control rejects +HP writes to root SYSCTRL, watchdog, and GPIO administration windows with +`SLVERR`; Hazard3 retains full management access. `axi4_mgmt_router` keeps APB/control addresses on this path and routes every memory window through an LP-to-HP data gateway. Hazard3 therefore shares the @@ -94,8 +108,8 @@ and a Common FIFO preserves write-data order where AXI4 W has no ID. | Master | Entry path | | --- | --- | -| HP I-cache | native AXI64, ID prefix 0 | -| HP D-cache | native AXI64, ID prefix 1 | +| HP core (OpenC906) | single 128-bit AXI4 master serialized by `axi4_downsizer_128to64`, ID prefix 0; `axi4_mmio_demux` splits off the MMIO window | +| retired HP D-cache slot | tied idle; ID-prefix map preserved | | central DMA | PCLK-to-HP async bridge, AXI32-to-64 upsizer | | I/O gateway A | USB2 and SDIO0, then PCLK-to-HP CDC and upsizer | | I/O gateway B | SDIO1 and SPI-SD, then PCLK-to-HP CDC and upsizer | @@ -203,9 +217,10 @@ files remain available only for optional PLL experiments. Behavioral RTL, firmware, directed data-plane/lifecycle/clock tests, manifest parity, and quality checks are the evidence for this implementation. HP stop implements a pre-drain cache request/ACK window, drain, coordinated flush, -actual-release status, and bounded forced reset. Vexii implements 64-byte -`Zicbom`; software still owns shared-range selection, and a forced reset cannot -preserve dirty cache data when the ACK times out. It must not be +actual-release status, and bounded forced reset. OpenC906 uses 64-byte cache +lines with T-Head custom-0 `dcache.cva`/`dcache.iva` maintenance instructions +instead of Zicbom; software still owns shared-range selection, and a forced +reset cannot preserve dirty cache data when the ACK times out. It must not be called cache coherent, power isolated, timing closed, CDC/RDC signed off, or silicon-qualified. Synthesis, netlist simulation, STA, MMMC, clock-tree, DFT, and analogue PLL qualification are separate gates. diff --git a/docs/mini-high-performance-traceability.md b/docs/mini-high-performance-traceability.md index b48609cf..e4fadf16 100644 --- a/docs/mini-high-performance-traceability.md +++ b/docs/mini-high-performance-traceability.md @@ -19,7 +19,7 @@ | Initiator ACL and first-fault attribution | Generated data policy, crossbar, SYSCTRL, and Fabric Monitor | target/execute/cache/range denial and injection tests | implemented: fixed policy is topology-generated and valid/ready fault reporting retains every accepted event across the HP/PCLK CDC | | Stable memory functional clocks | Memory integration | HP DFS while refresh/protocol engines continue | implemented digitally: SRAM is native HP AXI64; SDRAM and all serial targets cross directly from HP to stable memory as AXI64 before local downsizing | | Reset epoch and stale-response rejection | Async bridges | unilateral reset and clock-stop matrix | partial: coordinated warm flush and epoch implemented | -| HP normal and forced hot reset | AON lifecycle controller and Resource Controller | cache request/ACK, drain, timeout, flush, and recovery tests | implemented digitally: Zicbom and bounded ACK window exist; range policy and Linux service remain software work | +| HP normal and forced hot reset | AON lifecycle controller and Resource Controller | cache request/ACK, drain, timeout, flush, and recovery tests | implemented digitally: C906 custom-0 cache-maintenance instructions and bounded ACK window exist; range policy and Linux service remain software work | | Clock monitor and programmable timeout | AON clock/reset subsystem | 8x8 DFS and clock-loss tests | implemented | | Operational EXT-H ACL, timeout, and data path | Extension subsystem | transfer, denial, hang, and quiesce tests | implemented | | Ownership-aware IRQ handoff | Resource Controller and HP PLIC | idle handoff, owner lock, LP/HP exclusion, and fault tests | implemented for DMA, USB2, SDIO0/1, SPI-SD, EXT-H, and JPEG; downstream per-engine reset ACK remains pending | @@ -36,8 +36,12 @@ sources of truth. ## Historical RV32 verification evidence The results below predate the RV64 migration and must not be used as RV64 -qualification. Current generation selects `rv64imafdc_zicbom_max`; see -[HP RV64 validation](hp-rv64-validation.md) for migration-specific evidence. +qualification. The RV64 VexiiRiscv evidence recorded after that migration is +likewise historical: the HP core is now the locked, pre-generated T-Head +OpenC906 (RV64GC), and the `rv64imafdc_zicbom_max` VexiiRiscv configuration +survives only as the frozen Std-series generator asset. See +[HP RV64 validation](hp-rv64-validation.md) for the swap status and the new +evidence requirements. - The complete Python suite passes 308 tests, including directed AXI64 multi-ID/ACL/QoS, target isolation, native AXI64 SRAM, Fabric Monitor, @@ -64,7 +68,7 @@ qualification. Current generation selects `rv64imafdc_zicbom_max`; see The strict IHP130 warning-baseline comparison remains an observation: the baseline predates the fixed HP/product topology and does not contain many -generated VexiiRiscv, newly enabled peripheral, and PDK signatures. New warning +OpenC906, newly enabled peripheral, and PDK signatures. New warning signatures introduced directly by the data-plane, lifecycle, extension, and CDC integration were removed; the baseline was intentionally not regenerated or hand-edited in this change. diff --git a/docs/mini-soc-block-diagram.dot b/docs/mini-soc-block-diagram.dot index 39bff21f..ad14bb35 100644 --- a/docs/mini-soc-block-diagram.dot +++ b/docs/mini-soc-block-diagram.dot @@ -104,9 +104,13 @@ digraph mini_soc_block_diagram { label="HP data domain @ EXT72 / PLL"; style="rounded"; - vexii [ + c906 [ fillcolor="#DBEAFE", - label="VexiiRiscv hart 1\nindependent native AXI64 I-cache / D-cache" + label="OpenC906 hart 1\nsingle 128-bit AXI4 master\ninternal CLINT/PLIC @ 0x08000000" + ]; + hp_demux [ + fillcolor="#E0F2FE", + label="128 -> 64 serializing downsizer\n+ MMIO demux (0x02000000-0x2FFFFFFF)" ]; ext_h [ fillcolor="#DBEAFE", @@ -158,8 +162,9 @@ digraph mini_soc_block_diagram { lp_fabric -> lp_gateway [label="memory windows"]; hp_mmio -> lp_fabric [label="uncached MMIO"]; - vexii -> data_plane [label="I$ / D$ AXI64"]; - vexii -> hp_mmio [label="MMIO"]; + c906 -> hp_demux [label="AXI4 128-bit"]; + hp_demux -> data_plane [label="mem AXI64, slot 0"]; + hp_demux -> hp_mmio [label="MMIO window"]; io_gateway -> data_plane [label="M2-M4"]; lp_gateway -> data_plane [label="M5"]; ext_h -> data_plane [label="M7"]; diff --git a/docs/mini-soc-block-diagram.svg b/docs/mini-soc-block-diagram.svg index a4aac650..7f0fdce3 100644 --- a/docs/mini-soc-block-diagram.svg +++ b/docs/mini-soc-block-diagram.svg @@ -4,66 +4,66 @@ - - + + mini_soc_block_diagram -retroSoC Mini Product Architecture +retroSoC Mini Product Architecture cluster_aon - -AON @ REF24 + +AON @ REF24 cluster_lp - + LP control domain cluster_pclk - -PCLK register domain + +PCLK register domain cluster_hp - -HP data domain @ EXT72 / PLL + +HP data domain @ EXT72 / PLL cluster_memory - -Stable memory domain + +Stable memory domain clocks - -Clock and reset inputs -REF24, EXT72, audio -DVP, ULPI, JTAG + +Clock and reset inputs +REF24, EXT72, audio +DVP, ULPI, JTAG aon - -Clock/reset subsystem -PLL supervisor and clock monitor -HP lifecycle, pad mode, retained faults + +Clock/reset subsystem +PLL supervisor and clock monitor +HP lifecycle, pad mode, retained faults clocks->aon - - -REF24 / EXT72 + + +REF24 / EXT72 pads - -Pads and devices -SDRAM, QPI/OPI shared pads, XPI -USB2, SDIO, SPI-SD, GPIO/peripherals + +Pads and devices +SDRAM, QPI/OPI shared pads, XPI +USB2, SDIO, SPI-SD, GPIO/peripherals @@ -75,98 +75,98 @@ aon->hazard3 - - -LP clock/reset + + +LP clock/reset apb - -APB4 system + peripheral islands -SYSCTRL, Resource Controller -EXT-L/EXT-H, memory/peripheral control + +APB4 system + peripheral islands +SYSCTRL, Resource Controller +EXT-L/EXT-H, memory/peripheral control aon->apb - - -PCLK/reset + + +PCLK/reset - + data_plane - -Native AXI64 Data Plane -9 masters x 6 targets, global ID7 -target credits, QoS aging, generated ACL + +Native AXI64 Data Plane +9 masters x 6 targets, global ID7 +target credits, QoS aging, generated ACL aon->data_plane - - -HP clock/reset -block, drain, flush + + +HP clock/reset +block, drain, flush - + memory - -Fixed-present frontends -SDRAM | QPI | OPI/HyperBus | XPI -QPI/OPI boot-selected, inactive SLVERR + +Fixed-present frontends +SDRAM | QPI | OPI/HyperBus | XPI +QPI/OPI boot-selected, inactive SLVERR aon->memory - - -stable memory clock/reset + + +stable memory clock/reset lp_fabric - -32-bit LP control fabric -root access policy and fault routing + +32-bit LP control fabric +root access policy and fault routing hazard3->lp_fabric - - -AHB -> AXI32 + + +AHB -> AXI32 lp_gateway - -LP -> HP data gateway -AXI32 -> 64 + async bridge -background / recovery QoS + +LP -> HP data gateway +AXI32 -> 64 + async bridge +background / recovery QoS lp_fabric->lp_gateway - - -memory windows + + +memory windows lp_fabric->apb - - -LP -> PCLK APB + + +LP -> PCLK APB - + lp_gateway->data_plane - - -M5 + + +M5 @@ -178,162 +178,177 @@ hp_mmio->lp_fabric - - -uncached MMIO + + +uncached MMIO - + apb->pads - - - -control and peripheral I/O + + + +control and peripheral I/O - + ext_h - -EXT-H -AXI64 data master -fixed range ACL + +EXT-H +AXI64 data master +fixed range ACL - + apb->ext_h - - + + control / ownership - + monitor - -Fabric Monitor @ 0x2000_B000 -snapshot counters, wait/high-water -timeout/isolation, sticky first fault + +Fabric Monitor @ 0x2000_B000 +snapshot counters, wait/high-water +timeout/isolation, sticky first fault - + apb->monitor - - -PCLK -> HP APB + + +PCLK -> HP APB io_gateway - -DMA and I/O sub-fabrics -central DMA, USB2, SDIO0/1, SPI-SD -AXI32 -> 64 + async bridges + +DMA and I/O sub-fabrics +central DMA, USB2, SDIO0/1, SPI-SD +AXI32 -> 64 + async bridges - + io_gateway->pads - - - -payload + + + +payload - + io_gateway->data_plane - - -M2-M4 + + +M2-M4 - + -vexii - -VexiiRiscv hart 1 -independent native AXI64 I-cache / D-cache +c906 + +OpenC906 hart 1 +single 128-bit AXI4 master +internal CLINT/PLIC @ 0x08000000 - - -vexii->hp_mmio - - -MMIO + + +hp_demux + +128 -> 64 serializing downsizer ++ MMIO demux (0x02000000-0x2FFFFFFF) - + -vexii->data_plane - - -I$ / D$ AXI64 +c906->hp_demux + + +AXI4 128-bit + + + +hp_demux->hp_mmio + + +MMIO window + + + +hp_demux->data_plane + + +mem AXI64, slot 0 - + ext_h->data_plane - - -M7 + + +M7 - + guards - -Queued target guards -bounded SLVERR, timeout and isolation + +Queued target guards +bounded SLVERR, timeout and isolation - + data_plane->guards - - -five memory targets + + +five memory targets - + data_plane->monitor - - -events / fault + + +events / fault - + sram - -32 KiB on-chip SRAM -native AXI64 / ID7 + +32 KiB on-chip SRAM +native AXI64 / ID7 - + guards->sram - - -native AXI64 + + +native AXI64 - + memory_cdc - -Four direct HP -> memory AXI64 bridges -local AXI64 -> 32 adaptation + +Four direct HP -> memory AXI64 bridges +local AXI64 -> 32 adaptation - + guards->memory_cdc - - -SDRAM/QPI/OPI/XPI AXI64 + + +SDRAM/QPI/OPI/XPI AXI64 - + memory_cdc->memory - - -AXI32 frontends + + +AXI32 frontends - + memory->pads - - - -memory protocols + + + +memory protocols diff --git a/docs/soc-family-positioning.md b/docs/soc-family-positioning.md index 34e3832b..0f7ea389 100644 --- a/docs/soc-family-positioning.md +++ b/docs/soc-family-positioning.md @@ -27,14 +27,21 @@ advertised for a device or PDK. | Tier | Product role | Compute topology | Primary software | Defining boundary | | --- | --- | --- | --- | --- | | Tiny | Low-power MCU and edge-connectivity endpoint | One Hazard3 MCU core | Bare metal or RTOS | No MMU or external DRAM dependency | -| Mini | Low-cost heterogeneous Linux control SoC | RV32 Hazard3 management plus one RV64 VexiiRiscv application core | Embedded Linux or RT-Thread plus management firmware | Lightweight Linux and basic HMI, without a desktop-class accelerator requirement | +| Mini | Low-cost heterogeneous Linux control SoC | RV32 Hazard3 management plus one RV64 T-Head OpenC906 application core | Embedded Linux or RT-Thread plus management firmware | Lightweight Linux and basic HMI, without a desktop-class accelerator requirement | | Std | Heterogeneous RV32 graphical Linux edge SoC | Hazard3 management core plus VexiiRiscv performance and efficiency cores | Graphical Linux plus RTOS firmware | Full AXI4 memory fabric, GPU, audio, and AI acceleration | | Pro | Highest-performance coherent RV64 family tier | Hazard3 management core plus four coherent RV64 VexiiRiscv Linux cores | RV64 graphical Linux | Coherent SMP, high-bandwidth memory, GPU, NPU, and video codecs | The VexiiRiscv targets rely on the upstream core's documented RV32/RV64, single/dual-issue, cache, Sv32/Sv39, AXI4, and Linux capabilities. The exact [VexiiRiscv](https://github.com/SpinalHDL/VexiiRiscv) revision and generated -configuration must be locked and verified before integration. +configuration must be locked and verified before integration. The former Mini +HP VexiiRiscv configuration (RV64IMAFDC + Zicbom, reset vector `0x38000000`, +hart ID 1) is now preserved as a frozen Std-series generator asset: +`scripts/vexiiriscv/GenerateRetroSocStd.scala` (module +`vexiiriscv_std_generated`), driven by `make std-vexii-generate`, with the +locked VexiiRiscv revision retained in the dependency lock. Mini no longer +consumes it; the Mini HP core is the locked, pre-generated T-Head +[OpenC906](https://github.com/XUANTIE-RV/openc906). The names describe capability tiers, not die-size derivatives. In particular, Tiny is not a Mini with features disabled, and Std is not a Mini that merely @@ -170,7 +177,7 @@ feature reference when Wi-Fi is included. ### Status and Position retroSoC Mini is an open-source asymmetric RISC-V SoC with a fixed Hazard3 LP -management core and a fixed 32-bit VexiiRiscv HP application core. C0-C3 are +management core and a fixed RV64 T-Head OpenC906 HP application core. C0-C3 are available only in the separate MPW compatibility profile. RTL integration, a direct-Linux image flow, and LP boot firmware are implemented; repeatable Linux boot, performance, synthesis, timing, and hardware evidence are still qualification @@ -180,8 +187,7 @@ Mini is the price, complexity, and Linux-capability anchor for the family. It targets industrial control, protocol gateways, compact human-machine interfaces, and retro multimedia systems that need Linux but do not need a desktop-class graphics pipeline. Hazard3 remains the trusted management core, -and one RV32 VexiiRiscv application core runs Linux in the planned -configuration. +and one RV64 OpenC906 application core runs Linux. The product target starts at 64 MiB of external SDRAM, with 128 MiB preferred. A simple display controller or framebuffer is compatible with the Mini @@ -213,8 +219,11 @@ capabilities: window, and an 8 MiB PSRAM window. Address-window capacity does not guarantee that every implementation includes the corresponding physical memory. - AXI4 uses a 32-bit LP control plane and a 10x6 native AXI64 HP data plane - with seven-bit global IDs. Vexii I/D ports remain independent; DMA and I/O - masters cross into HP and current memory frontends are reached through + with seven-bit global IDs. The OpenC906 HP core presents a single 128-bit + AXI4 master, serialized through a 128-to-64 downsizer and demuxed into + data-plane master slot 0 and the MMIO window; the former separate + I-cache/D-cache ports are retired and master slot 1 is tied idle. DMA and + I/O masters cross into HP and current memory frontends are reached through 64-to-32 target adapters. Master 8 is the dedicated PCLK-to-HP AXI64/ID3 GA2D bridge for a direct single-job private-AXI64 2D engine; master 9 is the HP-native NPU path, tied safely idle until the Phase 3 DMA lands. @@ -232,7 +241,8 @@ capabilities: PSRAM, flash, or SPI-SD physical transaction. The experimental HP profile adds the fixed hart 1 core, a compatibility AXI -plane, HP ACLINT/PLIC, UART1, mailbox, reset release, and shared-JTAG selection. +plane, the C906 internal CLINT/PLIC, UART1, mailbox, reset release, and +shared-JTAG selection. Its detailed executable contract is [LP/HP Architecture](lp-hp-architecture.md). The generated address map, user-extension map, @@ -243,8 +253,8 @@ for the implemented baseline. ### Experimental Linux Configuration The Linux configuration keeps Hazard3 as the always-available trusted -management core and adds VexiiRiscv as the application processor. Hazard3 is -responsible for clock and memory initialization, image selection, VexiiRiscv +management core and adds OpenC906 as the application processor. Hazard3 is +responsible for clock and memory initialization, image selection, OpenC906 boot release, fault recovery, and final power-state control. Linux must not be able to reconfigure the management-core lifecycle controls. @@ -252,19 +262,22 @@ The frozen Mini RV64 configuration provides the following architectural target; validation status is recorded separately in [HP RV64 validation](hp-rv64-validation.md). The Std/Pro roadmap below remains independent of this implemented Mini profile. -- RV64IMAFDC with machine, supervisor, and user modes. +- RV64GC (RV64IMAFDC plus Zicsr and Zifencei) with machine, supervisor, and + user modes. - Sv39 virtual memory, hardware page-table walking, and the privileged CSRs required by the supported Linux kernel. -- LR/SC atomics, separate 16 KiB instruction and data caches, and uncached MMIO - regions. -- A PLIC-compatible external interrupt controller, CLINT-compatible timer and - software interrupts, and a deterministic reset vector. -- A documented DMA cache-maintenance contract unless the memory system supplies +- LR/SC atomics, separate 32 KiB instruction and data caches with 64-byte + lines, and uncached MMIO regions. +- The C906 internal PLIC (T-Head c900 layout) for external interrupts, the + C906 internal CLINT for timer and software interrupts, `time`-CSR mtime + delivery from the LP/global CLINT, and a deterministic reset vector. +- A documented DMA cache-maintenance contract (T-Head custom-0 + `dcache.cva`/`dcache.iva` instructions) unless the memory system supplies hardware coherency. The implemented management firmware waits for external memory, validates and places the OpenSBI firmware, device tree, kernel, and initial filesystem at -fixed addresses, and then releases the fixed VexiiRiscv reset vector. The +fixed addresses, and then releases the fixed HP reset vector. The bundle uses CRC32 for accidental-corruption detection, not secure boot. A future normal stop must first request Linux shutdown through the mailbox. After Linux acknowledges and flushes persistent data, the management core must @@ -279,9 +292,9 @@ implemented or cross-PDK guarantee: | Area | Minimum target | Preferred target | | --- | --- | --- | -| VexiiRiscv frequency | 150 MHz | PDK-qualified maximum above 150 MHz | +| HP core frequency | 150 MHz | PDK-qualified maximum above 150 MHz | | Main memory | 64 MiB SDRAM | 128 MiB SDRAM | -| L1 caches | 16 KiB I-cache and 16 KiB D-cache | Same, with measured refill and DMA behavior | +| L1 caches | 32 KiB I-cache and 32 KiB D-cache | Same, with measured refill and DMA behavior | | Memory transport | Native cache-line burst | Native burst with two to four outstanding transactions per master | | Boot storage | SPI NAND or qualified SDIO path | SDIO/eMMC plus recovery image | | Linux platform devices | UART, timer, interrupt controller, storage | Ethernet or USB selected by the product profile | diff --git a/publications/README.md b/publications/README.md index f1f86943..897efc1f 100644 --- a/publications/README.md +++ b/publications/README.md @@ -8,6 +8,10 @@ The canonical RTL/configuration inputs remain authoritative. The current working source includes the Mini RV64/Sv39 migration, V2 workload bundle checks, and minimal Linux `/init` handoff. RT-Thread's M-mode BSP and acceptance evidence are documented in [HP RV64 validation](../docs/hp-rv64-validation.md). +The HP core is being switched from VexiiRiscv to the locked T-Head OpenC906 +(default RV64GC configuration, core-internal c900 CLINT/PLIC, mhartid 1 via a +reviewed override); the Mini publication now describes that integration, and the +Overview drops the former HP ACLINT/HP PLIC SoC-peripheral labels (43 labels). These edits do not advance `mini.json.source_revision` or relabel an existing PDF. Review and commit the implementation snapshot before producing a matching new PDF; the source-drift check remains mandatory. @@ -246,9 +250,10 @@ initial-state/dependency summary, interface selection/subset matrices, multimedi format interoperability and an image-maintenance chapter. Its publication-only records live under `system-reference.json.product_details`; the `implementation_reference.py` collector validates source/reset bindings and -extracts explicit LP/HP parameters, PMA envelopes and build flags. The LP firmware +extracts explicit LP instance parameters, the fixed HP OpenC906 integration +constants and build flags. The LP firmware ISA/CSR choices are kept separate from hardware parameters. Unreviewed upstream -defaults and cache capacity are not inferred from the HP generator's sets/ways. +defaults and cache capacity are not inferred from the vendored HP core configuration. The Multimedia overview is outside the actual I2S IP page markers; its label ends the preceding IP header scope. All actual IP sections retain independent diff --git a/publications/build_datasheet.py b/publications/build_datasheet.py index 266417ae..09dba909 100644 --- a/publications/build_datasheet.py +++ b/publications/build_datasheet.py @@ -475,8 +475,6 @@ def check_document_sources(config: dict, data: dict) -> None: "opipsram": "OPI PSRAM", "dma": "Central DMA", "clint": "LP CLINT", - "hp_aclint": "HP ACLINT", - "hp_plic": "HP PLIC", "hp_mailbox": "LP/HP Mailbox", "ps2": "PS/2", "resource_ctrl": "Resource Controller", @@ -494,7 +492,7 @@ def check_document_sources(config: dict, data: dict) -> None: ] expected = {aliases.get(name, name.upper()) for name in names} | { "Hazard3", - "VexiiRiscv", + "OpenC906", "JTAG", "RCU", } diff --git a/publications/datasheets/diagram-circuits.json b/publications/datasheets/diagram-circuits.json index 8cc2c037..d59e18e6 100644 --- a/publications/datasheets/diagram-circuits.json +++ b/publications/datasheets/diagram-circuits.json @@ -4441,7 +4441,7 @@ "zigzag-dir": "horizontal" } ], - "note": "UART1 is the HP console instance with dedicated TX/RX pads and an HP PLIC route. DMA pacing and RTS/CTS are not connected for this instance. FIFO geometry and serial formatting are shared with UART0." + "note": "UART1 is the HP console instance with dedicated TX/RX pads and an HP external interrupt route (PLIC ID 17). DMA pacing and RTS/CTS are not connected for this instance. FIFO geometry and serial formatting are shared with UART0." }, "pwm": { "nodes": [ @@ -7273,72 +7273,27 @@ "hp-aclint": { "nodes": [ { - "id": "apb", - "title": "APB4 control\n32-bit register access", - "x": 0.0, - "y": 7.0, - "w": 4.0, - "h": 1.8, - "ports": [ - { - "id": "p0", - "direction": "out", - "width": 32, - "side": "south" - } - ], - "sources": [ - "rtl/ip/peripheral/apb4_clint.sv" - ] - }, - { - "id": "reg", - "title": "Register bank\nconfiguration / status", + "id": "tick", + "title": "LP CLINT timebase\n64-bit MTIME", "x": 0.0, "y": 3.5, "w": 4.0, "h": 1.8, "ports": [ - { - "id": "p0", - "direction": "in", - "width": 32, - "side": "north" - }, { "id": "p1", "direction": "out", "width": 64, "side": "east" - }, - { - "id": "p2", - "direction": "in", - "width": 64, - "side": "east" - }, - { - "id": "p5", - "direction": "out", - "width": null, - "side": "south", - "bundle": true } ], "sources": [ - "rtl/ip/peripheral/apb4_clint.sv", - "rtl/ip/peripheral/clint_reg.sv" - ], - "instance_source": { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "name": "u_clint_reg", - "module": "clint_reg", - "declaration_file": "rtl/ip/peripheral/clint_reg.sv" - } + "rtl/mini/top/apb4_periph.sv" + ] }, { "id": "core", - "title": "Time counter / comparator\nsoftware interrupt state", + "title": "OpenC906 internal CLINT\nc900 layout, core-BIU decode", "x": 6.3, "y": 3.5, "w": 4.0, @@ -7350,18 +7305,6 @@ "width": 64, "side": "west" }, - { - "id": "p2", - "direction": "out", - "width": 64, - "side": "west" - }, - { - "id": "p3", - "direction": "in", - "width": 1, - "side": "north" - }, { "id": "p4", "direction": "out", @@ -7371,38 +7314,20 @@ } ], "sources": [ - "rtl/ip/peripheral/apb4_clint.sv", - "rtl/ip/peripheral/clint_core.sv" + "rtl/mini/top/hp_subsystem.sv", + "rtl/mini/top/hp_core_wrapper.sv", + "rtl/mini/ip_overrides/aq_sysio_kid.v" ], "instance_source": { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "name": "u_clint_core", - "module": "clint_core", - "declaration_file": "rtl/ip/peripheral/clint_core.sv" + "file": "rtl/mini/top/hp_subsystem.sv", + "name": "u_hp_core_wrapper", + "module": "hp_core_wrapper", + "declaration_file": "rtl/mini/top/hp_core_wrapper.sv" } }, { - "id": "tick", - "title": "Shared timebase tick", - "x": 6.3, - "y": 7.0, - "w": 4.0, - "h": 1.8, - "ports": [ - { - "id": "p3", - "direction": "out", - "width": 1, - "side": "south" - } - ], - "sources": [ - "rtl/ip/peripheral/apb4_clint.sv" - ] - }, - { - "id": "irq", - "title": "HP timer/software routes", + "id": "hart", + "title": "HP hart 1\nM/S timer + software IRQ", "x": 12.6, "y": 3.5, "w": 4.0, @@ -7414,211 +7339,73 @@ "width": null, "side": "west", "bundle": true - }, - { - "id": "p5", - "direction": "in", - "width": null, - "side": "south", - "bundle": true } ], "sources": [ - "rtl/ip/peripheral/apb4_clint.sv" + "rtl/mini/ip_overrides/aq_sysio_kid.v" ] } ], "edges": [ { - "from": "apb.p0", - "to": "reg.p0", - "kind": "data", - "label": "APB4 / 32", - "style": "direct", - "bindings": [ - { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "text": ".apb4(apb4)" - } - ], - "instance_ports": [ - { - "node": "reg", - "port": "apb4", - "expression": "apb4" - } - ], - "zigzag-dir": "horizontal" - }, - { - "from": "reg.p1", + "from": "tick.p1", "to": "core.p1", "kind": "data", - "label": "LOAD / 64", + "label": "MTIME / 64", "style": "direct", "bindings": [ { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "text": ".mtime_load_value_o(s_mtime_load_value)" + "file": "rtl/mini/top/apb4_periph.sv", + "text": "assign hp_time_o = u_clint_if.mtime_o;" }, { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "text": ".mtime_load_value_i(s_mtime_load_value)" + "file": "rtl/mini/top/hp_subsystem.sv", + "text": ".time_i(time_i)" } ], "signals": [ { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "scope": "apb4_clint", - "symbol": "s_mtime_load_value", - "bits": 64 - }, - { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "scope": "apb4_clint", - "symbol": "s_mtime_load_value", - "bits": 64 - } - ], - "instance_ports": [ - { - "node": "reg", - "port": "mtime_load_value_o", - "expression": "s_mtime_load_value" - }, - { - "node": "core", - "port": "mtime_load_value_i", - "expression": "s_mtime_load_value" - } - ] - }, - { - "from": "core.p2", - "to": "reg.p2", - "kind": "data", - "label": "TIME / 64", - "style": "direct", - "bindings": [ - { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "text": ".mtime_o(s_mtime)" - }, - { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "text": ".mtime_i(s_mtime)" - } - ], - "signals": [ - { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "scope": "apb4_clint", - "symbol": "s_mtime", - "bits": 64 - }, - { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "scope": "apb4_clint", - "symbol": "s_mtime", + "file": "rtl/mini/top/retrosoc.sv", + "scope": "retrosoc", + "symbol": "s_hp_time", "bits": 64 } ], "instance_ports": [ { "node": "core", - "port": "mtime_o", - "expression": "s_mtime" - }, - { - "node": "reg", - "port": "mtime_i", - "expression": "s_mtime" - } - ] - }, - { - "from": "tick.p3", - "to": "core.p3", - "kind": "control", - "label": "TICK", - "style": "direct", - "bindings": [ - { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "text": ".tick_i(timebase_tick_i)" - } - ], - "signals": [ - { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "scope": "apb4_clint", - "symbol": "timebase_tick_i", - "bits": 1 - } - ], - "instance_ports": [ - { - "node": "core", - "port": "tick_i", - "expression": "timebase_tick_i" + "port": "time_i", + "expression": "time_i" } ], "zigzag-dir": "horizontal" }, { "from": "core.p4", - "to": "irq.p4", + "to": "hart.p4", "kind": "control", - "label": "Timer IRQ", + "label": "M/S IRQ", "style": "direct", "bindings": [ { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "text": ".timer_irq_o(s_timer_irq)" + "file": "rtl/mini/top/hp_core_wrapper.sv", + "text": ".pad_cpu_sys_cnt(time_i)" + }, + { + "file": "rtl/mini/ip_overrides/aq_sysio_kid.v", + "text": "input clint_core_mt_int;" } ], - "instance_ports": [ - { - "node": "core", - "port": "timer_irq_o", - "expression": "s_timer_irq" - } - ] - }, - { - "from": "reg.p5", - "to": "irq.p5", - "kind": "control", - "label": "Software IRQ", - "style": "dodge", - "bindings": [ - { - "file": "rtl/ip/peripheral/apb4_clint.sv", - "text": ".msip_o(s_msip)" - } - ], - "instance_ports": [ - { - "node": "reg", - "port": "msip_o", - "expression": "s_msip" - } - ], - "zigzag-dir": "horizontal", - "dodge-y": 1.7, - "dodge-margins": [ - 0, - 0 - ] + "zigzag-dir": "horizontal" } ], - "note": "The LP CLINT and HP ACLINT share this RTL family but own separate register windows and interrupt routing. HP logical contexts are not additional physical harts." + "note": "The OpenC906 CLINT is decoded inside the core BIU within the 0x08000000 system window and never appears on the SoC fabric. There is no memory-mapped mtime: the SoC drives the 64-bit time value into the core and software reads the time CSR." }, "hp-plic": { "nodes": [ { "id": "sources", - "title": "Peripheral IRQ sources\n32 source slots", + "title": "SoC peripheral IRQs\n16 external sources", "x": 0.0, "y": 3.5, "w": 4.0, @@ -7627,17 +7414,24 @@ { "id": "p0", "direction": "out", - "width": 32, + "width": 16, "side": "east" } ], "sources": [ - "rtl/mini/top/apb4_periph.sv" - ] + "rtl/mini/top/apb4_periph.sv", + "rtl/mini/top/retrosoc.sv" + ], + "instance_source": { + "file": "rtl/mini/top/retrosoc.sv", + "name": "u_apb4_periph", + "module": "apb4_periph", + "declaration_file": "rtl/mini/top/apb4_periph.sv" + } }, { - "id": "plic", - "title": "Pending / priority / claim\n2 context arbiters", + "id": "core", + "title": "OpenC906 internal PLIC\nc900 layout, ID = source + 16", "x": 6.3, "y": 3.5, "w": 4.0, @@ -7646,36 +7440,31 @@ { "id": "p0", "direction": "in", - "width": 32, + "width": 16, "side": "west" }, { "id": "p1", "direction": "out", - "width": 2, - "side": "east" - }, - { - "id": "p2", - "direction": "in", - "width": 32, - "side": "north" + "width": null, + "side": "east", + "bundle": true } ], "sources": [ - "rtl/mini/top/apb4_periph.sv", - "rtl/ip/peripheral/apb4_plic.sv" + "rtl/mini/top/hp_subsystem.sv", + "rtl/mini/top/hp_core_wrapper.sv" ], "instance_source": { - "file": "rtl/mini/top/apb4_periph.sv", - "name": "u_apb4_hp_plic", - "module": "apb4_plic", - "declaration_file": "rtl/ip/peripheral/apb4_plic.sv" + "file": "rtl/mini/top/hp_subsystem.sv", + "name": "u_hp_core_wrapper", + "module": "hp_core_wrapper", + "declaration_file": "rtl/mini/top/hp_core_wrapper.sv" } }, { - "id": "hp", - "title": "HP machine / supervisor\nexternal interrupt inputs", + "id": "hart", + "title": "HP hart 1\nM/S external interrupts", "x": 12.6, "y": 3.5, "w": 4.0, @@ -7684,114 +7473,71 @@ { "id": "p1", "direction": "in", - "width": 2, - "side": "west" + "width": null, + "side": "west", + "bundle": true } ], "sources": [ - "rtl/mini/top/apb4_periph.sv" - ] - }, - { - "id": "apb", - "title": "APB4 configuration\npriority / enable / threshold", - "x": 6.3, - "y": 7.0, - "w": 4.0, - "h": 1.8, - "ports": [ - { - "id": "p2", - "direction": "out", - "width": 32, - "side": "south" - } - ], - "sources": [ - "rtl/mini/top/apb4_periph.sv" + "rtl/mini/top/hp_core_wrapper.sv" ] } ], "edges": [ { "from": "sources.p0", - "to": "plic.p0", - "kind": "control", - "label": "IRQ / 32", - "style": "direct", - "bindings": [ - { - "file": "rtl/mini/top/apb4_periph.sv", - "text": ".source_i(s_hp_plic_source)" - } - ], - "signals": [ - { - "file": "rtl/mini/top/apb4_periph.sv", - "scope": "apb4_periph", - "symbol": "s_hp_plic_source", - "bits": 32 - } - ], - "instance_ports": [ - { - "node": "plic", - "port": "source_i", - "expression": "s_hp_plic_source" - } - ] - }, - { - "from": "plic.p1", - "to": "hp.p1", - "kind": "control", - "label": "CTX / 2", - "style": "direct", - "bindings": [ - { - "file": "rtl/mini/top/apb4_periph.sv", - "text": ".context_irq_o(s_hp_plic_context_irq)" - } - ], - "signals": [ - { - "file": "rtl/mini/top/apb4_periph.sv", - "scope": "apb4_periph", - "symbol": "s_hp_plic_context_irq", - "bits": 2 - } - ], - "instance_ports": [ - { - "node": "plic", - "port": "context_irq_o", - "expression": "s_hp_plic_context_irq" - } - ] - }, - { - "from": "apb.p2", - "to": "plic.p2", + "to": "core.p0", "kind": "data", - "label": "APB4 / 32", + "label": "SOURCES / 16", "style": "direct", "bindings": [ { - "file": "rtl/mini/top/apb4_periph.sv", - "text": ".apb4(u_hp_plic_apb4_if)" + "file": "rtl/mini/top/retrosoc.sv", + "text": ".hp_plic_src_o(s_hp_plic_src)" + }, + { + "file": "rtl/mini/top/hp_subsystem.sv", + "text": ".plic_src_i(plic_src_i)" + } + ], + "signals": [ + { + "file": "rtl/mini/top/retrosoc.sv", + "scope": "retrosoc", + "symbol": "s_hp_plic_src", + "bits": 16 } ], "instance_ports": [ { - "node": "plic", - "port": "apb4", - "expression": "u_hp_plic_apb4_if" + "node": "sources", + "port": "hp_plic_src_o", + "expression": "s_hp_plic_src" + }, + { + "node": "core", + "port": "plic_src_i", + "expression": "plic_src_i" + } + ], + "zigzag-dir": "horizontal" + }, + { + "from": "core.p1", + "to": "hart.p1", + "kind": "control", + "label": "MEIP / SEIP", + "style": "direct", + "bindings": [ + { + "file": "rtl/mini/top/hp_core_wrapper.sv", + "text": ".pad_plic_int_vld({224'd0, plic_src_i})" } ], "zigzag-dir": "horizontal" } ], - "note": "32 source slots feed two logical HP interrupt contexts. Pending/claimed state, priority and thresholds are inside apb4_plic. This is the HP external-interrupt controller, not the LP IRQ route." + "note": "The OpenC906 PLIC is decoded inside the core BIU at the base of the 0x08000000 system window and never appears on the SoC fabric. SoC external source n is delivered to the core as PLIC ID n+16; IDs 0-15 are reserved or internal." }, "hp-mailbox": { "nodes": [ @@ -8165,7 +7911,7 @@ "zigzag-dir": "horizontal" } ], - "note": "Ten resources retain independent owner/lock/quiesce/reset state. Resource 8 owns GA2D; resource 9 owns NPU and routes LP vector 33 / HP PLIC source 12. IRQ steering and cache handoff are control relationships, not a payload DMA path." + "note": "Ten resources retain independent owner/lock/quiesce/reset state. Resource 8 owns GA2D; resource 9 owns NPU and routes LP vector 33 / HP external source 12 (PLIC ID 28). IRQ steering and cache handoff are control relationships, not a payload DMA path." }, "monitor": { "nodes": [ @@ -10714,7 +10460,7 @@ }, { "id": "hp", - "title": "VexiiRiscv HP\nI-cache / D-cache", + "title": "OpenC906 HP\nAXI4 128-bit master, downsized to 64", "x": 6.3, "y": 7.0, "w": 4.0, @@ -11001,28 +10747,28 @@ "from": "hp.p1", "to": "fabric.p1", "kind": "data", - "label": "I-cache / 64", + "label": "Memory / 64", "style": "direct", "bindings": [ { "file": "rtl/mini/top/retrosoc.sv", - "text": ".icache_axi4(u_hp_icache_axi4_if)" + "text": ".mem_axi4(u_hp_mem_axi4_if)" }, { "file": "rtl/mini/top/retrosoc.sv", - "text": ".hp_icache_axi4(u_hp_icache_axi4_if)" + "text": ".hp_mem_axi4(u_hp_mem_axi4_if)" } ], "instance_ports": [ { "node": "hp", - "port": "icache_axi4", - "expression": "u_hp_icache_axi4_if" + "port": "mem_axi4", + "expression": "u_hp_mem_axi4_if" }, { "node": "fabric", - "port": "hp_icache_axi4", - "expression": "u_hp_icache_axi4_if" + "port": "hp_mem_axi4", + "expression": "u_hp_mem_axi4_if" } ], "zigzag-dir": "horizontal" diff --git a/publications/datasheets/diagram-packages.typ b/publications/datasheets/diagram-packages.typ index c5376fc1..8c9ffb27 100644 --- a/publications/datasheets/diagram-packages.typ +++ b/publications/datasheets/diagram-packages.typ @@ -114,9 +114,9 @@ #diagram-text[Relative byte boundaries: 0 · #c.granule · #c.covered_bytes] #v(4pt) #bc.region(width:100%,fill:white,stroke:0.6pt+ink,radius:0pt)[ - #bc.cell(width:77mm,height:12mm,fill:gray,stroke:0.6pt+ink)[#align(center+horizon)[CBO block 0: bytes 0–63]] + #bc.cell(width:77mm,height:12mm,fill:gray,stroke:0.6pt+ink)[#align(center+horizon)[Cache line 0: bytes 0–63]] #h(2mm) - #bc.cell(width:77mm,height:12mm,fill:gray,stroke:0.6pt+ink)[#align(center+horizon)[CBO block 1: bytes 64–127]] + #bc.cell(width:77mm,height:12mm,fill:gray,stroke:0.6pt+ink)[#align(center+horizon)[Cache line 1: bytes 64–127]] #linebreak() #v(4pt) #bc.cell(width:19mm,height:15mm,fill:gray,stroke:0.6pt+ink)[16 B \ before] @@ -125,8 +125,8 @@ #bc.cell(width:19mm,height:15mm,fill:pale-gold,stroke:0.6pt+ink)[16 B \ payload] #bc.cell(width:57mm,height:15mm,fill:gray,stroke:0.6pt+ink)[48 B after \ bytes 80–127] ] - #diagram-note[The software-declared 64-byte maintenance granule covers a 64-byte payload at offset 16 - using two blocks. Keep boundary bytes under compatible ownership. Relative offsets are illustrative; + #diagram-note[A 64-byte payload at offset 16 touches two 64-byte HP D-cache lines, so + maintenance spans both. Keep boundary bytes under compatible ownership. Relative offsets are illustrative; this is not a verified HP cache tag/set/way layout or an allocated buffer address.] #diagram-end("blockcell","cache-boundaries") ] diff --git a/publications/datasheets/features.json b/publications/datasheets/features.json index ae286c94..8c248068 100644 --- a/publications/datasheets/features.json +++ b/publications/datasheets/features.json @@ -35,9 +35,9 @@ "One management hart slot in the reference integration." ], "aclint": [ - "Two addressable hart slots; **HP consumes slot 1**.", - "Machine software and timer interrupts for the HP subsystem.", - "Separate address window from management CLINT." + "**Core-internal CLINT** of the OpenC906 HP hart (c900 layout).", + "Machine/supervisor timer and software interrupts; **no memory-mapped mtime**.", + "Decoded inside the core BIU; **no SoC register window**." ], "dma": [ "**Eight channel contexts** share a 32-bit AXI master.", @@ -181,9 +181,9 @@ "Clock division and memory-pad mode through SYSCTRL." ], "plic": [ - "32 source IDs, with **source 0 reserved**.", - "Two delivery contexts: machine and supervisor.", - "Priorities, masks, threshold and claim/complete semantics." + "**Core-internal PLIC** of the OpenC906 HP hart (c900 layout).", + "**16 SoC external sources**, delivered as PLIC ID = source + 16.", + "Machine/supervisor contexts; priorities, thresholds and claim/complete." ], "mpw-timer": [ "**MPW-selectable** timer and divider.", diff --git a/publications/datasheets/figures.typ b/publications/datasheets/figures.typ index f2fc8ba0..6388c7af 100644 --- a/publications/datasheets/figures.typ +++ b/publications/datasheets/figures.typ @@ -106,7 +106,7 @@ panel(0,0.4,-1.7,w,4.0,(2,1),weights:(2,1)) panel(1,0.4 + w + 0.3,-1.7,w,4.0,(2,2,1)) panel(2,0.4 + 2*(w + 0.3),-1.7,w,4.0,(2,2,1)) - panel(3,0.4,-6.0,w,4.0,(2,2)) + panel(3,0.4,-6.0,w,4.0,(2,)) panel(4,0.4 + w + 0.3,-6.0,w,4.0,(1,1,1)) panel(5,0.4 + 2*(w + 0.3),-6.0,w,4.0,(2,2,1)) panel(6,0.4,-10.3,2*w + 0.3,5.5,(3,3,3,2)) diff --git a/publications/datasheets/ip-catalog.json b/publications/datasheets/ip-catalog.json index 607209ad..edf06b84 100644 --- a/publications/datasheets/ip-catalog.json +++ b/publications/datasheets/ip-catalog.json @@ -309,8 +309,7 @@ { "id": "hp-platform", "regions": [ - "HP_ACLINT", - "HP_PLIC", + "HP_C906_SYS", "APB4_HP_MAILBOX" ], "irqs": [ @@ -320,7 +319,7 @@ "docs/ip/hp-platform.md", "docs/lp-hp-architecture.md" ], - "summary": "HP local timer/software interrupts, two-context PLIC and bidirectional mailbox." + "summary": "HP core-internal CLINT/PLIC window (decoded inside the OpenC906 core) and bidirectional mailbox." }, { "id": "resource", diff --git a/publications/datasheets/ip-content.json b/publications/datasheets/ip-content.json index 5561c0a9..d431b62e 100644 --- a/publications/datasheets/ip-content.json +++ b/publications/datasheets/ip-content.json @@ -1283,47 +1283,47 @@ "aclint": { "title": "HP ACLINT", "blocks": [ - "APB decoder", - "Two hart slots", - "64-bit timer", - "Compare registers", - "Hart 1 IRQ outputs" + "Core-internal CLINT", + "c900 layout", + "64-bit time input", + "M/S timer + software IRQ" ], "function_sections": [], "software_sections": [], "notes": [ - "The HP ACLINT is mapped at 0x02000000. The shared implementation provides two addressable hart slots, and hart slot 1 drives the HP software and timer interrupt inputs. MSIP1 is at offset 0x0004, MTIMECMP1 at 0x4008/0x400C, and the common MTIME at 0xBFF8/0xBFFC. This is separate from the management CLINT at 0x02010000.", - "Each 64-bit timer value is accessed as two 32-bit words. Use the retry and safe compare-update sequences below. The HP boot configuration uses a 1 MHz reference timebase; changing a CPU PLL setting does not redefine this reference." + "There is **no memory-mapped mtime**: the SoC drives the shared 64-bit time value from the management CLINT into the core, and HP software reads the time CSR. The compare value is programmed through the core-internal window; the supplied OpenSBI platform writes MTIMECMP at window offsets 0x4000/0x4004 with the 1 MHz reference timebase. Changing a CPU PLL setting does not redefine this reference.", + "Machine and supervisor timer/software interrupts follow the c900 per-hart order (M-SW, M-timer, S-SW, S-timer), as declared by the supplied device tree. The management CLINT at 0x10020000 is a separate LP-owned peripheral with its own chapter." ], "software_steps": [ - "HP consumes **hart slot 1** of the two-slot window. Do not use a management-CLINT base-address helper.", - "Read **high/low/high and retry** if the high words differ when a coherent RV32 time value is required.", - "Update compare using the **safe high/low sequence**. OpenSBI may provide this service for HP software." + "Use the OpenSBI platform services for HP timer and software interrupts; the supplied platform binds the ACLINT MSWI driver at the internal base with **first hart ID 1 and hart count 1**.", + "Program timer events through the platform's custom timer device, which reads the **time CSR** and writes MTIMECMP with the safe high/low sequence; do not assume a memory-mapped MTIME register.", + "Do not use a management-CLINT base-address helper for HP-local interrupts." ], "flow": [ - "Reference ticks / MSIP", - "Hart 1 compare / pending", - "HP MTIP / MSIP" + "SoC 64-bit time value", + "Core-internal compare / pending", + "HP M/S timer + software IRQ" ] }, "plic": { "title": "HP PLIC", "blocks": [ - "APB decoder", - "Source priorities", - "Pending/claimed bits", - "Context enables", - "Priority arbitration", - "Claim/complete" - ], - "function_sections": [ - "PLIC" + "Core-internal PLIC", + "c900 layout", + "16 SoC sources", + "PLIC ID = source + 16", + "M/S external contexts" ], + "function_sections": [], "software_sections": [], - "notes": [], + "notes": [ + "Sixteen SoC external interrupt sources drive the core's PLIC vector. **SoC source n is delivered to software as PLIC ID n+16**; IDs 0-15 are reserved or internal. Source 1 is UART1, source 2 is the HP-side mailbox doorbell, source 3 is EXT-H, and sources 4 through 12 are the resource-owned DMA, USB2, SDIO0, SDIO1, SPI-SD, JPEG, APU, GA2D and NPU lines. Sources 13 through 15 are reserved and tied low.", + "The c900 PLIC provides machine and supervisor external-interrupt contexts for the HP hart, with per-source priorities, enables, thresholds and claim/complete arbitration. Register-bit detail follows the T-Head C906 manuals; the supplied device tree declares the thead,c900-plic node with riscv,ndev = 31.", + "Resource-owned sources are suppressed unless HP is the exclusive owner; see the Resource Controller chapter for the ownership and routing contract." + ], "software_steps": [ - "Program source priority, the machine/supervisor **context enable and threshold**.", - "Read CLAIM_COMPLETE **once per claim**. Zero means no eligible source; a nonzero ID claims that source.", + "Program source priority and the machine/supervisor **context enable and threshold** in the core-internal PLIC window, using **PLIC ID = SoC source + 16**.", + "Read the claim register **once per claim**. Zero means no eligible source; a nonzero ID claims that source.", "Service the device cause, then write the claimed ID to the **same context** to complete it. A still-active level can pend again." ], "flow": [ @@ -1784,7 +1784,7 @@ "The deployed implementation advertises CAPABILITY=0x0000007F and OP_CAPABILITY=0x000001FE. It includes the complete eight-operator execution path; reusable module defaults and older phase comments do not describe the deployed configuration.", "The HP-native AXI64 master is index 9 and resource 9. It uses source ID zero, one outstanding read and one outstanding write, and an integrated maximum of eight beats per burst. It does not allocate a central-DMA channel.", "The PCLK register shell exchanges launch, result and snapshot mailboxes with HP computation. Resource quiesce waits for cancellation/drain; a coordinated clock pause retains the active job.", - "LP vector 33 (external ordinal 31) and HP PLIC source 12 are selected through resource ownership. No dedicated NPU pad, GPIO alternate function or camera/audio stream port is added.", + "LP vector 33 (external ordinal 31) and HP external source 12 (PLIC ID 28) are selected through resource ownership. No dedicated NPU pad, GPIO alternate function or camera/audio stream port is added.", "All APB writes require full word strobes. Unknown offsets, reserved-bit violations, busy configuration changes and disallowed START commands complete with PSLVERR without the prohibited side effect." ], "software_steps": [ @@ -2295,7 +2295,7 @@ "Read capability/format words, select an implemented operation, and obtain resource ownership. Confirm DATA_READY and that **no recovery is pending**.", "Allocate **disjoint bounded surfaces**, except the explicitly supported equal background/destination BLEND case. Validate pitch, format, dimensions, alignment and addresses with rs_ga2d_job_validate.", "Clean CPU-produced inputs as required, prepare destination ownership, and issue the required memory fence before configuring the job. Keep surfaces and configuration **stable while active**.", - "Call rs_ga2d_configure, then rs_ga2d_start. Use rs_ga2d_wait or the **owner-routed IRQ**; LP vector 32, external ordinal 30 and HP PLIC source 11 name different routing layers.", + "Call rs_ga2d_configure, then rs_ga2d_start. Use rs_ga2d_wait or the **owner-routed IRQ**; LP vector 32, external ordinal 30 and HP external source 11 (PLIC ID 27) name different routing layers.", "Capture terminal status, first-error details and counter snapshots **before acknowledging** W1C IRQ causes. Invalidate a DMA-written destination before CPU consumption where its mapping is cached.", "A polling timeout **does not prove hardware idle**. Use rs_ga2d_abort_wait to stop/drain accepted traffic, inspect recovery_required, and perform the documented resource/bridge rearm when required. A soft reset must not be used to discard in-flight bus obligations." ], diff --git a/publications/datasheets/ips/hp-aclint.typ b/publications/datasheets/ips/hp-aclint.typ index 5a0385eb..7bd41300 100644 --- a/publications/datasheets/ips/hp-aclint.typ +++ b/publications/datasheets/ips/hp-aclint.typ @@ -1,6 +1,7 @@ #import "../style.typ": * -#import "../ip-reference.typ": ip-reference +#import "../ip-reference.typ": inline, subhead +#import "../diagram-packages.typ": circuit-diagram #pagebreak(weak:true) @@ -10,15 +11,32 @@ ===== HP Local Interrupt Controller (ACLINT) -#let r=data.regions.find(r=>r.symbol=="HP_ACLINT") -Base address: #code(r.base_hex). Window size: #r.size_label. HP software and timer interrupts; *hart slot 1 is connected*. +#let chapter=data.chapters.at("aclint") +#let r=data.regions.find(r=>r.symbol=="HP_C906_SYS") +The HP local timer and software interrupt function is *internal to the OpenC906 core*: the core +BIU decodes the T-Head c900 CLINT layout inside the reserved system window at #code(r.base_hex) +(size #r.size_label), which never appears as a SoC fabric target. This chapter therefore has +*no SoC register table*; register-bit detail follows the T-Head C906 manuals, which remain +outside this publication's scope together with the CPU ISA/CSR manuals. -#ip-reference("hp-aclint","aclint",5,legacy:[ +#subhead("hp-aclint","Features and Block Diagram",5) +#list(..chapter.at("features",default:()).map(inline)) +#block(breakable:false)[ + #figure(circuit-diagram("hp-aclint"),kind:image,supplement:[Figure],caption:[#chapter.title integration boundary.]) + #label("circuit-hp-aclint") + ] -The HP ACLINT supplies local software and timer interrupts to VexiiRiscv. The PLIC -handles external interrupt sources, including the separate mailbox doorbell. These -controllers have *distinct address windows and interrupt semantics*. -]) +#subhead("hp-aclint","Functional Description",5) +#for paragraph in chapter.notes { par(inline(paragraph)) } + +#subhead("hp-aclint","Software",5) +#enum(..chapter.software_steps.map(inline)) +#block(breakable:false)[ + #set text(size:9pt) + #source("rtl/mini/top/hp_core_wrapper.sv",title:"Internal window and time/counter wiring") · + #source("app/ports/linux/opensbi/retrosoc_hp/platform.c",title:"OpenSBI MSWI and timer device") · + #source("app/ports/linux/linux/retrosoc_hp.dts",title:"thead,c900-clint declaration") +] #context metadata((kind:"ip-end",id:"hp-aclint",page:here().page())) diff --git a/publications/datasheets/ips/hp-mailbox.typ b/publications/datasheets/ips/hp-mailbox.typ index b69a46cc..437fa9e3 100644 --- a/publications/datasheets/ips/hp-mailbox.typ +++ b/publications/datasheets/ips/hp-mailbox.typ @@ -9,7 +9,7 @@ ===== LP/HP Mailbox #let r=data.regions.find(r=>r.symbol=="APB4_HP_MAILBOX") -Base address: #code(r.base_hex). Window size: #r.size_label. LP IRQ25 and HP PLIC source 2. +Base address: #code(r.base_hex). Window size: #r.size_label. LP IRQ25 and HP external source 2 (PLIC ID 18). #ip-reference("hp-mailbox","mailbox",5,legacy:[ diff --git a/publications/datasheets/ips/hp-plic.typ b/publications/datasheets/ips/hp-plic.typ index 088c833a..d777f0c5 100644 --- a/publications/datasheets/ips/hp-plic.typ +++ b/publications/datasheets/ips/hp-plic.typ @@ -1,6 +1,7 @@ #import "../style.typ": * -#import "../ip-reference.typ": ip-reference +#import "../ip-reference.typ": inline, subhead +#import "../diagram-packages.typ": circuit-diagram #pagebreak(weak:true) @@ -8,12 +9,32 @@ ===== HP Platform-Level Interrupt Controller (PLIC) -#let r=data.regions.find(r=>r.symbol=="HP_PLIC") -Base address: #code(r.base_hex). Window size: #r.size_label. HP machine and supervisor external interrupts. +#let chapter=data.chapters.at("plic") +#let r=data.regions.find(r=>r.symbol=="HP_C906_SYS") +The HP external interrupt controller is *internal to the OpenC906 core*: the core BIU decodes +the T-Head c900 PLIC layout at the base of the reserved system window at #code(r.base_hex) +(size #r.size_label), which never appears as a SoC fabric target. This chapter therefore has +*no SoC register table*; register-bit detail follows the T-Head C906 manuals, which remain +outside this publication's scope together with the CPU ISA/CSR manuals. -#ip-reference("hp-plic","plic",5,legacy:[ +#subhead("hp-plic","Features and Block Diagram",5) +#list(..chapter.at("features",default:()).map(inline)) +#block(breakable:false)[ + #figure(circuit-diagram("hp-plic"),kind:image,supplement:[Figure],caption:[#chapter.title integration boundary.]) + #label("circuit-hp-plic") + ] -]) +#subhead("hp-plic","Functional Description",5) +#for paragraph in chapter.notes { par(inline(paragraph)) } + +#subhead("hp-plic","Software",5) +#enum(..chapter.software_steps.map(inline)) +#block(breakable:false)[ + #set text(size:9pt) + #source("rtl/mini/top/hp_core_wrapper.sv",title:"Source wiring into the core") · + #source("rtl/mini/top/apb4_periph.sv",title:"SoC external source assignments") · + #source("app/ports/linux/linux/retrosoc_hp.dts",title:"thead,c900-plic declaration") +] #context metadata((kind:"ip-end",id:"hp-plic",page:here().page())) diff --git a/publications/datasheets/ips/resource.typ b/publications/datasheets/ips/resource.typ index f9faa4a9..88a65eaf 100644 --- a/publications/datasheets/ips/resource.typ +++ b/publications/datasheets/ips/resource.typ @@ -13,7 +13,7 @@ #ip-reference("resource","resource",4,legacy:[ *Ten resources* are managed: central DMA, USB2, SDIO0, SDIO1, SPI-SD, EXT-H, JPEG, APU, GA2D and NPU. Resource ABI 1.2 reports ten slots. Resource 9 owns the native-HP -NPU, including LP vector 33 / HP PLIC 12 steering. Resource 8 routes the GA2D +NPU, including LP vector 33 / HP external source 12 (PLIC ID 28) steering. Resource 8 routes the GA2D its IRQ according to its current owner and controls its private AXI64 lifecycle. GA2D supports FILL, COPY, bit-exact CONVERT, opaque alpha BLEND, A8 fixed-color foreground masks, and exact equal background/destination in-place composition. diff --git a/publications/datasheets/ips/uart1.typ b/publications/datasheets/ips/uart1.typ index 484c843a..caef8243 100644 --- a/publications/datasheets/ips/uart1.typ +++ b/publications/datasheets/ips/uart1.typ @@ -12,7 +12,7 @@ #ip-reference("uart1","uart",5,shared:"uart0",legacy:[ UART1 uses the *same 64-byte FIFO UART v3 ABI*, not a separate non-FIFO implementation. Its -dedicated TX/RX pads serve the HP console. HP PLIC source 1 is distinct from the LP vector +dedicated TX/RX pads serve the HP console. HP external source 1 (PLIC ID 17) is distinct from the LP vector number above. The initial Linux console uses OpenSBI/hvc0; a *native Linux UART driver remains a separate delivery item*. ]) diff --git a/publications/datasheets/overview-groups.json b/publications/datasheets/overview-groups.json index add9fae7..d45f551d 100644 --- a/publications/datasheets/overview-groups.json +++ b/publications/datasheets/overview-groups.json @@ -3,7 +3,7 @@ "title": "Processors and Debug", "items": [ "Hazard3", - "VexiiRiscv", + "OpenC906", "JTAG" ] }, @@ -31,8 +31,6 @@ "title": "Interrupts and IPC", "items": [ "LP CLINT", - "HP ACLINT", - "HP PLIC", "LP/HP Mailbox" ] }, diff --git a/publications/datasheets/register-annotations.json b/publications/datasheets/register-annotations.json index 1c093925..4aedce56 100644 --- a/publications/datasheets/register-annotations.json +++ b/publications/datasheets/register-annotations.json @@ -7069,76 +7069,6 @@ "description": "Machine time bits 63:32." } }, - "aclint": { - "msip.MSIP": { - "fields": [ - { - "name": "PENDING", - "lsb": 0, - "msb": 0, - "description": "Machine software-interrupt request for this hart.", - "reset": "0x0", - "expression": "reviewed field" - }, - { - "name": "Reserved", - "lsb": 1, - "msb": 31, - "description": "Reserved; write zero.", - "reset": "0x0", - "expression": "reserved" - } - ], - "access": "RW", - "reset": "0", - "description": "Per-hart software interrupt pending bit." - }, - "compare.MTIMECMP": { - "fields": [ - { - "name": "VALUE", - "lsb": 0, - "msb": 31, - "description": "Comparator bits 31:0.", - "reset": "0xffffffff", - "expression": "reviewed field" - } - ], - "access": "RW", - "reset": "0xFFFFFFFF", - "description": "Comparator bits 31:0." - }, - "main.MTIME": { - "fields": [ - { - "name": "VALUE", - "lsb": 0, - "msb": 31, - "description": "Machine time bits 31:0.", - "reset": "0x0", - "expression": "reviewed field" - } - ], - "access": "RW", - "reset": "0", - "description": "Machine time bits 31:0." - }, - "main.MTIMEH": { - "fields": [ - { - "name": "VALUE", - "lsb": 0, - "msb": 31, - "description": "Machine time bits 63:32.", - "reset": "0x0", - "expression": "reviewed field" - } - ], - "access": "RW", - "reset": "0", - "description": "Machine time bits 63:32." - } - }, "mpw-timer": { "main.USER_IP_APB_ID": { "fields": [ diff --git a/publications/datasheets/register-profiles.json b/publications/datasheets/register-profiles.json index 3d838724..b8b8827e 100644 --- a/publications/datasheets/register-profiles.json +++ b/publications/datasheets/register-profiles.json @@ -2233,251 +2233,6 @@ ], "support": [] }, - "plic": { - "document": "docs/ip/hp-platform.md", - "defines": [], - "rtl": [ - "rtl/ip/peripheral/apb4_plic.sv" - ], - "parameters": { - "NumMasters": 8, - "NumTargets": 6, - "ResourceCount": 8 - }, - "groups": [ - { - "id": "priority", - "title": "Source priorities", - "pattern": "(?!)", - "strip": "^", - "base": 0, - "stride": 4, - "count": 32 - }, - { - "id": "pending", - "title": "Pending sources", - "pattern": "(?!)", - "strip": "^", - "base": 4096, - "stride": 0, - "count": 1 - }, - { - "id": "enable", - "title": "Context enables", - "pattern": "(?!)", - "strip": "^", - "base": 8192, - "stride": 128, - "count": 2 - }, - { - "id": "context", - "title": "Context threshold and claim", - "pattern": "(?!)", - "strip": "^", - "base": 2097152, - "stride": 4096, - "count": 2 - } - ], - "extra": [ - { - "group": "priority", - "name": "PRIORITY", - "offset": 0, - "access": "RW", - "reset": "0", - "description": "Per-source three-bit priority.", - "fields": [ - { - "name": "PRIORITY", - "lsb": 0, - "msb": 2, - "description": "Priority 0 disables delivery; source 0 is reserved and hardwired zero.", - "reset": "Register reset applies", - "expression": "reviewed semantic field" - }, - { - "name": "Reserved", - "lsb": 3, - "msb": 31, - "description": "Reserved; preserve zero when writing.", - "reset": "0", - "expression": "reserved" - } - ] - }, - { - "group": "pending", - "name": "PENDING", - "offset": 0, - "access": "RO", - "reset": "0", - "description": "Pending sources; claim changes pending/claimed state.", - "fields": [ - { - "name": "Reserved", - "lsb": 0, - "msb": 0, - "description": "Reserved; preserve zero when writing.", - "reset": "0", - "expression": "reserved" - }, - { - "name": "PENDING", - "lsb": 1, - "msb": 31, - "description": "Bit n indicates pending source n. Source 0 remains zero.", - "reset": "Register reset applies", - "expression": "reviewed semantic field" - } - ] - }, - { - "group": "enable", - "name": "ENABLE", - "offset": 0, - "access": "RW", - "reset": "0", - "description": "Context source mask; context 0 is machine and context 1 supervisor.", - "fields": [ - { - "name": "Reserved", - "lsb": 0, - "msb": 0, - "description": "Reserved; preserve zero when writing.", - "reset": "0", - "expression": "reserved" - }, - { - "name": "ENABLE", - "lsb": 1, - "msb": 31, - "description": "Enable source n for this context. Source 0 cannot be enabled.", - "reset": "Register reset applies", - "expression": "reviewed semantic field" - } - ] - }, - { - "group": "context", - "name": "THRESHOLD", - "offset": 0, - "access": "RW", - "reset": "0", - "description": "Interrupt delivery threshold.", - "fields": [ - { - "name": "THRESHOLD", - "lsb": 0, - "msb": 2, - "description": "Only a source with priority strictly greater than this value is eligible.", - "reset": "Register reset applies", - "expression": "reviewed semantic field" - }, - { - "name": "Reserved", - "lsb": 3, - "msb": 31, - "description": "Reserved; preserve zero when writing.", - "reset": "0", - "expression": "reserved" - } - ] - }, - { - "group": "context", - "name": "CLAIM_COMPLETE", - "offset": 4, - "access": "RO claim / WO complete", - "reset": "0", - "description": "Claim and complete register; reads and writes have different side effects.", - "fields": [ - { - "name": "SOURCE_ID", - "lsb": 0, - "msb": 4, - "description": "Read claims the winning source, or zero if none. Write the nonzero claimed ID to complete it.", - "reset": "Register reset applies", - "expression": "reviewed semantic field" - }, - { - "name": "Reserved", - "lsb": 5, - "msb": 31, - "description": "Reserved; preserve zero when writing.", - "reset": "0", - "expression": "reserved" - } - ] - } - ], - "support": [] - }, - "aclint": { - "document": "docs/ip/clint.md", - "defines": [ - "rtl/ip/peripheral/clint_define.svh" - ], - "rtl": [ - "rtl/ip/peripheral/clint_reg.sv" - ], - "parameters": { - "HartNum": 2 - }, - "groups": [ - { - "id": "msip", - "title": "Per-hart software interrupt", - "pattern": "APB4_CLINT_MSIP", - "strip": "^APB4_CLINT_", - "base": 0, - "stride": 4, - "count": 2 - }, - { - "id": "compare", - "title": "Per-hart timer comparator", - "pattern": "APB4_CLINT_MTIMECMP", - "strip": "^APB4_CLINT_", - "base": 0, - "stride": 8, - "count": 2 - }, - { - "id": "main", - "title": "Shared 64-bit time", - "pattern": "APB4_CLINT_MTIMEH?", - "strip": "^APB4_CLINT_", - "base": 0, - "stride": 0, - "count": 1 - } - ], - "extra": [ - { - "group": "compare", - "name": "MTIMECMP_HI", - "offset": 16388, - "access": "RW", - "reset": "0xFFFFFFFF", - "description": "High word of the per-hart 64-bit machine timer comparator.", - "fields": [ - { - "name": "VALUE", - "lsb": 0, - "msb": 31, - "description": "Comparator bits 63:32.", - "reset": "Register reset applies", - "expression": "reviewed field" - } - ] - } - ], - "support": [] - }, "mpw-timer": { "document": "docs/ip/user-ip.md", "defines": [], diff --git a/publications/datasheets/sections/architecture.typ b/publications/datasheets/sections/architecture.typ index b4434b34..8cbe7ca0 100644 --- a/publications/datasheets/sections/architecture.typ +++ b/publications/datasheets/sections/architecture.typ @@ -24,11 +24,13 @@ halt, resume, register and system-bus access. LP retains control while HP is hel #source-note("docs/hazard3-debug.md", title:"Management debug transport and acceptance flow") === Application Processor -==== VexiiRiscv -The generated HP hart is a dual-issue RV64IMAFDC + Zicbom configuration, with supervisor/user -modes, Sv39 virtual memory and *64-byte cache-maintenance blocks*. Hart 1 uses native AXI64 -instruction and data paths. Its uncached MMIO path is downsized and crosses into the LP -control plane. OpenSBI/Linux inputs and generated-core configuration are dependency-locked. +==== OpenC906 +The HP hart is the locked T-Head OpenC906 pre-generated RTL in its default RV64GC +configuration, with supervisor/user modes and Sv39 virtual memory. Hart 1 issues a single +*128-bit AXI4 master*, downsized to the 64-bit HP data fabric and split into memory and MMIO +ports by address window. The uncached MMIO path is downsized further and crosses into the LP +control plane. Its CLINT/PLIC are *core-internal* (c900 layouts) and never appear as SoC +fabric targets. OpenSBI/Linux inputs and the vendored core revision are dependency-locked. #source-note("docs/lp-hp-architecture.md", title:"LP/HP architecture and boot contract") #include "processor-details.typ" @@ -70,7 +72,7 @@ An allowed entry does not guarantee throughput.] #pagebreak() #figure(matrix-diagram(), caption:[AXI64 memory access matrix: R = read, W = write, - = denied.]) -The I-cache is the only instruction-permitted initiator. HP cache attributes are preserved; +The HP memory master is the only instruction-permitted initiator. HP cache attributes are preserved; DMA, I/O gateways, LP gateway, JPEG, EXT-H, GA2D and NPU require non-cacheable transactions. XPI is read-only on this data plane; indirect writes use its APB-controlled command engine. @@ -94,7 +96,8 @@ advertise an implemented IP. data.regions.filter(r=>r.route in ("axi4","ram","reserved") and r.size > 4096).map(r=>( code(r.symbol),code(r.base_hex),code(r.end_hex),r.size_label)), widths:(1fr,1.1fr,1.1fr,0.65fr), - notes:[FLASH is the reset/boot alias. SPISD's former card-data aperture is reserved. The physical + notes:[FLASH is the reset/boot alias. SPISD's former card-data aperture is reserved. HP_C906_SYS + is reserved for the HP core's internal CLINT/PLIC decode; it is not a SoC fabric target. The physical capacity of fitted XPI/OPI devices remains board-dependent.], ) #ds-table("registers", [Register and interrupt-controller windows], @@ -150,7 +153,7 @@ qualification. No crystal-oscillator range or maximum core frequency is specifie == Interrupt System The management interrupt vector is 64 bits wide; two local causes and 62 external positions are distinct from the currently allocated source list. The following numbers are -LP vector bits, not HP PLIC source IDs. Peripheral-level status registers identify causes +LP vector bits, not HP PLIC IDs. Peripheral-level status registers identify causes within an aggregate source. Resource-controlled interrupts are routed according to ownership. #ds-table("lp-irqs", [LP interrupt vector], ([LP bit], [Source], [Description]), @@ -158,13 +161,16 @@ within an aggregate source. Resource-controlled interrupts are routed according widths:(0.45fr,1.25fr,2fr), ) -HP has local software/timer interrupts and a 32-source, two-context PLIC. Source 0 is -reserved; sources 1-12 are UART1, mailbox, EXT-H, DMA, USB2, SDIO0, SDIO1, SPI-SD, JPEG, APU, -GA2D and NPU. Sources 13-31 are reserved. GA2D uses LP vector bit 32 (external ordinal 30), -which is distinct from HP PLIC source 11; NPU uses LP vector bit 33 (external ordinal 31) -or HP PLIC source 12 according to Resource Controller ownership. The contexts drive machine -and supervisor external interrupts. -Claim/complete and priority rules are defined in the HP platform contract. +HP local software/timer interrupts come from the core-internal CLINT, and external sources +from the core-internal PLIC (T-Head c900 layouts, decoded inside the OpenC906 core). Sixteen +SoC external sources are wired; *SoC source n reaches software as PLIC ID n+16*. Source 1 is +UART1, source 2 is the mailbox doorbell, source 3 is EXT-H, and sources 4-12 are the +resource-owned DMA, USB2, SDIO0, SDIO1, SPI-SD, JPEG, APU, GA2D and NPU lines; sources 13-15 +are reserved. GA2D uses LP vector bit 32 (external ordinal 30), +which is distinct from HP external source 11; NPU uses LP vector bit 33 (external ordinal 31) +or HP external source 12 according to Resource Controller ownership. The PLIC drives the +hart's machine and supervisor external interrupts. +Claim/complete and priority rules follow the T-Head C906 manuals. #block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[ #set text(size:9pt) #source("docs/ip/hp-platform.md",title:"HP PLIC, local interrupts and mailbox") · LP software: @irq-runtime diff --git a/publications/datasheets/sections/clock-programming.typ b/publications/datasheets/sections/clock-programming.typ index 948b9324..91de97a9 100644 --- a/publications/datasheets/sections/clock-programming.typ +++ b/publications/datasheets/sections/clock-programming.typ @@ -12,7 +12,7 @@ the domains; the table below records which clock must be supplied to the relevan (([UART / I2C / general timer],[Actual clock driving the selected engine; check PCLK/root routing.],[Recalculate divisors/timing or counter period after that clock changes.]), ([I2S],[External audio-domain frequency, not the HP CPU clock.],[Select a compatible preset or exact programmable divisors while disabled.]), ([SDRAM / QPI / OPI / XPI],[Stable memory domain plus the controller's local divider/sampling convention.],[Convert device timing to controller cycles and reinitialize where required.]), - ([LP CLINT / HP ACLINT],[Configured CLINT timebase. The reference configuration selects 1 MHz.],[Use the timebase for deadlines rather than a core instruction frequency.]), + ([LP CLINT / HP time base],[Configured CLINT timebase; the HP core receives the 64-bit time value and software reads the time CSR. The reference configuration selects 1 MHz.],[Use the timebase for deadlines rather than a core instruction frequency.]), ([RTC / watchdog],[Their actual independent timing source and divider contract.],[Do not infer their tick from a CPU frequency change.]), ([DVP / ULPI / JTAG],[Externally supplied functional clock under the interface contract.],[Validate external clock availability and board timing separately.])), widths:(0.95fr,1.55fr,1.7fr)) diff --git a/publications/datasheets/sections/linux-runtime.typ b/publications/datasheets/sections/linux-runtime.typ index bb6c6a24..de1d4752 100644 --- a/publications/datasheets/sections/linux-runtime.typ +++ b/publications/datasheets/sections/linux-runtime.typ @@ -5,18 +5,20 @@ === OpenSBI platform and console path The supplied OpenSBI platform exposes *one application hart*, with hart ID #platform.hart_id. -LP remains the separate management firmware processor. The platform's ACLINT descriptor covers -two hart-indexed register positions beginning at zero so it can address hart 1; that storage +LP remains the separate management firmware processor. The platform's software-interrupt +descriptor targets the core-internal CLINT with first hart ID 1 and hart count 1; that storage range is not a declaration that Linux runs on both harts. The *kernel configuration disables SMP*. The early platform setup programs UART1, registers its polled console and initializes machine -software-interrupt support. Timer initialization uses the ACLINT machine timer. Console writes +software-interrupt support. Timer initialization registers a custom timer device that reads +the time CSR and programs the core-internal MTIMECMP; there is *no memory-mapped mtime*. +Console writes wait while TX is full; this loop has *no local timeout*. These implemented callbacks do not establish that all optional SBI services or all peripherals have native Linux drivers. #figure(sequence-diagram(( [*LP handoff* \ Existing bundle validation \ Release HP at OpenSBI], - [*OpenSBI on hart 1* \ UART1 SBI console \ ACLINT platform setup], + [*OpenSBI on hart 1* \ UART1 SBI console \ CLINT timer/MSWI setup], [*FW_JUMP* \ Enter Linux Image \ Pass the prepared DTB], [*Kernel / initramfs* \ SBI early console and hvc0 \ Run /init], [*Rootfs ready service* \ Print ready text \ Publish mailbox fields], @@ -27,11 +29,11 @@ The kernel uses #code(platform.bootargs). Console text therefore reaches UART1 t path in this configuration. The UART1 device-tree node's presence does not substitute for a native driver. The configured machine timer and software-interrupt path are distinct from external interrupt-controller and custom peripheral driver integration. -#source-note("app/ports/linux/opensbi/retrosoc_hp/platform.c",title:"Hart mapping, console callbacks and ACLINT setup") +#source-note("app/ports/linux/opensbi/retrosoc_hp/platform.c",title:"Hart mapping, console callbacks and timer/MSWI setup") #source-note("app/ports/linux/linux/retrosoc_hp.config",title:"RV64, SBI console and single-hart kernel configuration") === Device-tree and image consistency -The device-tree template, OpenSBI build arguments, boot-bundle bounds and actual generated HP +The device-tree template, OpenSBI build arguments, boot-bundle bounds and actual integrated HP core must agree. The existing image addresses in @boot-configuration remain authoritative; the following values explain the platform relationship rather than defining a second layout. @@ -39,11 +41,11 @@ the following values explain the platform relationship rather than defining a se ([Property],[Source value],[Consistency boundary]), (([CPU identity],[Hart #platform.hart_id],[Match OpenSBI's hart-index map and the generated core.]), ([Main memory],[#code(platform.memory_base), #(platform.memory_bytes / 1024 / 1024) MiB],[Device-tree envelope; actual external memory and boot-loader bounds must agree.]), - ([Timer base rate],[#platform.timebase_hz Hz],[Match ACLINT timebase-frequency and the OpenSBI mtimer declaration.]), + ([Timer base rate],[#platform.timebase_hz Hz],[Match the device-tree timebase-frequency and the OpenSBI timer-frequency declaration.]), ([CPU / UART clock declarations],[#platform.clock_hz Hz],[Nominal template values, not measured or dynamically synchronized frequencies.]), - ([MMU / cache maintenance],[Sv39; #(platform.cbom_bytes)-byte CBO blocks],[Software metadata must be checked against the generated HP artifact.]), + ([MMU / cache maintenance],[Sv39; 64-byte D-cache lines via T-Head extended operations],[Software must enable the extended instruction set before using the maintenance encodings.]), ([Initial ramdisk],[Start #code("0x"+str(platform.initrd_start,base:16))],[The source template's equal start/end is patched using the built uncompressed CPIO size.]), - ([Interrupt controllers],[ACLINT CPU causes; PLIC machine/supervisor contexts],[A DT node and binding alone do not demonstrate a complete driver or interrupt acceptance test.])), + ([Interrupt controllers],[Core-internal CLINT CPU causes; core-internal PLIC machine/supervisor contexts],[A DT node and binding alone do not demonstrate a complete driver or interrupt acceptance test.])), widths:(1fr,1.3fr,2.15fr)) The image builder replaces linux,initrd-end with the start plus the actual rootfs.cpio size. diff --git a/publications/datasheets/sections/memory-use.typ b/publications/datasheets/sections/memory-use.typ index a0da2b18..3580ba27 100644 --- a/publications/datasheets/sections/memory-use.typ +++ b/publications/datasheets/sections/memory-use.typ @@ -29,16 +29,17 @@ programming uses the command engine. Reserved ranges and inactive QPI/OPI window used as scratch space. Physical device capacity must match the controller and board setup. === Buffer ownership and alignment -The supplied HP platform metadata declares Zicbom with a 64-byte cache-maintenance block. Round shared -maintenance ranges to full blocks and *prevent unrelated owners from sharing a boundary block*. +The OpenC906 HP hart maintains its 64-byte D-cache lines with T-Head extended cache +operations (XTheadCmo). Round shared +maintenance ranges to full lines and *prevent unrelated owners from sharing a boundary line*. *Check address-plus-length overflow* before rounding. Device descriptors can impose additional alignment, byte-count, stride and memory-placement constraints; the DMA TCD is a separate 64-byte descriptor contract, not a universal transfer-alignment rule for every IP. -#figure(cache-boundary-diagram(),kind:image,supplement:[Figure],caption:[Software-declared maintenance blocks around a shared-buffer range.]) -Match the platform declaration to the generated HP artifact before deployment; this schematic +#figure(cache-boundary-diagram(),kind:image,supplement:[Figure],caption:[HP D-cache maintenance lines around a shared-buffer range.]) +Match the maintenance operations to the vendored HP core before deployment; this schematic does not independently establish physical cache-line geometry or total cache capacity. -#source-note("app/ports/linux/linux/retrosoc_hp.dts",title:"Software-declared cache-maintenance block size") +#source-note("app/ports/linux/smoke/start.S",title:"C906 cache-maintenance instruction encodings") #ds-table("buffer-ownership",[Shared-buffer responsibilities], ([Actor],[Responsibility before handoff],[Responsibility after completion]), @@ -70,8 +71,8 @@ does not independently establish physical cache-line geometry or total cache cap operation, then transfer the buffer to the application. These are integration sequences, not a new cache HAL. Linux drivers must use the DMA mapping -and synchronization interfaces appropriate to their platform. The existence of Zicbom and a -device-tree block-size property does not establish complete Linux DMA coherency integration. +and synchronization interfaces appropriate to their platform. The existence of core cache +maintenance operations does not establish complete Linux DMA coherency integration. === LP-to-HP and HP-to-LP handoff #figure(sequence-diagram(( @@ -93,6 +94,6 @@ transaction at the protocol level; retries require a new ownership decision. #source-note("docs/lp-hp-architecture.md",title:"Memory paths and non-coherent ownership contract") #source-note("docs/ip/resource-controller.md",title:"Cache request and clean acknowledgement") #source-note("docs/ip/dma.md",title:"DMA descriptors, transfer restrictions and completion") -#source-note("app/ports/linux/linux/retrosoc_hp.dts",title:"Linux RAM and cache-maintenance properties") +#source-note("app/ports/linux/linux/retrosoc_hp.dts",title:"Linux RAM and platform properties") #change-end("v05-emphasis-memory-use") diff --git a/publications/datasheets/sections/overview.typ b/publications/datasheets/sections/overview.typ index ce5b638e..52aebccc 100644 --- a/publications/datasheets/sections/overview.typ +++ b/publications/datasheets/sections/overview.typ @@ -36,7 +36,7 @@ #set list(tight:false,spacing:rhythm.cover-list-spacing,body-indent:rhythm.cover-list-indent) *Compute and control* - Hazard3 LP: boot, clocks, resource ownership and fault recovery. - - Dual-issue VexiiRiscv HP: RV64IMAFDC + Zicbom, Sv39. + - OpenC906 HP: RV64GC, Sv39, single 128-bit AXI4 master. - NPU: *64 dense MACs*, eight INT8 operator classes and 64 KiB private SRAM. - JTAG debug; fixed EXT-L control and EXT-H AXI64 slots. @@ -90,7 +90,7 @@ retained document title; no separate derivative specifications are inferred.] #change-start("v05-overview","NPU-inclusive functional inventory and configuration reference") retroSoC Mini combines a small management processor with an application processor and shared memory and I/O. Hazard3 retains authority over startup, clock transitions, resource ownership -and fault recovery. VexiiRiscv supplies the application-side compute and Linux integration. +and fault recovery. OpenC906 supplies the application-side compute and Linux integration. The design is intended for embedded control, basic human-machine interfaces, retro multimedia experimentation, education and ASIC prototyping. diff --git a/publications/datasheets/sections/processor-details.typ b/publications/datasheets/sections/processor-details.typ index b23b6bb0..0ee7c0bf 100644 --- a/publications/datasheets/sections/processor-details.typ +++ b/publications/datasheets/sections/processor-details.typ @@ -3,64 +3,59 @@ #let cpu = data.system_reference.product_details.cpu === Processor Configuration and Software-visible Capabilities -The table separates the actual LP instance arguments, the explicit HP generator settings and +The table separates the actual LP instance arguments, the fixed HP OpenC906 integration and the selected firmware build. It is a *configuration summary*, not a replacement for the CPU ISA/CSR manuals. A software compiler option does not remove a hardware extension or CSR block. #ds-table("processor-config",[Processor settings and the reference software configuration], - ([Property],[LP: instantiated Hazard3],[HP: explicit VexiiRiscv generator configuration]), - (([Hart / role],[Hart 0; root management.],[Hart 1; application/Linux platform.]), - ([Execution width],[RV32 integration.],[XLEN #cpu.hp.xlen / physical address width #cpu.hp.physicalWidth.]), - ([Configured extensions],cpu.lp_extensions.join(", "),cpu.hp_isa.filter(x=>not(x in ("s","u"))).join(", ")), - ([Privilege],[Machine-mode configuration, U_MODE = #cpu.lp.U_MODE.],[S and U selected by the generator, in addition to machine-mode operation.]), - ([MMU / software platform],[No LP MMU is advertised by this integration.],[Supplied software platform declares Sv39; verify agreement with the generated core before deployment.]), - ([Protection],[PMP_REGIONS = #cpu.lp.PMP_REGIONS.],[PMP entries = #cpu.hp.at("pmpParam.pmpSize") / granularity = #cpu.hp.at("pmpParam.granularity") bytes.]), - ([Reset entry],code(data.reset_address),code(cpu.hp.resetVector.trim("L",at:end))), - ([Trap / counter configuration],[MTVEC_INIT: #code(cpu.lp.MTVEC_INIT) \ Machine CSR: #cpu.lp.CSR_M_MANDATORY / counters: #cpu.lp.CSR_COUNTER.],[ASID width #cpu.hp.asidWidth and #cpu.hp.additionalPerformanceCounters additional performance counters. \ Time-read option: #cpu.hp.at("privParam.withRdTime").]), - ([Debug],[DEBUG_SUPPORT = #cpu.lp.DEBUG_SUPPORT \ Breakpoint triggers: #cpu.lp.BREAKPOINT_TRIGGERS.],[Embedded JTAG/debug configured; triggers #cpu.hp.at("privParam.debugTriggers").]), - ([Issue configuration],[Use the selected Hazard3 instance and upstream core contract.],[#cpu.hp.decoders decoders and #cpu.hp.lanes lanes configured.])), + ([Property],[LP: instantiated Hazard3],[HP: locked OpenC906 default configuration]), + (([Hart / role],[Hart 0; root management.],[Hart #cpu.hp.hartId; application/Linux platform.]), + ([Execution width],[RV32 integration.],[RV64 (#code(cpu.hp_isa_base) base); the core drives 40-bit addresses over a 32-bit physical fabric.]), + ([Configured extensions],cpu.lp_extensions.join(", "),[#cpu.hp_isa.join(", ") (the RV64GC set).]), + ([Privilege],[Machine-mode configuration, U_MODE = #cpu.lp.U_MODE.],[M/S/U per the C906 default configuration; the supplied software platform declares #cpu.hp_mmu.]), + ([Protection],[PMP_REGIONS = #cpu.lp.PMP_REGIONS.],[PMP per the T-Head C906 manuals; entry geometry is not separately extracted in this publication.]), + ([Reset entry],code(data.reset_address),code(cpu.hp.resetVector)), + ([Trap / counter configuration],[MTVEC_INIT: #code(cpu.lp.MTVEC_INIT) \ Machine CSR: #cpu.lp.CSR_M_MANDATORY / counters: #cpu.lp.CSR_COUNTER.],[No memory-mapped mtime; HP software reads the time CSR.]), + ([Debug],[DEBUG_SUPPORT = #cpu.lp.DEBUG_SUPPORT \ Breakpoint triggers: #cpu.lp.BREAKPOINT_TRIGGERS.],[JTAG debug through the core-internal Debug Module and the external DTM; the debug system-bus master is unconnected.]), + ([Bus interfaces],[Use the selected Hazard3 instance and upstream core contract.],[One #(cpu.hp.coreAxiDataWidth)-bit AXI4 master, downsized to the #(cpu.hp.fabricAxiDataWidth)-bit HP fabric; internal CLINT/PLIC window at #code(cpu.hp.sysWindowBase).])), widths:(0.8fr,1.6fr,1.75fr)) The reference LP build uses #code(cpu.build.ISA) with #code("HAVE_CSR="+cpu.build.HAVE_CSR). Those build choices are separate from the instantiated LP extension and mandatory CSR settings. -The HP profile selects #code(cpu.build.HP_CONFIG). OpenSBI, the device tree and the kernel -configuration *must remain consistent with the core that is actually generated and used*. +The HP core is the dependency-locked OpenC906 pre-generated RTL in its default configuration; +there is no Mini-side generator selection. OpenSBI, the device tree and the kernel +configuration *must remain consistent with the core that is actually integrated and used*. ==== Cache geometry and evidence basis -#ds-table("processor-cache-evidence",[Cache and generated-core evidence boundaries], +#ds-table("processor-cache-evidence",[Cache and vendored-core evidence boundaries], ([Item],[Recorded configuration],[Qualification]), - (([HP instruction cache],[Enable setting #cpu.hp.fetchL1Enable with #cpu.hp.fetchL1Sets sets and #cpu.hp.fetchL1Ways ways; minimum memory data width #cpu.hp.fetchMemDataWidthMin bits.],[Explicit generator settings.]), - ([HP data cache],[Enable setting #cpu.hp.lsuL1Enable with #cpu.hp.lsuL1Sets sets and #cpu.hp.lsuL1Ways ways; minimum memory data width #cpu.hp.lsuMemDataWidthMin bits.],[Explicit generator settings.]), - ([Cache total capacity],cpu.hp_cache_capacity,[Sets multiplied by ways is *not a byte capacity* without the reviewed block size.]), - ([Cache maintenance],[Zicbom selected; supplied platform metadata declares a 64-byte CBO block.],[Keep platform metadata and the eventual generated implementation consistent.]), + (([HP instruction cache],[32 KiB in the default OpenC906 configuration.],[Vendored default configuration; see the qualification note below.]), + ([HP data cache],[32 KiB in the default OpenC906 configuration; 64-byte lines.],[Vendored default configuration; see the qualification note below.]), + ([Cache total capacity],cpu.hp_cache_capacity,[Do not relabel a configured feature as a tested or silicon capability.]), + ([Cache maintenance],[T-Head extended operations (XTheadCmo custom-0 dcache clean/invalidate by address) on 64-byte lines; no Zicbom CBO block.],[Used by the supplied HP smoke image; the extended instruction set must be enabled in the machine status CSR first.]), ([Locked HP source],[#code(cpu.hp_revision.slice(0,12))],[The full dependency revision is recorded in the lock and publication manifest.]), - ([Generated HP artifact],cpu.generated_artifact_basis,[No new HP RTL generation or independent generated-manifest validation was performed for this publication.])), + ([Vendored HP RTL],cpu.generated_artifact_basis,[The Mini mhartid = #cpu.hp.hartId assignment comes from the reviewed override file, not from editing the vendored checkout.])), widths:(0.8fr,1.7fr,1.65fr)) -The current publication workspace does not supply the locked VexiiRiscv checkout and a matching -generated-core manifest for independent inspection. Only explicit repository generator settings -are listed as such. Upstream defaults, plugin expansion and derived byte capacities remain -unconfirmed until that artifact/source evidence is attached. Do not relabel a configured feature -as a tested generated-core or silicon capability. +The vendored OpenC906 checkout is a locked, managed input; the C906 user and integration +manuals ship with it and remain the register/CSR reference. This publication lists only +integration-visible settings and does not re-derive upstream implementation parameters. -==== PMA coverage versus implemented memory -#ds-table("hp-pma-coverage",[Explicit PMA envelopes in the HP generator], - ([Base],[Inclusive end],[Bytes],[Main memory],[Executable]), - cpu.pma.map(r=>(code(r.base),code(r.end),str(r.bytes),r.main,r.executable)), - widths:(1.1fr,1.1fr,0.8fr,0.65fr,0.65fr)) -A PMA envelope describes core-side attributes. It does not instantiate RAM or override the -SoC decoder, per-master ACL, resource owner or physical device. In particular, the generator's -SRAM attribute envelope is larger than the reference profile's 32 KiB physical SRAM region. -Use the generated address map and selected profile for capacity and valid access bounds. +==== System window and address decode +The HP core decodes its internal CLINT/PLIC window at #code(cpu.hp.sysWindowBase) inside the +core BIU; the matching 128 MiB SoC range is reserved and never reaches the external fabric. +The reset vector #code(cpu.hp.resetVector) and the 32-bit physical fabric are unchanged by the +core swap. Per-hart identity is fixed at integration time: the LP Hazard3 reports mhartid 0 +and the HP OpenC906 reports mhartid 1 through the reviewed override. -Before deploying a new HP image, retain the lock revision, generator source, generated RTL/hash -manifest and software build identity together. Check the core/device-tree feature agreement and +Before deploying a new HP image, retain the lock revision, vendored source identity, override +file and software build identity together. Check the core/device-tree feature agreement and the existing non-coherent buffer protocol. LP and HP configuration differences do not turn the two harts into a symmetric cache-coherent SMP platform. #block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[ #set text(size:9pt) #source("rtl/ip/core/mgmt_core_wrapper.sv",title:"LP instance") · - #source("scripts/vexiiriscv/GenerateRetroSocHp.scala",title:"HP configuration/PMA") · - #source("scripts/generate_vexiiriscv.py",title:"Artifact manifest") · + #source("rtl/mini/top/hp_core_wrapper.sv",title:"HP OpenC906 integration") · + #source("scripts/generate_openc906.py",title:"Vendored filelist and hart-ID override") · #source("app/ports/linux/linux/retrosoc_hp.dts",title:"HP platform properties") ] diff --git a/publications/datasheets/sections/routing-reference.typ b/publications/datasheets/sections/routing-reference.typ index 57f90a55..f0dc6cd5 100644 --- a/publications/datasheets/sections/routing-reference.typ +++ b/publications/datasheets/sections/routing-reference.typ @@ -19,7 +19,7 @@ selector zero has no dedicated peripheral request wire. WS2812 uses that softwar The endpoint IRQ column identifies the peripheral's own event line where one exists; it is *not the DMA transfer-completion interrupt*. Central DMA channel events aggregate at the DMA -resource's LP IRQ or HP PLIC source according to the central resource owner. Crypto has no +resource's LP IRQ or HP external source according to the central resource owner. Crypto has no separate LP vector entry in this integration; inspect its register status and DMA completion path. === Software channel allocation @@ -39,10 +39,11 @@ descriptors or 2D operation merely from fields in the descriptor structure. === Private DMA masters and owner-directed completion #ds-table("private-dma-routes",[Central and private-master routes with owner-directed interrupts], - ([Engine],[Native master / gateway],[LP vector bit],[HP PLIC source]), + ([Engine],[Native master / gateway],[LP vector bit],[HP external source]), programming.engines.map(r=>(link(label(r.id),r.name),r.master,str(r.lp_irq),str(r.hp_irq))), widths:(1.2fr,1.5fr,0.65fr,0.7fr)) -These HP source numbers are read from the actual PLIC assignments. The Resource Controller +These HP source numbers are read from the actual SoC interrupt wiring. On the OpenC906 +core-internal PLIC, software addresses each one as *PLIC ID = source + 16*. The Resource Controller selects one owner's route and masks routes according to its lifecycle contract; it does not deliver a completion to both owners. Private DMA engines do not consume a central DMA channel simply because both move memory. They can still share a gateway or destination bandwidth. diff --git a/publications/datasheets/sections/software-runtime.typ b/publications/datasheets/sections/software-runtime.typ index b852b9c5..741ad977 100644 --- a/publications/datasheets/sections/software-runtime.typ +++ b/publications/datasheets/sections/software-runtime.typ @@ -96,13 +96,13 @@ the C runtime dispatches LP external interrupts through Hazard3 Xh3irq; it is no (code("rs_irq_disable_external"),[Mask the selected external source.],[The no-CSR implementations return RS_ENOTSUP; they do not silently emulate interrupts.]), ([Global enable],[The caller controls the global interrupt-enable bit separately.],[Complete handler and source setup before enabling delivery.]), ([Default exception],[Print diagnostic mcause and stack pointer, then loop.],[No automatic TEST_STATUS failure or instruction recovery is generated.]), - ([External interrupt dispatch],[Claim the highest-priority Xh3irq source, call its installed handler, then restore context; mask a source with no handler.],[The peripheral cause still needs acknowledgement in the handler. HP PLIC claim/complete belongs to the HP platform.])), + ([External interrupt dispatch],[Claim the highest-priority Xh3irq source, call its installed handler, then restore context; mask a source with no handler.],[The peripheral cause still needs acknowledgement in the handler. HP claim/complete belongs to the core-internal PLIC on the HP platform.])), widths:(1.05fr,1.7fr,1.7fr)) The supplied IRQ example registers machine timer/software handlers, enables global delivery, updates the compare value in the timer handler and clears the software-pending source in its handler. Its bounded foreground waits are example-specific. LP vector bits, CPU cause numbers, -handler-table indexes and HP PLIC source IDs are distinct namespaces. See @dma-routing for +handler-table indexes and HP PLIC IDs (SoC source + 16) are distinct namespaces. See @dma-routing for hardware routes and @fault-code-reference for interpreting captured results. #source-note("crt/arch/riscv/system_irq.S",title:"Saved context and direct trap entry") #source-note("crt/src/core/system_irq_handler.c",title:"Registration, supported enables and default dispatch behavior") diff --git a/publications/datasheets/sections/software.typ b/publications/datasheets/sections/software.typ index 8573a02a..a23724cd 100644 --- a/publications/datasheets/sections/software.typ +++ b/publications/datasheets/sections/software.typ @@ -190,12 +190,12 @@ the source paths used for each row and allows later reports to be bound to a pro multimedia throughput, physical pin timing or whole-system Linux stability. The supplied Linux console uses #code("console=hvc0 earlycon=sbi"). OpenSBI contains the UART1 -console implementation and ACLINT timer/software-interrupt setup. UART1 and mailbox DT nodes +console implementation and the core-internal CLINT timer/software-interrupt setup. UART1 and mailbox DT nodes reserve their platform ABI; the presence of #code("status = okay") is not evidence that a native custom driver is available or correct. No generic HAL-to-Linux bridge is supplied here. === Validated-configuration record -A reusable run record must name the source commit, committed profile, generated HP core, +A reusable run record must name the source commit, committed profile, vendored HP core revision, toolchain/kernel/OpenSBI versions, device/model or board, command, log/result digest and tested feature set. Record skips and missing tools explicitly. Keep simulation, FPGA and silicon stages separate and retain failed runs as diagnostics rather than overwriting them diff --git a/publications/datasheets/sections/system-management.typ b/publications/datasheets/sections/system-management.typ index c9440a7b..1c266ef1 100644 --- a/publications/datasheets/sections/system-management.typ +++ b/publications/datasheets/sections/system-management.typ @@ -5,7 +5,7 @@ #include "routing-reference.typ" == Multicore Operation and Resource Ownership -Hazard3 is the *root-management hart*; VexiiRiscv is the application hart. Linux does not take +Hazard3 is the *root-management hart*; OpenC906 is the application hart. Linux does not take over the SoC's root clock, reset, admission and recovery controls merely by booting. Decide which software owns each resource and buffer *before enabling interrupts or bus mastering*. diff --git a/publications/datasheets/sections/usage-appendices.typ b/publications/datasheets/sections/usage-appendices.typ index 0dbb27ff..7818afed 100644 --- a/publications/datasheets/sections/usage-appendices.typ +++ b/publications/datasheets/sections/usage-appendices.typ @@ -105,7 +105,7 @@ the stated inclusive end address. Numeric suffixes in signal names denote signal not package pin numbers. `_i`, `_o` and `_n` retain their declared direction/polarity meaning. An RTL `inout` pad wrapper may contain a functionally input-only route. -LP interrupt vector bits, HP PLIC source IDs, DMA request values, software channel contexts +LP interrupt vector bits, HP external sources and their PLIC IDs, DMA request values, software channel contexts and native master slots are separate namespaces. A matching integer does not connect them. Clock configuration, nominal calculated rate, model timing and characterized pin timing are also distinct. Interpret every Min/Typ/Max entry with its stated evidence and conditions. diff --git a/publications/datasheets/soc-architecture.json b/publications/datasheets/soc-architecture.json index 3310342f..fed9abec 100644 --- a/publications/datasheets/soc-architecture.json +++ b/publications/datasheets/soc-architecture.json @@ -273,14 +273,17 @@ }, { "id": "hp_core", - "label": "VexiiRiscv\nI$ / D$ / FPU / MMU", + "label": "OpenC906\nI$ / D$ / FPU / MMU", "x": 107, "y": 4.793103448275862, "w": 43, "h": 11.896551724137932, "domain": "hp", "role": "module", - "ips": [], + "ips": [ + "hp-aclint", + "hp-plic" + ], "rotate": false, "clock": { "file": "rtl/mini/top/retrosoc.sv", @@ -844,48 +847,6 @@ "signal": "clk_pclk_i" } }, - { - "id": "hp-aclint", - "label": "HP ACLINT", - "x": 108, - "y": 118, - "w": 42, - "h": 5.5, - "domain": "pclk", - "role": "module", - "ips": [ - "hp-aclint" - ], - "rotate": false, - "clock": { - "file": "rtl/mini/top/retrosoc.sv", - "name": "u_apb4_periph", - "module": "apb4_periph", - "port": "clk_i", - "signal": "clk_pclk_i" - } - }, - { - "id": "hp-plic", - "label": "HP PLIC", - "x": 108, - "y": 125, - "w": 42, - "h": 5.5, - "domain": "pclk", - "role": "module", - "ips": [ - "hp-plic" - ], - "rotate": false, - "clock": { - "file": "rtl/mini/top/retrosoc.sv", - "name": "u_apb4_periph", - "module": "apb4_periph", - "port": "clk_i", - "signal": "clk_pclk_i" - } - }, { "id": "hp-mailbox", "label": "LP / HP Mailbox", @@ -2599,30 +2560,6 @@ "kind": "control", "arrow": true }, - { - "id": "e55", - "from": "cfg_right", - "to": "hp-aclint", - "source_side": "east", - "target_side": "west", - "source_position": 0.38392857142857145, - "target_position": 0.5, - "via": [], - "kind": "control", - "arrow": true - }, - { - "id": "e56", - "from": "cfg_right", - "to": "hp-plic", - "source_side": "east", - "target_side": "west", - "source_position": 0.6339285714285714, - "target_position": 0.5, - "via": [], - "kind": "control", - "arrow": true - }, { "id": "e57", "from": "cfg_right", @@ -3405,7 +3342,7 @@ }, "output_bits": { "file": "rtl/mini/top/retrosoc.sv", - "name": "u_hp_icache_axi4_if" + "name": "u_hp_mem_axi4_if" } } }, @@ -3812,11 +3749,11 @@ "masters": [ { "index": 0, - "name": "hp_icache" + "name": "hp_mem" }, { "index": 1, - "name": "hp_dcache" + "name": "hp_retired" }, { "index": 2, diff --git a/publications/datasheets/style.md b/publications/datasheets/style.md index c11fde8b..b50e8413 100644 --- a/publications/datasheets/style.md +++ b/publications/datasheets/style.md @@ -135,7 +135,8 @@ collector checks RTL/SDK request-number parity (including explicit QSPI/XPI aliases), coverage, actual connection snippets and referenced instances. Channel conventions are supported by driver call sites, not inferred from selector IDs. Private masters and central DMA contexts are different resources. Preserve -endpoint IRQ, aggregate DMA IRQ, LP vector bit and HP PLIC source as separate +endpoint IRQ, aggregate DMA IRQ, LP vector bit and HP external source (PLIC ID = source + 16 +on the OpenC906 internal PLIC) as separate fields/namespaces. Derive PLIC assignments and normal master credits from the current implementation; mark any connected zero-credit route explicitly. diff --git a/publications/datasheets/system-reference.json b/publications/datasheets/system-reference.json index daf01a88..f940dc18 100644 --- a/publications/datasheets/system-reference.json +++ b/publications/datasheets/system-reference.json @@ -582,16 +582,15 @@ "id": "hp-aclint", "title": "HP ACLINT", "implementation": "Integrated", - "scope": "Two addressable hart slots; HP consumes slot 1.", + "scope": "Core-internal CLINT of the OpenC906 HP hart (thead,c900-clint layout), decoded inside the core at 0x0C000000 within the 0x08000000 system window; no memory-mapped mtime.", "dependencies": "No additional off-chip component implied; use the selected clock/reset and access policy.", - "hal": "Register/platform interface; no standalone HAL example indexed.", - "linux": "OpenSBI timer/IPI and standard DT bindings present; target boot report not supplied.", + "hal": "Core-internal unit; no SoC register bank or standalone HAL example indexed.", + "linux": "OpenSBI uses the ACLINT software-interrupt driver at the core-internal base and a custom timer device reading the time CSR; target boot report not supplied.", "verification": "Tests available", "sources": [ "app/ports/linux/linux/retrosoc_hp.dts", "app/ports/linux/opensbi/retrosoc_hp/platform.c", - "docs/ip/clint.md", - "rtl/ip/peripheral/clint_reg.sv" + "rtl/mini/top/hp_core_wrapper.sv" ], "tests": [ "tests/test_hp_platform.py" @@ -602,16 +601,15 @@ "id": "hp-plic", "title": "HP PLIC", "implementation": "Integrated", - "scope": "32 source IDs, with source 0 reserved.", + "scope": "Core-internal PLIC of the OpenC906 HP hart (thead,c900-plic layout), decoded inside the core at 0x08000000; SoC external interrupt source n is delivered as PLIC ID n+16.", "dependencies": "No additional off-chip component implied; use the selected clock/reset and access policy.", - "hal": "Register/platform interface; no standalone HAL example indexed.", - "linux": "Standard PLIC DT binding present; target IRQ validation report not supplied.", + "hal": "Core-internal unit; no SoC register bank or standalone HAL example indexed.", + "linux": "thead,c900-plic DT binding present; target IRQ validation report not supplied.", "verification": "Tests available", "sources": [ "app/ports/linux/linux/retrosoc_hp.dts", "app/ports/linux/opensbi/retrosoc_hp/platform.c", - "docs/ip/hp-platform.md", - "rtl/ip/peripheral/apb4_plic.sv" + "rtl/mini/top/hp_core_wrapper.sv" ], "tests": [ "tests/test_hp_platform.py" @@ -2130,7 +2128,7 @@ { "id": "hp", "term": "HP", - "meaning": "VexiiRiscv application hart; asymmetric Linux platform.", + "meaning": "OpenC906 application hart; asymmetric Linux platform.", "sources": [ "docs/lp-hp-architecture.md", "docs/ip/dma.md", @@ -2179,12 +2177,12 @@ }, { "id": "cbo", - "term": "CBO / Zicbom", - "meaning": "Cache-block maintenance operation / RISC-V extension; not hardware coherency.", + "term": "XTheadCmo", + "meaning": "T-Head extended cache-maintenance operations used by OpenC906 HP software (64-byte line); not hardware coherency.", "sources": [ + "app/ports/linux/smoke/start.S", "docs/lp-hp-architecture.md", - "docs/ip/dma.md", - "crt/linker/ld2_all_sram.lds" + "docs/ip/dma.md" ] }, { @@ -2305,26 +2303,12 @@ "U_MODE" ], "hp_fields": [ - "additionalPerformanceCounters", - "asidWidth", - "decoders", - "fetchL1Enable", - "fetchL1Sets", - "fetchL1Ways", - "fetchMemDataWidthMin", - "lanes", - "lsuL1Enable", - "lsuL1Sets", - "lsuL1Ways", - "lsuMemDataWidthMin", - "physicalWidth", - "pmpParam.granularity", - "pmpParam.pmpSize", - "privParam.debugTriggers", - "privParam.withDebug", - "privParam.withRdTime", + "coreAxiDataWidth", + "externalInterruptSources", + "fabricAxiDataWidth", + "hartId", "resetVector", - "xlen" + "sysWindowBase" ] }, "reset": [ @@ -3388,9 +3372,10 @@ "rtl/ip/core/mgmt_core_wrapper.sv", "rtl/mini/top/resource_controller.sv", "rtl/mini/top/soc_clock_reset_subsystem.sv", - "scripts/generate_vexiiriscv.py", + "scripts/generate_openc906.py", "scripts/program_xpi_flash.py", - "scripts/vexiiriscv/GenerateRetroSocHp.scala", + "rtl/mini/ip_overrides/aq_sysio_kid.v", + "rtl/mini/top/hp_core_wrapper.sv", "tests/test_xpi_flash_tool.py" ] }, @@ -3727,32 +3712,6 @@ "docs/ip/clint.md" ] }, - { - "id": "hp_aclint", - "chapter": "hp-aclint", - "family": "aclint", - "mode": "PRODUCT", - "region": "HP_ACLINT", - "catalog": "hp-platform", - "qualification": "Use the named instance, ownership and reset conditions in the linked IP reference.", - "sources": [ - "docs/ip/hp-platform.md", - "docs/lp-hp-architecture.md" - ] - }, - { - "id": "hp_plic", - "chapter": "hp-plic", - "family": "plic", - "mode": "PRODUCT", - "region": "HP_PLIC", - "catalog": "hp-platform", - "qualification": "PRIORITY index 0 is reserved and hardwired zero; its generic array access does not make source 0 programmable. Context indices retain the HP-platform contract.", - "sources": [ - "docs/ip/hp-platform.md", - "docs/lp-hp-architecture.md" - ] - }, { "id": "apb4_hp_mailbox", "chapter": "hp-mailbox", @@ -3867,7 +3826,7 @@ "mode": "PRODUCT", "region": "APB4_NPU", "catalog": "npu", - "qualification": "Integrated native-HP NPU execution with eight operator classes, descriptor DMA and private SRAM; CAPABILITY=0x7F and OP_CAPABILITY=0x1FE. Resource 9 routes LP vector 33 / HP PLIC source 12. Use configured lifecycle, cache and descriptor admission rules; no native Linux driver, arbitrary model or current corpus/physical qualification is implied.", + "qualification": "Integrated native-HP NPU execution with eight operator classes, descriptor DMA and private SRAM; CAPABILITY=0x7F and OP_CAPABILITY=0x1FE. Resource 9 routes LP vector 33 / HP external source 12 (PLIC ID 28 on the OpenC906 internal PLIC). Use configured lifecycle, cache and descriptor admission rules; no native Linux driver, arbitrary model or current corpus/physical qualification is implied.", "sources": [ "docs/ip/npu.md", "rtl/ip/multimedia/npu_reg.sv", @@ -5355,7 +5314,7 @@ { "id": "aclint-index-range", "file": "app/ports/linux/opensbi/retrosoc_hp/platform.c", - "text": ".first_hartid = 0U,\n.hart_count = 2U," + "text": ".first_hartid = 1U,\n.hart_count = 1U," }, { "id": "sbi-console", @@ -5372,7 +5331,7 @@ { "id": "sbi-timer", "file": "app/ports/linux/opensbi/retrosoc_hp/platform.c", - "text": "return aclint_mtimer_cold_init(&s_mtimer, NULL);", + "text": "sbi_timer_set_device(&s_timer);", "function": "retrosoc_hp_timer_init" }, { @@ -5956,6 +5915,7 @@ "app/apps/hp_boot/main.c", "app/apps/xpi_flash_loader/startup.S", "app/ports/linux/linux/retrosoc_hp.dts", + "app/ports/linux/smoke/start.S", "configs/ci/ihp130-debug.mk", "configs/ci/ihp130-hp.mk", "configs/ci/ihp130-xpi-flash-loader.mk", @@ -6146,8 +6106,10 @@ "rtl/mini/top/extension_slot.sv", "rtl/mini/top/extension_subsystem.sv", "rtl/mini/top/fabric_monitor.sv", + "rtl/mini/top/hp_core_wrapper.sv", "rtl/mini/top/hp_subsystem.sv", "rtl/mini/top/memory_pad_mux.sv", + "rtl/mini/ip_overrides/aq_sysio_kid.v", "rtl/ip/core/mgmt_debug_wrapper.sv", "rtl/ip/memory/onchip_ram.sv", "rtl/mini/top/rcu.sv", diff --git a/publications/datasheets/waveforms.json b/publications/datasheets/waveforms.json index 781ca2fb..c9321598 100644 --- a/publications/datasheets/waveforms.json +++ b/publications/datasheets/waveforms.json @@ -1768,150 +1768,6 @@ }, "parameter_note": "Each LP or HP local interrupt block in this example has one hart." }, - "aclint": { - "source": { - "signal": [ - { - "name": "tick_i", - "wave": "0101010." - }, - { - "name": "mtime_o", - "wave": "=.=.=.==", - "data": [ - "N-1", - "N", - "N+1", - "N+2", - "N+2" - ] - }, - { - "name": "mtimecmp_i[0]", - "wave": "=.....=.", - "data": [ - "N", - "N+8" - ] - }, - { - "name": "timer_irq_o[0]", - "wave": "0..1...0" - } - ], - "config": { - "hscale": 1, - "skin": "lowkey" - } - }, - "note": "Scope: clint_core. Clock: clk_i; mtime tick and comparator update. Hart 0: the timer IRQ is a registered comparison of mtime_o against mtimecmp_i[0]. Updating compare above the current time deasserts the IRQ on a subsequent core edge; timebase tick spacing is illustrative.", - "clock_domain": "clk_i; mtime tick and comparator update", - "signals": { - "tick_i": { - "file": "rtl/ip/peripheral/clint_core.sv", - "scope": "clint_core", - "symbol": "tick_i", - "meaning": "Qualified timebase increments.", - "polarity": "active-high" - }, - "mtime_o": { - "file": "rtl/ip/peripheral/clint_core.sv", - "scope": "clint_core", - "symbol": "mtime_o", - "meaning": "MTIME advances through the programmed compare value.", - "polarity": "data" - }, - "mtimecmp_i[0]": { - "file": "rtl/ip/peripheral/clint_core.sv", - "scope": "clint_core", - "symbol": "mtimecmp_i", - "meaning": "Hart 0 compare is moved beyond the current time.", - "polarity": "data" - }, - "timer_irq_o[0]": { - "file": "rtl/ip/peripheral/clint_core.sv", - "scope": "clint_core", - "symbol": "timer_irq_o", - "meaning": "Registered timer interrupt follows comparison.", - "polarity": "active-high" - } - }, - "review_sources": [ - "rtl/ip/peripheral/clint_core.sv" - ], - "review_note": "Mapped mtime/mtimecmp aliases to ports and retained the registered comparator delay.", - "parameters": { - "HartNum": 1 - }, - "parameter_note": "Each LP or HP local interrupt block in this example has one hart." - }, - "plic": { - "source": { - "signal": [ - { - "name": "source_i[1]", - "wave": "010......" - }, - { - "name": "s_pending_q[1]", - "wave": "0.1.0...." - }, - { - "name": "s_claimed_q[1]", - "wave": "0...1..0." - }, - { - "name": "context_irq_o[0]", - "wave": "0.1.0...." - } - ], - "config": { - "hscale": 1, - "skin": "lowkey" - } - }, - "note": "Scope: apb4_plic. Clock: clk_i; APB access and service intervals omitted. Source 1 enabled for context 0 with priority above threshold. Claim clears pending and marks the source claimed; completion releases it. APB read/write handshakes and software service time are omitted.", - "clock_domain": "clk_i; APB access and service intervals omitted", - "signals": { - "source_i[1]": { - "file": "rtl/ip/peripheral/apb4_plic.sv", - "scope": "apb4_plic", - "symbol": "source_i", - "meaning": "Source 1 pulse.", - "polarity": "active-high" - }, - "s_pending_q[1]": { - "file": "rtl/ip/peripheral/apb4_plic.sv", - "scope": "apb4_plic", - "symbol": "s_pending_q", - "meaning": "Pending latch is set then cleared by a claim.", - "polarity": "active-high" - }, - "s_claimed_q[1]": { - "file": "rtl/ip/peripheral/apb4_plic.sv", - "scope": "apb4_plic", - "symbol": "s_claimed_q", - "meaning": "Claimed state persists until completion.", - "polarity": "active-high" - }, - "context_irq_o[0]": { - "file": "rtl/ip/peripheral/apb4_plic.sv", - "scope": "apb4_plic", - "symbol": "context_irq_o", - "meaning": "Context 0 interrupt while enabled pending priority wins.", - "polarity": "active-high" - } - }, - "review_sources": [ - "rtl/ip/peripheral/apb4_plic.sv" - ], - "review_note": "Reviewed priority arbitration, pending and claimed arrays. Removed claim-read/complete-write pseudo-signals and kept their software actions in the note.", - "parameters": { - "NumSources": 32, - "NumContexts": 2 - }, - "parameter_note": "Reference HP PLIC exposes 32 source slots and two contexts." - }, "mailbox": { "source": { "signal": [ diff --git a/publications/diagram_reference.py b/publications/diagram_reference.py index ab5c438d..104ffa88 100644 --- a/publications/diagram_reference.py +++ b/publications/diagram_reference.py @@ -206,9 +206,13 @@ def collect_diagrams(root: Path, spec: dict, regions: list[dict], system: dict) ("argument", 8, 32), ("crc7", 1, 7), ("end", 0, 1)]: raise ValueError("SDIO field order differs from the bound transmitter assembly") dts = (root / "app/ports/linux/linux/retrosoc_hp.dts").read_text(encoding="utf-8") - cbo = re.findall(r"riscv,cbom-block-size\s*=\s*<(\d+)>", dts) - if cbo != ["64"]: + if "riscv,cbom-block-size" in dts: raise ValueError("review cache-maintenance diagram after platform granule change") + smoke = (root / "app/ports/linux/smoke/start.S").read_text(encoding="utf-8") + if (".insn r 0x0b, 0x0, 0x01, x0, a0, x5" not in smoke + or ".insn r 0x0b, 0x0, 0x01, x0, a0, x6" not in smoke + or "csrs 0x7c0, t0" not in smoke): + raise ValueError("review cache-maintenance diagram after platform maintenance-operation change") windows = [{k: r[k] for k in ("symbol", "base", "size", "base_hex", "end_hex", "size_label")} for r in regions if r["size"] > 4096 and r["route"] in {"axi4", "ram"} and r["kind"] == "active"] if not windows or any(r["base"] + r["size"] > 1 << 32 for r in windows): diff --git a/publications/implementation_reference.py b/publications/implementation_reference.py index 0fe8bc43..30bb5ada 100644 --- a/publications/implementation_reference.py +++ b/publications/implementation_reference.py @@ -42,13 +42,49 @@ def lp_parameters(text: str) -> dict[str, str]: for name, value in parameters.items()} -def hp_parameters(text: str) -> tuple[dict[str, str], list[str]]: - text = without_comments(text) - values = unique_pairs(re.findall(r"^\s*param\.([A-Za-z][\w.]*)\s*=\s*([^\n]+)", text, re.M), "HP") - isa = re.findall(r"param\.addISA\(([^)]*)\)", text) - if len(isa) != 1: - raise ValueError("HP ISA configuration missing or ambiguous") - return values, re.findall(r'"([a-z0-9]+)"', isa[0]) +def hp_parameters(wrapper: str, override: str) -> dict[str, str]: + """Read the fixed OpenC906 integration constants from the Mini HP wrapper.""" + text = without_comments(wrapper) + constants = unique_pairs( + [(name, f"0x{int(value.replace('_', ''), 16):08X}") + for name, value in re.findall( + r"localparam\s+logic\s+\[39:0\]\s+(HpResetVector|HpApbBase)\s*=\s*40'h([0-9A-Fa-f_]+)\s*;", text)], + "HP") + interfaces = {} + for body, name in re.findall( + r"axi4_if\s*#\s*\(([^;]+?)\)\s*(u_c906_axi4_if|u_hp_64_axi4_if)\s*\(", text, re.S): + width = re.findall(r"\.\s*DATA_WIDTH\s*\(\s*(\d+)\s*\)", body) + if len(width) != 1 or name in interfaces: + raise ValueError("HP interface width missing or ambiguous") + interfaces[name] = width[0] + sources = re.findall(r"input\s+logic\s+\[15:0\]\s+plic_src_i\b", text) + hart = re.findall(r"assign\s+sysio_core_hartid\[2:0\]\s*=\s*3'd(\d)\s*;", without_comments(override)) + if len(constants) != 2 or len(interfaces) != 2 or len(sources) != 1 or len(hart) != 1: + raise ValueError("HP OpenC906 integration constants missing or ambiguous") + return { + "resetVector": constants["HpResetVector"], + "sysWindowBase": constants["HpApbBase"], + "coreAxiDataWidth": interfaces["u_c906_axi4_if"], + "fabricAxiDataWidth": interfaces["u_hp_64_axi4_if"], + "externalInterruptSources": "16", + "hartId": hart[0], + } + + +def hp_isa(dts: str) -> dict[str, object]: + """Read the software-visible HP ISA/MMU identity from the reviewed device tree.""" + cpu = re.findall(r"cpu@1\s*\{(.*?)hp_cpu_intc:", dts, re.S) + if len(cpu) != 1: + raise ValueError("HP device-tree CPU node missing or ambiguous") + node = cpu[0] + compatible = re.findall(r'compatible\s*=\s*"thead,c906"', node) + base = re.findall(r'riscv,isa-base\s*=\s*"(\w+)"', node) + extensions = re.findall(r'riscv,isa-extensions\s*=\s*((?:\s*"[a-z0-9]+",?)+)\s*;', node) + mmu = re.findall(r'mmu-type\s*=\s*"riscv,(\w+)"', node) + if not compatible or len(base) != 1 or len(extensions) != 1 or len(mmu) != 1: + raise ValueError("HP device-tree ISA/MMU identity missing or ambiguous") + return {"compatible": "thead,c906", "isa_base": base[0], + "extensions": re.findall(r'"([a-z0-9]+)"', extensions[0]), "mmu": mmu[0]} def reset_assignments(text: str, signal: str, module: str | None = None) -> dict[str, str]: @@ -115,32 +151,28 @@ def validate_details(spec: dict, ids: set[str], root: Path, active_limits: set[s def collect_details(root: Path, spec: dict, ids: set[str], active_limits: set[str]) -> dict: validate_details(spec, ids, root, active_limits) lp = lp_parameters((root / "rtl/ip/core/mgmt_core_wrapper.sv").read_text(encoding="utf-8")) - hp_source = (root / "scripts/vexiiriscv/GenerateRetroSocHp.scala").read_text(encoding="utf-8") - hp, hp_isa = hp_parameters(hp_source) + hp = hp_parameters((root / "rtl/mini/top/hp_core_wrapper.sv").read_text(encoding="utf-8"), + (root / "rtl/mini/ip_overrides/aq_sysio_kid.v").read_text(encoding="utf-8")) + identity = hp_isa((root / "app/ports/linux/linux/retrosoc_hp.dts").read_text(encoding="utf-8")) for required, actual, name in ((spec["cpu"]["lp_fields"], lp, "LP"), (spec["cpu"]["hp_fields"], hp, "HP")): if len(set(required)) != len(required) or not set(required) <= set(actual): raise ValueError(f"missing or duplicate requested {name} parameters") config = json.loads((root / "publications/datasheets/mini.json").read_text(encoding="utf-8")) profile = (root / config["profile"]).read_text(encoding="utf-8") - build = unique_pairs(re.findall(r"^\s*(ISA|HAVE_CSR|HAVE_HP|HP_CONFIG)\s*:?=\s*([^\n#]+)", profile, re.M), "firmware") - if set(build) != {"ISA", "HAVE_CSR", "HAVE_HP", "HP_CONFIG"}: + build = unique_pairs(re.findall(r"^\s*(ISA|HAVE_CSR|HAVE_HP)\s*:?=\s*([^\n#]+)", profile, re.M), "firmware") + if set(build) != {"ISA", "HAVE_CSR", "HAVE_HP"} or build["HAVE_HP"] != "YES": raise ValueError("incomplete firmware/core profile identity") lock = json.loads((root / "dependencies/dependencies.lock.json").read_text(encoding="utf-8")) result = copy.deepcopy(spec) result["cpu"] = { - "lp": lp, "hp": hp, "hp_isa": hp_isa, "build": build, + "lp": lp, "hp": hp, "hp_isa": identity["extensions"], "build": build, + "hp_isa_base": identity["isa_base"], "hp_mmu": identity["mmu"], + "hp_compatible": identity["compatible"], "lp_extensions": [name.removeprefix("EXTENSION_") for name, value in lp.items() if name.startswith("EXTENSION_") and value == "1"], - "hp_revision": lock["sources"]["vexiiriscv"]["revision"], - "generated_artifact_basis": "Not supplied in the publication evidence set", - "hp_cache_capacity": "Unconfirmed; upstream default block size not independently reviewed", + "hp_revision": lock["sources"]["openc906"]["revision"], + "generated_artifact_basis": "Pre-generated vendored OpenC906 RTL at the locked revision, with the reviewed retroSoC hart-ID override; no new core generation", + "hp_cache_capacity": "Default OpenC906 configuration (32 KiB instruction + 32 KiB data L1 per the T-Head C906 manuals); not independently re-measured", } - pma = re.findall(r"SizeMapping\((0x[0-9A-Fa-f]+)L,\s*(0x[0-9A-Fa-f]+)L\),\s*isMain\s*=\s*(true|false),\s*isExecutable\s*=\s*(true|false)", without_comments(hp_source)) - if not pma: - raise ValueError("explicit HP PMA mappings missing") - result["cpu"]["pma"] = [{"base": f"0x{int(base, 16):08X}", - "end": f"0x{int(base, 16)+int(size, 16)-1:08X}", - "bytes": int(size, 16), "main": main, "executable": execute} - for base, size, main, execute in pma] result["service_results"] = [{"executed": str(e).lower(), "passed": str(p).lower(), "meaning": programming_result({"executed": e, "passed": p})} for e, p in ((False, True), (False, False), (True, False), (True, True))] diff --git a/publications/register_reference.py b/publications/register_reference.py index 436712c9..1d50dc71 100644 --- a/publications/register_reference.py +++ b/publications/register_reference.py @@ -927,7 +927,6 @@ def extract_profile(ip: str, spec: dict, annotations: dict) -> dict: "mailbox": "hp_mailbox", "monitor": "fabric_monitor", "extensions": "extension", - "aclint": "clint", "wdg": "watchdog", }.get(ip, ip) candidates = [f"crt/include/retrosoc/hal/{alias}_regs.h", f"crt/src/hal/{alias}.c"] diff --git a/publications/software_reference.py b/publications/software_reference.py index fd3e7cdd..884c07a7 100644 --- a/publications/software_reference.py +++ b/publications/software_reference.py @@ -164,7 +164,7 @@ def linux_platform(root: Path) -> dict: if harts != ["1"] or hart_ids != ["1"] or len(cpu) != 1 or not re.search(r"\breg\s*=\s*<1>\s*;", cpu[0]): raise ValueError("Linux/OpenSBI hart identity changed") timebase = dt_value("timebase-frequency") - mtimer = re.findall(r"\.mtime_freq\s*=\s*(\d+)UL", platform) + mtimer = re.findall(r"\.timer_freq\s*=\s*(\d+)UL", platform) if mtimer != [str(timebase)]: raise ValueError("Linux/OpenSBI timebase mismatch") profile = (root / "configs/ci/ihp130-hp.mk").read_text(encoding="utf-8") @@ -181,8 +181,11 @@ def linux_platform(root: Path) -> dict: raise ValueError("CPU and UART device-tree clock declarations disagree") if dt_value("linux,initrd-start") != dt_value("linux,initrd-end"): raise ValueError("reviewed initrd template placeholder changed") + controllers = re.findall(r'"(thead,c900-clint|thead,c900-plic)"', dts) + if controllers != ["thead,c900-clint", "thead,c900-plic"] or dt_value("riscv,ndev") != 31: + raise ValueError("Linux internal CLINT/PLIC declaration changed") return {"hart_id": 1, "timebase_hz": timebase, "clock_hz": int(clocks[0]), - "cbom_bytes": dt_value("riscv,cbom-block-size"), "memory_base": memory[0][0], + "memory_base": memory[0][0], "memory_bytes": int(memory[0][1], 0), "initrd_start": dt_value("linux,initrd-start"), "initrd_template_end": dt_value("linux,initrd-end"), "bootargs": bootargs[0], "ready_writes": ready_mailbox(root)} diff --git a/quality/warnings/ihp130/rtl-lint.json b/quality/warnings/ihp130/rtl-lint.json index 5c1ca7be..fa8720dd 100644 --- a/quality/warnings/ihp130/rtl-lint.json +++ b/quality/warnings/ihp130/rtl-lint.json @@ -1,5 +1,25 @@ { "entries": [ + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'PENDING_HALT'", + "signature": "00613cbcf18b5ae9" + }, + { + "count": 1, + "example": "UNOPTFLAT:$ROOT/rtl/mini/top/soc_data_plane.sv:: Signal unoptimizable: Circular combinational logic: 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_data_plane.s_fault_src_req'", + "signature": "006951ae8e85fb3c" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF2_INF'", + "signature": "0085c1fa9e533c5b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex1_rm'", + "signature": "0093857457b057c7" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'U_MODE'", @@ -10,16 +30,71 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/common/rtl/utils/lfsr.sv:: Filename 'lfsr' does not match MODULE name: 'lfsr_galois'", "signature": "01c46f4bd15fd09d" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'l32_1_shift_result'[47:32]", + "signature": "01f27a19981f3321" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT28'", + "signature": "02074ad9e0cec50d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_XPERM'", "signature": "0225d6b274c92cdf" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex4_func'", + "signature": "022b475166801808" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'wbt_ctrl_src0_info'[6:1]", + "signature": "024025885447390f" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'CLN'", + "signature": "0260721d9a72b34b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'da_xx_fwd_dst_reg'[5]", + "signature": "02f06ec223af474a" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZBKX'", "signature": "037662c8f3e92464" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Bits of signal are not used: 's_kp_cin'[63:33]", + "signature": "038169101e64ed24" + }, + { + "count": 7, + "example": "PINMISSING:$ROOT/rtl/tech/tc_io.sv:: Instance has missing pin: 'iovdd'", + "signature": "03a1cd14ac4187b7" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'tmp_prio_split_pslverr'[9:3,0]", + "signature": "03acfa83cd4c76cf" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'scntinhbt_updt_value'[1]", + "signature": "03b214403faa2e4b" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 16 bits on the LHS, but LHS's REPLICATE generates 13 bits.", + "signature": "042584f94cd93e3b" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_9_io_pad'", @@ -30,6 +105,36 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_BREV8'", "signature": "0466b2d33d754335" }, + { + "count": 4, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SINGLE_FRAC'", + "signature": "04d0168e906a5e4d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_encode_core.sv:: Signal is not used: 's_builder_done'", + "signature": "04fa4614f5453264" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT29'", + "signature": "04fbf64a86bf846c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_aes_sram_engine.sv:: Signal is not used: 's_core_busy'", + "signature": "0513e3c66e12c705" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator COND expects 16 bits on the Conditional False, but Conditional False's CONST '13'h0' generates 13 bits.", + "signature": "056ab79898976dc1" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator EQ expects 32 bits on the LHS, but LHS's REPLICATE generates 29 bits.", + "signature": "056babacc8916b46" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT24'", @@ -45,11 +150,46 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER21'", "signature": "05b67f901c971eb6" }, + { + "count": 2, + "example": "WIDTHCONCAT:$ROOT/rtl/ip/multimedia/npu_local_sram.sv:: Replication of more that --replication-limit 8192 is suspect: 16384", + "signature": "05f011398075f54a" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT11'", + "signature": "060b59ee519cba8f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'jtlb_tag_idx'[8:6]", + "signature": "061a6f0b11a6e743" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_A'", "signature": "063886be780f8b00" }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 32 bits on the RHS, but RHS's CONST '14'h1' generates 14 bits.", + "signature": "065b4c1c18674963" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'hart_claim_read_data_tmp'[63:42]", + "signature": "065f879b8183ab73" + }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's SEL generates 6 bits.", + "signature": "069108e3563bcca4" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/tech/tc_pll_ics55_ecos.sv:: Instance pin connected by name with empty reference: 'CKTST'", + "signature": "06a0cde9c074157d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT15'", @@ -62,19 +202,64 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/store_decoder.v:: Filename 'store_decoder' does not match MODULE name: 'mpw_core_kianv_rv32i_store_decoder'", - "signature": "078a551602e8a9bd" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'div_func'[19:3]", + "signature": "072a20f95d7dcfbc" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpaddr15_value'[0]", + "signature": "07ab1755f40da120" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER9H'", "signature": "07e5366c14fe6a62" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SINGLE1_ID'", + "signature": "080eb1f6219cd54f" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA4'", + "signature": "081117a25e837784" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF2_SNAN'", + "signature": "087690ac5812a6b9" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_partial_result_3'[80:79]", + "signature": "08947e344779eaef" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex3_e_tmp_0'[11]", + "signature": "08ba36f1749bcb69" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpcfg0_value'[62:61,54:53,46:45,38:37,30:29,22:21,14:13,6:5]", + "signature": "08cc36b275528e44" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ff1_64_bit'[7:6]", + "signature": "08d7b147891f5e63" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER16'", "signature": "08e2a109c0d25a59" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_transform.sv:: Bits of function variable are not used: 's_scaled'[47:24]", + "signature": "08efbb7bfd1550b8" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_core.v:: Signal is not used: 'x_pmp_cfg_addr'", @@ -85,11 +270,36 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_XNOR'", "signature": "0973116d3d4b3b32" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ECH_RD'", + "signature": "0a27c258072f1640" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ORC_B'", "signature": "0a39c354055278da" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_3'[81]", + "signature": "0a498e4ab1557b20" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'wb0_vld'[0]", + "signature": "0a8524e3a89f5c18" + }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS's REPLICATE generates 8 bits.", + "signature": "0ac0945162f35364" + }, + { + "count": 1, + "example": "UNOPTFLAT:$ROOT/rtl/mini/top/axi4_data_crossbar.sv:: Signal unoptimizable: Circular combinational logic: 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_data_plane.u_data_crossbar.t_awready'", + "signature": "0ad3c69f9d7ff3e2" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUSRCA_RS1'", @@ -100,6 +310,16 @@ "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_10_io_pad'", "signature": "0ae233839a6211b2" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Signal is not driven, nor used: 's_out_read_addr'", + "signature": "0b0b7ad594537527" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator GTE expects 32 bits on the LHS, but LHS's SEL generates 9 bits.", + "signature": "0b0e7952964c6f61" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_13_io_pad'", @@ -120,36 +340,171 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Parameter is not used: 'DCSR_CAUSE_HALTREQ'", "signature": "0b7b8393d0f9480a" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Signal is not driven, nor used: 'B_BM_MUX'", + "signature": "0bcf56d462d98ff6" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'W_ADDR'", "signature": "0bdf9e1cb55e00af" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_c0_0'[105]", + "signature": "0bf13ce8d19503d7" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bus_mtx_ip_paddr'[1:0]", + "signature": "0c15a41c33ff7d1d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'icache_refill_addr'[0]", + "signature": "0c322d4a67bde640" + }, + { + "count": 2, + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/jpeg_mcu_builder.sv:: Declaration of signal hides declaration in upper scope: 'sampling_i'", + "signature": "0c98c7d97f5d5208" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'icache_miss_addr'[0]", + "signature": "0c9c8488349afbf3" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 13 bits on the LHS, but LHS's REPLICATE generates 7 bits.", + "signature": "0cba0018db579323" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p2_0_cout'[82]", + "signature": "0cbc715d1f38ceb8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vtb_entry_fls'[3:2]", + "signature": "0ce4a137ed5b8280" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_15_io_pad'", "signature": "0d25f4003bf6a215" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/core/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'clk_en'", + "signature": "0d3abae90f203735" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Parameter is not used: 'EXTENSION_ZCA'", "signature": "0d4b7a581134891f" }, + { + "count": 1, + "example": "STMTDLY:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v:: Ignoring delay on this statement due to --no-timing", + "signature": "0d5f78e2f1441349" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT20'", + "signature": "0d8778189234369a" + }, + { + "count": 1, + "example": "UNSIGNED:$BUILD/generated/openc906/openc906_combined.v:: Comparison is constant due to unsigned arithmetic", + "signature": "0deeef2023ed5ad5" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_REGADDR'", "signature": "0e22c168d3675281" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex3_rm'", + "signature": "0e3383a026b71706" + }, + { + "count": 3, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF_EXPN'", + "signature": "0e4a7e4810b991bf" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_MINU'", "signature": "0e5990f9b94e5942" }, + { + "count": 1, + "example": "STMTDLY:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v:: Ignoring delay on this statement due to --no-timing", + "signature": "0e5ec586910891eb" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT23'", + "signature": "0ed994e06f115498" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'wb1_vld'[0]", + "signature": "0ef9ad865ee539ed" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pfb_ld_pc'[0]", + "signature": "0f7c924dcc271db6" + }, + { + "count": 4, + "example": "PINMISSING:$BUILD/generated/pin_map/rtl/retrosoc_asic_pad_bindings.svh:: Instance has missing pin: 'vdd'", + "signature": "0f80a2f9d9e2ec91" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'icache_data_idx'[13:12]", + "signature": "0f8d6b98d8b825b1" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT3'", "signature": "0fc1f528cb6bfcf4" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/peripheral/dma_core.sv:: Signal is not used: 's_tcd_count_q'", + "signature": "0fd42649704ac907" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_rready'", + "signature": "0ff317fa19b6b4a6" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF2_NORM'", + "signature": "1096c8e8ab943f2f" + }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'BF16_EXPN'", + "signature": "10d820c2bf46bdc9" + }, + { + "count": 1, + "example": "WIDTHTRUNC:$BUILD/generated/openc906/openc906_combined.v:: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's AND generates 32 bits.", + "signature": "113b26f8864a16b6" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Bits of signal are not used: 'rec_k_slice_i'[15:11]", + "signature": "117a61d76e6e19d6" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/mini/dv/sva/rib_protocol_sva.sv:: Filename 'rib_protocol_sva' does not match MODULE name: 'rib_bus_sva'", @@ -160,6 +515,26 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_core.v:: Signal is not used: 'fd_cir_raw'", "signature": "11b5f42331ff8f8b" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'utlb_hit_flg'[10]", + "signature": "11bd7b113384e8e0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'right_8_6_shift_num'[15:8]", + "signature": "11e3e1c39b7e56ba" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'div_suber_res1_01'[65:64]", + "signature": "1251baaee3e4a903" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_encoder.sv:: Signal is not used: 's_transform_ready'", + "signature": "127618a8102ff02d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'MVENDORID_VAL'", @@ -170,10 +545,20 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MEIPA'", "signature": "12bdd500c7a3121d" }, + { + "count": 3, + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/jpeg_mcu_builder.sv:: Declaration of signal hides declaration in upper scope: 'format_i'", + "signature": "13033043904ba44e" + }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/serv/user_core_design.sv:: Instance pin connected by name with empty reference: 'o_ext_rs2'", - "signature": "12e1c9d3c592f1e6" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'STIMECMP1'", + "signature": "134a26a0b985283e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'wbt_ctrl_src0_info'[6]", + "signature": "141203070d5b8386" }, { "count": 1, @@ -185,11 +570,51 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER5H'", "signature": "145e16b1336a7477" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'rtu_retire_halt_info'[0]", + "signature": "1483629d2bd694be" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_awprot'", + "signature": "14aa5d3d9a3fc174" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_montgomery_sram.sv:: Bits of signal are not used: 'resp_i'[52:42,9:0]", + "signature": "14ede1edabcd1b89" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_2'[81]", + "signature": "15041c4139e3a46e" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Bits of function variable are not used: 'relative'[25:11]", "signature": "15357b2357c7b4df" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_wstrb'", + "signature": "157917edf9efa5bf" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dcache_tag_dout_bank0'[118,88,58,28]", + "signature": "15b6c72703de539e" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT27'", + "signature": "15f4ab31b606ad7a" + }, + { + "count": 1, + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/jpeg_quantizer.sv:: Declaration of signal hides declaration in upper scope: 'reciprocal_i'", + "signature": "162afb420a741b8f" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER19H'", @@ -200,6 +625,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER24H'", "signature": "164b237b29a8d155" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex4_stall'", + "signature": "1663c09291b62132" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'M_OP_REM'", @@ -207,8 +637,8 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Signal is not used: 'irq_i'", - "signature": "16dc4f6527a9664e" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pf_req_va'[39:16,5:0]", + "signature": "16de774e4c3495aa" }, { "count": 1, @@ -222,19 +652,44 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'tid'", - "signature": "17869ed3816eaa41" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ADD_D_WIDTH'", + "signature": "179a96d0cc9b77a3" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dtu_rtu_dpc'[63:40]", + "signature": "17ab56d613dd1bc6" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER23H'", "signature": "17cdabd58cde47df" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_mem_ctrl.sv:: Bits of signal are not used: 's_read_resp'[9:0]", + "signature": "17e5f182f7b92ae5" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_frac'[63:53]", + "signature": "17ea6a5aae11a840" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'l32_0_shift_out_val'[8:0]", + "signature": "1808b28c10b0bec2" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_CLMUL'", "signature": "1841f569b8cc3a63" }, + { + "count": 4, + "example": "PINMISSING:$BUILD/generated/pin_map/rtl/retrosoc_asic_pad_bindings.svh:: Instance has missing pin: 'vss'", + "signature": "18ace5c3b6d85898" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MIP'", @@ -245,16 +700,46 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER6'", "signature": "18c677611636b19e" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF1_QNAN'", + "signature": "18f8f379cd2ce3c6" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'xpi_nss3_o_pad'", "signature": "1906e34634cd1781" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_0_xx_ex3_eu_sel'[9:1]", + "signature": "193d3aa1ff82a9e9" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p1_1_cout'[81]", + "signature": "19518a61131d17cf" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv:: Filename 'cdc_rst_ctrlr' does not match MODULE name: 'cdc_reset_barrier'", "signature": "196664f3e8a8a28c" }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator LT expects 9 bits on the LHS, but LHS's REPLICATE generates 8 bits.", + "signature": "19681be5eaabcd7f" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 16 bits on the RHS, but RHS's REPLICATE generates 13 bits.", + "signature": "19754804c5945fe0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cp0_mmu_wdata'[54:46]", + "signature": "197b26c8f8313727" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR12'", @@ -262,8 +747,23 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'unblock_out'", - "signature": "19952b366d20fca9" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_norm_src0'[63:32]", + "signature": "19a0d8957641daba" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MTIMECMPH2'", + "signature": "1a0499fdd33d37e4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'iui_regs_wdata'[43:28]", + "signature": "1a238fa67e50fe49" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'l32_1_shift_out_val'", + "signature": "1b75945668726721" }, { "count": 1, @@ -272,14 +772,29 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/user_core_design.sv:: Bits of signal are not used: 'irq_i'[31:2,0]", - "signature": "1bcd31858745187e" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'carry_p'[0]", + "signature": "1bb4d819095a6ac9" + }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNW expects 13 bits on the Assign RHS, but Assign RHS's COND generates 14 bits.", + "signature": "1bb6eca3bc036cba" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'sbdata_zero_value'", + "signature": "1bd3dafd7e14161a" }, { "count": 1, "example": "DECLFILENAME:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v:: Filename 'sg13g2_io' does not match MODULE name: 'sg13g2_Corner'", "signature": "1bdede804d1ae734" }, + { + "count": 5, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF'", + "signature": "1bf7be956f5ab26d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER17'", @@ -302,14 +817,59 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/cells.v:: Filename 'cells' does not match MODULE name: 'mpw_core_kianv_rv32i_buffer_cell'", - "signature": "1d7a1fd21f436220" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Bits of signal are not used: 's_job_config'[31:10,7:4,2]", + "signature": "1d501d42a940635e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_id_inst_data'[197]", + "signature": "1d5345136f49f341" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator AND expects 32 bits on the RHS, but RHS's CONST '7'h7f' generates 7 bits.", + "signature": "1d57954afcaa80ae" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR2'", "signature": "1d7c1482404aab5d" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'iui_regs_wdata'[63:32,27:25]", + "signature": "1d948ffd9a7cf0af" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_3_xx_ex1_func'[19,11,9:6,3:1]", + "signature": "1daa9da1b6964a31" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'hpcp_rtu_cnt_en'", + "signature": "1dc05ef6e49dc732" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_1_xx_ex1_func'[19:14,11:9]", + "signature": "1dd068fc5dfc7abd" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator SUB expects 37 bits on the LHS, but LHS's VARREF 's_full_k_q' generates 25 bits.", + "signature": "1df4d28f5beade41" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'wbt_ctrl_src1_info'[6:1]", + "signature": "1e0e973b7a818d18" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Parameter is not used: 'P_ERROR_PATTERN'", + "signature": "1e4dcc4bc9ff12e6" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_XH3BEXTM'", @@ -320,6 +880,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZILSD'", "signature": "1ebe452d9a83ff1e" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_arvalid'", + "signature": "1f0093a2dc766b2a" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'IRQ_PRIORITY_BITS'", @@ -335,16 +900,81 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_HARDWIRED_CFG'", "signature": "1f8bf1a9461e2d28" }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator COND expects 14 bits on the Conditional False, but Conditional False's SEL generates 13 bits.", + "signature": "20031371007cfe5d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MEPC'", "signature": "2075469dae6126d1" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vtb_entry_st_fwd_vld'[3:2]", + "signature": "21300d9a4cffe0ea" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Parameter is not used: 'P_FORCE_ERROR'", + "signature": "214432645147435e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_decoder.sv:: Signal is not used: 'quant_i'", + "signature": "220078378bc97847" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_double_sub_inc2_r'[56,1:0]", + "signature": "22256bedb11a288a" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA11'", + "signature": "2225ca178364282e" + }, + { + "count": 1, + "example": "UNDRIVEN:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Signal is not driven: 's_desc_faddr'", + "signature": "224229fe61a29059" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_p0_0_cout'[105]", + "signature": "22484d9b35e9319c" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT13'", + "signature": "22717066b2158192" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Signal is not driven, nor used: 's_out_read_valid'", + "signature": "2286589a0c3beb15" + }, + { + "count": 3, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS's REPLICATE generates 16 bits.", + "signature": "22f4cf008ebe8232" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'kid_clk'[0]", + "signature": "2310868376a6142f" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZBC'", "signature": "23236599e40a834a" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv:: Signal is not used: 'aruser'", + "signature": "2377b96d0d3218b8" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_STORE_FAULT'", @@ -352,19 +982,79 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/load_decoder.v:: Filename 'load_decoder' does not match MODULE name: 'mpw_core_kianv_rv32i_load_decoder'", - "signature": "2433f234b7caaa2b" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_decoder.sv:: Signal is not used: 's_transform_start'", + "signature": "23d67c1440ff3590" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'mcontext'[63:13]", + "signature": "244d45157104d8f1" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Bits of signal are not used: 'FCT7'[6,4:0]", - "signature": "24678d8b6abaec70" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ag_pipe_pa'[3:0]", + "signature": "2459bad7424ea2c0" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT26'", + "signature": "2460f1314777f120" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Signal is not used: 's_gap_stream_last'", + "signature": "24731ab40ab40aa3" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vtb_entry_wdata_ready'[3:2]", + "signature": "24859fecc087266f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_0_xx_ex1_eu_sel'[9:1]", + "signature": "249753811aa71134" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/retrosoc.sv:: Instance pin connected by name with empty reference: 'write_pending_o'", + "signature": "24af4443bd9174cd" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rtu_cp0_vxsat'", + "signature": "24d834b153ca0e33" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 26 bits on the RHS, but RHS's REPLICATE generates 14 bits.", + "signature": "24f0291353786cfc" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'STIMECMPH1'", + "signature": "2538e5d6dbbf7711" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'frac_num_in'[0]", + "signature": "253a5c0baa1d1428" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER28H'", "signature": "257c44235bf03ff7" }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/rtl/ip/multimedia/npu_pkg.sv:: Parameter is not used: 'LocalBytes'", + "signature": "25bc0d2d4d991988" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's EXTEND generates 6 bits.", + "signature": "25c0976385cc0366" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER15H'", @@ -372,14 +1062,49 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_decode.v:: Filename 'serv_decode' does not match MODULE name: 'mpw_core_serv_serv_decode'", - "signature": "263e9997bd006810" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pad_yy_scan_enable'", + "signature": "26395b6936321f95" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'single1_denorm_shift_num'", + "signature": "266a2f87b4e99cb8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Signal is not used: 'B_DLY'", + "signature": "26980aa3de592a02" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_double_add_inc1_r'[2:0]", + "signature": "269825826cac85da" + }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'BF16_WIDTH'", + "signature": "26ff488db76659f2" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPCFG2'", "signature": "270714b35fca9eb1" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpaddr11_value'[0]", + "signature": "272833bf278ca960" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT31'", + "signature": "2811ac3bbe88344c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'apb_access_pb'[15:4]", + "signature": "2818e1a5fb39c605" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT7'", @@ -395,16 +1120,51 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_ECALL_M'", "signature": "2835c1b086dc09a8" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT29'", + "signature": "283daa722abf0777" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/ga2d_dma.sv:: Instance pin connected by name with empty reference: 'write_strobe_o'", + "signature": "286d8f907e833eb9" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER28'", "signature": "28e02ced23709273" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_job_decoder.sv:: Bits of signal are not used: 's_w14'[15:0]", + "signature": "29050cce6d09b07c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex2_func'", + "signature": "2926fe01ba1c51b5" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'right_8_5_shift_num'[15:8]", + "signature": "293b1f33d47df47c" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ZIP'", "signature": "297075c5bd4bc7a8" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'iui_inst_func'[19:10]", + "signature": "2996456e9107d96a" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_arburst'", + "signature": "299d0aa03d88df53" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/axi4_interconnect.sv:: Signal is not used: 's_target_grant'", @@ -415,6 +1175,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ROL'", "signature": "29e5389475068e49" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'l32_0_shift_result'[47:32]", + "signature": "2a25f7aef4208083" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT18'", @@ -425,11 +1190,66 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MIMPID'", "signature": "2a766dc57899e3d4" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_reg.sv:: Bits of signal are not used: 's_perf_word'[5]", + "signature": "2a7b9b354267772f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_5'[65]", + "signature": "2a889a26fb6947d7" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vtb_entry_split_cnt_vld'[3:2]", + "signature": "2ac70feb352ce05a" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA5'", + "signature": "2b0a3ec36dd6e484" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'idu_iu_ex1_pipedown_vld'", + "signature": "2b8305599660f610" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'CANCLE'", + "signature": "2b96845ba1520bf9" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/rv_opcodes.vh:: Parameter is not used: 'RV_RS2_BITS'", "signature": "2ba7afcc1b2d4504" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpaddr9_value'[0]", + "signature": "2bb8c8b0993aef62" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex2_eu_sel'", + "signature": "2bc6dff07a85783c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_entropy_decoder.sv:: Signal is not used: 's_code'", + "signature": "2bfcf31bc6f9005e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'prio_split_paddr'[23:21,11:9,1:0]", + "signature": "2c0741769019062b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'iui_special_vsetvl_rs1'", + "signature": "2c193cfff57d79e7" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/debug/dm/hazard3_dm.v:: Parameter is not used: 'SBERROR_OK'", @@ -437,14 +1257,64 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/serv/user_core_design.sv:: Instance pin connected by name with empty reference: 'o_ext_rs1'", - "signature": "2d836e64c9a530a8" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex4_rm'", + "signature": "2d38b28d12e9d55a" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT18'", + "signature": "2d522520df7a6517" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'iui_inst_vld_no_brir'", + "signature": "2d72e306c680b543" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'rdl_icc_acc_idx'[1]", + "signature": "2d77458289871977" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'data_shift'[3]", + "signature": "2dca5cad38c82aa9" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MTIMECMP3'", + "signature": "2e2e76bbb2e6666e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pred_btb_tar_pc'[39:16]", + "signature": "2e499a6a94067783" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'right_8_4_shift_num'[15:8]", + "signature": "2e60d9903e0ff007" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'SLEEP'", "signature": "2e8ad717e150a3a3" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF1_CNAN'", + "signature": "2ec1aec50441ae78" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v:: Signal is not used: 'A_BIST_RW_ACCESS'", + "signature": "2ee94236a6774beb" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vtb_entry_fof_vld'[3:2]", + "signature": "2f0f7eb7b34a69cb" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT6'", @@ -452,24 +1322,34 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/mpw/core/kianv_rv32i/user_core_design.sv:: Parameter is not used: 'ID'", - "signature": "2f7f43158f51ce91" + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_awcache'", + "signature": "2f6e10f026559d5c" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER31H'", "signature": "2f8f81579ac32905" }, + { + "count": 6, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_local_sram.sv:: Operator ADD expects 4 bits on the RHS, but RHS's REPLICATE generates 2 bits.", + "signature": "2ffc8be948f6cc45" + }, { "count": 1, - "example": "PINMISSING:$ROOT/rtl/managed/mpw/core/serv/serv/serv_synth_wrapper.v:: Instance has missing pin: 'o_ren'", - "signature": "305227638ca60a5e" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Signal is not used: 's_feed_p_q'", + "signature": "30562273697c9558" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_BEXTM'", "signature": "30f478c3390543de" }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/rtl/ip/multimedia/jpeg_marker_parser.sv:: Parameter is not used: 'ErrorTruncated'", + "signature": "314ed02ea5344c9a" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_LH'", @@ -477,59 +1357,174 @@ }, { "count": 1, - "example": "LATCH:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Latch inferred for signal 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_axi4_sdram.u_sdram_axi4.unnamedblk2.wr_frag' (not all control paths of combinational always assign a value)", - "signature": "323ff436024777f0" + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_awid'", + "signature": "320688d809cab7af" }, { "count": 1, - "example": "WIDTHEXPAND:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Operator COND expects 32 bits on the Conditional True, but Conditional True's LTS generates 1 bits.", - "signature": "3265b302c6465933" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cp0_mmu_satp_data'[43:28]", + "signature": "3260ef39e583fe81" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'biu_ifu_rresp'[0]", + "signature": "326edb38039b6225" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_LW'", "signature": "3279cc6e12dab448" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/apb4_crypto.sv:: Signal is not used: 's_merged'", + "signature": "32a7801604b6e464" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p0_0_cout'[81]", + "signature": "32be193f95a872d9" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'double_pipe_srt_remainder'[58]", + "signature": "32cb8b91a4e44085" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_REFETCH'", "signature": "32cb9f5d916d8bf7" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT26'", + "signature": "32de6335632ed0de" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'plic_int_sync'[0]", + "signature": "3320327e18e6aae1" + }, + { + "count": 7, + "example": "PINMISSING:$ROOT/rtl/tech/tc_io.sv:: Instance has missing pin: 'iovss'", + "signature": "33362aca2bb5379c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vtb_entry_split_cnt_3'", + "signature": "333b1b53fca043a1" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MVENDORID'", "signature": "335de7bf8e6c35ef" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'retire_sub_hmpsp_result'[38:0]", + "signature": "338f08688df94a04" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT27'", + "signature": "3422cf3097ca4f58" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'mhpmevtx_value'[63:6]", + "signature": "342cbffec1bc290d" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator ADD expects 8 bits on the LHS, but LHS's VARREF 'DTM_ABITS' generates 6 bits.", + "signature": "342e7ecac7edeabc" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dc_xx_pa'[2:0]", + "signature": "3455023055f6466c" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'BREAKPOINT_TRIGGERS'", "signature": "348a60446f3a10ba" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'tmp_pos'", + "signature": "349887c43cd73e5f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rtu_cp0_vstart'", + "signature": "34997e59c4e16fb7" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv:: Filename 'cdc_2phase' does not match MODULE name: 'cdc_2phase_src'", "signature": "34ac155b3b3991a1" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/security/crypto_sha2_sram_engine.sv:: Instance pin connected by name with empty reference: 'error_bank_o'", + "signature": "34cf77d44bf5b175" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Bits of signal are not used: 's_restart_interval'[31:16]", + "signature": "34d6d16973ad6d72" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'prio_split_pprot'[2,0]", + "signature": "34da5bae211a90a4" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 17 bits on the LHS, but LHS's VARREF 's_ty_q' generates 13 bits.", + "signature": "35085642b670d26c" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'REDUCED_BYPASS'", "signature": "354fd21123f3a2ac" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'wb_en'[0]", + "signature": "358e0415f06bc3b8" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'WB_IDLE'", + "signature": "35ac98ef9263d40d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'MTVEC_WMASK'", "signature": "35b0cd2fbd79cc6e" }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'D_TAG_INDEX_LEN'", + "signature": "35c692e8904ee531" + }, { "count": 1, - "example": "PROCASSINIT:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Procedural assignment to declaration with initial value: 'XRES'", - "signature": "35c9018653a86b06" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT14'", + "signature": "35cb10d6ade0cb1a" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MCYCLE'", "signature": "35f62a32fb6091eb" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT22'", + "signature": "360d1e688fff9a51" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER29'", @@ -537,8 +1532,13 @@ }, { "count": 1, - "example": "LATCH:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Latch inferred for signal 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_axi4_sdram.u_sdram_axi4.unnamedblk1.rd_last' (not all control paths of combinational always assign a value)", - "signature": "36b0e0e13aa17c74" + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 17 bits on the LHS, but LHS's VARREF 's_tx_q' generates 13 bits.", + "signature": "36889f22ea4e7303" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_sha2_sram_engine.sv:: Signal is not used: 's_scrub_busy'", + "signature": "36b731bff19c1c54" }, { "count": 1, @@ -547,13 +1547,28 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/register_file.v:: Filename 'register_file' does not match MODULE name: 'mpw_core_kianv_rv32i_register_file'", - "signature": "371cb75a0d31b40d" + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'FAST_BRANCHCMP'", + "signature": "3755f80888534459" }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'FAST_BRANCHCMP'", - "signature": "3755f80888534459" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex3_bhalf0_result'[7]", + "signature": "3755fe06617afa4a" + }, + { + "count": 8, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'WE_WIDTH'", + "signature": "377840f5601e0416" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'STIMECMPH3'", + "signature": "377f48c8390dd196" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT14'", + "signature": "378cd288d7091175" }, { "count": 1, @@ -565,11 +1580,21 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR0'", "signature": "37becfab88bb012e" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'CORE_ID'", + "signature": "37ca80be6cd52a6c" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/common/rtl/base/ecc_secded.sv:: Filename 'ecc_secded' does not match PACKAGE name: 'secded_layout_pkg'", "signature": "37d30349cb202ff8" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'dmcs2'", + "signature": "37f09ce3861375a6" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MSECCFGH'", @@ -580,16 +1605,81 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MARCHID'", "signature": "38ad11a2801514f5" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'viq0_xx_ex1_gp_sel'[2:0]", + "signature": "3926b49fdfd8b613" + }, + { + "count": 4, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator SUB expects 32 bits on the LHS, but LHS's REPLICATE generates 29 bits.", + "signature": "3947b595643ed83e" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT25'", + "signature": "39a35f3fe64a0d52" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_8_io_pad'", "signature": "39ad425791d14c56" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF3_CNAN'", + "signature": "39adb2c9c4651b2d" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator COND expects 58 bits on the Conditional False, but Conditional False's REPLICATE generates 34 bits.", + "signature": "39b7654021290678" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex1_id_reg'", + "signature": "39f8eb2ed4e7c3d3" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/tech/tc_pll_ics55_ecos.sv:: Instance pin connected by name with empty reference: 'CKOUT2'", + "signature": "3a27b6e61ceff0ca" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p1_0_cout'[65]", + "signature": "3a6ffde48c7533dc" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'FLG_WIDTH'", + "signature": "3a9f49c4003f104f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bound1_cmp_result'[6:0]", + "signature": "3b3b1ee6bf6fc0fc" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'func'[19:14,11:8,4:3]", + "signature": "3b62467f7b8248c0" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Bits of function variable are not used: 'last_addr'[11:0]", "signature": "3baa9bf591c869f4" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bju_func'[19:12,10:9]", + "signature": "3be3924bcf5bc1ec" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_0'[65]", + "signature": "3beb3424b40a8830" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_SC_W'", @@ -597,14 +1687,19 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Instance pin connected by name with empty reference: 'DLEN'", - "signature": "3c5580a10ed37c86" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Bits of function variable are not used: 's_quotient'[63:32]", + "signature": "3c19147c68c699d3" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT4'", "signature": "3c7e39bdb12c336a" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'WEN'[30:24,22:16,14:8,6:0]", + "signature": "3c8d430e4e87bee9" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v:: Signal is not driven, nor used: 'notifier'", @@ -612,8 +1707,18 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_debug.v:: Filename 'serv_debug' does not match MODULE name: 'mpw_core_serv_serv_debug'", - "signature": "3cbc392ed49a0052" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_0_xx_ex2_func'", + "signature": "3c96e5acc1726594" + }, + { + "count": 2, + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator ADD expects 32 bits on the LHS, but LHS's VARREF 'HART_NUM' generates 5 bits.", + "signature": "3ccb2b9f35c9491a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_0_xx_ex2_rm'", + "signature": "3ce36b92cd542852" }, { "count": 1, @@ -625,6 +1730,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR3'", "signature": "3d0bc595bdd25546" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bju_not_ex1_tar_pc'[0]", + "signature": "3d202a00e3b5e260" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_decoder.sv:: Signal is not used: 's_transform_ready'", + "signature": "3d5395d4f799bc3c" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_instr_decompress.v:: Signal is not used: 'uop_ctr_nxt'", @@ -632,29 +1747,94 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/ip/tiny_timer/user_ip_design.sv:: Filename 'user_ip_design' does not match MODULE name: 'mpw_i1'", - "signature": "3dbdfe4b6b6e6b2b" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'apbif_addr'[39:32]", + "signature": "3d9216312edd4a75" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR6'", "signature": "3dbffffd21477a1a" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'iui_special_vsetvl'", + "signature": "3dd9957240a5f80e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_core.sv:: Signal is not used: 's_job_base_q'", + "signature": "3ddba8b3fcd0a1d5" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'iui_vsetvl_data'[4]", + "signature": "3dde18e466d1fde3" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT20'", + "signature": "3df9f7ecd1d38042" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/soc_data_plane.sv:: Instance pin connected by name with empty reference: 'write_pending_o'", + "signature": "3e1191e94da368b8" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_MULOP'", "signature": "3e3ced20ab2d11ea" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Bits of signal are not used: 's_wrow_abs'[33:11]", + "signature": "3e4ebe2f0d1d01e0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_1_xx_ex1_eu_sel'[9:8,5:2,0]", + "signature": "3e694db122fe93cb" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_30_io_pad'", "signature": "3f1d0963252c64c8" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_1'[81]", + "signature": "4013c109f71a7451" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZCLSD'", "signature": "402ae240d37858c6" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT22'", + "signature": "40740f3bcd050109" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pb_work_zero'", + "signature": "41540898d8a1400e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex1_id_reg'", + "signature": "4167b9153b6baf68" + }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 34 bits on the Assign RHS, but Assign RHS's ADD generates 35 bits.", + "signature": "41c0b5c07e8d8a39" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT31'", + "signature": "41e80ea803877747" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER8'", @@ -670,16 +1850,41 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MENVCFG'", "signature": "4215449e4df3de5e" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p0_1_cout'[81]", + "signature": "425771268100288b" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER13'", "signature": "42bd6d7013835fc4" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'tdt_dm_dtu_halt_req_cause'", + "signature": "42d9405d913b2633" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Signal is not used: 's_encode_busy'", + "signature": "42e0a06241dac2ba" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_core.sv:: Bits of signal are not used: 'launch_data_i'[127:112]", + "signature": "42eb4d5679557bd6" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TIME'", "signature": "4306e7c3b887b709" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ifu_cp0_warm_up'", + "signature": "438894209807f5cc" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER26'", @@ -690,16 +1895,56 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_LTU'", "signature": "43de1e8c0580a8f6" }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator COND expects 58 bits on the Conditional True, but Conditional True's REPLICATE generates 34 bits.", + "signature": "43edcb8de4f3856d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex1_id_reg'", + "signature": "43fde45d4ff34569" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'alu_func'[19,4]", + "signature": "4431d99e11c343a5" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT22'", + "signature": "445faa8de7c06a5d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apu_kws_engine.sv:: Bits of function variable are not used: 'lookup_i'[27:17]", + "signature": "447e308ac8567e8b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_1'[65]", + "signature": "45354a15c280e804" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHARTID'", "signature": "455c87de9a6187f4" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT20'", + "signature": "4567ca915033cf26" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_12_io_pad'", "signature": "456b371e296b1f23" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MTIMECMPH3'", + "signature": "456df3d2ff5666ba" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TSELECT'", @@ -710,11 +1955,31 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_BCOND'", "signature": "4584857873073628" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ALL'", + "signature": "45af1203920382dd" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex2_func'", + "signature": "4617385c2b483c82" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_RS2'", "signature": "461a7b607180c0ae" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT18'", + "signature": "46558dd316641bb3" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'hg_sel_core'", + "signature": "465fd1c079f71e3a" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER15'", @@ -727,13 +1992,23 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_rf_ram_if.v:: Filename 'serv_rf_ram_if' does not match MODULE name: 'mpw_core_serv_serv_rf_ram_if'", - "signature": "46ea1f9d6bc05519" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT24'", + "signature": "471e9e20ad06f60d" }, { "count": 1, - "example": "WIDTHEXPAND:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Operator COND expects 32 bits on the Conditional True, but Conditional True's LT generates 1 bits.", - "signature": "4733c5d026ac9e5f" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex1_srcv2_type'", + "signature": "471fbd64b7f89b92" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pad_biu_rid'[7:4]", + "signature": "472e91443da528d6" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex3_mult_expnt_p1'[12:11]", + "signature": "473db926a60b4b37" }, { "count": 2, @@ -742,14 +2017,49 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/control_unit.v:: Filename 'control_unit' does not match MODULE name: 'mpw_core_kianv_rv32i_control_unit'", - "signature": "47ccc730f259e974" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex3_rm'", + "signature": "47cdb8541c01dcae" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex4_rm'", + "signature": "4813df6dc31978bd" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'srcv0_type'[34:28,20:0]", + "signature": "4852aa40fccdfc08" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex4_rm'", + "signature": "488ad278c100b0d6" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_op1_single0'[30:0]", + "signature": "489e1439b69a156c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'lsu_dtu_ldst_addr'[3:0]", + "signature": "48ee6187b9a3b1e3" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p1_1_cout'[65]", + "signature": "48fe86e768dc31ca" }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_irq_ctrl.v:: Bits of signal are not used: 'wdata_raw'[31:7]", "signature": "4900218b5efcf61e" }, + { + "count": 1, + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator ADD expects 32 bits on the RHS, but RHS's CONST '7'h1' generates 7 bits.", + "signature": "490ef80f57c31e50" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v:: Signal is not used: 'A_BIST_W_ACCESS'", @@ -760,6 +2070,16 @@ "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'audclk_i_pad'", "signature": "49308ef54c516e86" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'kid_arb_int_pulse'", + "signature": "49b8889a3a8fa4d1" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF1_INF'", + "signature": "49c49ea13290d0a9" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'CSR_COUNTER'", @@ -767,19 +2087,19 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/serv/serv/serv_synth_wrapper.v:: Instance pin connected by name with empty reference: 'o_mdu_valid'", - "signature": "4a0123e6f14fc5ec" - }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'OPCODE'", - "signature": "4a34235c605f92a2" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'STIMECMPH2'", + "signature": "4a2c46e554b4fe14" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUSRCA_PC'", "signature": "4a5301b26725055d" }, + { + "count": 1, + "example": "UNDRIVEN:$ROOT/rtl/mini/top/retrosoc.sv:: Bits of signal are not driven: 'unused_cdc_epoch'[7:0]", + "signature": "4a7522bd66a42849" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TINFO'", @@ -790,6 +2110,11 @@ "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_2_io_pad'", "signature": "4ae2caed82a929f4" }, + { + "count": 8, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DATA_WIDTH'", + "signature": "4b298d8bb879338c" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_INSTR_ILLEGAL'", @@ -800,6 +2125,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_MRET'", "signature": "4c2a4a8300420a20" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ICHE'", + "signature": "4c3b820ec4436ef4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_double_sub_r'[56]", + "signature": "4c3db2ab7d5e9b86" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'MULH_FAST'", @@ -807,34 +2142,84 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_decode.v:: Bits of signal are not used: 'i_wb_rdt'[31,29:27,24:23,19:15,11:7]", - "signature": "4cbcaba91ae93f45" + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Signal is not used: 'A_DLY'", + "signature": "4cb1365b43acb0a9" + }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/ga2d_dma.sv:: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 's_read_total_bytes_q' generates 8 bits.", + "signature": "4d043ba28c0472e8" }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_ctrl.v:: Filename 'serv_ctrl' does not match MODULE name: 'mpw_core_serv_serv_ctrl'", - "signature": "4d15929229697246" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vlsu_vidu_split_cancel'", + "signature": "4d671ef585a1be79" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT30'", "signature": "4de9df4639f15bf4" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'tag_idx'[5:0]", + "signature": "4e10284c74f0c215" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT19'", + "signature": "4e4d74a513d95251" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Signal is not used: 's_perf_clear'", + "signature": "4e54702f4b3b8d96" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rem_add1_op1_s'", + "signature": "4e701e647e52be35" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF2_ID'", + "signature": "4e8f09f09f411228" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/tech/tc_clk.sv:: Filename 'tc_clk' does not match MODULE name: 'tc_clk_inv'", "signature": "4ec048718bb177a1" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT30'", + "signature": "4eea1a2b27a5d53e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'double_pipe_total_qt_rt'[57,2:0]", + "signature": "4f384a7d003f0523" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'CSR_WTYPE_C'", "signature": "4f4910761ec270d7" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/ga2d_pixel.sv:: Bits of signal are not used: 's_background_rgba'[31:24]", + "signature": "4fa9f77bcf4163bd" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_LOAD_FAULT'", "signature": "4fb8fdc3c3390dbb" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ref_tag'[11:0]", + "signature": "4fb92c73b3260b85" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_HARDWIRED_ADDR'", @@ -845,6 +2230,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MEDELEG'", "signature": "4fcb995a51d1180a" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MCNTWEN'", + "signature": "5058380dcc9af19d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR13'", @@ -855,6 +2245,11 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_instr_decompress.v:: Signal is not used: 'rst_n'", "signature": "507b9eff33d37568" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT26'", + "signature": "50a0755472793577" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv:: Signal is not used: 'aclk'", @@ -865,6 +2260,21 @@ "example": "WIDTHEXPAND:$ROOT/rtl/ip/memory/sdram_core.sv:: Operator ADD expects 3 bits on the LHS, but LHS's SEL generates 1 bits.", "signature": "516ba44ddfe59750" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dtm_pad_tms_o'", + "signature": "5191bc4f9f7460e6" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_wvalid'", + "signature": "51a4282e62ff4d48" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apu_microcode_loader.sv:: Bits of function variable are not used: 's_mixed'[50:0]", + "signature": "51a6e3e03af27680" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_BSET'", @@ -875,6 +2285,31 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_C'", "signature": "51fb79f7714621a3" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bju_op_func'[0]", + "signature": "520e281276df01ba" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex4_expnt_rst'[12:11]", + "signature": "5216b94858c01b65" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT23'", + "signature": "522d7fdfa3207679" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dm_paddr'[1:0]", + "signature": "525504f3c6dc301f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'create1_en'[0]", + "signature": "527e031a082a8765" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER13H'", @@ -890,11 +2325,51 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_SB'", "signature": "5298c4e58dca3b51" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex3_sel'", + "signature": "52b4268b4a123194" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER27H'", "signature": "52b807210a574b9c" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dc_st_data_shift'[3]", + "signature": "52c9190adfb41750" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Signal is not used: 's_plane2_stride'", + "signature": "52e2f33752922647" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpaddr12_value'[0]", + "signature": "5317b74f4f72d7d4" + }, + { + "count": 1, + "example": "UNOPTFLAT:$ROOT/rtl/mini/top/axi4_target_guard.sv:: Signal unoptimizable: Circular combinational logic: 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_data_plane.gen_memory_target[0].u_target_guard.s_write_timeout_pending'", + "signature": "5337fe9aa9cd8c84" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_arcache'", + "signature": "53808cbd2cfb25e4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex4_func'", + "signature": "53ac95fb891e8ace" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/core/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'fence_i_vld'", + "signature": "53c290a79269312d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'M_OP_MUL'", @@ -912,14 +2387,64 @@ }, { "count": 1, - "example": "EOFNEWLINE:$ROOT/rtl/managed/clusterip/i2c/rtl/i2c_if.sv:: Missing newline at end of file (POSIX 3.206).", - "signature": "54113bbce1e87b2a" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pad_cpu_apb_base'[26:0]", + "signature": "5433b5cdc7f3495b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'close_ff1_t_t0'[0]", + "signature": "543a928826386d7e" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT12'", + "signature": "544d27aaa043f04e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_decode_core.sv:: Signal is not used: 's_component_id'", + "signature": "5488fb9f572d5854" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_wdata'", + "signature": "54b6bb6ceeb686b0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_func'[19:7,3]", + "signature": "54f68ac48f04c51a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cp0_xx_mrvbr'[0]", + "signature": "5507d1d957d32c67" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Parameter is not used: 'DCSR_CAUSE_EBREAK'", "signature": "550e02682aa2da16" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_src0_bhalf'[31:16]", + "signature": "553c8a4d84f3b2e3" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator LT expects 32 bits on the LHS, but LHS's REPLICATE generates 29 bits.", + "signature": "5563ec0d7ff2df43" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'PA'", + "signature": "559f285cf6d8d9df" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT24'", + "signature": "56049d65466cea18" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER10H'", @@ -930,6 +2455,26 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MIDELEG'", "signature": "56eba9c6e5b585b8" }, + { + "count": 1, + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator SUB expects 8 bits on the RHS, but RHS's VARREF 'DTM_ABITS' generates 6 bits.", + "signature": "56f56a356c122a84" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dc_xx_pa'[39:12,5:0]", + "signature": "56f7ff199aad4f5d" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_CUSBUF7'", + "signature": "572e183af043412f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_0_xx_ex5_sel'", + "signature": "5734b18a737fb969" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MCAUSE'", @@ -940,6 +2485,31 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_AMO'", "signature": "5746a6ef992cd0f3" }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator SUB expects 7 bits on the RHS, but RHS's VARREF 's_pbase_q' generates 4 bits.", + "signature": "574f988dcc0d5dd8" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT21'", + "signature": "579477a7711a2aa4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_dma.sv:: Bits of function variable are not used: 's_mask'[8]", + "signature": "57d08ec34f8b1019" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'PRIO_SPLIT1_FOR_CMP'", + "signature": "57f54d850396fbfe" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_4'[65]", + "signature": "5819f8fc0449eded" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_LB'", @@ -947,14 +2517,69 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/kianv_rv32i/user_core_design.sv:: Instance pin connected by name with empty reference: 'PC'", - "signature": "5908191e9b3f7093" + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/core/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'hexcl'", + "signature": "58aaef9ec233fda2" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'BCOND_NZERO'", "signature": "591eebcbf05ae38c" }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator GTE expects 14 bits on the RHS, but RHS's CONST '5'h8' generates 5 bits.", + "signature": "592ec8e084d21632" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bju_cur_pc_ext'[0]", + "signature": "59c11c83f281d0a8" + }, + { + "count": 3, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/jpeg_block_decoder.sv:: Instance pin connected by name with empty reference: 'start_ready_o'", + "signature": "59de5b5c54a94f1a" + }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DOUBLE_WIDTH'", + "signature": "5a2c0336a0e060a2" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator SUB expects 18 bits on the RHS, but RHS's REPLICATE generates 14 bits.", + "signature": "5a61d0afa53412ba" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_bhalf0_sub_r'[11,9:0]", + "signature": "5a6a7ec2a5e813af" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vlsu_index_stall'", + "signature": "5a919aa5078b3764" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT_NUM'", + "signature": "5ac02252e9f35596" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_awvalid'", + "signature": "5ac164b872f7f975" + }, + { + "count": 1, + "example": "DECLFILENAME:$BUILD/generated/openc906/openc906_combined.v:: Filename 'openc906_combined' does not match MODULE name: 'BUFGCE'", + "signature": "5ac3d7d8660b0f10" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_64x32_c2.v:: Signal is not used: 'A_W_ACCESS'", + "signature": "5b00cc7abaa28639" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ROR'", @@ -962,8 +2587,43 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Instance pin connected by name with empty reference: 'DEBUG'", - "signature": "5b5b61b7f9634714" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'rot'[4]", + "signature": "5b2e134847a43185" + }, + { + "count": 1, + "example": "UNDRIVEN:$ROOT/rtl/mini/top/retrosoc.sv:: Bits of signal are not driven: 'unused_cdc_clear_busy'[0]", + "signature": "5b38c0558d0661b5" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'mst_paddr'[134:120,107:93,80:67,53:39,26:18]", + "signature": "5b3ef86f4115fb25" + }, + { + "count": 1, + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/jpeg_mcu_reconstructor.sv:: Declaration of signal hides declaration in upper scope: 'block_i'", + "signature": "5b5d0dd8d3fcebd4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'apbw_dmcs2'", + "signature": "5ba9994c513e8975" + }, + { + "count": 1, + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/jpeg_transform.sv:: Declaration of signal hides declaration in upper scope: 'inverse_i'", + "signature": "5bc7e80fbc92c710" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT28'", + "signature": "5c217fe38a4b325a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv:: Signal is not used: 'awuser'", + "signature": "5c708ab2d848645c" }, { "count": 1, @@ -980,6 +2640,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MINSTRETH'", "signature": "5d19ef0c8ba1c56f" }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'BF16_FRAC'", + "signature": "5d2e7d29134467fb" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dcache_tag_dout_bank1'[118,88,58,28]", + "signature": "5d44142ee1a8eb8a" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT11'", @@ -990,6 +2660,41 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'M_OP_MULHSU'", "signature": "5d65541dc13b8bfb" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT26'", + "signature": "5d7496c960645df4" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'clk_en_bf_latch'", + "signature": "5d8287c7de07ba6e" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DTM_DMIACCREG_WIDTH'", + "signature": "5de2367b892d93b8" + }, + { + "count": 8, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ADDR_WIDTH'", + "signature": "5df82a7231153738" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT17'", + "signature": "5e1b5f43d4301113" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ag_pipe_va_add_unalign'[2:0]", + "signature": "5e5c40c26a435012" + }, + { + "count": 2, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS's SUB generates 34 bits.", + "signature": "5e84eb60242584f1" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_OR'", @@ -1000,26 +2705,81 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MTVAL'", "signature": "5f0f64553ce97b85" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'double_pipe_ex2_special_result'[63]", + "signature": "5f159ecf362a2de6" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZCB'", "signature": "5f188e1e6e7624cc" }, + { + "count": 4, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 32 bits on the LHS, but LHS's REPLICATE generates 29 bits.", + "signature": "5f3aabf86d32f8f8" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_GRAIN'", "signature": "5f511bc2d35407ec" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'mmu_ifu_so'", + "signature": "5f71501e4f2a69b5" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'hart_ie_pprot'[0]", + "signature": "5f8cbfd5909db0ba" + }, + { + "count": 4, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/apu_microcode_loader.sv:: Operator FUNCREF 'trap_detail' expects 12 bits on the Function Argument, but Function Argument's SEL generates 11 bits.", + "signature": "5fc1431144b97bec" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'lsu_vl_upval'", + "signature": "5fe503b2d7a7b838" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'RESET_REGFILE'", "signature": "60076cfad9a08606" }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator LT expects 14 bits on the LHS, but LHS's REPLICATE generates 13 bits.", + "signature": "6025c20341decd09" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_PACKH'", "signature": "604b08fddeace7e0" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Instance pin connected by name with empty reference: 'access_err_port_o'", + "signature": "6055a8ad5734d57c" + }, + { + "count": 3, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/jpeg_decode_core.sv:: Instance pin connected by name with empty reference: 'start_ready_o'", + "signature": "60652dd82fa74152" + }, + { + "count": 1, + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/ga2d_pixel.sv:: Declaration of signal hides declaration in upper scope: 's_alpha'", + "signature": "60ae37611b68789e" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA9'", + "signature": "60ce82cd6074c1a2" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_14_io_pad'", @@ -1027,19 +2787,64 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_bufreg.v:: Filename 'serv_bufreg' does not match MODULE name: 'mpw_core_serv_serv_bufreg'", - "signature": "61aa422d0c89d539" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'half1_denorm_shift_num'", + "signature": "610fd7ed19bfc5a7" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_2'[65]", + "signature": "613a27969d382171" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'lsu_vlsu_func'[19:12,9:0]", + "signature": "61567550a818cd0d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpaddr10_value'[0]", + "signature": "6185c331e95c4662" + }, + { + "count": 3, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Instance pin connected by name with empty reference: 'start_ready_o'", + "signature": "61aa0dc9732fc80d" }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v:: Signal is not used: 'A_W_ACCESS'", "signature": "61ba634af74ae785" }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS's REPLICATE generates 13 bits.", + "signature": "620a7ec02b762f80" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPCFGM0'", "signature": "623bf821e2a9c639" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex4_sel'", + "signature": "623df1da3227959f" + }, + { + "count": 1, + "example": "SPECIFYIGN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v:: Ignoring unsupported: specify block construct", + "signature": "624f1fd7c7e5396a" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF3_QNAN'", + "signature": "62547d5989d6b9e8" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SSIP2'", + "signature": "627ba21166809d6b" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT28'", @@ -1047,13 +2852,48 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_synth_wrapper.v:: Filename 'serv_synth_wrapper' does not match MODULE name: 'mpw_core_serv_serv_synth_wrapper'", - "signature": "63e3dd4583dab654" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ID_NUM'", + "signature": "63a1b3e1bd611993" + }, + { + "count": 3, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'srcv0_type'[42,35:28,21:0]", + "signature": "63f05284b486918d" }, { "count": 1, - "example": "PROCASSINIT:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Procedural assignment to declaration with initial value: 'IDATA2'", - "signature": "64038d5659d02861" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'idu_iu_ex1_src0_reg'[5]", + "signature": "649d8d7e8617a0ec" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_encoder.sv:: Signal is not used: 's_quant_ready'", + "signature": "64b3fe1f5eec0cb2" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'xx_create_init_pa'[5:0]", + "signature": "64bad8d85473d311" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 58 bits on the RHS, but RHS's REPLICATE generates 34 bits.", + "signature": "64d44f6b8b5f5463" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_64x32_c2.v:: Signal is not driven, nor used: 'notifier'", + "signature": "64d494d05b73e739" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Bits of signal are not used: 's_input_format'[31:3]", + "signature": "64e1e82120d31a11" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_0_xx_ex4_rm'", + "signature": "65235737bed4ec83" }, { "count": 1, @@ -1065,31 +2905,116 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/dv/verilator/rtl/QSPIFlash.sv:: Bits of signal are not used: 's_raddr'[31:24]", "signature": "658adb1a54f05dd5" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF3_SNAN'", + "signature": "6590311f54ccf3dc" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'alu_adder_src2'[63:7,4:0]", + "signature": "65e80bd6b2e2a654" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_wbt_src0_reg'[5]", + "signature": "65f3ba49a13ee25b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'bhalf1_denorm_shift_num'", + "signature": "66054491fd5301c3" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex1_srcv2'", + "signature": "662418737d78b93c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'idu_vidu_ex1_vec_gateclk_sel'", + "signature": "666bbdbf4d10699f" + }, + { + "count": 2, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS's REPLICATE generates 28 bits.", + "signature": "668f58a0f81c4b00" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'MUL_FASTER'", "signature": "66bea68133be6a24" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT17'", + "signature": "66e7794d69562913" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER30'", "signature": "67011f5eacc2e78f" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_single_special'[63:32]", + "signature": "67363899c7ded36e" + }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS's ADD generates 16 bits.", + "signature": "6788da3abbd7ed97" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmp_csr_wen'[17:10,1]", + "signature": "67d0b74df558c9a5" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT21'", "signature": "67e8e8f7c1532aac" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apu_kws_sram_client.sv:: Bits of function variable are not used: 'address_i'[15:9,5,1:0]", + "signature": "683e28e61c321ede" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT20'", "signature": "687cf8025c3b151b" }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ff1_32_bit'[13:5]", + "signature": "68811fad053aeb71" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT13'", + "signature": "68821f2a3b920120" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_mcu_builder.sv:: Bits of function variable are not used: 's_pixel1'[7:0]", + "signature": "68a7d4c1781711a1" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'CAUSE'", + "signature": "68b9c7d483f13321" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_LOAD_ALIGN'", "signature": "68e41749beb432ef" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_mem_ctrl.sv:: Signal is not used: 's_scrub_busy'", + "signature": "68f52d42950f03da" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_SEXT_H'", @@ -1097,14 +3022,59 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Filename 'darkriscv' does not match MODULE name: 'mpw_core_darkriscv_darkriscv'", - "signature": "6988e9cf3eee9ca1" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/ga2d_core.sv:: Bits of function variable are not used: 'value_i'[31:2]", + "signature": "696438272c4f4a3d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rem_add2_op1_s'", + "signature": "6967eacfaab5ce9a" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT23'", + "signature": "69767a63bbf628e2" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv:: Signal is not used: 'ruser'", + "signature": "698f3c7c814af36f" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER14H'", "signature": "699eaad14a6020d7" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex4_stall'", + "signature": "69a1a5a941614a66" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_gpr_src2_reg'[5]", + "signature": "69c46812077a48c0" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT13'", + "signature": "6a1232e318cb60e7" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_encode_core.sv:: Bits of signal are not used: 's_token_payload_out'[155]", + "signature": "6a270e0702941282" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_mcu_builder.sv:: Bits of function variable are not used: 's_pixel3'[7:0]", + "signature": "6a41ec33ac77ed9d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'arcache'[3:2,0]", + "signature": "6a9df07a2ea93589" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TDATA1'", @@ -1115,6 +3085,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/rv_opcodes.vh:: Parameter is not used: 'RV_RS1_BITS'", "signature": "6af66eb3b381eef4" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/soc_data_plane.sv:: Bits of signal are not used: 's_master_idle'[5,1:0]", + "signature": "6b92483b1afec9b5" + }, + { + "count": 4, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/jpeg_transform.sv:: Operator ADD expects 48 bits on the RHS, but RHS's ARRAYSEL generates 25 bits.", + "signature": "6bfff568137deac7" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER20H'", @@ -1122,19 +3102,64 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/serv/serv/serv_synth_wrapper.v:: Instance pin connected by name with empty reference: 'o_ext_rs1'", - "signature": "6c870030d5ccb560" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'bid'", + "signature": "6c7cb28a039fea8a" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MSECCFG'", "signature": "6cb6b8ad455cc035" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'regs_tvec'[1]", + "signature": "6cf860adab9eb257" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'PGS_WIDTH'", + "signature": "6d37bd173da5182c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'tag_din'[118,88,58,28]", + "signature": "6d586041a2c56818" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF0_ID'", + "signature": "6d84c07c022cff58" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'busif_clr_kid_ip'[0]", + "signature": "6df806cdeea296d4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_srcv1'[63:52]", + "signature": "6e2d2cadd3fbbc56" + }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/ga2d_dma.sv:: Operator ADD expects 32 bits on the LHS, but LHS's VARREF 's_row_index_q' generates 16 bits.", + "signature": "6e3cf2adf37cff88" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_UNZIP'", "signature": "6f439f5e9a4d68c8" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_decoder.sv:: Signal is not used: 's_quant_ready'", + "signature": "6f445c0a8b0f022b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rid'", + "signature": "6f4c8b6298ba8342" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/debug/dm/hazard3_dm.v:: Bits of signal are not used: 'dmi_paddr'[1:0]", @@ -1142,14 +3167,39 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/serv/user_core_design.sv:: Instance pin connected by name with empty reference: 'o_mdu_valid'", - "signature": "6fd395c55ba8ba26" + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v:: Signal is not used: 'A_W_ACCESS'", + "signature": "7049aac2959de7b5" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_E'", "signature": "70d98e6c61f99efe" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dc_xx_pa'[39:22,5:0]", + "signature": "70e671572f5c0572" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_aes_sram_core.sv:: Bits of signal are not used: 'constant_resp_i'[52:42,9:0]", + "signature": "70e8a19dc4d22e6d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex4_eu_sel'", + "signature": "70f211e175df33d0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'right_8_1_shift_num'[15]", + "signature": "712a1296ce312be2" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator LTE expects 38 bits on the RHS, but RHS's REPLICATE generates 30 bits.", + "signature": "7152f64b90484487" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'INSTRET'", @@ -1157,13 +3207,28 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/rv_opcodes.vh:: Parameter is not used: 'RV_RS1_LSB'", - "signature": "720de1ded416bbe9" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_special_sign'[3]", + "signature": "7182e22fc31f4ed3" }, { "count": 1, - "example": "LATCH:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Latch inferred for signal 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_axi4_sdram.u_sdram_axi4.unnamedblk1.rd_frag' (not all control paths of combinational always assign a value)", - "signature": "727e3bf5db241f8b" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_rnd_adder_f_p1_f'[53:52]", + "signature": "71b649649efc0fc1" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 14 bits on the LHS, but LHS's REPLICATE generates 4 bits.", + "signature": "71e533c864a57e81" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'iu_ifu_bht_cur_pc'", + "signature": "720a2432c0978e2d" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/rv_opcodes.vh:: Parameter is not used: 'RV_RS1_LSB'", + "signature": "720de1ded416bbe9" }, { "count": 1, @@ -1175,11 +3240,36 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZBS'", "signature": "73ca0e54008058b8" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_arid'", + "signature": "740932ad706ace0f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_mcu_reconstructor.sv:: Bits of function variable are not used: 's_sum'[0]", + "signature": "7410864dfd37b058" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT25'", + "signature": "74297985fcc903a4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vlsu_rbus_vpr_wb_req'", + "signature": "74616d3df5bc6c87" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ANDN'", "signature": "746a132b58684b0c" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT30'", + "signature": "747ba1b96deba4ea" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER9'", @@ -1187,13 +3277,13 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_rf_if.v:: Filename 'serv_rf_if' does not match MODULE name: 'mpw_core_serv_serv_rf_if'", - "signature": "74d93eda664174c1" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF2_ZERO'", + "signature": "74a52bea6929ac84" }, { - "count": 1, - "example": "EOFNEWLINE:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v:: Missing newline at end of file (POSIX 3.206).", - "signature": "7503098f8f45feb2" + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_1_xx_ex2_eu_sel'[9:8,5:1]", + "signature": "753ff1a945af14e3" }, { "count": 1, @@ -1202,19 +3292,74 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_bufreg.v:: Signal is not used: 'i_shamt'", - "signature": "758916bc522c013a" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'kid_int_active'", + "signature": "75924ac6bbdb6f61" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex1_srcv2_type'", + "signature": "759a2c9f9a5b4a68" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SLV_DIV'", + "signature": "7611b730a6d2e589" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'core0_pad_retire'", + "signature": "76835b75c29b104d" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MCOUNTEREN'", "signature": "776c10307a688b62" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'iui_regs_wdata'[63:32,30:27,22:8]", + "signature": "778bcba57a2bb228" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/managed/hazard3/hdl/arith/hazard3_onehot_encode.v:: Operator LT expects 32 bits on the LHS, but LHS's VARREF 'i' generates 7 bits.", + "signature": "77a2b85a18b92d9c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'byte_zero'[0]", + "signature": "77c130e2d5b64ab2" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MSLEEP'", "signature": "77cfd15c72609921" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_1_xx_ex3_eu_sel'[9:8,5:1]", + "signature": "77ef5fe31e725f8b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex3_func'", + "signature": "78d594c24d6130ed" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'apb_mst_penable_pre'", + "signature": "78f9fdd44c54d953" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_decode_core.sv:: Signal is not used: 's_component_factor'", + "signature": "790ebe18b260d539" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ACTION_01'", + "signature": "797b0e82c7a8820f" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'uart0_rx_i_pad'", @@ -1222,19 +3367,74 @@ }, { "count": 1, - "example": "SPECIFYIGN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v:: Ignoring unsupported: specify block construct", - "signature": "7a759d6e07651fd8" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT25'", + "signature": "79bcd773f0a95d43" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/ga2d_dma.sv:: Instance pin connected by name with empty reference: 'write_address_o'", + "signature": "79c21e20eb88ea25" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF3_NORM'", + "signature": "7a2f677b6121b6ea" + }, + { + "count": 7, + "example": "PINMISSING:$ROOT/rtl/tech/tc_io.sv:: Instance has missing pin: 'vdd'", + "signature": "7a58d5740d345646" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cp0_pmp_wdata'[62:61,54:53,46:45,38,6:5]", + "signature": "7a67166eabf1325e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_64x32_c2.v:: Signal is not used: 'B_W_ACCESS'", + "signature": "7a6bb014a7ad51f1" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT14'", + "signature": "7a8b0cbf595d929c" + }, + { + "count": 2, + "example": "STMTDLY:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_64x32_c2.v:: Ignoring delay on this statement due to --no-timing", + "signature": "7ab9216316c2af0f" }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_0_io_pad'", "signature": "7b105b7a92957ce9" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_CUSBUF6'", + "signature": "7b254f4f8492ab7d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'int_sec_infor'[0]", + "signature": "7b5f7be4c22e80c4" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_awaddr'", + "signature": "7b8ae98a765aec51" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Signal is not used: 'match_urw'", "signature": "7b9059d806e00577" }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator GT expects 37 bits on the RHS, but RHS's CONST '25'h400' generates 25 bits.", + "signature": "7ba18373efb1a01b" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_CTZ'", @@ -1245,6 +3445,11 @@ "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_18_io_pad'", "signature": "7be345de9e1435dd" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Signal is not used: 's_kh_q'", + "signature": "7bf6258a50db9e2e" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER20'", @@ -1252,13 +3457,18 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/femtorv32/user_core_design.sv:: Bits of signal are not used: 's_mem_addr'[1:0]", - "signature": "7d77240b3d7ea34d" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'dt_trig_en'", + "signature": "7caa31e03bebfd2b" }, { "count": 1, - "example": "LATCH:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Latch inferred for signal 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_axi4_sdram.u_sdram_axi4.unnamedblk2.wr_legal' (not all control paths of combinational always assign a value)", - "signature": "7dccafa79aaf23d1" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'bhalf2_denorm_shift_num'", + "signature": "7ce3c6dbb058902f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'prio_split_pwdata'[63:37,31:5]", + "signature": "7d2379d785ce5a25" }, { "count": 1, @@ -1270,6 +3480,21 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'aresetn'", "signature": "7e24f33fb923deb5" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_src1'[62:32]", + "signature": "7e5c59ccbfd2d319" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'exception_codes_onehot'[31:18]", + "signature": "7ea3f769e9a04f6c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'single0_total_qt_rt'[27]", + "signature": "7ebf064ad2c09590" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT16'", @@ -1285,11 +3510,21 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER27'", "signature": "7f30d21586d6102f" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_encoder.sv:: Signal is not used: 's_transform_block'", + "signature": "7f9ef3fa9288774a" + }, { "count": 1, "example": "UNOPTFLAT:$ROOT/rtl/ip/memory/axi4_sdram.sv:: Signal unoptimizable: Circular combinational logic: 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_axi4_sdram.s_wr_cmd_ready'", "signature": "7fb5bf9e2485a568" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_half0_sub_r'[14,12:0]", + "signature": "7fc5075b5fc9fe71" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR11'", @@ -1307,14 +3542,29 @@ }, { "count": 1, - "example": "PROCASSINIT:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Procedural assignment to declaration with initial value: 'HLT2'", - "signature": "80f9f1e6b043cbcd" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'jtlb_data_idx'[8:6]", + "signature": "80ff70f0a4a7c057" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ZEXT_H'", "signature": "8128a297b319a139" }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/rtl/ip/security/crypto_pkg.sv:: Parameter is not used: 'SHA2_256'", + "signature": "8173dcef985f898a" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_araddr'", + "signature": "819548a7eb8116f6" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MSIP2'", + "signature": "824671bdad9cc121" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT9'", @@ -1325,16 +3575,56 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_SH'", "signature": "830d44a2987b0b08" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_decode_core.sv:: Signal is not used: 's_table_portal_status'", + "signature": "83111637431ba8fb" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT31'", + "signature": "8313b0317de560c7" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv:: Signal is not driven, nor used: 's_ack_src_d'", "signature": "83a2f710883a0dfd" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'rtu_cp0_epc'[0]", + "signature": "83e3abda06796e93" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ELEM'", + "signature": "83fbd3c86aa3467e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/sdio_reg.sv:: Bits of signal are not used: 's_host_ctrl_q'[1]", + "signature": "84058b3af12fb120" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Signal is not used: 's_plane2_addr'", + "signature": "841ea4c0bcde002d" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v:: Filename 'RM_IHPSG13_1P_core_behavioral_bm_bist' does not match MODULE name: 'SRAM_1P_behavioral_bm_bist'", "signature": "842a1042c53ad9f4" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pred_btb_cur_pc'[39:16]", + "signature": "843c3175a89af6b9" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'busif_set_kid_ip'[0]", + "signature": "8441919d22e1cea5" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v:: Signal is not driven, nor used: 'notifier'", @@ -1352,8 +3642,13 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_rf_top.v:: Filename 'serv_rf_top' does not match MODULE name: 'mpw_core_serv_serv_rf_top'", - "signature": "847336fd629f5dd2" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex3_eu_sel'", + "signature": "846d332651c0d027" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_bhalf_special'[63:16]", + "signature": "847aa0a26ca4b6d2" }, { "count": 1, @@ -1362,8 +3657,33 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Instance pin connected by name with empty reference: 'HLT'", - "signature": "8558e9362c52e672" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bound2_cmp_result'[6:0]", + "signature": "84bdc7418f00fd87" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'right_8_2_shift_num'[15]", + "signature": "850fdeaed22fb779" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_encoder.sv:: Signal is not used: 'reciprocal_i'", + "signature": "852c2c9230ef9f70" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT14'", + "signature": "85676419c95eaeb5" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vtb_entry_split_cnt_2'", + "signature": "8575c8acfd9aa0d8" + }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator SUB expects 13 bits on the RHS, but RHS's REPLICATE generates 4 bits.", + "signature": "8588989e002ef6f4" }, { "count": 1, @@ -1372,19 +3692,24 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'DBER'", - "signature": "860000f57059e276" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_0_xx_ex2_eu_sel'[9:1]", + "signature": "85b0e6ecefd23337" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'rot_ori'[3]", + "signature": "85b7adb8f7dcf4ea" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_wlast'", + "signature": "85cba8a9ac7b3253" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER29H'", "signature": "860ed6ab6f7358e7" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/ribp_if.sv:: Signal is not used: 'resp_err'", - "signature": "863536f8ba40d4d4" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER7'", @@ -1400,10 +3725,55 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/ahbl_if.sv:: Signal is not used: 'hburst'", "signature": "86dee9662e8be179" }, + { + "count": 6, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DWORD'", + "signature": "876786e0f5c22d70" + }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_csr.v:: Filename 'serv_csr' does not match MODULE name: 'mpw_core_serv_serv_csr'", - "signature": "87460dffad298589" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pad_plic_int_cfg'[0]", + "signature": "879d93c54ae8a3dd" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'div_quotient_reg'[63:62]", + "signature": "87d5e1fc68df89b2" + }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'VA'", + "signature": "87d6e648d77e8786" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'icache_read_idx'[16,1:0]", + "signature": "886f62b38bfae977" + }, + { + "count": 3, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/jpeg_block_encoder.sv:: Instance pin connected by name with empty reference: 'start_ready_o'", + "signature": "8885d7fc8cb9602b" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT22'", + "signature": "88c9a6fa98dcd5a6" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'mmu_ifu_sh'", + "signature": "88d493bf28768d52" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'icache_tag_idx'[8]", + "signature": "89108ed44163d389" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bus_mtx_ict_pwdata'[31:10]", + "signature": "8939b080157fc3a1" }, { "count": 1, @@ -1415,11 +3785,26 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER7H'", "signature": "89b57cfd9ce81270" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF1_SNAN'", + "signature": "89e94ac15e1aba5b" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/core/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'unblock_out'", + "signature": "89fac762ef066a2d" + }, { "count": 1, "example": "DECLFILENAME:$BUILD/generated/soc_topology/rtl/soc_irq_sva.svh:: Filename 'soc_irq_sva' does not match MODULE name: 'soc_irq_topology_sva'", "signature": "8a26d3d8b6031430" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'refill_icache_addr'[11:0]", + "signature": "8a32e190a33d4a48" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZBA'", @@ -1427,13 +3812,68 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_top.v:: Signal is not used: 'i_ext_rd'", - "signature": "8b07c3661061041d" + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_64x32_c2.v:: Signal is not used: 'A_RW_ACCESS'", + "signature": "8a61c43ec5bcf281" }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/alu.v:: Filename 'alu' does not match MODULE name: 'mpw_core_kianv_rv32i_alu'", - "signature": "8b12b31c58ed721e" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'int_sec_infor_pack'[256]", + "signature": "8a6f6cfd64d2db10" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'VREG'", + "signature": "8a75b9cb695373de" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_0_xx_ex4_func'", + "signature": "8a97c56d11926f97" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'tc_vpn_masked'[26:6]", + "signature": "8aa0b5bc11358193" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'EXTRESUMETRI_NUM'", + "signature": "8aa369bfad3c00a8" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MATCH'", + "signature": "8aa9bc45bd5ca95f" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_arlock'", + "signature": "8aaa90774c54135a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_sha2_sram_engine.sv:: Bits of signal are not used: 'constant_resp_i'[52:42,9:0]", + "signature": "8aadb348a354d930" + }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF_WIDTH'", + "signature": "8abf9db017bb9a07" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 33 bits on the RHS, but RHS's REPLICATE generates 30 bits.", + "signature": "8ae0b40eda465fa4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_wbt_src1_reg'[5]", + "signature": "8aee71570ecf3780" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cntinten_wen'[1]", + "signature": "8b710b43e88d6e3d" }, { "count": 1, @@ -1445,6 +3885,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_STORE_ALIGN'", "signature": "8bff5f666595c600" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT15'", + "signature": "8c27e1a70887bd4a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pb_4zero'", + "signature": "8c788e456a4dd55d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT13'", @@ -1457,8 +3907,18 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_mem_if.v:: Filename 'serv_mem_if' does not match MODULE name: 'mpw_core_serv_serv_mem_if'", - "signature": "8ce54decea192223" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_1_xx_ex1_func'[19:14,11:2]", + "signature": "8ccbda18476ff1c8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pad_yy_scan_rst_b'", + "signature": "8cd393fc7c0f40dd" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DATA_WIDTH_D'", + "signature": "8ce372dc42befcac" }, { "count": 1, @@ -1467,8 +3927,53 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/femtorv32/user_core_design.sv:: Signal is not used: 'irq_i'", - "signature": "8d790409df1b9130" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ctrl_wbt_ctrl_fp_srcvm_info'", + "signature": "8d87386d1157d58c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_1_xx_ex1_func'[19:14,11:8]", + "signature": "8d9592c1717718d8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex3_half0_result'[10]", + "signature": "8dcd47276c4e5305" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT24'", + "signature": "8e00370ab7472250" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'awcache'[3:2,0]", + "signature": "8e037de8916c9105" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT24'", + "signature": "8e166cb2001726b5" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_half0_add_r'[13:0]", + "signature": "8e2ee8c3f52aceea" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ex2_l8_0_result'", + "signature": "8ec59943261a5af1" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_bhalf0_add_r'[10:0]", + "signature": "8ed661f2c7f5294d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_64x32_c2.v:: Signal is not used: 'B_RW_ACCESS'", + "signature": "8edb639ac604dfbd" }, { "count": 1, @@ -1482,8 +3987,8 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Parameter is not used: 'CPTR'", - "signature": "90b5295c79348584" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'wbt_ctrl_src2_info'[6:1]", + "signature": "9111f51c49ec3631" }, { "count": 1, @@ -1492,44 +3997,89 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_compdec.v:: Filename 'serv_compdec' does not match MODULE name: 'mpw_core_serv_serv_compdec'", - "signature": "919d5b48b7478d65" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MTIMECMPH1'", + "signature": "91491bf14cea49f3" }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'fence_i_vld'", - "signature": "91ab8a02fe74bc67" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'WEN'[86:44,42:0]", + "signature": "919845240f1fe8ce" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'idu_vidu_ex1_inst_data'[179:156,154:0]", + "signature": "91cc84f58aa2fd0b" + }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS's VARREF 's_slot_comb' generates 14 bits.", + "signature": "91d146d1e480f928" }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_20_io_pad'", "signature": "91d173ea76bfbe4d" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/extend.v:: Filename 'extend' does not match MODULE name: 'mpw_core_kianv_rv32i_extend'", - "signature": "91fb20ae71cf950e" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER8H'", "signature": "921769e0c596b243" }, - { - "count": 14, - "example": "WIDTHTRUNC:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Logical operator COND expects 1 bit on the Conditional Test, but Conditional Test's VARREF 'FLUSH' generates 2 bits.", - "signature": "921eafa817a9bd24" - }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_alu.v:: Filename 'serv_alu' does not match MODULE name: 'mpw_core_serv_serv_alu'", - "signature": "922d32fb4cc8c14b" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT25'", "signature": "92a5f90729168667" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MSIP1'", + "signature": "92a61405a4e1ecbf" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'WB_CMPLT'", + "signature": "92ce7e5aa4657e22" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_3_xx_ex1_eu_sel'[9:1]", + "signature": "92dd44e307d0bc63" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'iui_inst_sel_dp'", + "signature": "92f66a8177d6f224" + }, + { + "count": 5, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'WORD'", + "signature": "9331ede983e68a6e" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_awsize'", + "signature": "9355f27fb8353312" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_gpr_src1_reg'[5]", + "signature": "936c6485da0fb243" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/rtl/ip/multimedia/npu_pkg.sv:: Parameter is not used: 'MaxTilePositions'", + "signature": "93780f3801ae90b1" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_right_max'[12]", + "signature": "9463534421af6389" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT16'", + "signature": "9465df5ce36fbc74" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/arith/hazard3_alu.v:: Bits of signal are not used: 'funct7_32b'[6:4,0]", @@ -1557,19 +4107,44 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'tdest'", - "signature": "94ce4081818687e6" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex2_stall'", + "signature": "94e4393b8c49f01e" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_XOR'", "signature": "9502b7b09131a66e" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'hreg_arbx_int_en'[0]", + "signature": "952ccf6252bb8c79" + }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator SUB expects 13 bits on the LHS, but LHS's REPLICATE generates 5 bits.", + "signature": "954a6d53af013b16" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_16_io_pad'", "signature": "95598327a2a371fe" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'STIMECMP3'", + "signature": "9571226f7bbf3df6" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'iui_regs_wdata'[63:32]", + "signature": "95a04c6a6094ac92" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'EXTHALTTRI_NUM'", + "signature": "95a6ffb929615af7" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPCFG3'", @@ -1580,21 +4155,61 @@ "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'xpi_nss2_o_pad'", "signature": "95f6e45df454ca6c" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT19'", + "signature": "9617c49030e3870b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bresp'[0]", + "signature": "961f2d6cd305c0e0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dcache_tag_sel'[3:2]", + "signature": "963afe5a2cedbd6b" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_INSTR_MISALIGN'", "signature": "96441e3b1ba09ba6" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apu_kws_sram_client.sv:: Signal is not driven, nor used: 'mem'", + "signature": "96675d7d99689140" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZCMP'", "signature": "969ffdabeba218cf" }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'srcv1_type'[42,35:28,21:0]", + "signature": "96cde530f1e09693" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'iui_special_rs2'[63:16]", + "signature": "96d3117e65b2b275" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF3_ID'", + "signature": "96dde16fedb11775" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/rv_opcodes.vh:: Parameter is not used: 'RV_RD_LSB'", "signature": "96de634c26e5f4e9" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_awlen'", + "signature": "96f924510d79ce15" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUSRCB_RS2'", @@ -1607,8 +4222,28 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/serv/serv/serv_synth_wrapper.v:: Instance pin connected by name with empty reference: 'o_ext_rs2'", - "signature": "97c4c18434036ee7" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ff1_l_pred_t0_d_onehot'", + "signature": "97a85549a630b91e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex3_no_d_norm_e'[10:8]", + "signature": "97ad85e997f81ce6" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_src1_sel'[52]", + "signature": "97ae60a253dcd12a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_norm_src1'[63:32]", + "signature": "9849fbe74a7fbcfa" + }, + { + "count": 3, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'FUNC_WIDTH'", + "signature": "985b96d5859e2026" }, { "count": 1, @@ -1617,24 +4252,84 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Parameter is not used: 'ID'", - "signature": "991c233582d6c42e" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex3_sel'", + "signature": "98e1f92fc7b72355" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rtu_cp0_vs_dirty_updt_dp'", + "signature": "991294054c8c19a9" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'wbt_ctrl_fp_srcv2_info'[2:1]", + "signature": "993abd8d2a930712" }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/tech/tc_io.sv:: Filename 'tc_io' does not match MODULE name: 'tc_io_xtl_pad'", "signature": "9951f9ae3feb0409" }, + { + "count": 4, + "example": "PINMISSING:$BUILD/generated/pin_map/rtl/retrosoc_asic_pad_bindings.svh:: Instance has missing pin: 'iovdd'", + "signature": "996e9430a2211167" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'l16_3_shift_out_val'", + "signature": "997ee5afa88bd8e7" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dcache_acc_virt_idx'[1]", + "signature": "998382625cef9ad4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Signal is not used: 's_acc_drain_last'", + "signature": "9988dfc8ea8fb50e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'idu_iu_ex1_inst_vld'", + "signature": "999236626a9bcee0" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_LBU'", "signature": "999e827601c9bbf9" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_arlen'", + "signature": "99da49c60d0376e8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'iui_special_vsetvl_dp'", + "signature": "9a037fee9895e474" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pop1_halt_info'", + "signature": "9a29430dbce88bbd" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'W_DATA'", "signature": "9a8da429dccc9d9e" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'BHALF_WIDTH'", + "signature": "9a9fb324e68ff84a" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_awlock'", + "signature": "9afcf03bc6d171e6" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER24'", @@ -1645,6 +4340,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_NONE'", "signature": "9b366cc3d457b803" }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Operator VAR 'P_ERROR_PATTERN' expects 32 bits on the Initial value, but Initial value's CONST '40'h0' generates 40 bits.", + "signature": "9b3dfa4397ebfbf4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'div_suber_res1_11'[65:64]", + "signature": "9b5a0a1bdb04108b" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT23'", @@ -1652,13 +4357,33 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_state.v:: Filename 'serv_state' does not match MODULE name: 'mpw_core_serv_serv_state'", - "signature": "9ba602ead7642f62" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_special_sel_1'[6:0]", + "signature": "9bce9e488c2d4fd6" }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_top.v:: Filename 'serv_top' does not match MODULE name: 'mpw_core_serv_serv_top'", - "signature": "9bc9f670bb4d815b" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'araddr'[39:14,5:0]", + "signature": "9c2f6e39a091ea52" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'l16_1_shift_out_val'", + "signature": "9c58a7c35c79d260" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT12'", + "signature": "9cd9f101db886a63" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_double_add_inc2_r'[2:0]", + "signature": "9cecbe269cce1ec6" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cp0_mmu_tlb_va'[26:8]", + "signature": "9cef5e9ee9745ae7" }, { "count": 1, @@ -1667,19 +4392,44 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Signal is not used: 'KDEBUG'", - "signature": "9d47d91d05df4c14" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MATCH_TRIGGER'", + "signature": "9d565eb67563a1d8" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_MULDIV'", "signature": "9d7dbfa39624c866" }, + { + "count": 7, + "example": "PINMISSING:$ROOT/rtl/tech/tc_io.sv:: Instance has missing pin: 'vss'", + "signature": "9d870f12f87fa1b7" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator GTE expects 32 bits on the LHS, but LHS's SEL generates 5 bits.", + "signature": "9dc92458ef9acda8" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT15'", + "signature": "9df6417b07f12aeb" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'cpu_debug_port'", + "signature": "9e05f7eb8a161781" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'INSTRETH'", "signature": "9e0e1f130a9a1c41" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex1_srcv2'", + "signature": "9ea0244a4701362b" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_BEXT'", @@ -1690,6 +4440,46 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_ALUSRC'", "signature": "9f38b53fad1d8eaf" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Bits of signal are not used: 's_add_byte_off'[12]", + "signature": "9f3a2014b7c95af8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'plic_ctrl_reg_rd_en'", + "signature": "9f3efa95208be426" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT30'", + "signature": "9f51af5a0340814b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vlsu_rbus_vpr_wb_data'", + "signature": "9f6a548a7c1b1ccf" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'BHALF_EXPN'", + "signature": "9f798c0b3bc17709" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'tselect_wr_en'[9:8]", + "signature": "9f84bf4e80978faf" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v:: Signal is not used: 'A_BIST_W_ACCESS'", + "signature": "9fd921937621b747" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'right_8_0_shift_num'[15]", + "signature": "9ff6b3a539b8111c" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'M_OP_DIV'", @@ -1697,8 +4487,18 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_rf_ram.v:: Filename 'serv_rf_ram' does not match MODULE name: 'mpw_core_serv_serv_rf_ram'", - "signature": "a0268fa525ada4e8" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ptw_flg'[8:6]", + "signature": "a006bc04b9806640" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT12'", + "signature": "a01f0d54cf31c99f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex3_func'", + "signature": "a03f3000db08968f" }, { "count": 1, @@ -1712,14 +4512,59 @@ }, { "count": 1, - "example": "LATCH:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Latch inferred for signal 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_axi4_sdram.u_sdram_axi4.unnamedblk2.wr_window' (not all control paths of combinational always assign a value)", - "signature": "a0a13d42578ce432" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'double_total_qt_rt'[57]", + "signature": "a0a317e681313740" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF1_ZERO'", + "signature": "a0b8a87183d8b1e0" + }, + { + "count": 1, + "example": "DECLFILENAME:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_udp.v:: Filename 'sg13g2_udp' does not match PRIMITIVE name: 'ihp_latch'", + "signature": "a0c35dbdc76e39db" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex2_sel'", + "signature": "a178a946dcde26e4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_0_xx_ex4_eu_sel'[9:1]", + "signature": "a19126b15dfe4425" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MSCRATCH'", "signature": "a1da501e9a774202" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v:: Signal is not driven, nor used: 'notifier'", + "signature": "a1ed690c8b9e7b70" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'STB_WFC'", + "signature": "a22b6bc610693483" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bju_ag_cur_pc'[0]", + "signature": "a2992ffd0b58c045" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'e_diff_contrary'[11]", + "signature": "a347dd0ba6c4f6ef" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'hg_sel_exttri'", + "signature": "a36e8d953e89126b" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_19_io_pad'", @@ -1730,16 +4575,51 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'BCOND_NEVER'", "signature": "a3a2cef6f858e478" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex4_sel'", + "signature": "a3e311bfa69d69e1" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apu_kws_coeff_loader.sv:: Bits of signal are not used: 's_stat_q'[31:12,7:0]", + "signature": "a42b3b1a605cf198" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SLAVE_NUM'", + "signature": "a47fb4ac4312ffd1" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER18H'", "signature": "a4a092906e99db1e" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MTIMECMP1'", + "signature": "a4a0c8c82ed01053" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_11_io_pad'", "signature": "a4fe4861aca999f6" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_encoder.sv:: Signal is not used: 's_quant_start'", + "signature": "a53f80e0303404df" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'SE'", + "signature": "a54c066cd6d106b8" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MSIP3'", + "signature": "a56a5b56209a825f" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_core.v:: Signal is not used: 'xm_rs1'", @@ -1750,6 +4630,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'RESET_VECTOR'", "signature": "a589fc7ea4415f28" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_decode_core.sv:: Signal is not used: 's_table_portal_data'", + "signature": "a5f59a1684df60a7" + }, + { + "count": 5, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'BYTE'", + "signature": "a60503bc16719307" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPCFG1'", @@ -1760,6 +4650,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER30H'", "signature": "a61c1c9e7a2c63cb" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'result_1_0'[83:81]", + "signature": "a6362f653253c4e1" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_MAX'", @@ -1775,11 +4670,36 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv:: Filename 'cdc_sync' does not match MODULE name: 'cdc_sync_det'", "signature": "a6f0024b7dbf24d8" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT20'", + "signature": "a726dd464ac13c95" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER21H'", "signature": "a76ee7e5b7a83137" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Bits of signal are not used: 's_seg_addr_full'[63:32]", + "signature": "a78852a255ef4e76" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'result_1_1'[83:81]", + "signature": "a78f2e3c256f2bd1" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p0_2_cout'[81]", + "signature": "a7912a597e691657" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'INV'", + "signature": "a7cef3f37d2daaa9" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TDATA3'", @@ -1787,14 +4707,34 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/datapath_unit.v:: Filename 'datapath_unit' does not match MODULE name: 'mpw_core_kianv_rv32i_datapath_unit'", - "signature": "a8b290ac02eeb458" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cp0_lsu_icc_addr'[63:32,29:14,5:0]", + "signature": "a827c9a3d0129b7f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'rdl_dc_acc_tag'[11:0]", + "signature": "a8ecf692958c3b83" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_srcv0'[63:52]", + "signature": "a90658a868f82c71" }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/ip/memory/axi4_sdram.sv:: Filename 'axi4_sdram' does not match IFACE name: 'sdram_if'", "signature": "a90916740809d34f" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex2_rm'", + "signature": "a9120c5f354a8ae1" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vlsu_vidu_split_pause'", + "signature": "a959c8b71dd33901" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'M_OP_MULH'", @@ -1802,13 +4742,38 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Filename 'user_core_design' does not match MODULE name: 'mpw_c3'", - "signature": "a9bdcbc773cd52d9" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_adder_b_double'[8:0]", + "signature": "a9f76d07da9557db" + }, + { + "count": 3, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'idu_iu_ex1_dst_preg'[5]", + "signature": "a9f8879e9c984412" + }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator SUB expects 10 bits on the RHS, but RHS's REPLICATE generates 7 bits.", + "signature": "aa471b7c69a34a45" }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/mpw/core/serv/user_core_design.sv:: Parameter is not used: 'ID'", - "signature": "aac36aa7f03bedcc" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'hmpep_sub_retire_result'[38:0]", + "signature": "aa5a7dfce4062081" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_CUSBUF5'", + "signature": "aa60790a157e2994" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex3_rm'", + "signature": "aa82a21f0d5ef951" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex4_func'", + "signature": "aa8f8f054d51eea8" }, { "count": 1, @@ -1825,21 +4790,46 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'DMDATA0'", "signature": "ab9a7ea21fe47060" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pad_biu_bresp'", + "signature": "aba3ba568de2773c" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Bits of function variable are not used: 'rem_bytes'[1:0]", "signature": "abcf2df31283e92a" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT21'", + "signature": "abdd73a29b7ba7be" + }, { "count": 1, "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/hazard3/hdl/hazard3_cpu_2port.v:: Instance pin connected by name with empty reference: 'bus_aph_panic_i'", "signature": "ac01cb1c5156a90f" }, + { + "count": 3, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF_FRAC'", + "signature": "ac693aa2daef768b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'bhalf3_denorm_shift_num'", + "signature": "ac6c26ccfbd1127a" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_SRA'", "signature": "ad17543edfb08816" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'groups'", + "signature": "ad1808b682151105" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER22H'", @@ -1850,6 +4840,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_SLL'", "signature": "ad4f8be15c20afb7" }, + { + "count": 3, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DOUBLE_EXPN'", + "signature": "ad573cf95fc7e9a5" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF1_NORM'", + "signature": "adb24c485f3fba2c" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_EXCEPT'", @@ -1860,6 +4860,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'CYCLEH'", "signature": "ae37dfea9fdb082d" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_CUSBUF3'", + "signature": "ae39bd13c6654d24" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_1_xx_ex4_sel'", + "signature": "aeab684c35948bc7" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_BCLR'", @@ -1870,6 +4880,11 @@ "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_1_io_pad'", "signature": "af455b0b2cff2ee2" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT17'", + "signature": "af56dd4958606e89" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_HARDWIRED'", @@ -1882,14 +4897,79 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_bufreg.v:: Signal is not used: 'i_cnt_done'", - "signature": "b091d4717edc7d92" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_src1_half'[31:16]", + "signature": "afc0d7b3d3199568" + }, + { + "count": 3, + "example": "WIDTHTRUNC:$BUILD/generated/openc906/openc906_combined.v:: Bit extraction of var[1:0] requires 1 bit index, not 5 bits.", + "signature": "affdbb62dcc395f9" + }, + { + "count": 3, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DOUBLE_FRAC'", + "signature": "b042b9b81bbea5a4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ag_dc_sh'", + "signature": "b09ffa01f9682bb8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'half3_denorm_shift_num'", + "signature": "b0be058fee15690f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apu_microcode_pkg.sv:: Bits of function variable are not used: 'pc_i'[11]", + "signature": "b0e389217b20ac28" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT21'", + "signature": "b124f4098f4f5929" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_table_register_bank.sv:: Bits of signal are not used: 'entry_data_i'[31:21]", + "signature": "b12c25ec458171dd" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_encoder.sv:: Signal is not used: 's_transform_start'", + "signature": "b1661a4ec13b5d73" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DATA_WIDTH_S'", + "signature": "b17883ac4bcd16fd" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_dma.sv:: Signal is not used: 's_read_master_done'", + "signature": "b179d8c33ec7e50d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'div_suber_res1_10'[65:64]", + "signature": "b1c377f7ef54793e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ag_dc_sec'", + "signature": "b1f767d61f2205dd" }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_core.v:: Signal is not used: 'x_pmp_cfg_wen'", "signature": "b2033a254b6a4b40" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vlsu_rbus_vpr_wb_index'", + "signature": "b226f1702fc3a433" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MSTATUS'", @@ -1900,6 +4980,11 @@ "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Instance pin connected by name with empty reference: 'cnt_o'", "signature": "b2c208417d5eeeaf" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p1_0_cout'[81]", + "signature": "b3097d43bc7f4c3f" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT10'", @@ -1907,13 +4992,18 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/serv/serv/serv_synth_wrapper.v:: Instance pin connected by name with empty reference: 'o_ext_funct3'", - "signature": "b33436b1ff46abe0" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ag_addr_align'[3]", + "signature": "b3c4b14eaac80458" }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/user_core_design.sv:: Filename 'user_core_design' does not match MODULE name: 'mpw_c1'", - "signature": "b338d7c52717ef30" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_rsa_sram_core.sv:: Signal is not used: 's_mont_busy'", + "signature": "b3fca045398f7f71" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex3_func'", + "signature": "b470c3be134bf8b1" }, { "count": 1, @@ -1921,20 +5011,115 @@ "signature": "b484191be733e6cc" }, { - "count": 1, - "example": "LATCH:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Latch inferred for signal 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_axi4_sdram.u_sdram_axi4.unnamedblk1.rd_window' (not all control paths of combinational always assign a value)", - "signature": "b4c791ac1b3ded32" + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pad_yy_scan_mode'", + "signature": "b50e0400c0131550" }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'hmaster'", - "signature": "b74039e6d6f9ab8b" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SSIP1'", + "signature": "b523a89c19a232fd" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex4_eu_sel'", + "signature": "b54a3f0623a8ec9a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pslverr'", + "signature": "b5529a4c8bd6b69e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_requantizer.sv:: Bits of signal are not used: 's_rdp_exponent'[7:5]", + "signature": "b55cddd44d0605a3" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Bits of signal are not used: 's_irq_coalesce'[31:16]", + "signature": "b57d8d8e1cc7c66a" + }, + { + "count": 1, + "example": "STMTDLY:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v:: Ignoring delay on this statement due to --no-timing", + "signature": "b5d5e3b4295a5494" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pop1_pred_taken'", + "signature": "b5ddfd78d4f8de2a" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_CUSBUF1'", + "signature": "b5ead736e1f810c6" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpaddr8_value'[0]", + "signature": "b613ed0eaada917c" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HART_CT_DIV'", + "signature": "b6622ffaf61a7671" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_mcu_builder.sv:: Bits of function variable are not used: 's_pixel2'[7:0]", + "signature": "b6991b6b9f88aa93" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT15'", + "signature": "b6cbb16be82b979d" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT25'", + "signature": "b70ff9fbc47d9fb6" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_encode_core.sv:: Signal is not used: 's_packer_last'", + "signature": "b727e22373a3dde0" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_bready'", + "signature": "b73084ca38426e82" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpaddr14_value'[0]", + "signature": "b73b59a465c73e52" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cp0_lsu_dcache_read_idx'[16:14,3:0]", + "signature": "b74d5d9dcc24becf" + }, + { + "count": 3, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator GTE expects 34 bits on the LHS, but LHS's REPLICATE generates 33 bits.", + "signature": "b75f2f5be3389868" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT19'", + "signature": "b76530fd92c7fce0" }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'xpi_nss1_o_pad'", "signature": "b77f4ffe8d801781" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_quantizer.sv:: Bits of function variable are not used: 's_product'[31:24]", + "signature": "b7a1d395468d8d69" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_INSTR_FAULT'", @@ -1942,19 +5127,39 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/kianv_rv32i/user_core_design.sv:: Bits of signal are not used: 's_rib_addr'[1:0]", - "signature": "b84731bc0aca0116" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex3_eu_sel'", + "signature": "b84ba4edfbf4777f" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_bufreg.v:: Signal is not used: 'i_shift_op'", - "signature": "b84ce77b6a0beea3" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'half0_total_qt_rt'[15]", + "signature": "b860f6ea614ee7c4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Bits of signal are not used: 's_c906_araddr'[39:32]", + "signature": "b88794ca3d260561" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dcache_data_way'[3,1]", + "signature": "b887dc75dae2e3f2" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpaddr13_value'[0]", + "signature": "b888f1ad7b051456" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER11H'", "signature": "b8b28bfbcced7941" }, + { + "count": 1, + "example": "SPECIFYIGN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_64x32_c2.v:: Ignoring unsupported: specify block construct", + "signature": "b8b57914df1fdde6" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_LHU'", @@ -1967,14 +5172,39 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'DAER'", - "signature": "b99832da36ca9be2" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'alu_shift_src1'[63:12]", + "signature": "b91fa23a6cf36908" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'l64_shift_out_val'[11:0]", + "signature": "b96ca3a079f41b2c" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'core0_pad_retire_pc'", + "signature": "ba1975512f6c4bf4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'hpcp_retire_pc'[0]", + "signature": "ba3892c104791eda" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rtu_cp0_vl'", + "signature": "bb2e3ec49a9f82b4" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'M_OP_DIVU'", "signature": "bb92bfd7f1c31784" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'WB_EX2'", + "signature": "bbbe272bd3935d4e" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v:: Signal is not used: 'A_RW_ACCESS'", @@ -1985,6 +5215,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT22'", "signature": "bc187dd87cebc30a" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_special_sel_final_t'[6,0]", + "signature": "bc4193454636b3be" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER10'", @@ -1995,6 +5230,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_MAXU'", "signature": "bcc80c4cfe4e47c7" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Signal is not used: 's_vec_drain_last'", + "signature": "bce9a46f248b10c4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex3_stall'", + "signature": "bcf18c31310ff6b0" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER16H'", @@ -2007,8 +5252,13 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'IERR'", - "signature": "bd725aee67be20ac" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'kid_arb_int_prio'[4:0]", + "signature": "bd77c07684d242ec" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/ga2d_dma.sv:: Instance pin connected by name with empty reference: 'write_data_o'", + "signature": "bdd11c6bd1d55327" }, { "count": 1, @@ -2022,13 +5272,13 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_LT'", - "signature": "bdf951d9ebe5829e" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_sub_r_shift'[27,1:0]", + "signature": "bdf3874d6c87006a" }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/design_elements.v:: Filename 'design_elements' does not match MODULE name: 'mpw_core_kianv_rv32i_mux2'", - "signature": "be2743ec0029efad" + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_LT'", + "signature": "bdf951d9ebe5829e" }, { "count": 1, @@ -2037,34 +5287,144 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/kianv_harris_mc_edition.v:: Filename 'kianv_harris_mc_edition' does not match MODULE name: 'mpw_core_kianv_rv32i_kianv_harris_mc_edition'", - "signature": "be840f05b8706e9a" + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dtm_pad_tms_oe'", + "signature": "be823b51e91e8432" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SINGLE0_ID'", + "signature": "bf1ff3e078a71362" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'NOP'", + "signature": "bf31767e3a303d59" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_MATCH_NAPOT'", "signature": "bf91d18fa461423f" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/peripheral/dma_core.sv:: Signal is not used: 's_tcd_head_q'", + "signature": "bfe5f6ce7026c603" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/core/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'fence_d_vld'", + "signature": "c00d9447f41e7e1c" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF2_CNAN'", + "signature": "c02b261e8cd9646d" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT11'", + "signature": "c0546b72a1d27c7d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vtb_entry_st_fwd_fp_bus'[3:2]", + "signature": "c0701575e9d34b85" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dc_hit_pfb_pc'[0]", + "signature": "c0e6690b6a6c5641" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bju_src2_raw'[63:13,0]", + "signature": "c1109f2f2d62aeaf" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_SHXADD'", "signature": "c18ba22b0ecb8975" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_awburst'", + "signature": "c19227586683195b" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT11'", + "signature": "c20714d3edb69edf" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'FPU_WIDTH'", + "signature": "c24e965cc42d5a6e" + }, + { + "count": 4, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pfb_xx_pa'[39:12,5:0]", + "signature": "c25ead4f5dfa3974" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's REPLICATE generates 6 bits.", + "signature": "c283a1a27397017c" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA2'", + "signature": "c29b15c1999e3639" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_half_special'[63:16]", + "signature": "c3537d4f3c140e48" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_0_xx_ex3_rm'", + "signature": "c35cfdad02fbdde8" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MINSTRET'", "signature": "c368010fa9b24394" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'iui_special_rs1_x0'", + "signature": "c371ab0b7e34b3ea" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Bits of function variable are not used: 'relative'[23:0]", "signature": "c38337519880cc10" }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/rtl/tech/tc_io.sv:: Parameter is not used: 'ReadWhileDriving'", + "signature": "c3910bc7f6ca8452" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_fp_inst_data'[149:134,128:113,107:100,94:87,74:69]", + "signature": "c3abc6ac2e5fb4a7" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MTVEC'", "signature": "c3c6921e6ec5e293" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pmpcfg2_value'[62:59,54:51,46:43,38:35,30:27,22:19,14:11,6:3]", + "signature": "c3eeb7b3729a1294" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_e_onehot'[10:0]", + "signature": "c40f14166ce13295" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/common/rtl/utils/register.sv:: Filename 'register' does not match MODULE name: 'dff'", @@ -2086,25 +5446,85 @@ "signature": "c4ee8325f56a145d" }, { - "count": 68, + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT27'", + "signature": "c52c1784f96965d8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_aes_sram_core.sv:: Bits of signal are not used: 'work_resp_i'[52:42,9:0]", + "signature": "c5349eca877ebead" + }, + { + "count": 74, "example": "SPECIFYIGN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v:: Ignoring unsupported: specify block construct", "signature": "c54331448f63ac73" }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cp0_dtu_satp'[63:60,43:0]", + "signature": "c570446551c8df7e" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_5_io_pad'", "signature": "c6838d7b98284986" }, + { + "count": 2, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/security/crypto_aes_sram_engine.sv:: Instance pin connected by name with empty reference: 'count_o'", + "signature": "c6a189542faedb7c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'awaddr'[39:14,3:0]", + "signature": "c6bad75b39d885eb" + }, + { + "count": 1, + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/ga2d_pixel.sv:: Declaration of signal hides declaration in upper scope: 's_green'", + "signature": "c6c2e1e2e508980c" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v:: Signal is not used: 'A_DLY'", "signature": "c6eaac59b0d903b1" }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 33 bits on the RHS, but RHS's REPLICATE generates 21 bits.", + "signature": "c6fa8e0f4f367c48" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_wbt_src2_reg'[5]", + "signature": "c72a6fa5eac535d3" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT21'", + "signature": "c72c0b095bcbc7af" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_SW'", "signature": "c7c55c60199f03dc" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_job_decoder.sv:: Signal is not used: 'block_new_i'", + "signature": "c7c5a73298cacc18" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/security/crypto_aes_sram_engine.sv:: Instance pin connected by name with empty reference: 'error_bank_o'", + "signature": "c8076bd72805ff90" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'icache_refill_prot'[4,0]", + "signature": "c813be5c047676a2" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MENVCFGH'", @@ -2115,10 +5535,40 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER12'", "signature": "c81f1fa284769bd5" }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_1_xx_ex1_eu_sel'[9:8,5:1]", + "signature": "c83be41f4c32a60f" + }, { "count": 1, - "example": "EOFNEWLINE:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v:: Missing newline at end of file (POSIX 3.206).", - "signature": "c8d29b5d34c1cef1" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_CUSBUF4'", + "signature": "c8605be327e226b8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rem_add1_op1_h'", + "signature": "c86d973d2a146f9b" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'PADDR'", + "signature": "c870722fcf77f49c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'WEN'[96,94:48,46:0]", + "signature": "c88ca90242161764" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_3'[65]", + "signature": "c8cf518e43f12fb7" + }, + { + "count": 3, + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/jpeg_quantizer.sv:: Declaration of signal hides declaration in upper scope: 'quant_i'", + "signature": "c8ecf8e11e5b351b" }, { "count": 1, @@ -2130,6 +5580,16 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/tech/tc_io.sv:: Signal is not used: 'dum'", "signature": "c9712a26c3ee209d" }, + { + "count": 3, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS's ADD generates 17 bits.", + "signature": "c98fe2a7d6e66623" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_special_sign_final'[1:0]", + "signature": "c9d0adedcbfe7497" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_EBREAK'", @@ -2137,8 +5597,38 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Signal is not used: 'IHLT'", - "signature": "ca81f9845d564cad" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'paddr'[31:16]", + "signature": "c9d7e71e2c28f865" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_op1_half0'[14:0]", + "signature": "c9f2af09a5ba1c7d" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'VLD_VL'", + "signature": "c9fe189420db788a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vtb_entry_wdata_vld'[3:2]", + "signature": "ca3e9154e3af40cb" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'idu_iu_ex1_split'", + "signature": "ca51798f2d102bfb" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'idu_iu_ex1_src1_reg'[5]", + "signature": "caaf74a60737baeb" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT13'", + "signature": "caba554e7a395098" }, { "count": 1, @@ -2155,6 +5645,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT19'", "signature": "cb50e4344c949ae7" }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS's COND generates 16 bits.", + "signature": "cbc9e987be4f0593" + }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/ga2d_pixel.sv:: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's DIV generates 17 bits.", + "signature": "cc4355cd26116d4b" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER18'", @@ -2162,19 +5662,39 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/femtorv32/user_core_design.sv:: Filename 'user_core_design' does not match MODULE name: 'mpw_c2'", - "signature": "cc6f6a46c3f5f750" + "example": "UNUSEDPARAM:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Parameter is not used: 'P_ERROR_ADDR'", + "signature": "ccaaa050deb5fd6e" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZIFENCEI'", "signature": "ccaef8db9c88cc45" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_arsize'", + "signature": "cd1e97431e0d9725" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'sba_wr_addr_pre'[63:40]", + "signature": "cd371714d12fe3cd" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'IMP_EBREAK'", + "signature": "cd4c378e3df73e02" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TDATA2'", "signature": "cd5cf66d20bbf174" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ag_pipe_lmul'", + "signature": "cd7f51256c2a449e" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MSTATUSH'", @@ -2182,13 +5702,63 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Bits of signal are not used: 's_cpu_addr'[1:0]", - "signature": "cd8ce722cd01946e" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SW'", + "signature": "cdbf99ec24b7f026" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/peripheral/pll_ctrl_if.sv:: Signal is not used: 'req_sel_o'", - "signature": "cd98cd5f8ba452a7" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA7'", + "signature": "cdd05960f1e2dd4a" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'tdt_dm_pad_arprot'", + "signature": "cde422929b129487" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ff1_8_bit'", + "signature": "ce54aa5fae2e407a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Bits of signal are not used: 's_ring_control'[31:2]", + "signature": "ce803512e5a0c220" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'l16_0_shift_out_val'[5:0]", + "signature": "cec04b4bb2da1c29" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Bits of signal are not used: 's_output_format'[31:3]", + "signature": "cf1b0e2a22af237a" + }, + { + "count": 5, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/jpeg_transform.sv:: Operator SUB expects 48 bits on the LHS, but LHS's ARRAYSEL generates 25 bits.", + "signature": "cf277a8abf7f9c38" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT19'", + "signature": "cf2870fe96a3d5fa" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'iui_regs_imm'[11:5]", + "signature": "cf4d666d8708b32a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apu_kws_sram_client.sv:: Bits of function variable are not used: 'address_i'[14:9,5,1:0]", + "signature": "cf6a3b5f02cd59fe" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/soc_data_plane.sv:: Bits of signal are not used: 's_target_abort_mem'[0]", + "signature": "cf8f7e0965bbd48b" }, { "count": 1, @@ -2202,29 +5772,59 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_aligner.v:: Filename 'serv_aligner' does not match MODULE name: 'mpw_core_serv_serv_aligner'", - "signature": "d080db27a7911a99" + "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Bits of signal are not used: 's_c906_awaddr'[39:32]", + "signature": "d0997104ae05986d" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'tstrb'", - "signature": "d107b15c3ab26a79" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ag_pipe_va_add_access_size'[3]", + "signature": "d0b5d779039ee823" }, { "count": 1, - "example": "PROCASSINIT:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Procedural assignment to declaration with initial value: 'FLUSH'", - "signature": "d14379be6774bed8" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'TIMING'", + "signature": "d11d4d4182d2c112" }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'fence_d_vld'", - "signature": "d253cb3cc4d59917" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'create0_en'[0]", + "signature": "d148b0668f17e888" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT18'", + "signature": "d1af40cc8d0b1f8e" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'rresp'[0]", + "signature": "d1f917c1cb7e86a0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'tmp_sel2'[0]", + "signature": "d2bd651cc8258670" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_MIN'", "signature": "d2c20fae872b2b1e" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv:: Signal is not used: 'buser'", + "signature": "d2e40b3430f973f6" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'WEN'[56:29,27:0]", + "signature": "d2f309c24778c526" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_CUSBUF0'", + "signature": "d3e2d8560b86dc85" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT29'", @@ -2235,11 +5835,26 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT31'", "signature": "d4d4e4656eaa6158" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Signal is not used: 'time_b'", + "signature": "d4e04430e6cf5154" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv:: Signal is not used: 'aresetn'", "signature": "d4f29a2333f1740c" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex5_vreg'[1:0]", + "signature": "d52eed28807da3f5" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pf_icache_addr'[11:0]", + "signature": "d531b1621ccff697" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_frontend.v:: Signal is not used: 'pmp_i_kill'", @@ -2247,8 +5862,8 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/serv/user_core_design.sv:: Instance pin connected by name with empty reference: 'o_ext_funct3'", - "signature": "d58234033d48f20a" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT16'", + "signature": "d54d07010a77c2bd" }, { "count": 1, @@ -2257,13 +5872,63 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/kianv_rv32i/user_core_design.sv:: Signal is not used: 'irq_i'", - "signature": "d693384e3d8f6143" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_rsa_sram_core.sv:: Signal is not used: 's_scrub_busy'", + "signature": "d5efbb1e6d720a94" }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/main_fsm.v:: Filename 'main_fsm' does not match MODULE name: 'mpw_core_kianv_rv32i_main_fsm'", - "signature": "d7ce843ff26f9abe" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT12'", + "signature": "d5f94dcebd72a995" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT15'", + "signature": "d6548261b1b8b36d" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT28'", + "signature": "d664e6d37afa779e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Signal is not used: 's_decode_busy'", + "signature": "d683d2933c860a9c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rtu_cp0_vs_dirty_updt'", + "signature": "d6a93599c4b67a89" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/jpeg_transform.sv:: Operator ADD expects 48 bits on the LHS, but LHS's ARRAYSEL generates 25 bits.", + "signature": "d6bb6ceffa0a3d8c" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT29'", + "signature": "d738ff3258a4d33a" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'core0_pad_halted'", + "signature": "d744280b48b8d70d" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/common/rtl/cdc/cdc_advanced.sv:: Instance pin connected by name with empty reference: 'source_busy_o'", + "signature": "d7ad03232a4f58be" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'addr_alian'[1:0]", + "signature": "d7cceb21d7c4ca6b" + }, + { + "count": 1, + "example": "SPECIFYIGN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v:: Ignoring unsupported: specify block construct", + "signature": "d7fe04597178ec7b" }, { "count": 1, @@ -2272,8 +5937,48 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'hexcl'", - "signature": "d92b91d2e2895f82" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DOUBLE_ID'", + "signature": "d81e41407523b055" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vlsu_index_up_mask'", + "signature": "d8a38377f9a17c0e" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 17 bits on the LHS, but LHS's VARREF 's_pack_base_q' generates 13 bits.", + "signature": "d8dcfd4ae673f6d5" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'PTE_LEVEL'", + "signature": "d8df3e0229c5a586" + }, + { + "count": 1, + "example": "MULTIDRIVEN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Signal has multiple driving blocks with different clocking: 'u_mem.i_SRAM_2P_behavioral.mem_arr'", + "signature": "d8ee935b4b86cf95" + }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ASSIGNW expects 34 bits on the Assign RHS, but Assign RHS's ADD generates 58 bits.", + "signature": "d983245aaf99d323" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'tmp_prio_split_pslverr_pre'[9:3,0]", + "signature": "d983932596a94479" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'data_zero32'[31:24]", + "signature": "d9e29d61e01f5c73" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/dvp_core.sv:: Bits of signal are not used: 's_err_flags_q'[3:1]", + "signature": "da1045467462ab5c" }, { "count": 1, @@ -2287,14 +5992,99 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_bufreg.v:: Signal is not used: 'i_right_shift_op'", - "signature": "da5c9ee48fb062c2" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'sysio_biu_apb_base'[26:0]", + "signature": "da5e4b79d253f911" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_wbt_dst1_reg'[5]", + "signature": "da7516d43944b632" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT30'", + "signature": "da7da2a1351d4399" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'l16_2_shift_out_val'", + "signature": "da98ac58014c8c12" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT17'", + "signature": "daca6b8884c1c91a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'stb_entry_shift'[3]", + "signature": "db068f270b77509c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'idu_vidu_ex1_inst_data'[179:75,72:69,66:0]", + "signature": "dbaa02d329561d11" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'alu_shift_shifter_rst'[127:64]", + "signature": "dc3c1b9a5ca355e3" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'mul_ex1_func'[19:9]", + "signature": "dc5c15556d5e91c0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ctrl_dis_fp_dep_stall_dp'", + "signature": "dcb0e4898bc704cc" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pfb_entry_vld'[0]", + "signature": "dcb2012ff4b74e9a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v:: Signal is not used: 'A_RW_ACCESS'", + "signature": "dcbf31e62ee7ad07" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMCNT16'", + "signature": "dd09b5f46fd921d4" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_requantizer.sv:: Bits of function variable are not used: 's_quotient'[63:32]", + "signature": "dd3ce17472557118" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'data_idx'[13,2:0]", + "signature": "dd4ca0bb3c25e7de" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_op1_bhalf0'[14:0]", + "signature": "ddd1075950d53468" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bju_not_ex1_tar_pc_raw'[63:40]", + "signature": "de10803345469d91" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT5'", "signature": "de3f21f8cf8fdc37" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'type_legal'[3]", + "signature": "de452ad758d18fb1" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'BCOND_ALWAYS'", @@ -2302,8 +6092,48 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/ip/tiny_gpio/user_ip_design.sv:: Filename 'user_ip_design' does not match MODULE name: 'mpw_i2'", - "signature": "e07b8a155dddaf8f" + "example": "UNUSEDPARAM:$ROOT/rtl/ip/security/crypto_pkg.sv:: Parameter is not used: 'AES_KEY_256'", + "signature": "de664bbb6ad1b9f2" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'lsu_dtu_halt_info'[13:0]", + "signature": "dec37e57b6043d81" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT23'", + "signature": "ded7c9a411c4aedb" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF2_QNAN'", + "signature": "dee2c7283821ee35" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'aarpostexec_zero'", + "signature": "df1140cd3b4a4daa" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/apb4_jpeg.sv:: Bits of signal are not used: 's_encode_config'[31:10,7:0]", + "signature": "df508bd7c16d89a0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'data_for_code'[29]", + "signature": "df824ab1d4c419cd" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Bits of signal are not used: 's_div_rem_q'[32]", + "signature": "dfd6a9b317c1aeda" + }, + { + "count": 4, + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 3 bits.", + "signature": "e03b23fc26c668c5" }, { "count": 1, @@ -2317,8 +6147,13 @@ }, { "count": 1, - "example": "PROCASSINIT:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Procedural assignment to declaration with initial value: 'XSTATE'", - "signature": "e0b77a59b0aaab6c" + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/security/crypto_sha2_sram_engine.sv:: Instance pin connected by name with empty reference: 'clear_done_o'", + "signature": "e09e2b26b0d9445f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vtb_entry_seq_last'[3:2]", + "signature": "e0c4e53306047149" }, { "count": 1, @@ -2335,6 +6170,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MCYCLEH'", "signature": "e1142fcbcdebe68e" }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/rtl/ip/security/crypto_pkg.sv:: Parameter is not used: 'SHA2_224'", + "signature": "e13a32cb301d61df" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR14'", @@ -2342,13 +6182,18 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Bits of signal are not used: 'ALL1'[7:0]", - "signature": "e1ff29a15b0f88f8" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dirty_idx'[13,5:0]", + "signature": "e161b3f07965c5a1" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'EBRK'", - "signature": "e20a76642504e640" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HINFO_WIDTH'", + "signature": "e1c37fdb66aff12b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pad_biu_bid'[7:4]", + "signature": "e1c43d9259b48fb0" }, { "count": 1, @@ -2360,11 +6205,31 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER4H'", "signature": "e222b0513c30b791" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF3_INF'", + "signature": "e27fcabe3e8fd162" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT16'", + "signature": "e2c6161c111850a3" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/jpeg_decode_core.sv:: Instance pin connected by name with empty reference: 'marker_count_o'", + "signature": "e2d52dd41f28ae97" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_XH3PMPM'", "signature": "e31b91c4f12034d8" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ifu_iu_chgflw_pc'[0]", + "signature": "e31cc7a4f52fddb2" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER25H'", @@ -2377,8 +6242,18 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Filename 'darkbridge' does not match MODULE name: 'mpw_core_darkriscv_darkbridge'", - "signature": "e4c474bba48b64a4" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'mmu_addr_ge_upaddr7'", + "signature": "e3cd8b1e83b7ff14" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rem_add2_op1_h'", + "signature": "e450ba6fee72e8c2" + }, + { + "count": 1, + "example": "SYNCASYNCNET:$BUILD/generated/openc906/openc906_combined.v:: Signal flopped as both synchronous and async: 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_hp_subsystem.u_hp_core_wrapper.u_openc906.x_aq_mp_clk_top.apb_clk_en_f'", + "signature": "e46b9b8c91c01d42" }, { "count": 1, @@ -2390,6 +6265,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER23'", "signature": "e4da334e9e8fc79b" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA6'", + "signature": "e5021c4e8c937b33" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'IRQ_INPUT_BYPASS'", @@ -2397,8 +6277,8 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/femtorv32/femtorv32_tachyon.v:: Filename 'femtorv32_tachyon' does not match MODULE name: 'mpw_core_femtorv32_FemtoRV32'", - "signature": "e59a2ed7d300e59e" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SSIP3'", + "signature": "e5875856f3532d4e" }, { "count": 1, @@ -2410,16 +6290,66 @@ "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v:: Signal is not used: 'A_W_ACCESS'", "signature": "e5d4d191dfd2d654" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'iui_special_vsetvl_rs2'", + "signature": "e60520659ce2a715" + }, + { + "count": 6, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/jpeg_transform.sv:: Operator SUB expects 48 bits on the RHS, but RHS's ARRAYSEL generates 25 bits.", + "signature": "e656ad1d6b4b85a1" + }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/hp_core_wrapper.sv:: Instance pin connected by name with empty reference: 'core0_pad_lpmd_b'", + "signature": "e674bda479f74c58" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'pred_bht_pc'", + "signature": "e6e31c96d4796743" + }, { "count": 1, "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/memory/axi4_sdram.sv:: Instance pin connected by name with empty reference: 'stall_event_o'", "signature": "e70628e53a3e89ff" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA8'", + "signature": "e75943209c42e0d2" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MEIEA'", "signature": "e76bc25ed2f5fd1d" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'addr_ge_upaddr7'", + "signature": "e77a8763e4c182ee" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex2_func'", + "signature": "e7860cb85d5178f8" + }, + { + "count": 2, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/security/crypto_aes_sram_engine.sv:: Instance pin connected by name with empty reference: 'clear_done_o'", + "signature": "e79aeccb4822c723" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vec_pcgen_idle'", + "signature": "e7cef716a6dee61d" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_byte_joiner.sv:: Bits of function variable are not used: 's_mask'[8]", + "signature": "e7e108eb62af7e8d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'MCONFIGPTR_VAL'", @@ -2435,16 +6365,56 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT8'", "signature": "e83b011f2d06370d" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'srcv1_type'[47:42,40:28,26:0]", + "signature": "e840443626b6cf9e" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/ahbl_if.sv:: Signal is not used: 'hmastlock'", "signature": "e89ec00ecbba1b7c" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'tag_wen'[118,88,58,28]", + "signature": "e8aab42251dc7c83" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ACTION'", + "signature": "e8bc1e347e848210" + }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator GTE expects 14 bits on the LHS, but LHS's REPLICATE generates 13 bits.", + "signature": "e8d9aaddc89d59cc" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator GT expects 10 bits on the RHS, but RHS's REPLICATE generates 7 bits.", + "signature": "e8da9ef1c76c60a1" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_c0_0'[81]", + "signature": "e92c4cfc6137817f" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT18'", + "signature": "e931d13dc8f4024c" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_PACK'", "signature": "e949934a93e18883" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/core/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'hmaster'", + "signature": "e955233353e5fced" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_REV8'", @@ -2452,19 +6422,44 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'tuser'", - "signature": "e95d96d8ad151b2c" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_wbt_dst0_reg'[5]", + "signature": "e9728fa469b075b7" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MISA'", "signature": "e98223c9514b66f3" }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'INT_INFO'", + "signature": "e99593fc78094326" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 16 bits on the LHS, but LHS's VARREF 's_pidx_off_q' generates 13 bits.", + "signature": "e9ce67b9fb40b8cf" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_mcu_reconstructor.sv:: Bits of signal are not used: 's_x_next'[4]", + "signature": "e9fd5188dc9b040c" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'aclk'", "signature": "ea1bfdc6665f301a" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_p3_0_cout'[67]", + "signature": "eaad4bf7d712e185" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator GTE expects 32 bits on the LHS, but LHS's SEL generates 10 bits.", + "signature": "ead933e2816787ed" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER11'", @@ -2472,8 +6467,18 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'IBER'", - "signature": "eb3d616b6dee920d" + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/jpeg_entropy_encoder.sv:: Declaration of signal hides declaration in upper scope: 'block_i'", + "signature": "eb1e0e96c7d29698" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_src0_half'[31:16]", + "signature": "eb316efdefeaff9f" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA3'", + "signature": "eb43ec433e99bb4f" }, { "count": 1, @@ -2482,13 +6487,13 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/alu_decoder.v:: Filename 'alu_decoder' does not match MODULE name: 'mpw_core_kianv_rv32i_alu_decoder'", - "signature": "eb5f0be7986cc73d" + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPCFG0'", + "signature": "eb68f07f41323cfb" }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPCFG0'", - "signature": "eb68f07f41323cfb" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_encoder.sv:: Signal is not used: 'quant_i'", + "signature": "eb75115461d78eda" }, { "count": 1, @@ -2500,11 +6505,46 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Bits of function variable are not used: 'relative'[25:11,1:0]", "signature": "ebb10a629d037132" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_0_xx_ex3_func'", + "signature": "ebe9e46f805d2fc8" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_MEMOP'", "signature": "ebefcbb26f1f9236" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_src1_bhalf'[31:16]", + "signature": "ec1407c805d62f2f" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_job_decoder.sv:: Bits of signal are not used: 's_w0'[7:0]", + "signature": "ec308774e16d1602" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'cntof_wen'[1]", + "signature": "ec44cd6cec625c2a" + }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator ADD expects 34 bits on the RHS, but RHS's REPLICATE generates 31 bits.", + "signature": "ec99ba0e8bb2b669" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vlsu_create_split_cnt'[7:4]", + "signature": "ecd9d68f82b46eb8" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'sseg_nf'[2]", + "signature": "ece7fdc67b37dcf0" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_CPOP'", @@ -2515,31 +6555,101 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_instr_decompress.v:: Signal is not used: 'clk'", "signature": "ed08afc8d4d88e2d" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_partial_result_2'[80:79]", + "signature": "ed09f90e36e81e38" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_ctrl_dis_inst_func'[19:7,5:0]", + "signature": "ed427443f363bfa1" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ORN'", "signature": "ed65b8fc5dfa9713" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/npu_control_cdc.sv:: Instance pin connected by name with empty reference: 'dst_data_o'", + "signature": "ed695ecdc1f8067d" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER6H'", "signature": "ed9c746af4e9606b" }, + { + "count": 1, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/security/crypto_sha2_sram_engine.sv:: Instance pin connected by name with empty reference: 'count_o'", + "signature": "eda5f3300f18bd56" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p0_0_cout'[65]", + "signature": "edc5758351993b29" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'M_OP_MULHU'", "signature": "ede3244c1286a834" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_decoder.sv:: Signal is not used: 's_quant_block'", + "signature": "ee3bed4cb9ff45e0" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'core_dm_halted_req'", + "signature": "ee4f30d6dddd45ed" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'pfb_entry_evict'[0]", + "signature": "ee7c50105636ca40" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_DATA10'", + "signature": "ee8b670e11a2b103" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TCONTROL'", "signature": "eee1f40880b0c327" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'ctrl_xx_amp_lock'", + "signature": "eef420e39b0b068c" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'dp_gpr_src0_reg'[5]", + "signature": "ef006b97777cd347" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v:: Signal is not used: 'A_RW_ACCESS'", "signature": "ef9e0f44cb68cbc6" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bus_mtx_ip_pprot'[0]", + "signature": "efa0a032fc37c823" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex3_shift_limit_one_hot'[16:0]", + "signature": "efa25221bf4d7c9a" + }, + { + "count": 2, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/jpeg_coefficient_engine.sv:: Instance pin connected by name with empty reference: 'start_ready_o'", + "signature": "efa593c43fc044ee" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER3H'", @@ -2550,35 +6660,105 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_SHAMT'", "signature": "f01ee8e98e13b055" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv:: Signal is not used: 'wuser'", + "signature": "f03160983c561746" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'DCHE'", + "signature": "f03c50719aa231ad" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_double_sub_inc1_r'[56,1:0]", + "signature": "f0cc32df993afcbb" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'wbt_ctrl_src1_info'[6]", + "signature": "f0f99643ba063305" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT14'", "signature": "f1bc2dba4772b6f5" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Signal is not used: 'time_a'", + "signature": "f1cf01795cf29266" + }, + { + "count": 1, + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/ga2d_pixel.sv:: Declaration of signal hides declaration in upper scope: 's_red'", + "signature": "f1e4d301d37fc11c" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'CSR_WTYPE_W'", "signature": "f1f0ace29e0a56d0" }, { - "count": 30, - "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_pad_bindings.svh:: Instance pin connected by name with empty reference: 'p2c'", - "signature": "f2548a0d3b636cfb" + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'TYPE'", + "signature": "f1fa5bb5bfa11882" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'IAER'", - "signature": "f25b476d1b027768" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'smcir_local_en'", + "signature": "f215916927f9a5fb" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_decoder.sv:: Signal is not used: 'reciprocal_i'", + "signature": "f271cab163662f4e" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'STIMECMP2'", + "signature": "f29f96447516730e" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/axi4_downsizer_128to64.sv:: Signal is not used: 's_wide_write_accept'", + "signature": "f2a4b334dded2004" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'CYCLE'", "signature": "f2d3d9e31d7a7e1b" }, + { + "count": 2, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/multimedia/jpeg_encode_core.sv:: Instance pin connected by name with empty reference: 'start_ready_o'", + "signature": "f2dc2e1cc0e76401" + }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/load_alignment.v:: Filename 'load_alignment' does not match MODULE name: 'mpw_core_kianv_rv32i_load_alignment'", - "signature": "f3ca76116b68f4b6" + "example": "VARHIDDEN:$ROOT/rtl/ip/multimedia/ga2d_pixel.sv:: Declaration of signal hides declaration in upper scope: 's_blue'", + "signature": "f3552dbd5a0de1be" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MTIMECMP2'", + "signature": "f38afd73a4a7d8d6" + }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ADD_S_WIDTH'", + "signature": "f3df58b835eca563" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'half2_denorm_shift_num'", + "signature": "f3f7f016e74a2a02" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_p1_2_cout'[65]", + "signature": "f3fd037d9a1240d8" }, { "count": 1, @@ -2590,11 +6770,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MCOUNTINHIBIT'", "signature": "f423f1b5d0e86d3f" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'clk_en'", - "signature": "f47d3d0e2ee1e85b" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/rv_opcodes.vh:: Parameter is not used: 'RV_RD_BITS'", @@ -2607,8 +6782,28 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_bufreg2.v:: Filename 'serv_bufreg2' does not match MODULE name: 'mpw_core_serv_serv_bufreg2'", - "signature": "f54afe8681d27688" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'VPN_WIDTH'", + "signature": "f52f5b864dc29a47" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF1_ID'", + "signature": "f544618a2c21c3e3" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_table_store.sv:: Bits of signal are not used: 's_selected_addr'[13]", + "signature": "f58b9146efcb711b" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT11'", + "signature": "f6195099035e856d" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'scontext'[63:34]", + "signature": "f658108d2a1aefa9" }, { "count": 1, @@ -2617,8 +6812,23 @@ }, { "count": 1, - "example": "PROCASSINIT:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Procedural assignment to declaration with initial value: 'XDACK2'", - "signature": "f6df617b050f423b" + "example": "WIDTHEXPAND:$BUILD/generated/openc906/openc906_combined.v:: Operator AND expects 32 bits on the RHS, but RHS's REPLICATE generates 10 bits.", + "signature": "f65ebdd9d5499a1a" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HALF3_ZERO'", + "signature": "f6bc20b8311f3d6f" + }, + { + "count": 1, + "example": "DECLFILENAME:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Filename 'RM_IHPSG13_2P_core_behavioral_ideal' does not match MODULE name: 'SRAM_2P_behavioral'", + "signature": "f71d9c63ba03b5da" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'lsu_sew'", + "signature": "f7402f90c250df51" }, { "count": 1, @@ -2632,33 +6842,68 @@ }, { "count": 1, - "example": "LATCH:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Latch inferred for signal 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_axi4_sdram.u_sdram_axi4.unnamedblk1.rd_legal' (not all control paths of combinational always assign a value)", - "signature": "f88aacfc3533fc19" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_3_xx_ex4_eu_sel'", + "signature": "f78b78a27fa8ae15" }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/mpw/core/femtorv32/user_core_design.sv:: Parameter is not used: 'ID'", - "signature": "f8ccdc52cbaf47d1" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT27'", + "signature": "f7999f4f222ec2db" + }, + { + "count": 3, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SILEN'", + "signature": "f876080e43e97f4c" + }, + { + "count": 2, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/multimedia/npu_scheduler.sv:: Operator SUB expects 32 bits on the RHS, but RHS's REPLICATE generates 29 bits.", + "signature": "f88223dc551f7b30" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_top.v:: Bits of signal are not used: 'i_wb_rdt'[1:0]", - "signature": "f8e1f216abc4cf66" + "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/axi4_data_crossbar.sv:: Bits of function variable are not used: 'prot'[1:0]", + "signature": "f8c2d762a98d0167" }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_immdec.v:: Filename 'serv_immdec' does not match MODULE name: 'mpw_core_serv_serv_immdec'", - "signature": "fa013b7604aa02e4" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'CI'", + "signature": "f8c34077f1936888" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'mpw_core_darkriscv_CUS'", - "signature": "fa062947facd4f28" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'BHALF_FRAC'", + "signature": "f95a37d403535734" }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/store_alignment.v:: Filename 'store_alignment' does not match MODULE name: 'mpw_core_kianv_rv32i_store_alignment'", - "signature": "fa433f8c5842eccb" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'MHPMEVT29'", + "signature": "f97fadd5c91084e6" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SHPMCNT31'", + "signature": "f9c8a9b141305453" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/security/crypto_aes_sram_engine.sv:: Signal is not used: 's_scrub_busy'", + "signature": "f9cac91bb463c82c" + }, + { + "count": 2, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ff1_16_bit'[23:4]", + "signature": "f9fc5b132481c728" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'HPMCNT28'", + "signature": "fa05b2db11d68820" + }, + { + "count": 2, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/multimedia/ga2d_pixel.sv:: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's DIV generates 16 bits.", + "signature": "fa4869d30957d636" }, { "count": 1, @@ -2666,15 +6911,35 @@ "signature": "fa69f904dbfc975e" }, { - "count": 11, + "count": 10, "example": "SPECIFYIGN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v:: Ignoring unsupported: specify block construct", "signature": "faa191e2dbf4a242" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'right_8_3_shift_num'[15]", + "signature": "faab504761af81dd" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_oper0'[62:51]", + "signature": "fb1c216168ac9a9d" + }, + { + "count": 1, + "example": "CMPCONST:$ROOT/rtl/ip/multimedia/ga2d_reg.sv:: Comparison is constant due to limited range", + "signature": "fb2c6285016a3ff0" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER26H'", "signature": "fb8dd2e470f5c46d" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex1_oper1'[62:51]", + "signature": "fbaef88fc3321732" + }, { "count": 1, "example": "WIDTHTRUNC:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits.", @@ -2685,11 +6950,41 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'BRANCH_PREDICTOR'", "signature": "fbfddc8034ecebce" }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'XLEN'", + "signature": "fc183f15b96d1bfd" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'OFFSET_CUSBUF2'", + "signature": "fc3469bb128dce33" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_ALUOP'", "signature": "fc6f395584c3a436" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_accumulator.sv:: Bits of function variable are not used: 's_w2'[1]", + "signature": "fc79d7cc2b462dbe" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'ex2_right_max'[12:7]", + "signature": "fcbcda1ce6de046a" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'bus_mtx_plic_ctrl_pwdata'[31,29:1]", + "signature": "fccb34fe1beff591" + }, + { + "count": 4, + "example": "PINMISSING:$BUILD/generated/pin_map/rtl/retrosoc_asic_pad_bindings.svh:: Instance has missing pin: 'iovss'", + "signature": "fcf878701fa36f31" + }, { "count": 4, "example": "WIDTHEXPAND:$ROOT/rtl/ip/memory/sdram_core.sv:: Operator ADD expects 3 bits on the RHS, but RHS's SEL generates 1 bits.", @@ -2700,6 +6995,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'MUL_FAST'", "signature": "fdfdd60c167ee421" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/npu_core.sv:: Signal is not used: 's_timeout_q'", + "signature": "fe1d2f4b51b81ecf" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TIMEH'", @@ -2707,14 +7007,39 @@ }, { "count": 1, - "example": "PROCASSINIT:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Procedural assignment to declaration with initial value: 'XATAI2'", - "signature": "fe2cb50cfb98e646" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'vpu_group_2_xx_ex1_srcv2_type'", + "signature": "fe44b07d89f0285e" + }, + { + "count": 4, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SINGLE_EXPN'", + "signature": "fe45a0d25e2db162" + }, + { + "count": 2, + "example": "BLKSEQ:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_2P_core_behavioral_ideal.v:: Blocking assignment '=' in sequential logic process", + "signature": "fe7cbb1b8652adf5" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/multimedia/jpeg_block_decoder.sv:: Signal is not used: 's_quant_start'", + "signature": "fea7befc2e3c1424" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Bits of signal are not used: 'vpu_group_3_xx_ex1_imm'[4,0]", + "signature": "feba074e2588b8c4" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT26'", "signature": "febfea7999fe3850" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'rlast'", + "signature": "fedb5446064b6352" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MIE'", @@ -2726,19 +7051,34 @@ "signature": "ff4abd0f3eebcb86" }, { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Signal is not used: 'DRW'", - "signature": "ff50b50e66d518a8" + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'SINGLE_WIDTH'", + "signature": "ffb90c1e6c226fd5" }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/user_core_design.sv:: Filename 'user_core_design' does not match MODULE name: 'mpw_c0'", - "signature": "ffc1cca248daf538" + "example": "UNUSEDSIGNAL:$BUILD/generated/openc906/openc906_combined.v:: Signal is not used: 'iutlb_arb_read'", + "signature": "ffcf2fcd27e3dc89" }, { "count": 1, - "example": "LATCH:$ROOT/rtl/ip/memory/sdram_axi4.sv:: Latch inferred for signal 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_axi4_sdram.u_sdram_axi4.unnamedblk2.wr_last' (not all control paths of combinational always assign a value)", - "signature": "ffcdc1d42d579e2c" + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'COUNT'", + "signature": "ffdf20f7e994bac1" + }, + { + "count": 1, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'CA'", + "signature": "ffec064f3fee6c04" + }, + { + "count": 1, + "example": "IMPLICIT:$BUILD/generated/openc906/openc906_combined.v:: Signal definition not found, creating implicitly: 'sync_sys_apb_rst_b'", + "signature": "fff34514b5de4378" + }, + { + "count": 2, + "example": "UNUSEDPARAM:$BUILD/generated/openc906/openc906_combined.v:: Parameter is not used: 'ENTRY_NUM'", + "signature": "ffffd87703f4898a" } ], "profile": "ihp130", diff --git a/rtl/README.md b/rtl/README.md index 2e997bd2..3aba7527 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -12,10 +12,17 @@ notices. `filelist/` selects PDK-specific RTL sources; `tech/` contains technology wrappers. Respect managed upstream boundaries and use setup helpers rather than editing generated MPW output. -The optional IHP130 LP/HP profile integrates VexiiRiscv through self-owned -wrappers, a 64-to-32 compatibility plane, HP ACLINT/PLIC, mailbox, UART1, and -SYSCTRL lifecycle signals. The generated CPU Verilog lives only below -`build//generated/vexiiriscv/` and is an external lint boundary. See +The optional IHP130 LP/HP profile integrates the locked, pre-generated T-Head +OpenC906 HP core through self-owned wrappers, a serializing 128-to-64 +downsizer with an MMIO demux, the C906 internal CLINT/PLIC, mailbox, UART1, and +SYSCTRL lifecycle signals. `make setup-openc906` (part of `make setup`) +restores the locked checkout and `make openc906-prepare` emits the generated +filelist and manifest below `build//generated/openc906/`; the OpenC906 +sources are an external lint boundary. The reviewed hart-ID and sysmap +address-attribute overrides live in `rtl/mini/ip_overrides/` and are applied +by filelist generation, never by editing the vendored checkout. The former +VexiiRiscv HP generator is preserved +only as the frozen Std-series asset (`make std-vexii-generate`). See [LP/HP Architecture](../docs/lp-hp-architecture.md). RTL changes require an affected firmware build and simulation. Use diff --git a/rtl/mini/Makefile b/rtl/mini/Makefile index 017020b6..2f5ffab9 100644 --- a/rtl/mini/Makefile +++ b/rtl/mini/Makefile @@ -182,7 +182,7 @@ RTL_FILELISTS := $(MEMORY_MAP_FILELIST) $(SOC_TOPOLOGY_FILELIST) $(USER_EXTENSIO $(GENERATED_FL_DIR)/core_hazard3.fl \ $(if $(filter MPW,$(MINI_MODE)),$(MPW_OUTPUT_DIR)/core/core.fl,$(USER_EXTENSIONS_DIR)/legacy_core.fl) \ $(if $(filter MPW,$(MINI_MODE)),$(MPW_OUTPUT_DIR)/ip/ip.fl,$(USER_EXTENSIONS_DIR)/legacy_ip.fl) \ - $(if $(filter YES,$(HAVE_HP)),$(HP_GENERATED_DIR)/vexiiriscv.fl) \ + $(if $(filter YES,$(HAVE_HP)),$(HP_GENERATED_FL)) \ $(GENERATED_FL_DIR)/top.fl RTL_FLIST := $(foreach filelist,$(RTL_FILELISTS),-f $(filelist)) #====================== end ====================== diff --git a/rtl/mini/address_map/memory_map.json b/rtl/mini/address_map/memory_map.json index 70cd711f..661dad35 100644 --- a/rtl/mini/address_map/memory_map.json +++ b/rtl/mini/address_map/memory_map.json @@ -220,22 +220,13 @@ "burst": "incr16" }, { - "symbol": "HP_ACLINT", - "base": "0x02000000", - "size": "0x00010000", - "route": "apb4_periph", - "kind": "active", + "symbol": "HP_C906_SYS", + "base": "0x08000000", + "size": "0x08000000", + "route": "reserved", + "kind": "reserved", "public": true, - "user_access": "rw" - }, - { - "symbol": "HP_PLIC", - "base": "0x0C000000", - "size": "0x04000000", - "route": "apb4_periph", - "kind": "active", - "public": true, - "user_access": "rw" + "user_access": "none" }, { "symbol": "APB4_GPIO", diff --git a/rtl/mini/filelist/top.fl b/rtl/mini/filelist/top.fl index b481e6d5..51a38bcf 100644 --- a/rtl/mini/filelist/top.fl +++ b/rtl/mini/filelist/top.fl @@ -25,6 +25,8 @@ /top/axi42apb4_periph.sv /top/axi4_word_bridge.sv /top/axi4_downsizer_64to32.sv +/top/axi4_downsizer_128to64.sv +/top/axi4_mmio_demux.sv /top/hp_axi4_mux3.sv /top/axi42ram.sv /top/rib_error_slave.sv diff --git a/rtl/mini/integration/generate_soc_topology.py b/rtl/mini/integration/generate_soc_topology.py index 97dc92a3..5d699d3c 100644 --- a/rtl/mini/integration/generate_soc_topology.py +++ b/rtl/mini/integration/generate_soc_topology.py @@ -21,8 +21,8 @@ FABRIC_PROTOCOLS = {name: "axi4" for name in FABRIC_LINK_NAMES} IRQ_GROUP_NAMES = ("apb4_periph", "apb4_system") IRQ_VECTOR_WIDTH = 64 DATA_MASTER_NAMES = ( - "hp_icache", - "hp_dcache", + "hp_mem", + "hp_retired", "dma", "io_gateway_a", "io_gateway_b", diff --git a/rtl/mini/integration/soc_topology.json b/rtl/mini/integration/soc_topology.json index fabc08da..8290c35b 100644 --- a/rtl/mini/integration/soc_topology.json +++ b/rtl/mini/integration/soc_topology.json @@ -366,17 +366,17 @@ "data_master_policies": [ { "index": 0, - "name": "hp_icache", + "name": "hp_mem", "read_targets": ["sram", "sdram", "qpi", "opi", "xpi"], - "write_targets": [], + "write_targets": ["sram", "sdram", "qpi", "opi"], "allow_instruction": true, "require_noncacheable": false }, { "index": 1, - "name": "hp_dcache", - "read_targets": ["sram", "sdram", "qpi", "opi", "xpi"], - "write_targets": ["sram", "sdram", "qpi", "opi"], + "name": "hp_retired", + "read_targets": [], + "write_targets": [], "allow_instruction": false, "require_noncacheable": false }, @@ -625,41 +625,27 @@ }, { "slot": 24, - "name": "hp_aclint", - "timed_interface": "u_hp_aclint_apb4_if", - "pure_interface": "u_hp_aclint_apb4_pure_if", - "region": "HP_ACLINT" - }, - { - "slot": 25, - "name": "hp_plic", - "timed_interface": "u_hp_plic_apb4_if", - "pure_interface": "u_hp_plic_apb4_pure_if", - "region": "HP_PLIC" - }, - { - "slot": 26, "name": "jpeg", "timed_interface": "u_jpeg_apb4_if", "pure_interface": "u_jpeg_apb4_pure_if", "region": "APB4_JPEG" }, { - "slot": 27, + "slot": 25, "name": "apu", "timed_interface": "u_apu_apb4_if", "pure_interface": "u_apu_apb4_pure_if", "region": "APB4_APU" }, { - "slot": 28, + "slot": 26, "name": "ga2d", "timed_interface": "u_ga2d_apb4_if", "pure_interface": "u_ga2d_apb4_pure_if", "region": "APB4_GA2D" }, { - "slot": 29, + "slot": 27, "name": "npu", "timed_interface": "u_npu_apb4_if", "pure_interface": "u_npu_apb4_pure_if", diff --git a/rtl/mini/ip_overrides/aq_sysio_kid.v b/rtl/mini/ip_overrides/aq_sysio_kid.v new file mode 100644 index 00000000..800550a8 --- /dev/null +++ b/rtl/mini/ip_overrides/aq_sysio_kid.v @@ -0,0 +1,203 @@ +// retroSoC controlled override of the vendored OpenC906 aq_sysio_kid.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/cpu/rtl/aq_sysio_kid.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (Mini LP/HP contract): the HP core must report mhartid=1 +// (the LP Hazard3 core is hart 0). Upstream hardwires sysio_core_hartid to +// 3'b0 and exposes no top-level hart-id port, so this file substitutes the +// vendored module with sysio_core_hartid = 3'd1. Everything else is +// byte-identical to upstream. Keep in sync when the lock revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ +module aq_sysio_kid( + apb_clk_en, + axim_clk_en, + clint_core_ms_int, + clint_core_mt_int, + clint_core_ss_int, + clint_core_st_int, + core_pad_lpmd_b, + core_sysio_lpmd_b, + cpurst_b, + forever_cpuclk, + pad_yy_icg_scan_en, + plic_core_me_int, + plic_core_se_int, + sysio_core_hartid, + sysio_core_me_int, + sysio_core_ms_int, + sysio_core_mt_int, + sysio_core_se_int, + sysio_core_ss_int, + sysio_core_st_int +); + +// &Ports; @23 +input apb_clk_en; +input axim_clk_en; +input clint_core_ms_int; +input clint_core_mt_int; +input clint_core_ss_int; +input clint_core_st_int; +input [1:0] core_sysio_lpmd_b; +input cpurst_b; +input forever_cpuclk; +input pad_yy_icg_scan_en; +input plic_core_me_int; +input plic_core_se_int; +output [1:0] core_pad_lpmd_b; +output [2:0] sysio_core_hartid; +output sysio_core_me_int; +output sysio_core_ms_int; +output sysio_core_mt_int; +output sysio_core_se_int; +output sysio_core_ss_int; +output sysio_core_st_int; + +// &Regs; @24 +reg clint_core_ms_int_cpu; +reg clint_core_mt_int_cpu; +reg clint_core_ss_int_cpu; +reg clint_core_st_int_cpu; +reg [1:0] core_pad_lpmd_b; +reg plic_core_me_int_cpu; +reg plic_core_se_int_cpu; + +// &Wires; @25 +wire apb_clk_en; +wire axim_clk_en; +wire clint_core_ms_int; +wire clint_core_mt_int; +wire clint_core_ss_int; +wire clint_core_st_int; +wire [1:0] core_sysio_lpmd_b; +wire cpurst_b; +wire forever_cpuclk; +wire kid_int_clk; +wire kid_int_clk_en; +wire pad_yy_icg_scan_en; +wire plic_core_me_int; +wire plic_core_se_int; +wire sysio_clk_en; +wire [2:0] sysio_core_hartid; +wire sysio_core_me_int; +wire sysio_core_ms_int; +wire sysio_core_mt_int; +wire sysio_core_se_int; +wire sysio_core_ss_int; +wire sysio_core_st_int; +wire sysio_kid_clk; + + +//input +assign sysio_clk_en = axim_clk_en; +// &Instance("gated_clk_cell", "x_sysio_kid_gated_clk"); @29 +gated_clk_cell x_sysio_kid_gated_clk ( + .clk_in (forever_cpuclk ), + .clk_out (sysio_kid_clk ), + .external_en (1'b0 ), + .global_en (1'b1 ), + .local_en (sysio_clk_en ), + .module_en (1'b0 ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect(.clk_in (forever_cpuclk), @30 +// .external_en (1'b0 ), @31 +// .global_en (1'b1 ), @32 +// .module_en (1'b0 ). @33 +// .local_en (sysio_clk_en ), @34 +// .clk_out (sysio_kid_clk ) @35 +// ); @36 + +//output +always @(posedge sysio_kid_clk or negedge cpurst_b) +begin + if (!cpurst_b) + begin + core_pad_lpmd_b[1:0] <= 2'b11; + end + else if (axim_clk_en) + begin + core_pad_lpmd_b[1:0] <= core_sysio_lpmd_b[1:0]; + end +end + +// &Force("output", "sysio_core_me_int"); @51 +// &Force("output", "sysio_core_mt_int"); @52 +// &Force("output", "sysio_core_ms_int"); @53 +// &Force("output", "sysio_core_se_int"); @54 +// &Force("output", "sysio_core_st_int"); @55 +// &Force("output", "sysio_core_ss_int"); @56 + +assign kid_int_clk_en = apb_clk_en; +// &Instance("gated_clk_cell", "x_sysio_kid_int_gated_clk"); @59 +gated_clk_cell x_sysio_kid_int_gated_clk ( + .clk_in (forever_cpuclk ), + .clk_out (kid_int_clk ), + .external_en (1'b0 ), + .global_en (1'b1 ), + .local_en (kid_int_clk_en ), + .module_en (1'b0 ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect(.clk_in (forever_cpuclk), @60 +// .external_en (1'b0 ), @61 +// .global_en (1'b1 ), @62 +// .module_en (1'b0 ). @63 +// .local_en (kid_int_clk_en), @64 +// .clk_out (kid_int_clk ) @65 +// ); @66 + +always @(posedge kid_int_clk or negedge cpurst_b) +begin + if (!cpurst_b) + begin + plic_core_me_int_cpu <= 1'b0; + plic_core_se_int_cpu <= 1'b0; + clint_core_ms_int_cpu <= 1'b0; + clint_core_ss_int_cpu <= 1'b0; + clint_core_mt_int_cpu <= 1'b0; + clint_core_st_int_cpu <= 1'b0; + end + else if (apb_clk_en) + begin + plic_core_me_int_cpu <= plic_core_me_int; + plic_core_se_int_cpu <= plic_core_se_int; + clint_core_ms_int_cpu <= clint_core_ms_int; + clint_core_ss_int_cpu <= clint_core_ss_int; + clint_core_mt_int_cpu <= clint_core_mt_int; + clint_core_st_int_cpu <= clint_core_st_int; + end +end + +assign sysio_core_me_int = plic_core_me_int_cpu; +assign sysio_core_se_int = plic_core_se_int_cpu; +assign sysio_core_ms_int = clint_core_ms_int_cpu; +assign sysio_core_ss_int = clint_core_ss_int_cpu; +assign sysio_core_mt_int = clint_core_mt_int_cpu; +assign sysio_core_st_int = clint_core_st_int_cpu; + +// retroSoC: HP hart id is 1 (LP Hazard3 is hart 0); upstream ties this to 3'b0. +assign sysio_core_hartid[2:0] = 3'd1; + +// &Force("output","core_pad_lpmd_b"); @100 +// &ModuleEnd; @103 +endmodule diff --git a/rtl/mini/ip_overrides/sysmap.h b/rtl/mini/ip_overrides/sysmap.h new file mode 100644 index 00000000..5fb936b6 --- /dev/null +++ b/rtl/mini/ip_overrides/sysmap.h @@ -0,0 +1,72 @@ +// retroSoC controlled override of the vendored OpenC906 sysmap.h. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/mmu/rtl/sysmap.h +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change: the upstream default region table targets a 40-bit +// reference map and marks the entire low 2.4 GiB (including the Mini +// peripheral window) as cacheable/bufferable memory. The OpenC906 user +// manual (section 3, sysmap.h) requires the integrator to configure address +// attributes per SoC and explicitly requires CLINT/PLIC regions to be +// non-cacheable devices. This override maps the Mini address map: +// +// region 0: 0x0000_0000-0x01FF_FFFF flash XIP -> normal cacheable +// region 1: 0x0200_0000-0x2FFF_FFFF MMIO window (incl. the core-internal +// CLINT/PLIC window 0x0800_0000-0x0FFF_FFFF) -> device SO/NC/NB +// region 2: 0x3000_0000-0x4FFF_FFFF SRAM/SDRAM/PSRAM/OPI -> cacheable +// region 3: 0x5000_0000-0x5FFF_FFFF XPI window -> normal cacheable +// region 4: 0x6000_0000-0x7FFF_FFFF reserved -> device SO/NC/NB +// region 5-7: everything above -> device SO/NC/NB (also the +// out-of-table default per the user manual) +// +// Flag bit layout (aq_mmu_utlb.v: utlb_so=flg[9]=pma[4], utlb_ca=pma[3]): +// flag[4]=SO (strong order) flag[3]=C (cacheable) flag[2]=B (bufferable) +// flag[1]=shareable flag[0]=security (unused without TEE) +// +// Keep in sync when the lock revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// ADDR is 28-bit, 4K address +// Flag includes: Strong Order, Cacheable, Bufferable, Shareable, Security + + `define SYSMAP_BASE_ADDR0 28'h02000 + `define SYSMAP_FLG0 5'b01111 + + `define SYSMAP_BASE_ADDR1 28'h30000 + `define SYSMAP_FLG1 5'b10011 + + `define SYSMAP_BASE_ADDR2 28'h50000 + `define SYSMAP_FLG2 5'b01111 + + `define SYSMAP_BASE_ADDR3 28'h60000 + `define SYSMAP_FLG3 5'b01111 + + `define SYSMAP_BASE_ADDR4 28'h80000 + `define SYSMAP_FLG4 5'b10011 + + `define SYSMAP_BASE_ADDR5 28'hC0000 + `define SYSMAP_FLG5 5'b10011 + + `define SYSMAP_BASE_ADDR6 28'hFF00000 + `define SYSMAP_FLG6 5'b10011 + + `define SYSMAP_BASE_ADDR7 28'hFFFFFFF + `define SYSMAP_FLG7 5'b10011 + +//End ct_mmu_sysmap diff --git a/rtl/mini/top/apb4_periph.sv b/rtl/mini/top/apb4_periph.sv index 9a8a06c8..34aac80c 100644 --- a/rtl/mini/top/apb4_periph.sv +++ b/rtl/mini/top/apb4_periph.sv @@ -90,10 +90,7 @@ module apb4_periph #( input logic [3:0] fault_wstrb_i, input logic fault_reserved_i, output logic [63:0] hp_time_o, - output logic hp_timer_irq_o, - output logic hp_software_irq_o, - output logic hp_machine_external_irq_o, - output logic hp_supervisor_external_irq_o, + output logic [15:0] hp_plic_src_o, output logic apu_idle_o, output logic jpeg_idle_o, output logic ga2d_idle_o, @@ -177,7 +174,6 @@ axi4_stream_if #( ); clint_if u_clint_if (); - clint_if #(.HartNum(2)) u_hp_clint_if (); dma_req_if u_dma_req_if (); apb4_if u_psram_mem_apb4_if ( .pclk (clk_mem_i), @@ -221,8 +217,7 @@ axi4_stream_if #( logic s_dma_xpi_tx_stall_mem; logic s_dma_xpi_rx_stall_mem; logic s_mailbox_lp_irq, s_mailbox_hp_irq; - logic [31:0] s_hp_plic_source; - logic [ 1:0] s_hp_plic_context_irq; + logic [15:0] s_hp_plic_source; logic [ 3:0] s_unused_optional_status; axi42apb4_periph u_axi42apb4_periph ( @@ -244,11 +239,8 @@ axi4_stream_if #( assign u_dma_req_if.i2c1_rx_proc = ~s_dma_i2c1_rx_stall; assign u_dma_req_if.crypto_in_proc = s_dma_crypto_in_proc; assign u_dma_req_if.crypto_out_proc = s_dma_crypto_out_proc; - assign hp_time_o = u_hp_clint_if.mtime_o; - assign hp_timer_irq_o = u_hp_clint_if.timer_irq_o[1]; - assign hp_software_irq_o = u_hp_clint_if.software_irq_o[1]; - assign hp_machine_external_irq_o = s_hp_plic_context_irq[0]; - assign hp_supervisor_external_irq_o = s_hp_plic_context_irq[1]; + assign hp_time_o = u_clint_if.mtime_o; + assign hp_plic_src_o = s_hp_plic_source; assign resource_irq_raw_o = { s_npu_irq_raw, s_ga2d_irq_raw, @@ -389,24 +381,6 @@ axi4_stream_if #( .hp_irq_o(s_mailbox_hp_irq) ); - apb4_clint #( - .HartNum(2) - ) u_apb4_hp_aclint ( - .clk_i (clk_i), - .rst_n_i (rst_n_i), - .timebase_tick_i(timebase_tick_i), - .apb4 (u_hp_aclint_apb4_if), - .clint (u_hp_clint_if) - ); - - apb4_plic u_apb4_hp_plic ( - .clk_i (clk_i), - .rst_n_i (rst_n_i), - .source_i (s_hp_plic_source), - .apb4 (u_hp_plic_apb4_if), - .context_irq_o(s_hp_plic_context_irq) - ); - apb4_timer u_apb4_timer0 ( .clk_i (clk_i), .rst_n_i (rst_n_i), diff --git a/rtl/mini/top/axi4_data_crossbar.sv b/rtl/mini/top/axi4_data_crossbar.sv index 665260a6..cbc3e6e1 100644 --- a/rtl/mini/top/axi4_data_crossbar.sv +++ b/rtl/mini/top/axi4_data_crossbar.sv @@ -304,7 +304,9 @@ module axi4_data_crossbar #( endfunction function automatic logic [CountWidth-1:0] master_write_limit(input int unsigned master); - if ((master == 1) || (master == 2) || (master == 7)) return CountWidth'(2); + // Master 0 is the merged HP core port (instruction and data); it inherits + // the retired HP data port's write credits. Master 1 is the retired slot. + if ((master == 0) || (master == 2) || (master == 7)) return CountWidth'(2); if (((master >= 3) && (master <= 6)) || (master == 8) || (master == 9)) return CountWidth'(1); return '0; endfunction diff --git a/rtl/mini/top/axi4_downsizer_128to64.sv b/rtl/mini/top/axi4_downsizer_128to64.sv new file mode 100644 index 00000000..054e223f --- /dev/null +++ b/rtl/mini/top/axi4_downsizer_128to64.sv @@ -0,0 +1,327 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 + +`include "axi4_define.svh" + +// Serializing 128-bit to 64-bit AXI4 downsizer for the OpenC906 BIU master. +// Accepts one outstanding wide transaction per direction and emits legal +// narrow bursts. The C906 only issues size-4 INCR (len 1/4) and WRAP4 reads +// and size<=4 INCR writes, so no burst splitting is required: a size-4 wide +// burst maps to a doubled-length narrow burst (WRAP4x16B becomes WRAP8x8B). +module axi4_downsizer_128to64 #( + parameter int unsigned WideIdWidth = 8 +) ( + input logic clk_i, + input logic rst_n_i, + input logic clear_i, + axi4_if.slave wide, + axi4_if.master narrow +); + typedef enum logic { + Idle, + Active + } channel_state_e; + + channel_state_e s_read_state_d, s_read_state_q; + channel_state_e s_write_state_d, s_write_state_q; + logic s_read_state_bits_q; + logic s_write_state_bits_q; + logic [WideIdWidth-1:0] s_read_id_d, s_read_id_q; + logic [WideIdWidth-1:0] s_write_id_d, s_write_id_q; + logic [2:0] s_read_size_d, s_read_size_q; + logic [2:0] s_write_size_d, s_write_size_q; + logic [31:0] s_read_addr_d, s_read_addr_q; + logic [31:0] s_write_addr_d, s_write_addr_q; + logic s_read_upper_d, s_read_upper_q; + logic s_write_upper_d, s_write_upper_q; + logic [63:0] s_read_lower_d, s_read_lower_q; + logic [1:0] s_read_resp_d, s_read_resp_q; + logic s_read_accept; + logic s_write_addr_accept; + logic s_narrow_read_accept; + logic s_narrow_write_accept; + logic s_wide_read_accept; + logic s_wide_write_accept; + logic s_b_pending_d, s_b_pending_q; + logic [1:0] s_b_resp_d, s_b_resp_q; + + assign s_read_state_q = channel_state_e'(s_read_state_bits_q); + assign s_write_state_q = channel_state_e'(s_write_state_bits_q); + + // Address channels are forwarded combinationally while idle; a size-4 wide + // burst doubles its beat count on the narrow side, all other transfers + // pass through unchanged. + assign wide.arready = (s_read_state_q == Idle) && narrow.arready; + assign narrow.arvalid = (s_read_state_q == Idle) && wide.arvalid; + assign narrow.arid = '0; + assign narrow.araddr = wide.araddr; + assign narrow.arlen = (wide.arsize == 3'd4) ? 8'((wide.arlen << 1) | 8'd1) : wide.arlen; + assign narrow.arsize = (wide.arsize == 3'd4) ? 3'd3 : wide.arsize; + assign narrow.arburst = wide.arburst; + assign narrow.arlock = wide.arlock; + assign narrow.arcache = wide.arcache; + assign narrow.arprot = wide.arprot; + assign narrow.arqos = wide.arqos; + assign narrow.arregion = wide.arregion; + assign narrow.aruser = '0; + assign s_read_accept = wide.arvalid && wide.arready; + + assign wide.rid = s_read_id_q; + assign wide.rdata = (s_read_size_q == 3'd4) ? {narrow.rdata, s_read_lower_q} : + s_read_addr_q[3] ? {narrow.rdata, 64'd0} : {64'd0, narrow.rdata}; + assign wide.rresp = (s_read_size_q == 3'd4) && (s_read_resp_q != `AXI4_RESP_OKAY) ? + s_read_resp_q : narrow.rresp; + assign wide.rlast = narrow.rlast; + assign wide.ruser = '0; + assign wide.rvalid = (s_read_state_q == Active) && narrow.rvalid && + ((s_read_size_q != 3'd4) || s_read_upper_q); + assign narrow.rready = (s_read_state_q == Active) && + (((s_read_size_q == 3'd4) && !s_read_upper_q) || wide.rready); + assign s_narrow_read_accept = narrow.rvalid && narrow.rready; + assign s_wide_read_accept = wide.rvalid && wide.rready; + + always_comb begin + s_read_state_d = s_read_state_q; + s_read_id_d = s_read_id_q; + s_read_size_d = s_read_size_q; + s_read_addr_d = s_read_addr_q; + s_read_upper_d = s_read_upper_q; + s_read_lower_d = s_read_lower_q; + s_read_resp_d = s_read_resp_q; + + if (s_read_accept) begin + s_read_state_d = Active; + s_read_id_d = wide.arid; + s_read_size_d = wide.arsize; + s_read_addr_d = wide.araddr; + s_read_upper_d = 1'b0; + s_read_resp_d = `AXI4_RESP_OKAY; + end + + if (s_narrow_read_accept && (s_read_size_q == 3'd4)) begin + if (!s_read_upper_q) begin + s_read_lower_d = narrow.rdata; + s_read_resp_d = narrow.rresp; + s_read_upper_d = 1'b1; + end else begin + s_read_upper_d = 1'b0; + s_read_resp_d = `AXI4_RESP_OKAY; + end + end + + if (s_wide_read_accept && narrow.rlast) s_read_state_d = Idle; + + if (clear_i) begin + s_read_state_d = Idle; + s_read_upper_d = 1'b0; + s_read_resp_d = `AXI4_RESP_OKAY; + end + end + + assign wide.awready = (s_write_state_q == Idle) && narrow.awready; + assign narrow.awvalid = (s_write_state_q == Idle) && wide.awvalid; + assign narrow.awid = '0; + assign narrow.awaddr = wide.awaddr; + assign narrow.awlen = (wide.awsize == 3'd4) ? 8'((wide.awlen << 1) | 8'd1) : wide.awlen; + assign narrow.awsize = (wide.awsize == 3'd4) ? 3'd3 : wide.awsize; + assign narrow.awburst = wide.awburst; + assign narrow.awlock = wide.awlock; + assign narrow.awcache = wide.awcache; + assign narrow.awprot = wide.awprot; + assign narrow.awqos = wide.awqos; + assign narrow.awregion = wide.awregion; + assign narrow.awuser = '0; + assign s_write_addr_accept = wide.awvalid && wide.awready; + + assign narrow.wdata = (s_write_size_q == 3'd4) ? + (s_write_upper_q ? wide.wdata[127:64] : wide.wdata[63:0]) : + (s_write_addr_q[3] ? wide.wdata[127:64] : wide.wdata[63:0]); + assign narrow.wstrb = (s_write_size_q == 3'd4) ? + (s_write_upper_q ? wide.wstrb[15:8] : wide.wstrb[7:0]) : + (s_write_addr_q[3] ? wide.wstrb[15:8] : wide.wstrb[7:0]); + assign narrow.wlast = (s_write_size_q != 3'd4) ? wide.wlast : s_write_upper_q && wide.wlast; + assign narrow.wuser = '0; + assign narrow.wvalid = (s_write_state_q == Active) && wide.wvalid; + assign wide.wready = (s_write_state_q == Active) && narrow.wready && + ((s_write_size_q != 3'd4) || s_write_upper_q); + assign s_narrow_write_accept = narrow.wvalid && narrow.wready; + assign s_wide_write_accept = wide.wvalid && wide.wready; + + assign wide.bid = s_write_id_q; + assign wide.bresp = s_b_resp_q; + assign wide.buser = '0; + assign wide.bvalid = s_b_pending_q; + assign narrow.bready = (s_write_state_q == Active) && !s_b_pending_q; + + always_comb begin + s_write_state_d = s_write_state_q; + s_write_id_d = s_write_id_q; + s_write_size_d = s_write_size_q; + s_write_addr_d = s_write_addr_q; + s_write_upper_d = s_write_upper_q; + s_b_pending_d = s_b_pending_q; + s_b_resp_d = s_b_resp_q; + + if (s_write_addr_accept) begin + s_write_state_d = Active; + s_write_id_d = wide.awid; + s_write_size_d = wide.awsize; + s_write_addr_d = wide.awaddr; + s_write_upper_d = 1'b0; + s_b_pending_d = 1'b0; + end + + if (s_narrow_write_accept && (s_write_size_q == 3'd4)) s_write_upper_d = !s_write_upper_q; + + if (narrow.bvalid && narrow.bready) begin + s_b_pending_d = 1'b1; + s_b_resp_d = narrow.bresp; + end + if (wide.bvalid && wide.bready) begin + s_b_pending_d = 1'b0; + s_write_state_d = Idle; + end + + if (clear_i) begin + s_write_state_d = Idle; + s_write_upper_d = 1'b0; + s_b_pending_d = 1'b0; + s_b_resp_d = `AXI4_RESP_OKAY; + end + end + + dffr #( + .DATA_WIDTH(1) + ) u_read_state_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_read_state_d), + .dat_o (s_read_state_bits_q) + ); + + dffr #( + .DATA_WIDTH(1) + ) u_write_state_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_write_state_d), + .dat_o (s_write_state_bits_q) + ); + + dffr #( + .DATA_WIDTH(WideIdWidth) + ) u_read_id_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_read_id_d), + .dat_o (s_read_id_q) + ); + dffr #( + .DATA_WIDTH(WideIdWidth) + ) u_write_id_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_write_id_d), + .dat_o (s_write_id_q) + ); + dffr #( + .DATA_WIDTH(3) + ) u_read_size_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_read_size_d), + .dat_o (s_read_size_q) + ); + dffr #( + .DATA_WIDTH(3) + ) u_write_size_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_write_size_d), + .dat_o (s_write_size_q) + ); + dffr #( + .DATA_WIDTH(32) + ) u_read_addr_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_read_addr_d), + .dat_o (s_read_addr_q) + ); + dffr #( + .DATA_WIDTH(32) + ) u_write_addr_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_write_addr_d), + .dat_o (s_write_addr_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_read_upper_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_read_upper_d), + .dat_o (s_read_upper_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_write_upper_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_write_upper_d), + .dat_o (s_write_upper_q) + ); + dffr #( + .DATA_WIDTH(64) + ) u_read_lower_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_read_lower_d), + .dat_o (s_read_lower_q) + ); + dffr #( + .DATA_WIDTH(2) + ) u_read_resp_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_read_resp_d), + .dat_o (s_read_resp_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_b_pending_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_b_pending_d), + .dat_o (s_b_pending_q) + ); + dffr #( + .DATA_WIDTH(2) + ) u_b_resp_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_b_resp_d), + .dat_o (s_b_resp_q) + ); + +`ifndef SYNTHESIS + property p_wide_read_geometry; + @(posedge clk_i) disable iff (!rst_n_i) wide.arvalid |-> + ((wide.arsize <= 3'd4) && + ((wide.arsize != 3'd4) || + ((wide.arlen <= 8'd15) && (wide.araddr[3:0] == 4'd0) && + ((wide.arburst != `AXI4_BURST_TYPE_WRAP) || (wide.arlen == 8'd3))))); + endproperty + assert property (p_wide_read_geometry); + + property p_wide_write_geometry; + @(posedge clk_i) disable iff (!rst_n_i) wide.awvalid |-> + ((wide.awsize <= 3'd4) && + ((wide.awsize != 3'd4) || + ((wide.awlen <= 8'd15) && (wide.awaddr[3:0] == 4'd0) && + (wide.awburst == `AXI4_BURST_TYPE_INCR)))); + endproperty + assert property (p_wide_write_geometry); +`endif +endmodule diff --git a/rtl/mini/top/axi4_mmio_demux.sv b/rtl/mini/top/axi4_mmio_demux.sv new file mode 100644 index 00000000..ea2551c6 --- /dev/null +++ b/rtl/mini/top/axi4_mmio_demux.sv @@ -0,0 +1,203 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 + +`include "axi4_define.svh" + +// Routes the single OpenC906 64-bit data stream between the HP data fabric +// and the MMIO chain by address window. The upstream master is the +// serializing axi4_downsizer_128to64, so at most one read and one write are +// outstanding at any time; the routing decision is registered at the address +// handshake and held until the response completes. +module axi4_mmio_demux #( + parameter logic [31:0] MmioBase = 32'h0200_0000, + parameter logic [31:0] MmioLimit = 32'h3000_0000 +) ( + input logic clk_i, + input logic rst_n_i, + input logic clear_i, + axi4_if.slave source, + axi4_if.master mem, + axi4_if.master mmio +); + typedef enum logic { + Idle, + Active + } channel_state_e; + + channel_state_e s_read_state_d, s_read_state_q; + channel_state_e s_write_state_d, s_write_state_q; + logic s_read_state_bits_q; + logic s_write_state_bits_q; + logic s_read_sel_d, s_read_sel_q; + logic s_write_sel_d, s_write_sel_q; + logic s_read_route_mmio; + logic s_write_route_mmio; + logic s_read_accept; + logic s_write_accept; + logic s_read_done; + logic s_write_done; + + assign s_read_state_q = channel_state_e'(s_read_state_bits_q); + assign s_write_state_q = channel_state_e'(s_write_state_bits_q); + + assign s_read_route_mmio = (source.araddr >= MmioBase) && (source.araddr < MmioLimit); + assign s_write_route_mmio = (source.awaddr >= MmioBase) && (source.awaddr < MmioLimit); + + assign source.arready = (s_read_state_q == Idle) && + (s_read_route_mmio ? mmio.arready : mem.arready); + assign mem.arvalid = (s_read_state_q == Idle) && !s_read_route_mmio && source.arvalid; + assign mmio.arvalid = (s_read_state_q == Idle) && s_read_route_mmio && source.arvalid; + assign mem.arid = source.arid; + assign mmio.arid = source.arid; + assign mem.araddr = source.araddr; + assign mmio.araddr = source.araddr; + assign mem.arlen = source.arlen; + assign mmio.arlen = source.arlen; + assign mem.arsize = source.arsize; + assign mmio.arsize = source.arsize; + assign mem.arburst = source.arburst; + assign mmio.arburst = source.arburst; + assign mem.arlock = source.arlock; + assign mmio.arlock = source.arlock; + assign mem.arcache = source.arcache; + assign mmio.arcache = source.arcache; + assign mem.arprot = source.arprot; + assign mmio.arprot = source.arprot; + assign mem.arqos = source.arqos; + assign mmio.arqos = source.arqos; + assign mem.arregion = source.arregion; + assign mmio.arregion = source.arregion; + assign mem.aruser = source.aruser; + assign mmio.aruser = source.aruser; + assign s_read_accept = source.arvalid && source.arready; + + assign source.rid = s_read_sel_q ? mmio.rid : mem.rid; + assign source.rdata = s_read_sel_q ? mmio.rdata : mem.rdata; + assign source.rresp = s_read_sel_q ? mmio.rresp : mem.rresp; + assign source.rlast = s_read_sel_q ? mmio.rlast : mem.rlast; + assign source.ruser = s_read_sel_q ? mmio.ruser : mem.ruser; + assign source.rvalid = (s_read_state_q == Active) && (s_read_sel_q ? mmio.rvalid : mem.rvalid); + assign mem.rready = (s_read_state_q == Active) && !s_read_sel_q && source.rready; + assign mmio.rready = (s_read_state_q == Active) && s_read_sel_q && source.rready; + assign s_read_done = source.rvalid && source.rready && source.rlast; + + assign source.awready = (s_write_state_q == Idle) && + (s_write_route_mmio ? mmio.awready : mem.awready); + assign mem.awvalid = (s_write_state_q == Idle) && !s_write_route_mmio && source.awvalid; + assign mmio.awvalid = (s_write_state_q == Idle) && s_write_route_mmio && source.awvalid; + assign mem.awid = source.awid; + assign mmio.awid = source.awid; + assign mem.awaddr = source.awaddr; + assign mmio.awaddr = source.awaddr; + assign mem.awlen = source.awlen; + assign mmio.awlen = source.awlen; + assign mem.awsize = source.awsize; + assign mmio.awsize = source.awsize; + assign mem.awburst = source.awburst; + assign mmio.awburst = source.awburst; + assign mem.awlock = source.awlock; + assign mmio.awlock = source.awlock; + assign mem.awcache = source.awcache; + assign mmio.awcache = source.awcache; + assign mem.awprot = source.awprot; + assign mmio.awprot = source.awprot; + assign mem.awqos = source.awqos; + assign mmio.awqos = source.awqos; + assign mem.awregion = source.awregion; + assign mmio.awregion = source.awregion; + assign mem.awuser = source.awuser; + assign mmio.awuser = source.awuser; + assign s_write_accept = source.awvalid && source.awready; + + // AXI4 has no WID; with a single outstanding write the W channel follows + // the registered address routing until WLAST. + assign mem.wdata = source.wdata; + assign mmio.wdata = source.wdata; + assign mem.wstrb = source.wstrb; + assign mmio.wstrb = source.wstrb; + assign mem.wlast = source.wlast; + assign mmio.wlast = source.wlast; + assign mem.wuser = source.wuser; + assign mmio.wuser = source.wuser; + assign mem.wvalid = (s_write_state_q == Active) && !s_write_sel_q && source.wvalid; + assign mmio.wvalid = (s_write_state_q == Active) && s_write_sel_q && source.wvalid; + assign source.wready = (s_write_state_q == Active) && (s_write_sel_q ? mmio.wready : mem.wready); + + assign source.bid = s_write_sel_q ? mmio.bid : mem.bid; + assign source.bresp = s_write_sel_q ? mmio.bresp : mem.bresp; + assign source.buser = s_write_sel_q ? mmio.buser : mem.buser; + assign source.bvalid = (s_write_state_q == Active) && (s_write_sel_q ? mmio.bvalid : mem.bvalid); + assign mem.bready = (s_write_state_q == Active) && !s_write_sel_q && source.bready; + assign mmio.bready = (s_write_state_q == Active) && s_write_sel_q && source.bready; + assign s_write_done = source.bvalid && source.bready; + + always_comb begin + s_read_state_d = s_read_state_q; + s_read_sel_d = s_read_sel_q; + if (s_read_accept) begin + s_read_state_d = Active; + s_read_sel_d = s_read_route_mmio; + end + if (s_read_done) s_read_state_d = Idle; + if (clear_i) s_read_state_d = Idle; + end + + always_comb begin + s_write_state_d = s_write_state_q; + s_write_sel_d = s_write_sel_q; + if (s_write_accept) begin + s_write_state_d = Active; + s_write_sel_d = s_write_route_mmio; + end + if (s_write_done) s_write_state_d = Idle; + if (clear_i) s_write_state_d = Idle; + end + + dffr #( + .DATA_WIDTH(1) + ) u_read_state_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_read_state_d), + .dat_o (s_read_state_bits_q) + ); + + dffr #( + .DATA_WIDTH(1) + ) u_write_state_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_write_state_d), + .dat_o (s_write_state_bits_q) + ); + + dffr #( + .DATA_WIDTH(1) + ) u_read_sel_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_read_sel_d), + .dat_o (s_read_sel_q) + ); + + dffr #( + .DATA_WIDTH(1) + ) u_write_sel_dffr ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_write_sel_d), + .dat_o (s_write_sel_q) + ); + +`ifndef SYNTHESIS + property p_single_outstanding_read; + @(posedge clk_i) disable iff (!rst_n_i) source.arvalid |-> (s_read_state_q == Idle); + endproperty + assert property (p_single_outstanding_read); + + property p_single_outstanding_write; + @(posedge clk_i) disable iff (!rst_n_i) source.awvalid |-> (s_write_state_q == Idle); + endproperty + assert property (p_single_outstanding_write); +`endif +endmodule diff --git a/rtl/mini/top/hp_core_wrapper.sv b/rtl/mini/top/hp_core_wrapper.sv index 3983279c..f0054d59 100644 --- a/rtl/mini/top/hp_core_wrapper.sv +++ b/rtl/mini/top/hp_core_wrapper.sv @@ -3,167 +3,257 @@ `include "axi4_define.svh" +// OpenC906 HP core integration. +// +// Contract (docs/ip/hp-platform.md): +// - Reset vector 0x38000000 (pad_cpu_rvba), internal CLINT/PLIC window at +// 0x08000000 (pad_cpu_apb_base; 128 MiB aligned, decoded inside the BIU, +// never reaches the external bus). +// - Single 128-bit AXI4 master, downsized to the 64-bit HP fabric and split +// into the data-fabric port and the MMIO port by address window. +// - mhartid reports 1 via the controlled aq_sysio_kid.v override (LP is +// hart 0). SoC interrupt source n drives pad_plic_int_vld[n] and appears +// to software as PLIC ID n+16. +// - The JTAG DTM (tdt_dmi_top) runs on a divide-by-2 sys_apb clock; its +// hartreset request participates in the core reset so debugger resets +// preserve the existing lifecycle semantics. +// - No low-power or DFT support: scan/mbist inputs are tied off and the +// debug SBA AXI master is left unconnected. module hp_core_wrapper ( - // verilog_format: off -- preserve generated-core boundary alignment + // verilog_format: off -- preserve the HP integration boundary alignment input logic clk_i, input logic rst_n_i, input logic core_reset_i, input logic [63:0] time_i, - input logic timer_irq_i, - input logic software_irq_i, - input logic machine_external_irq_i, - input logic supervisor_external_irq_i, + input logic [15:0] plic_src_i, input logic jtag_tck_i, input logic jtag_tms_i, input logic jtag_tdi_i, input logic jtag_trst_n_i, output logic jtag_tdo_o, output logic debug_reset_req_o, - axi4_if.master icache_axi4, - axi4_if.master dcache_axi4, + axi4_if.master mem_axi4, axi4_if.master mmio_axi4 // verilog_format: on ); - logic s_unused_debug_stoptime; + localparam logic [39:0] HpResetVector = 40'h00_3800_0000; + localparam logic [39:0] HpApbBase = 40'h00_0800_0000; - assign icache_axi4.awid = '0; - assign icache_axi4.awaddr = '0; - assign icache_axi4.awlen = '0; - assign icache_axi4.awsize = '0; - assign icache_axi4.awburst = '0; - assign icache_axi4.awlock = '0; - assign icache_axi4.awcache = '0; - assign icache_axi4.awprot = '0; - assign icache_axi4.awqos = '0; - assign icache_axi4.awregion = '0; - assign icache_axi4.awuser = '0; - assign icache_axi4.awvalid = 1'b0; - assign icache_axi4.wdata = '0; - assign icache_axi4.wstrb = '0; - assign icache_axi4.wlast = 1'b0; - assign icache_axi4.wuser = '0; - assign icache_axi4.wvalid = 1'b0; - assign icache_axi4.bready = 1'b1; + logic s_sys_apb_clk; + logic s_sys_apb_rst_b; + logic s_core_rst_b; + logic s_hartreset_n; + logic s_ndmreset_n; + logic s_dtm_tdo; + logic s_dtm_tdo_en; + logic [11:0] s_dmi_paddr; + logic s_dmi_psel; + logic s_dmi_penable; + logic s_dmi_pwrite; + logic [31:0] s_dmi_pwdata; + logic [31:0] s_dmi_prdata; + logic s_dmi_pready; + logic s_dmi_pslverr; + // The C906 drives 40-bit addresses; the Mini HP fabric is 32-bit physical. + logic [39:0] s_c906_araddr; + logic [39:0] s_c906_awaddr; - // verilog_format: off -- generated VexiiRiscv ports are upstream ABI - vexii_riscv_hp_generated u_vexii_riscv_hp_generated ( - .EmbeddedRiscvJtag_logic_jtag_tms (jtag_tms_i), - .EmbeddedRiscvJtag_logic_jtag_tdi (jtag_tdi_i), - .EmbeddedRiscvJtag_logic_jtag_tdo (jtag_tdo_o), - .EmbeddedRiscvJtag_logic_jtag_tck (jtag_tck_i), - .EmbeddedRiscvJtag_logic_ndmreset (debug_reset_req_o), - .LsuL1Axi4Plugin_logic_axi_aw_valid (dcache_axi4.awvalid), - .LsuL1Axi4Plugin_logic_axi_aw_ready (dcache_axi4.awready), - .LsuL1Axi4Plugin_logic_axi_aw_payload_addr (dcache_axi4.awaddr), - .LsuL1Axi4Plugin_logic_axi_aw_payload_id (dcache_axi4.awid), - .LsuL1Axi4Plugin_logic_axi_aw_payload_len (dcache_axi4.awlen), - .LsuL1Axi4Plugin_logic_axi_aw_payload_size (dcache_axi4.awsize), - .LsuL1Axi4Plugin_logic_axi_aw_payload_burst (dcache_axi4.awburst), - .LsuL1Axi4Plugin_logic_axi_aw_payload_cache (dcache_axi4.awcache), - .LsuL1Axi4Plugin_logic_axi_aw_payload_prot (dcache_axi4.awprot), - .LsuL1Axi4Plugin_logic_axi_w_valid (dcache_axi4.wvalid), - .LsuL1Axi4Plugin_logic_axi_w_ready (dcache_axi4.wready), - .LsuL1Axi4Plugin_logic_axi_w_payload_data (dcache_axi4.wdata), - .LsuL1Axi4Plugin_logic_axi_w_payload_strb (dcache_axi4.wstrb), - .LsuL1Axi4Plugin_logic_axi_w_payload_last (dcache_axi4.wlast), - .LsuL1Axi4Plugin_logic_axi_b_valid (dcache_axi4.bvalid), - .LsuL1Axi4Plugin_logic_axi_b_ready (dcache_axi4.bready), - .LsuL1Axi4Plugin_logic_axi_b_payload_id (dcache_axi4.bid), - .LsuL1Axi4Plugin_logic_axi_b_payload_resp (dcache_axi4.bresp), - .LsuL1Axi4Plugin_logic_axi_ar_valid (dcache_axi4.arvalid), - .LsuL1Axi4Plugin_logic_axi_ar_ready (dcache_axi4.arready), - .LsuL1Axi4Plugin_logic_axi_ar_payload_addr (dcache_axi4.araddr), - .LsuL1Axi4Plugin_logic_axi_ar_payload_id (dcache_axi4.arid), - .LsuL1Axi4Plugin_logic_axi_ar_payload_len (dcache_axi4.arlen), - .LsuL1Axi4Plugin_logic_axi_ar_payload_size (dcache_axi4.arsize), - .LsuL1Axi4Plugin_logic_axi_ar_payload_burst (dcache_axi4.arburst), - .LsuL1Axi4Plugin_logic_axi_ar_payload_cache (dcache_axi4.arcache), - .LsuL1Axi4Plugin_logic_axi_ar_payload_prot (dcache_axi4.arprot), - .LsuL1Axi4Plugin_logic_axi_r_valid (dcache_axi4.rvalid), - .LsuL1Axi4Plugin_logic_axi_r_ready (dcache_axi4.rready), - .LsuL1Axi4Plugin_logic_axi_r_payload_data (dcache_axi4.rdata), - .LsuL1Axi4Plugin_logic_axi_r_payload_id (dcache_axi4.rid), - .LsuL1Axi4Plugin_logic_axi_r_payload_resp (dcache_axi4.rresp), - .LsuL1Axi4Plugin_logic_axi_r_payload_last (dcache_axi4.rlast), - .PrivilegedPlugin_logic_rdtime (time_i), - .PrivilegedPlugin_logic_harts_0_int_m_timer (timer_irq_i), - .PrivilegedPlugin_logic_harts_0_int_m_software (software_irq_i), - .PrivilegedPlugin_logic_harts_0_int_m_external (machine_external_irq_i), - .PrivilegedPlugin_logic_harts_0_int_s_external (supervisor_external_irq_i), - .FetchL1Axi4Plugin_logic_axi_ar_valid (icache_axi4.arvalid), - .FetchL1Axi4Plugin_logic_axi_ar_ready (icache_axi4.arready), - .FetchL1Axi4Plugin_logic_axi_ar_payload_addr (icache_axi4.araddr), - .FetchL1Axi4Plugin_logic_axi_ar_payload_id (icache_axi4.arid[0]), - .FetchL1Axi4Plugin_logic_axi_ar_payload_len (icache_axi4.arlen), - .FetchL1Axi4Plugin_logic_axi_ar_payload_size (icache_axi4.arsize), - .FetchL1Axi4Plugin_logic_axi_ar_payload_burst (icache_axi4.arburst), - .FetchL1Axi4Plugin_logic_axi_ar_payload_cache (icache_axi4.arcache), - .FetchL1Axi4Plugin_logic_axi_ar_payload_prot (icache_axi4.arprot), - .FetchL1Axi4Plugin_logic_axi_r_valid (icache_axi4.rvalid), - .FetchL1Axi4Plugin_logic_axi_r_ready (icache_axi4.rready), - .FetchL1Axi4Plugin_logic_axi_r_payload_data (icache_axi4.rdata), - .FetchL1Axi4Plugin_logic_axi_r_payload_id (icache_axi4.rid[0]), - .FetchL1Axi4Plugin_logic_axi_r_payload_resp (icache_axi4.rresp), - .FetchL1Axi4Plugin_logic_axi_r_payload_last (icache_axi4.rlast), - .PrivilegedPlugin_logic_harts_0_debug_stoptime (s_unused_debug_stoptime), - .LsuCachelessAxi4Plugin_logic_axi_aw_valid (mmio_axi4.awvalid), - .LsuCachelessAxi4Plugin_logic_axi_aw_ready (mmio_axi4.awready), - .LsuCachelessAxi4Plugin_logic_axi_aw_payload_addr (mmio_axi4.awaddr), - .LsuCachelessAxi4Plugin_logic_axi_aw_payload_size (mmio_axi4.awsize), - .LsuCachelessAxi4Plugin_logic_axi_aw_payload_cache (mmio_axi4.awcache), - .LsuCachelessAxi4Plugin_logic_axi_aw_payload_prot (mmio_axi4.awprot), - .LsuCachelessAxi4Plugin_logic_axi_w_valid (mmio_axi4.wvalid), - .LsuCachelessAxi4Plugin_logic_axi_w_ready (mmio_axi4.wready), - .LsuCachelessAxi4Plugin_logic_axi_w_payload_data (mmio_axi4.wdata), - .LsuCachelessAxi4Plugin_logic_axi_w_payload_strb (mmio_axi4.wstrb), - .LsuCachelessAxi4Plugin_logic_axi_w_payload_last (mmio_axi4.wlast), - .LsuCachelessAxi4Plugin_logic_axi_b_valid (mmio_axi4.bvalid), - .LsuCachelessAxi4Plugin_logic_axi_b_ready (mmio_axi4.bready), - .LsuCachelessAxi4Plugin_logic_axi_b_payload_resp (mmio_axi4.bresp), - .LsuCachelessAxi4Plugin_logic_axi_ar_valid (mmio_axi4.arvalid), - .LsuCachelessAxi4Plugin_logic_axi_ar_ready (mmio_axi4.arready), - .LsuCachelessAxi4Plugin_logic_axi_ar_payload_addr (mmio_axi4.araddr), - .LsuCachelessAxi4Plugin_logic_axi_ar_payload_size (mmio_axi4.arsize), - .LsuCachelessAxi4Plugin_logic_axi_ar_payload_cache (mmio_axi4.arcache), - .LsuCachelessAxi4Plugin_logic_axi_ar_payload_prot (mmio_axi4.arprot), - .LsuCachelessAxi4Plugin_logic_axi_r_valid (mmio_axi4.rvalid), - .LsuCachelessAxi4Plugin_logic_axi_r_ready (mmio_axi4.rready), - .LsuCachelessAxi4Plugin_logic_axi_r_payload_data (mmio_axi4.rdata), - .LsuCachelessAxi4Plugin_logic_axi_r_payload_resp (mmio_axi4.rresp), - .LsuCachelessAxi4Plugin_logic_axi_r_payload_last (mmio_axi4.rlast), - .clk (clk_i), - .reset (!rst_n_i || core_reset_i), - .EmbeddedRiscvJtag_logic_debug_reset (!jtag_trst_n_i) + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(128), + .ID_WIDTH (8), + .USER_WIDTH(1) + ) u_c906_axi4_if ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(64), + .ID_WIDTH (3), + .USER_WIDTH(1) + ) u_hp_64_axi4_if ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + + // The debug module clock must be slower than the core clock; divide the + // core clock by two (JTAG tck is always slower still). + clk_int_even_div_static #( + .DIV_VALUE_WIDTH(1) + ) u_sys_apb_clk_div ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .clk_o (s_sys_apb_clk) + ); + + // The debug module lives in the JTAG reset domain so that a lifecycle + // reset of the core does not detach the debugger; the DM hartreset + // request joins the core reset exactly like the previous ndmreset path. + assign s_sys_apb_rst_b = rst_n_i && jtag_trst_n_i; + assign s_core_rst_b = rst_n_i && !core_reset_i && s_hartreset_n; + assign debug_reset_req_o = !s_ndmreset_n; + assign jtag_tdo_o = s_dtm_tdo && s_dtm_tdo_en; + + // verilog_format: off -- vendored OpenC906 ports are upstream ABI + openC906 u_openc906 ( + .pll_core_cpuclk (clk_i), + .axim_clk_en (1'b1), + .sys_apb_clk (s_sys_apb_clk), + .sys_apb_rst_b (s_sys_apb_rst_b), + .pad_cpu_rst_b (s_core_rst_b), + .pad_cpu_rvba (HpResetVector), + .pad_cpu_apb_base (HpApbBase), + .pad_cpu_sys_cnt (time_i), + .pad_plic_int_vld ({224'd0, plic_src_i}), + .pad_plic_int_cfg (240'd0), + .biu_pad_araddr (s_c906_araddr), + .biu_pad_arburst (u_c906_axi4_if.arburst), + .biu_pad_arcache (u_c906_axi4_if.arcache), + .biu_pad_arid (u_c906_axi4_if.arid), + .biu_pad_arlen (u_c906_axi4_if.arlen), + .biu_pad_arlock (u_c906_axi4_if.arlock), + .biu_pad_arprot (u_c906_axi4_if.arprot), + .biu_pad_arsize (u_c906_axi4_if.arsize), + .biu_pad_arvalid (u_c906_axi4_if.arvalid), + .biu_pad_awaddr (s_c906_awaddr), + .biu_pad_awburst (u_c906_axi4_if.awburst), + .biu_pad_awcache (u_c906_axi4_if.awcache), + .biu_pad_awid (u_c906_axi4_if.awid), + .biu_pad_awlen (u_c906_axi4_if.awlen), + .biu_pad_awlock (u_c906_axi4_if.awlock), + .biu_pad_awprot (u_c906_axi4_if.awprot), + .biu_pad_awsize (u_c906_axi4_if.awsize), + .biu_pad_awvalid (u_c906_axi4_if.awvalid), + .biu_pad_bready (u_c906_axi4_if.bready), + .biu_pad_rready (u_c906_axi4_if.rready), + .biu_pad_wdata (u_c906_axi4_if.wdata), + .biu_pad_wlast (u_c906_axi4_if.wlast), + .biu_pad_wstrb (u_c906_axi4_if.wstrb), + .biu_pad_wvalid (u_c906_axi4_if.wvalid), + .pad_biu_arready (u_c906_axi4_if.arready), + .pad_biu_awready (u_c906_axi4_if.awready), + .pad_biu_bid (u_c906_axi4_if.bid), + .pad_biu_bresp (u_c906_axi4_if.bresp), + .pad_biu_bvalid (u_c906_axi4_if.bvalid), + .pad_biu_rdata (u_c906_axi4_if.rdata), + .pad_biu_rid (u_c906_axi4_if.rid), + .pad_biu_rlast (u_c906_axi4_if.rlast), + .pad_biu_rresp (u_c906_axi4_if.rresp), + .pad_biu_rvalid (u_c906_axi4_if.rvalid), + .pad_biu_wready (u_c906_axi4_if.wready), + .pad_tdt_dm_arready (1'b0), + .pad_tdt_dm_awready (1'b0), + .pad_tdt_dm_bid (4'd0), + .pad_tdt_dm_bresp (2'd0), + .pad_tdt_dm_bvalid (1'b0), + .pad_tdt_dm_core_unavail(1'b0), + .pad_tdt_dm_rdata (128'd0), + .pad_tdt_dm_rid (4'd0), + .pad_tdt_dm_rlast (1'b0), + .pad_tdt_dm_rresp (2'd0), + .pad_tdt_dm_rvalid (1'b0), + .pad_tdt_dm_wready (1'b0), + .pad_yy_dft_clk_rst_b (rst_n_i), + .pad_yy_icg_scan_en (1'b0), + .pad_yy_mbist_mode (1'b0), + .pad_yy_scan_enable (1'b0), + .pad_yy_scan_mode (1'b0), + .pad_yy_scan_rst_b (1'b1), + .core0_pad_halted (), + .core0_pad_lpmd_b (), + .core0_pad_retire (), + .core0_pad_retire_pc (), + .cpu_debug_port (), + .tdt_dm_pad_araddr (), + .tdt_dm_pad_arburst (), + .tdt_dm_pad_arcache (), + .tdt_dm_pad_arid (), + .tdt_dm_pad_arlen (), + .tdt_dm_pad_arlock (), + .tdt_dm_pad_arprot (), + .tdt_dm_pad_arsize (), + .tdt_dm_pad_arvalid (), + .tdt_dm_pad_awaddr (), + .tdt_dm_pad_awburst (), + .tdt_dm_pad_awcache (), + .tdt_dm_pad_awid (), + .tdt_dm_pad_awlen (), + .tdt_dm_pad_awlock (), + .tdt_dm_pad_awprot (), + .tdt_dm_pad_awsize (), + .tdt_dm_pad_awvalid (), + .tdt_dm_pad_bready (), + .tdt_dm_pad_hartreset_n(s_hartreset_n), + .tdt_dm_pad_ndmreset_n (s_ndmreset_n), + .tdt_dm_pad_rready (), + .tdt_dm_pad_wdata (), + .tdt_dm_pad_wlast (), + .tdt_dm_pad_wstrb (), + .tdt_dm_pad_wvalid (), + .tdt_dmi_paddr (s_dmi_paddr), + .tdt_dmi_penable (s_dmi_penable), + .tdt_dmi_prdata (s_dmi_prdata), + .tdt_dmi_pready (s_dmi_pready), + .tdt_dmi_psel (s_dmi_psel), + .tdt_dmi_pslverr (s_dmi_pslverr), + .tdt_dmi_pwdata (s_dmi_pwdata), + .tdt_dmi_pwrite (s_dmi_pwrite) + ); + + tdt_dmi_top u_tdt_dmi_top ( + .pad_tdt_dtm_jtag2_sel(1'b0), + .pad_tdt_dtm_tap_en (1'b1), + .pad_tdt_dtm_tclk (jtag_tck_i), + .pad_tdt_dtm_tdi (jtag_tdi_i), + .pad_tdt_dtm_tms_i (jtag_tms_i), + .pad_tdt_dtm_trst_b (jtag_trst_n_i), + .pad_tdt_icg_scan_en (1'b0), + .pad_yy_scan_mode (1'b0), + .pad_yy_scan_rst_b (1'b1), + .sys_apb_clk (s_sys_apb_clk), + .sys_apb_rst_b (s_sys_apb_rst_b), + .tdt_dmi_paddr (s_dmi_paddr), + .tdt_dmi_penable (s_dmi_penable), + .tdt_dmi_prdata (s_dmi_prdata), + .tdt_dmi_pready (s_dmi_pready), + .tdt_dmi_psel (s_dmi_psel), + .tdt_dmi_pslverr (s_dmi_pslverr), + .tdt_dmi_pwdata (s_dmi_pwdata), + .tdt_dmi_pwrite (s_dmi_pwrite), + .tdt_dtm_pad_tdo (s_dtm_tdo), + .tdt_dtm_pad_tdo_en (s_dtm_tdo_en), + .tdt_dtm_pad_tms_o (), + .tdt_dtm_pad_tms_oe () ); // verilog_format: on - assign icache_axi4.arid[2:1] = '0; - assign icache_axi4.arlock = 1'b0; - assign icache_axi4.arqos = '0; - assign icache_axi4.arregion = '0; - assign icache_axi4.aruser = '0; - assign dcache_axi4.awlock = 1'b0; - assign dcache_axi4.awqos = '0; - assign dcache_axi4.awregion = '0; - assign dcache_axi4.awuser = '0; - assign dcache_axi4.wuser = '0; - assign dcache_axi4.arlock = 1'b0; - assign dcache_axi4.arqos = '0; - assign dcache_axi4.arregion = '0; - assign dcache_axi4.aruser = '0; - assign mmio_axi4.awid = '0; - assign mmio_axi4.awlen = '0; - assign mmio_axi4.awburst = `AXI4_BURST_TYPE_INCR; - assign mmio_axi4.awlock = 1'b0; - assign mmio_axi4.awqos = '0; - assign mmio_axi4.awregion = '0; - assign mmio_axi4.awuser = '0; - assign mmio_axi4.wuser = '0; - assign mmio_axi4.arid = '0; - assign mmio_axi4.arlen = '0; - assign mmio_axi4.arburst = `AXI4_BURST_TYPE_INCR; - assign mmio_axi4.arlock = 1'b0; - assign mmio_axi4.arqos = '0; - assign mmio_axi4.arregion = '0; - assign mmio_axi4.aruser = '0; + assign u_c906_axi4_if.araddr = s_c906_araddr[31:0]; + assign u_c906_axi4_if.awaddr = s_c906_awaddr[31:0]; + // The C906 BIU has no qos/region/user sidebands; tie the interface fields. + assign u_c906_axi4_if.arqos = '0; + assign u_c906_axi4_if.arregion = '0; + assign u_c906_axi4_if.aruser = '0; + assign u_c906_axi4_if.awqos = '0; + assign u_c906_axi4_if.awregion = '0; + assign u_c906_axi4_if.awuser = '0; + assign u_c906_axi4_if.wuser = '0; + + axi4_downsizer_128to64 u_hp_downsizer ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .clear_i(core_reset_i), + .wide (u_c906_axi4_if), + .narrow (u_hp_64_axi4_if) + ); + + axi4_mmio_demux u_hp_mmio_demux ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .clear_i(core_reset_i), + .source (u_hp_64_axi4_if), + .mem (mem_axi4), + .mmio (mmio_axi4) + ); endmodule diff --git a/rtl/mini/top/hp_subsystem.sv b/rtl/mini/top/hp_subsystem.sv index 11c7083b..ca435e4a 100644 --- a/rtl/mini/top/hp_subsystem.sv +++ b/rtl/mini/top/hp_subsystem.sv @@ -7,38 +7,30 @@ module hp_subsystem ( input logic rst_n_i, input logic core_reset_i, input logic [63:0] time_i, - input logic timer_irq_i, - input logic software_irq_i, - input logic machine_external_irq_i, - input logic supervisor_external_irq_i, + input logic [15:0] plic_src_i, input logic jtag_tck_i, input logic jtag_tms_i, input logic jtag_tdi_i, input logic jtag_trst_n_i, output logic jtag_tdo_o, output logic debug_reset_req_o, - axi4_if.master icache_axi4, - axi4_if.master dcache_axi4, + axi4_if.master mem_axi4, axi4_if.master mmio_axi4 // verilog_format: on ); hp_core_wrapper u_hp_core_wrapper ( - .clk_i (clk_i), - .rst_n_i (rst_n_i), - .core_reset_i (core_reset_i), - .time_i (time_i), - .timer_irq_i (timer_irq_i), - .software_irq_i (software_irq_i), - .machine_external_irq_i (machine_external_irq_i), - .supervisor_external_irq_i(supervisor_external_irq_i), - .jtag_tck_i (jtag_tck_i), - .jtag_tms_i (jtag_tms_i), - .jtag_tdi_i (jtag_tdi_i), - .jtag_trst_n_i (jtag_trst_n_i), - .jtag_tdo_o (jtag_tdo_o), - .debug_reset_req_o (debug_reset_req_o), - .icache_axi4 (icache_axi4), - .dcache_axi4 (dcache_axi4), - .mmio_axi4 (mmio_axi4) + .clk_i (clk_i), + .rst_n_i (rst_n_i), + .core_reset_i (core_reset_i), + .time_i (time_i), + .plic_src_i (plic_src_i), + .jtag_tck_i (jtag_tck_i), + .jtag_tms_i (jtag_tms_i), + .jtag_tdi_i (jtag_tdi_i), + .jtag_trst_n_i (jtag_trst_n_i), + .jtag_tdo_o (jtag_tdo_o), + .debug_reset_req_o(debug_reset_req_o), + .mem_axi4 (mem_axi4), + .mmio_axi4 (mmio_axi4) ); endmodule diff --git a/rtl/mini/top/retrosoc.sv b/rtl/mini/top/retrosoc.sv index fae5a137..42d29978 100644 --- a/rtl/mini/top/retrosoc.sv +++ b/rtl/mini/top/retrosoc.sv @@ -99,9 +99,7 @@ module retrosoc ( axi4_if #(.ADDR_WIDTH(32), .DATA_WIDTH(32), .ID_WIDTH(1), .USER_WIDTH(1)) u_apu_axi4_if (.aclk(clk_pclk_i), .aresetn(rst_pclk_n_i)); axi4_if #(.ADDR_WIDTH(32), .DATA_WIDTH(64), .ID_WIDTH(3), .USER_WIDTH(1)) - u_hp_icache_axi4_if (.aclk(clk_hp_i), .aresetn(rst_hp_n_i)); - axi4_if #(.ADDR_WIDTH(32), .DATA_WIDTH(64), .ID_WIDTH(3), .USER_WIDTH(1)) - u_hp_dcache_axi4_if (.aclk(clk_hp_i), .aresetn(rst_hp_n_i)); + u_hp_mem_axi4_if (.aclk(clk_hp_i), .aresetn(rst_hp_n_i)); axi4_if #(.ADDR_WIDTH(32), .DATA_WIDTH(64), .ID_WIDTH(3), .USER_WIDTH(1)) u_hp_mmio_wide_axi4_if (.aclk(clk_hp_i), .aresetn(rst_hp_n_i)); axi4_if #(.ADDR_WIDTH(32), .DATA_WIDTH(32), .ID_WIDTH(1), .USER_WIDTH(1)) @@ -193,10 +191,7 @@ module retrosoc ( logic s_lp_jtag_tdo; logic s_debug_hp_sel_jtag; logic [63:0] s_hp_time; - logic s_hp_timer_irq; - logic s_hp_software_irq; - logic s_hp_machine_external_irq; - logic s_hp_supervisor_external_irq; + logic [15:0] s_hp_plic_src; logic s_data_plane_idle; logic s_data_plane_flush_busy; logic s_mgmt_router_idle; @@ -449,27 +444,22 @@ module retrosoc ( `ifdef HAVE_HP hp_subsystem u_hp_subsystem ( - .clk_i (clk_hp_core_i), - .rst_n_i (rst_hp_n_i), - .core_reset_i (!s_hp_lifecycle_release_hp), - .time_i (s_hp_time), - .timer_irq_i (s_hp_timer_irq), - .software_irq_i (s_hp_software_irq), - .machine_external_irq_i (s_hp_machine_external_irq), - .supervisor_external_irq_i(s_hp_supervisor_external_irq), - .jtag_tck_i (jtag_tck_i), - .jtag_tms_i (s_debug_hp_sel_jtag ? jtag_tms_i : 1'b1), - .jtag_tdi_i (s_debug_hp_sel_jtag ? jtag_tdi_i : 1'b0), - .jtag_trst_n_i (jtag_trst_n_i), - .jtag_tdo_o (s_hp_jtag_tdo), - .debug_reset_req_o (s_hp_debug_reset_req), - .icache_axi4 (u_hp_icache_axi4_if), - .dcache_axi4 (u_hp_dcache_axi4_if), - .mmio_axi4 (u_hp_mmio_wide_axi4_if) + .clk_i (clk_hp_core_i), + .rst_n_i (rst_hp_n_i), + .core_reset_i (!s_hp_lifecycle_release_hp), + .time_i (s_hp_time), + .plic_src_i (s_hp_plic_src), + .jtag_tck_i (jtag_tck_i), + .jtag_tms_i (s_debug_hp_sel_jtag ? jtag_tms_i : 1'b1), + .jtag_tdi_i (s_debug_hp_sel_jtag ? jtag_tdi_i : 1'b0), + .jtag_trst_n_i (jtag_trst_n_i), + .jtag_tdo_o (s_hp_jtag_tdo), + .debug_reset_req_o(s_hp_debug_reset_req), + .mem_axi4 (u_hp_mem_axi4_if), + .mmio_axi4 (u_hp_mmio_wide_axi4_if) ); `else - axi4_master_idle u_hp_icache_idle (.axi4(u_hp_icache_axi4_if)); - axi4_master_idle u_hp_dcache_idle (.axi4(u_hp_dcache_axi4_if)); + axi4_master_idle u_hp_mem_idle (.axi4(u_hp_mem_axi4_if)); axi4_master_idle u_hp_mmio_idle (.axi4(u_hp_mmio_wide_axi4_if)); assign s_hp_jtag_tdo = 1'b0; assign s_hp_debug_reset_req = 1'b0; @@ -613,8 +603,7 @@ module retrosoc ( .ext_h_read_limit_i (s_ext_h_read_limit), .ext_h_write_base_i (s_ext_h_write_base), .ext_h_write_limit_i (s_ext_h_write_limit), - .hp_icache_axi4 (u_hp_icache_axi4_if), - .hp_dcache_axi4 (u_hp_dcache_axi4_if), + .hp_mem_axi4 (u_hp_mem_axi4_if), .dma_axi4 (u_dma_axi4_if), .sdio0_axi4 (u_sdio0_axi4_if), .sdio1_axi4 (u_sdio1_axi4_if), @@ -872,96 +861,93 @@ module retrosoc ( apb4_periph #( .EnableP7(ApuEnableP7) ) u_apb4_periph ( - .clk_i (clk_pclk_i), - .rst_n_i (rst_pclk_n_i), - .clk_aud_i (clk_aud_i), - .rst_aud_n_i (rst_aud_n_i), - .clk_ulpi_i (clk_ulpi_i), - .clk_mem_i (clk_mem_i), - .rst_mem_n_i (rst_mem_n_i), - .clk_hp_i (clk_hp_i), - .rst_hp_n_i (rst_hp_n_i), - .debug_halted_i (s_mgmt_debug_halted), - .timebase_tick_i (timebase_tick_i), - .ext_h_hp_irq_i ((s_ext_h_owner == 2'd1) ? s_ext_h_irq_raw : 1'b0), - .resource_irq_lp_i (s_resource_irq_lp), - .resource_irq_hp_i (s_resource_irq_hp), - .apu_owner_i (s_resource_owner[7]), - .apu_owner_lock_i (s_resource_owner_lock[7]), - .apu_quiesce_i (s_resource_quiesce[7]), - .apu_reset_i (s_resource_reset[7]), - .apu_bridge_epoch_i (s_apu_bridge_epoch), - .jpeg_quiesce_i (s_resource_quiesce[6]), - .jpeg_reset_i (s_resource_reset[6]), - .ga2d_quiesce_i (s_resource_quiesce[8]), - .ga2d_reset_i (s_resource_reset[8]), - .ga2d_source_stop_i (s_ga2d_source_stop), - .ga2d_source_safe_idle_i (s_ga2d_source_safe_idle), - .ga2d_block_ack_i (s_resource_block_ack_pclk[8]), - .ga2d_bridge_clear_busy_i (s_ga2d_bridge_clear_busy), - .ga2d_bridge_epoch_i (s_ga2d_bridge_epoch), - .ga2d_data_ready_i (s_ga2d_data_ready), - .npu_owner_i (s_resource_owner[9]), - .npu_owner_lock_i (s_resource_owner_lock[9]), - .npu_quiesce_i (s_resource_quiesce[9]), - .npu_reset_i (s_resource_reset[9]), - .npu_hp_block_new_i (s_hp_block_hp), - .npu_hp_flush_i (s_hp_flush_hp), - .mem_pad_mode_i (s_mem_pad_mode_lp), - .cfg_axi4 (u_cfg_pclk_axi4_if), - .dma_axi4 (u_dma_axi4_if), - .sdio0_axi4 (u_sdio0_axi4_if), - .sdio1_axi4 (u_sdio1_axi4_if), - .usb2_axi4 (u_usb2_axi4_if), - .apu_axi4 (u_apu_axi4_if), - .jpeg_axi4 (u_jpeg_wide_axi4_if), - .ga2d_axi4 (u_ga2d_wide_axi4_if), - .npu_axi4 (u_npu_wide_axi4_if), - .psram_axi4 (u_data_qpi_axi4_if), - .xpi_axi4 (u_data_xpi_axi4_if), - .spisd_axi4 (u_spisd_axi4_if), - .opipsram_axi4 (u_data_opi_axi4_if), - .gpio (u_gpio_if), - .user_gpio (u_user_gpio_if), - .uart (u_uart0_if), - .uart1 (u_uart1_if), - .psram (u_psram_raw_if), - .spisd (u_spisd_if), - .i2c0 (u_i2c0_if), - .i2s (u_i2s_if), - .ws2812 (u_ws2812_if), - .xpi (xpi), - .sysctrl (u_sysctrl_if), - .pll_ctrl (pll_ctrl), - .clock_ctrl (clock_ctrl), - .sdram_cfg (u_sdram_cfg_pclk_if), - .sram_cfg (u_sram_cfg_pclk_if), - .dvp (u_dvp_if), - .sdio0 (u_sdio0_if), - .sdio1 (sdio1), - .usb2 (usb2), - .opipsram (u_opipsram_raw_if), - .i2c1 (u_i2c1_if), - .fault_valid_i (s_data_plane_fault_valid_pclk || s_bus_fault_valid), - .fault_addr_i (s_fault_addr_mux), - .fault_wstrb_i (s_fault_wstrb_mux), - .fault_reserved_i (s_fault_reserved_mux), - .hp_time_o (s_hp_time), - .hp_timer_irq_o (s_hp_timer_irq), - .hp_software_irq_o (s_hp_software_irq), - .hp_machine_external_irq_o (s_hp_machine_external_irq), - .hp_supervisor_external_irq_o(s_hp_supervisor_external_irq), - .resource_irq_raw_o (s_resource_irq_raw), - .apu_idle_o (s_apu_idle), - .jpeg_idle_o (s_jpeg_idle), - .ga2d_idle_o (s_ga2d_idle), - .ga2d_core_safe_idle_o (s_ga2d_core_safe_idle), - .npu_idle_o (s_npu_idle), - .npu_block_ack_o (s_npu_block_ack), - .npu_hp_pause_ack_o (s_npu_hp_pause_ack), - .npu_hp_flush_busy_o (s_npu_hp_flush_busy), - .npu_hp_idle_o (s_npu_hp_idle), - .irq_o (s_apb4_periph_irq) + .clk_i (clk_pclk_i), + .rst_n_i (rst_pclk_n_i), + .clk_aud_i (clk_aud_i), + .rst_aud_n_i (rst_aud_n_i), + .clk_ulpi_i (clk_ulpi_i), + .clk_mem_i (clk_mem_i), + .rst_mem_n_i (rst_mem_n_i), + .clk_hp_i (clk_hp_i), + .rst_hp_n_i (rst_hp_n_i), + .debug_halted_i (s_mgmt_debug_halted), + .timebase_tick_i (timebase_tick_i), + .ext_h_hp_irq_i ((s_ext_h_owner == 2'd1) ? s_ext_h_irq_raw : 1'b0), + .resource_irq_lp_i (s_resource_irq_lp), + .resource_irq_hp_i (s_resource_irq_hp), + .apu_owner_i (s_resource_owner[7]), + .apu_owner_lock_i (s_resource_owner_lock[7]), + .apu_quiesce_i (s_resource_quiesce[7]), + .apu_reset_i (s_resource_reset[7]), + .apu_bridge_epoch_i (s_apu_bridge_epoch), + .jpeg_quiesce_i (s_resource_quiesce[6]), + .jpeg_reset_i (s_resource_reset[6]), + .ga2d_quiesce_i (s_resource_quiesce[8]), + .ga2d_reset_i (s_resource_reset[8]), + .ga2d_source_stop_i (s_ga2d_source_stop), + .ga2d_source_safe_idle_i (s_ga2d_source_safe_idle), + .ga2d_block_ack_i (s_resource_block_ack_pclk[8]), + .ga2d_bridge_clear_busy_i(s_ga2d_bridge_clear_busy), + .ga2d_bridge_epoch_i (s_ga2d_bridge_epoch), + .ga2d_data_ready_i (s_ga2d_data_ready), + .npu_owner_i (s_resource_owner[9]), + .npu_owner_lock_i (s_resource_owner_lock[9]), + .npu_quiesce_i (s_resource_quiesce[9]), + .npu_reset_i (s_resource_reset[9]), + .npu_hp_block_new_i (s_hp_block_hp), + .npu_hp_flush_i (s_hp_flush_hp), + .mem_pad_mode_i (s_mem_pad_mode_lp), + .cfg_axi4 (u_cfg_pclk_axi4_if), + .dma_axi4 (u_dma_axi4_if), + .sdio0_axi4 (u_sdio0_axi4_if), + .sdio1_axi4 (u_sdio1_axi4_if), + .usb2_axi4 (u_usb2_axi4_if), + .apu_axi4 (u_apu_axi4_if), + .jpeg_axi4 (u_jpeg_wide_axi4_if), + .ga2d_axi4 (u_ga2d_wide_axi4_if), + .npu_axi4 (u_npu_wide_axi4_if), + .psram_axi4 (u_data_qpi_axi4_if), + .xpi_axi4 (u_data_xpi_axi4_if), + .spisd_axi4 (u_spisd_axi4_if), + .opipsram_axi4 (u_data_opi_axi4_if), + .gpio (u_gpio_if), + .user_gpio (u_user_gpio_if), + .uart (u_uart0_if), + .uart1 (u_uart1_if), + .psram (u_psram_raw_if), + .spisd (u_spisd_if), + .i2c0 (u_i2c0_if), + .i2s (u_i2s_if), + .ws2812 (u_ws2812_if), + .xpi (xpi), + .sysctrl (u_sysctrl_if), + .pll_ctrl (pll_ctrl), + .clock_ctrl (clock_ctrl), + .sdram_cfg (u_sdram_cfg_pclk_if), + .sram_cfg (u_sram_cfg_pclk_if), + .dvp (u_dvp_if), + .sdio0 (u_sdio0_if), + .sdio1 (sdio1), + .usb2 (usb2), + .opipsram (u_opipsram_raw_if), + .i2c1 (u_i2c1_if), + .fault_valid_i (s_data_plane_fault_valid_pclk || s_bus_fault_valid), + .fault_addr_i (s_fault_addr_mux), + .fault_wstrb_i (s_fault_wstrb_mux), + .fault_reserved_i (s_fault_reserved_mux), + .hp_time_o (s_hp_time), + .hp_plic_src_o (s_hp_plic_src), + .resource_irq_raw_o (s_resource_irq_raw), + .apu_idle_o (s_apu_idle), + .jpeg_idle_o (s_jpeg_idle), + .ga2d_idle_o (s_ga2d_idle), + .ga2d_core_safe_idle_o (s_ga2d_core_safe_idle), + .npu_idle_o (s_npu_idle), + .npu_block_ack_o (s_npu_block_ack), + .npu_hp_pause_ack_o (s_npu_hp_pause_ack), + .npu_hp_flush_busy_o (s_npu_hp_flush_busy), + .npu_hp_idle_o (s_npu_hp_idle), + .irq_o (s_apb4_periph_irq) ); axi4_sdram u_axi4_sdram ( diff --git a/rtl/mini/top/soc_data_plane.sv b/rtl/mini/top/soc_data_plane.sv index 0e1bf21b..e0bf9f2f 100644 --- a/rtl/mini/top/soc_data_plane.sv +++ b/rtl/mini/top/soc_data_plane.sv @@ -23,8 +23,7 @@ module soc_data_plane ( input logic [31:0] ext_h_read_limit_i, input logic [31:0] ext_h_write_base_i, input logic [31:0] ext_h_write_limit_i, - axi4_if.slave hp_icache_axi4, - axi4_if.slave hp_dcache_axi4, + axi4_if.slave hp_mem_axi4, axi4_if.slave dma_axi4, axi4_if.slave sdio0_axi4, axi4_if.slave sdio1_axi4, @@ -206,16 +205,7 @@ module soc_data_plane ( .DATA_WIDTH(64), .ID_WIDTH (7), .USER_WIDTH(1) - ) u_hp_icache_prefixed_axi4 ( - .aclk (clk_hp_i), - .aresetn(rst_hp_n_i) - ); - axi4_if #( - .ADDR_WIDTH(32), - .DATA_WIDTH(64), - .ID_WIDTH (7), - .USER_WIDTH(1) - ) u_hp_dcache_prefixed_axi4 ( + ) u_hp_mem_prefixed_axi4 ( .aclk (clk_hp_i), .aresetn(rst_hp_n_i) ); @@ -506,24 +496,17 @@ module soc_data_plane ( axi4_id_prefix #( .MasterIndex(4'd0) - ) u_hp_icache_prefix ( - .source(hp_icache_axi4), - .sink (u_hp_icache_prefixed_axi4) + ) u_hp_mem_prefix ( + .source(hp_mem_axi4), + .sink (u_hp_mem_prefixed_axi4) ); - axi4_connector u_hp_icache_connector ( - .source(u_hp_icache_prefixed_axi4), + axi4_connector u_hp_mem_connector ( + .source(u_hp_mem_prefixed_axi4), .sink (u_master_axi4[0]) ); - axi4_id_prefix #( - .MasterIndex(4'd1) - ) u_hp_dcache_prefix ( - .source(hp_dcache_axi4), - .sink (u_hp_dcache_prefixed_axi4) - ); - axi4_connector u_hp_dcache_connector ( - .source(u_hp_dcache_prefixed_axi4), - .sink (u_master_axi4[1]) - ); + // The retired split instruction/data HP ports collapsed into hp_mem_axi4; + // crossbar master slot 1 is kept idle to preserve the ID-prefix map. + axi4_master_idle u_hp_retired_idle (.axi4(u_master_axi4[1])); axi4_connector u_dma_source_connector ( .source(dma_axi4), diff --git a/rtl/rtl_style_audit.json b/rtl/rtl_style_audit.json index ad5f310d..1dc7ba28 100644 --- a/rtl/rtl_style_audit.json +++ b/rtl/rtl_style_audit.json @@ -381,11 +381,13 @@ "axi4_async_bridge.sv", "axi4_bus.sv", "axi4_data_crossbar.sv", + "axi4_downsizer_128to64.sv", "axi4_downsizer_64to32.sv", "axi4_id_prefix.sv", "axi4_interconnect.sv", "axi4_master_idle.sv", "axi4_mgmt_router.sv", + "axi4_mmio_demux.sv", "axi4_target_guard.sv", "axi4_upsizer_32to64.sv", "axi4_word_bridge.sv", diff --git a/scripts/README.md b/scripts/README.md index 16e73a1d..44b9e027 100644 --- a/scripts/README.md +++ b/scripts/README.md @@ -126,8 +126,9 @@ SRAM CoreMark quick report into `meta/coremark.json`; it requires one valid than replace, the common `SIM_TEST_PASS` simulation verdict. `generate_vexiiriscv.py` verifies the locked VexiiRiscv revision, rejects local -source changes before and after generation, and generates the fixed HP core -below `build/`; generated RTL is never tracked. +source changes before and after generation, and generates the fixed Std-series +core (preserved from the retired Mini HP configuration) below `build/`; generated +RTL is never tracked. `setup_hp_linux.py` installs the locked OpenSBI, Linux, and Buildroot revisions and can resume a checkout left without `HEAD` by an interrupted fetch. `build_hp_linux.py` builds the RV64 `lp64d` userspace/OpenSBI image set with the repo-owned diff --git a/scripts/build_hp_apu.py b/scripts/build_hp_apu.py index afc87d05..fa6dda0e 100644 --- a/scripts/build_hp_apu.py +++ b/scripts/build_hp_apu.py @@ -25,7 +25,7 @@ def build(args: argparse.Namespace) -> None: subprocess.run( [ compiler, - "-march=rv64imafdc_zicbom_zicsr_zifencei", + "-march=rv64imafdc_zicsr_zifencei", "-mabi=lp64d", "-nostdlib", "-nostartfiles", diff --git a/scripts/build_hp_linux.py b/scripts/build_hp_linux.py index 0d3fd5ce..df6b0d78 100644 --- a/scripts/build_hp_linux.py +++ b/scripts/build_hp_linux.py @@ -250,7 +250,7 @@ def build(args: argparse.Namespace) -> None: f"PLATFORM_DIR={external / 'opensbi'}", "PLATFORM_RISCV_XLEN=64", "PLATFORM_RISCV_ABI=lp64d", - "PLATFORM_RISCV_ISA=rv64imafdc_zicbom_zicsr_zifencei", + "PLATFORM_RISCV_ISA=rv64imafdc_zicsr_zifencei", "FW_TEXT_START=0x38000000", "FW_JUMP=y", "FW_JUMP_ADDR=0x38400000", diff --git a/scripts/build_hp_smoke.py b/scripts/build_hp_smoke.py index 68500422..e9768df4 100644 --- a/scripts/build_hp_smoke.py +++ b/scripts/build_hp_smoke.py @@ -22,7 +22,7 @@ def build(args: argparse.Namespace) -> None: objcopy = f"{args.cross}objcopy" command = [ compiler, - "-march=rv64imafdc_zicbom_zicsr_zifencei", + "-march=rv64imafdc_zicsr_zifencei", "-mabi=lp64d", "-nostdlib", "-nostartfiles", diff --git a/scripts/check_format.py b/scripts/check_format.py index bd85ce7a..08c7582f 100644 --- a/scripts/check_format.py +++ b/scripts/check_format.py @@ -21,6 +21,10 @@ SELF_OWNED_RTL_ROOTS = { ("rtl", "tech"), ("tests", "rtl"), } +# Vendored upstream sources carried with a reviewed patch (e.g. the OpenC906 +# hart-ID override) keep upstream formatting so they stay diffable against +# the locked revision. +VENDORED_RTL_DIRS = ("ip_overrides",) def tracked_files(root: Path) -> list[Path]: @@ -41,7 +45,9 @@ def format_files(paths: Iterable[Path], kind: str) -> list[Path]: return sorted( path for path in paths - if path.suffix in RTL_SUFFIXES and tuple(path.parts[:2]) in SELF_OWNED_RTL_ROOTS + if path.suffix in RTL_SUFFIXES + and tuple(path.parts[:2]) in SELF_OWNED_RTL_ROOTS + and not any(part in VENDORED_RTL_DIRS for part in path.parts) ) raise ValueError(f"unknown format kind: {kind}") diff --git a/scripts/generate_openc906.py b/scripts/generate_openc906.py new file mode 100644 index 00000000..a3bd7af7 --- /dev/null +++ b/scripts/generate_openc906.py @@ -0,0 +1,174 @@ +#!/usr/bin/env python3 +"""Emit the Mini HP OpenC906 filelist from the locked vendored source. + +The OpenC906 repository ships pre-generated Verilog below +``C906_RTL_FACTORY/gen_rtl`` together with upstream filelists that use a +``${CODE_BASE_PATH}`` placeholder and mix compilation-unit macro headers with +sources. This script resolves the placeholder to the locked checkout and +substitutes the reviewed retroSoC overrides from ``rtl/mini/ip_overrides/`` +for their vendored counterparts: + +- ``aq_sysio_kid.v``: upstream hardwires mhartid to 0; the Mini LP/HP + contract requires the HP core to report hart 1. +- ``sysmap.h``: the upstream default region table marks the Mini peripheral + window cacheable/bufferable; the override maps the Mini address map with + the MMIO window (including the core-internal CLINT/PLIC window) as + strong-order non-cacheable, as the OpenC906 user manual requires. + +All sources are concatenated into a single compilation unit +(``openc906_combined.v``) because gen_rtl relies on header macros being +visible in every source; one file preserves that semantics for tools with +per-file compilation units (slang/Yosys) and is equivalent for +Verilator/Icarus/VCS. The vendored checkout itself is never modified. +""" + +from __future__ import annotations + +import argparse +import hashlib +import json +import subprocess +from pathlib import Path +from typing import Any + + +GENERATED_MODULE = "openC906" +UPSTREAM_FILELISTS = ( + "C906_RTL_FACTORY/gen_rtl/filelists/C906_asic_rtl.fl", + "C906_RTL_FACTORY/gen_rtl/filelists/tdt_dmi_top_rtl.fl", +) +# vendored relpath -> (override relpath below rtl/mini/ip_overrides/, sha256 of +# the vendored file at the locked revision). The sha256 pins force a review of +# the override whenever the locked OpenC906 revision moves. +OVERRIDE_DIR = Path("rtl/mini/ip_overrides") +OVERRIDES = { + "C906_RTL_FACTORY/gen_rtl/cpu/rtl/aq_sysio_kid.v": ( + "aq_sysio_kid.v", + "afb4d8da4c9fb01edf9286c69111c9799ccf0cc66c339dadad1705efdd35dd8c", + ), + "C906_RTL_FACTORY/gen_rtl/mmu/rtl/sysmap.h": ( + "sysmap.h", + "0389089a42ef762768e57bbb4fdcbe6b95f33ab650b5bacc0de8122e0d8711d5", + ), +} + + +def run(command: list[str], cwd: Path) -> str: + result = subprocess.run(command, cwd=cwd, check=True, capture_output=True, text=True) + return result.stdout.strip() + + +def sha256(path: Path) -> str: + digest = hashlib.sha256() + with path.open("rb") as source: + for chunk in iter(lambda: source.read(1024 * 1024), b""): + digest.update(chunk) + return digest.hexdigest() + + +def locked_revision(lock_path: Path) -> str: + document: dict[str, Any] = json.loads(lock_path.read_text(encoding="utf-8")) + source = document.get("sources", {}).get("openc906") + if not isinstance(source, dict) or not isinstance(source.get("revision"), str): + raise ValueError("dependency lock has no openc906 source revision") + return source["revision"] + + +def validate_locked_source(source: Path, expected: str) -> str: + actual = run(["git", "rev-parse", "HEAD"], source) + if actual != expected: + raise ValueError(f"OpenC906 revision mismatch: expected {expected}, found {actual}") + status = run(["git", "status", "--short"], source) + if status: + raise ValueError("OpenC906 source has local changes:\n" + status) + return actual + + +def collect_sources(root: Path, source: Path) -> tuple[list[Path], dict[str, str]]: + """Resolve upstream filelists to absolute source paths with overrides.""" + files: list[Path] = [] + used: dict[str, str] = {} + for filelist in UPSTREAM_FILELISTS: + for line in (source / filelist).read_text(encoding="utf-8").splitlines(): + entry = line.strip() + if not entry or entry.startswith("#"): + continue + resolved = Path(entry.replace("${CODE_BASE_PATH}", str(source / "C906_RTL_FACTORY"))) + if not resolved.is_file(): + raise FileNotFoundError(f"upstream filelist entry not found: {resolved}") + if resolved.suffix != ".h" and resolved.suffix != ".v": + raise ValueError(f"unexpected upstream filelist entry kind: {resolved}") + relative = resolved.relative_to(source).as_posix() + if relative in OVERRIDES: + override_name, expected_sha256 = OVERRIDES[relative] + if sha256(resolved) != expected_sha256: + raise ValueError( + f"vendored {Path(relative).name} digest changed; re-review the " + "override before updating OVERRIDES" + ) + resolved = (root / OVERRIDE_DIR / override_name).resolve() + if not resolved.is_file(): + raise FileNotFoundError(f"override not found: {resolved}") + used[relative] = override_name + files.append(resolved) + missing = set(OVERRIDES) - set(used) + if missing: + raise ValueError(f"override target(s) not present in upstream filelists: {missing}") + return files, used + + +def generate(args: argparse.Namespace) -> None: + root = args.root.resolve() + source = args.source.resolve() + output = args.output.resolve() + expected = locked_revision(args.lock.resolve()) + actual = validate_locked_source(source, expected) + + files, used = collect_sources(root, source) + output.mkdir(parents=True, exist_ok=True) + + combined = output / "openc906_combined.v" + chunks = [ + "// retroSoC build-time concatenation of the locked OpenC906 RTL.\n", + "// Do not edit; regenerate with `make openc906-prepare`.\n", + ] + for path in files: + chunks.append(f"\n// ---- begin: {path.name} ----\n") + chunks.append(path.read_text(encoding="utf-8")) + chunks.append("\n") + combined.write_text("".join(chunks), encoding="utf-8") + (output / "openc906.fl").write_text(str(combined) + "\n", encoding="utf-8") + + manifest = { + "schema_version": 1, + "module": GENERATED_MODULE, + "configuration": "openc906_default_rv64gc", + "openc906_revision": actual, + "source_status": [], + "overrides": { + target: { + "override": str(OVERRIDE_DIR / override_name), + "expected_upstream_sha256": OVERRIDES[target][1], + } + for target, override_name in sorted(used.items()) + }, + "file_count": len(files), + } + args.manifest.resolve().parent.mkdir(parents=True, exist_ok=True) + args.manifest.resolve().write_text( + json.dumps(manifest, indent=2, sort_keys=True) + "\n", encoding="utf-8" + ) + + +def main() -> None: + parser = argparse.ArgumentParser() + parser.add_argument("--root", type=Path, required=True) + parser.add_argument("--source", type=Path, required=True) + parser.add_argument("--output", type=Path, required=True) + parser.add_argument("--manifest", type=Path, required=True) + parser.add_argument("--lock", type=Path, required=True) + generate(parser.parse_args()) + + +if __name__ == "__main__": + main() diff --git a/scripts/generate_vexiiriscv.py b/scripts/generate_vexiiriscv.py index 7be7fe66..c1f7641a 100644 --- a/scripts/generate_vexiiriscv.py +++ b/scripts/generate_vexiiriscv.py @@ -1,5 +1,9 @@ #!/usr/bin/env python3 -"""Generate the locked VexiiRiscv HP core below the selected build variant.""" +"""Generate the locked VexiiRiscv Std-series core below the selected build variant. + +The generator is a Std-series asset preserved from the retired Mini HP +configuration; Mini no longer consumes it. +""" from __future__ import annotations @@ -12,8 +16,8 @@ from pathlib import Path from typing import Any -GENERATOR_CLASS = "vexiiriscv.GenerateRetroSocHp" -GENERATED_MODULE = "vexii_riscv_hp_generated" +GENERATOR_CLASS = "vexiiriscv.GenerateRetroSocStd" +GENERATED_MODULE = "vexiiriscv_std_generated" def run(command: list[str], cwd: Path) -> str: @@ -86,7 +90,7 @@ def generate(args: argparse.Namespace) -> None: environment["COURSIER_CACHE"] = str(sbt_cache / "coursier") subprocess.run(command, cwd=source, check=True, env=environment) - generated = output / "vexii_riscv_hp_generated.v" + generated = output / "vexiiriscv_std_generated.v" if not generated.is_file(): raise FileNotFoundError(f"VexiiRiscv generator did not create {generated}") validate_locked_source(source, expected) @@ -95,6 +99,7 @@ def generate(args: argparse.Namespace) -> None: manifest = { "schema_version": 1, "module": GENERATED_MODULE, + "product": "std", "configuration": "rv64imafdc_zicbom_max", "xlen": 64, "physical_address_width": 32, @@ -102,7 +107,7 @@ def generate(args: argparse.Namespace) -> None: "vexiiriscv_revision": actual, "source_status": [], "submodules": submodules, - "generator": str((scala_dir / "GenerateRetroSocHp.scala").relative_to(root)), + "generator": str((scala_dir / "GenerateRetroSocStd.scala").relative_to(root)), "files": {generated.name: sha256(generated)}, } args.manifest.resolve().parent.mkdir(parents=True, exist_ok=True) diff --git a/scripts/npu_compiler.py b/scripts/npu_compiler.py index 1bf7e947..6937eae5 100644 --- a/scripts/npu_compiler.py +++ b/scripts/npu_compiler.py @@ -287,6 +287,14 @@ static void rs_{prefix}_cache_clean(const void *pointer, uint32_t bytes) {{ uintptr_t cursor = (uintptr_t)pointer & ~(uintptr_t)UINT32_C(63); uintptr_t end = ((uintptr_t)pointer + bytes + UINT32_C(63)) & ~(uintptr_t)UINT32_C(63); while (cursor < end) {{ __asm__ volatile("cbo.clean 0(%0)" :: "r"(cursor) : "memory"); cursor += 64U; }} +#elif defined(__riscv) + /* OpenC906 (T-Head C906): custom-0 dcache.cva, 0x0250000b | rs1<<15 */ + uintptr_t cursor = (uintptr_t)pointer & ~(uintptr_t)UINT32_C(63); + uintptr_t end = ((uintptr_t)pointer + bytes + UINT32_C(63)) & ~(uintptr_t)UINT32_C(63); + while (cursor < end) {{ + __asm__ volatile(".insn r 0x0b, 0x0, 0x01, x0, %0, x5" :: "r"(cursor) : "memory"); + cursor += 64U; + }} #else (void)pointer; (void)bytes; #endif @@ -297,6 +305,14 @@ static void rs_{prefix}_cache_invalidate(const void *pointer, uint32_t bytes) {{ uintptr_t cursor = (uintptr_t)pointer & ~(uintptr_t)UINT32_C(63); uintptr_t end = ((uintptr_t)pointer + bytes + UINT32_C(63)) & ~(uintptr_t)UINT32_C(63); while (cursor < end) {{ __asm__ volatile("cbo.inval 0(%0)" :: "r"(cursor) : "memory"); cursor += 64U; }} +#elif defined(__riscv) + /* OpenC906 (T-Head C906): custom-0 dcache.iva, 0x0260000b | rs1<<15 */ + uintptr_t cursor = (uintptr_t)pointer & ~(uintptr_t)UINT32_C(63); + uintptr_t end = ((uintptr_t)pointer + bytes + UINT32_C(63)) & ~(uintptr_t)UINT32_C(63); + while (cursor < end) {{ + __asm__ volatile(".insn r 0x0b, 0x0, 0x01, x0, %0, x6" :: "r"(cursor) : "memory"); + cursor += 64U; + }} #else (void)pointer; (void)bytes; #endif diff --git a/scripts/run_npu_p6_verilator.py b/scripts/run_npu_p6_verilator.py index 9dfda92a..d1336810 100644 --- a/scripts/run_npu_p6_verilator.py +++ b/scripts/run_npu_p6_verilator.py @@ -111,7 +111,7 @@ def build_variants(timestamp: str, log_dir: Path) -> dict[str, Path]: def qualification_configuration(variants: dict[str, Path]) -> dict[str, object]: - selected = ("MINI_MODE", "APP", "SIMU", "HP_CONFIG", "EXT_CLK_HZ") + selected = ("MINI_MODE", "APP", "SIMU", "EXT_CLK_HZ") configurations: dict[str, dict[str, str]] = {} for workload, variant in variants.items(): manifest = json.loads((variant / "meta/manifest.json").read_text(encoding="utf-8")) @@ -128,7 +128,6 @@ def qualification_configuration(variants: dict[str, Path]) -> dict[str, object]: "MINI_MODE": "PRODUCT", "APP": "hp_boot", "SIMU": "VERILATOR", - "HP_CONFIG": "rv64imafdc_zicbom_max", "EXT_CLK_HZ": "72000000", } if configuration != expected: diff --git a/scripts/setup_openc906.py b/scripts/setup_openc906.py new file mode 100644 index 00000000..86bbec48 --- /dev/null +++ b/scripts/setup_openc906.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +"""Install the locked OpenC906 source used by Mini product profiles.""" + +from __future__ import annotations + +import argparse +from pathlib import Path + +from dependency_lock import source +from setup_helpers import ensure_git_repo + + +ROOT = Path(__file__).resolve().parents[1] + + +def main() -> int: + parser = argparse.ArgumentParser() + parser.add_argument("--update", action="store_true") + args = parser.parse_args() + dependency = source("openc906") + destination = ROOT / dependency["destination"] + ensure_git_repo( + dependency["url"], + destination, + dependency["revision"], + recursive=dependency.get("recursive", False), + update=args.update, + ) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/scripts/vexiiriscv/GenerateRetroSocHp.scala b/scripts/vexiiriscv/GenerateRetroSocStd.scala similarity index 91% rename from scripts/vexiiriscv/GenerateRetroSocHp.scala rename to scripts/vexiiriscv/GenerateRetroSocStd.scala index 1c8e7201..6aa19a7e 100644 --- a/scripts/vexiiriscv/GenerateRetroSocHp.scala +++ b/scripts/vexiiriscv/GenerateRetroSocStd.scala @@ -8,9 +8,11 @@ import vexiiriscv.misc.EmbeddedRiscvJtag import java.nio.file.{Files, Paths} -/** Generates the fixed retroSoC RV64 application core. */ -object GenerateRetroSocHp extends App { - require(args.length == 1, "usage: GenerateRetroSocHp ") +/** Generates the fixed retroSoC Std-series RV64 application core configuration + * (preserved from the retired Mini HP configuration). + */ +object GenerateRetroSocStd extends App { + require(args.length == 1, "usage: GenerateRetroSocStd ") val output = Paths.get(args(0)).toAbsolutePath.normalize Files.createDirectories(output) @@ -120,6 +122,6 @@ object GenerateRetroSocHp extends App { ) ) ) - VexiiRiscv(plugins).setDefinitionName("vexii_riscv_hp_generated") + VexiiRiscv(plugins).setDefinitionName("vexiiriscv_std_generated") } } diff --git a/tests/rtl/apb4_topology_tb.sv b/tests/rtl/apb4_topology_tb.sv index c0640621..7c9b4ffc 100644 --- a/tests/rtl/apb4_topology_tb.sv +++ b/tests/rtl/apb4_topology_tb.sv @@ -16,7 +16,7 @@ module apb4_topology_tb; begin s_decode_addr = address; #1; - if (s_psel_comb !== (30'd1 << slot)) begin + if (s_psel_comb !== (28'd1 << slot)) begin $fatal(1, "unexpected APB4 target slot for %h: got %b", address, s_psel_comb); end end @@ -33,9 +33,9 @@ module apb4_topology_tb; expect_select(`SOC_ADDR_APB4_SDIO0_BASE, 15); expect_select(`SOC_ADDR_APB4_SDIO1_BASE, 18); expect_select(`SOC_ADDR_APB4_CRYPTO_BASE, 19); - expect_select(`SOC_ADDR_APB4_GA2D_BASE, 28); - expect_select(`SOC_ADDR_APB4_APU_BASE, 27); - expect_select(`SOC_ADDR_APB4_NPU_BASE, 29); + expect_select(`SOC_ADDR_APB4_GA2D_BASE, 26); + expect_select(`SOC_ADDR_APB4_APU_BASE, 25); + expect_select(`SOC_ADDR_APB4_NPU_BASE, 27); $display("SoC topology APB4 routing test passed"); $finish; end diff --git a/tests/rtl/axi4_downsizer_128to64_tb.sv b/tests/rtl/axi4_downsizer_128to64_tb.sv new file mode 100644 index 00000000..a6c10e9c --- /dev/null +++ b/tests/rtl/axi4_downsizer_128to64_tb.sv @@ -0,0 +1,420 @@ +`timescale 1ns / 1ps + +`include "axi4_define.svh" + +module axi4_downsizer_128to64_tb; + logic clk_i = 1'b0; + logic rst_n_i = 1'b0; + + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(128), + .ID_WIDTH (8), + .USER_WIDTH(1) + ) wide ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(64), + .ID_WIDTH (3), + .USER_WIDTH(1) + ) narrow ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + + always #5 clk_i = ~clk_i; + + axi4_downsizer_128to64 #( + .WideIdWidth(8) + ) u_dut ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .clear_i(1'b0), + .wide (wide), + .narrow (narrow) + ); + + // Lower-half RRESP of the wide beat currently being recombined. + logic [1:0] last_lower_resp; + + function automatic logic [127:0] wide_write_data(input int beat); + return {64'hD00D_0000_0000_0000 + 64'(beat), 64'hB00B_0000_0000_0000 + 64'(beat)}; + endfunction + + function automatic logic [15:0] wide_write_strb(input int beat); + return (beat % 2 == 0) ? 16'hFFFF : 16'hC33C; + endfunction + + function automatic logic [63:0] narrow_read_data(input int beat); + return 64'h3000_0000_0000_0000 + 64'(beat); + endfunction + + function automatic logic [63:0] size2_read_data(input int beat); + return 64'hA5A5_0000_0000_0000 + 64'(beat); + endfunction + + task automatic init_bus; + begin + wide.awid = '0; + wide.awaddr = '0; + wide.awlen = '0; + wide.awsize = `AXI4_BURST_SIZE_16BYTES; + wide.awburst = `AXI4_BURST_TYPE_INCR; + wide.awlock = `AXI4_LOCK_NORM; + wide.awcache = `AXI4_CACHE_NO_BUF; + wide.awprot = `AXI4_PROT_DATA; + wide.awqos = `AXI4_QOS_NORMAL; + wide.awregion = `AXI4_REGION_NORMAL; + wide.awuser = '0; + wide.awvalid = 1'b0; + wide.wdata = '0; + wide.wstrb = '0; + wide.wlast = 1'b0; + wide.wuser = '0; + wide.wvalid = 1'b0; + wide.bready = 1'b0; + wide.arid = '0; + wide.araddr = '0; + wide.arlen = '0; + wide.arsize = `AXI4_BURST_SIZE_16BYTES; + wide.arburst = `AXI4_BURST_TYPE_INCR; + wide.arlock = `AXI4_LOCK_NORM; + wide.arcache = `AXI4_CACHE_NO_BUF; + wide.arprot = `AXI4_PROT_DATA; + wide.arqos = `AXI4_QOS_NORMAL; + wide.arregion = `AXI4_REGION_NORMAL; + wide.aruser = '0; + wide.arvalid = 1'b0; + wide.rready = 1'b0; + narrow.awready = 1'b0; + narrow.wready = 1'b0; + narrow.bid = '0; + narrow.bresp = `AXI4_RESP_OKAY; + narrow.buser = '0; + narrow.bvalid = 1'b0; + narrow.arready = 1'b0; + narrow.rid = '0; + narrow.rdata = '0; + narrow.rresp = `AXI4_RESP_OKAY; + narrow.rlast = 1'b0; + narrow.ruser = '0; + narrow.rvalid = 1'b0; + last_lower_resp = `AXI4_RESP_OKAY; + end + endtask + + task automatic accept_read(input logic [31:0] address, input logic [7:0] length, + input logic [2:0] size, input logic [1:0] burst, input logic [7:0] id, + input logic [7:0] expected_length); + begin + @(negedge clk_i); + wide.araddr = address; + wide.arlen = length; + wide.arsize = size; + wide.arburst = burst; + wide.arid = id; + wide.arvalid = 1'b1; + #1; + if (wide.arready) $fatal(1, "read address ignored narrow backpressure"); + narrow.arready = 1'b1; + #1; + if (!narrow.arvalid || narrow.arid != 3'd0 || narrow.araddr != address || + narrow.arlen != expected_length || + narrow.arsize != ((size == 3'd4) ? 3'd3 : size) || narrow.arburst != burst) begin + $fatal(1, "read address conversion mismatch"); + end + @(posedge clk_i); + @(negedge clk_i); + wide.arvalid = 1'b0; + narrow.arready = 1'b0; + end + endtask + + task automatic accept_write(input logic [31:0] address, input logic [7:0] length, + input logic [2:0] size, input logic [7:0] id, + input logic [7:0] expected_length); + begin + @(negedge clk_i); + wide.awaddr = address; + wide.awlen = length; + wide.awsize = size; + wide.awburst = `AXI4_BURST_TYPE_INCR; + wide.awid = id; + wide.awvalid = 1'b1; + #1; + if (wide.awready) $fatal(1, "write address ignored narrow backpressure"); + narrow.awready = 1'b1; + #1; + if (!narrow.awvalid || narrow.awid != 3'd0 || narrow.awaddr != address || + narrow.awlen != expected_length || + narrow.awsize != ((size == 3'd4) ? 3'd3 : size) || + narrow.awburst != `AXI4_BURST_TYPE_INCR) begin + $fatal(1, "write address conversion mismatch"); + end + @(posedge clk_i); + @(negedge clk_i); + wide.awvalid = 1'b0; + narrow.awready = 1'b0; + end + endtask + + // Returns the narrow write response while the wide master is not ready; the + // response must be buffered privately and presented once with the registered + // wide ID, held stable until the wide handshake completes. + task automatic return_write_response(input logic [7:0] expected_id, input logic [1:0] response); + begin + @(negedge clk_i); + narrow.bresp = response; + narrow.bvalid = 1'b1; + wide.bready = 1'b0; + #1; + if (!narrow.bready) $fatal(1, "narrow write response was not accepted into buffer"); + if (wide.bvalid) $fatal(1, "write response bypassed the buffer"); + @(posedge clk_i); + @(negedge clk_i); + narrow.bvalid = 1'b0; + #1; + if (!wide.bvalid || wide.bid != expected_id || wide.bresp != response) begin + $fatal(1, "buffered write response mismatch"); + end + repeat (2) @(posedge clk_i); + if (!wide.bvalid || wide.bid != expected_id || wide.bresp != response) begin + $fatal(1, "write response changed under backpressure"); + end + @(negedge clk_i); + wide.bready = 1'b1; + @(posedge clk_i); + @(negedge clk_i); + wide.bready = 1'b0; + #1; + if (wide.bvalid) $fatal(1, "duplicate write response"); + end + endtask + + // Drives one wide size-4 write beat whose two narrow halves stream back to + // back. The narrow side raises wlast only on the upper half of the final + // wide beat; the wide master sees wready only on the upper halves. + task automatic send_wide_write_beat(input logic [127:0] data, input logic [15:0] strb, + input logic wide_last); + begin + @(negedge clk_i); + wide.wdata = data; + wide.wstrb = strb; + wide.wlast = wide_last; + wide.wvalid = 1'b1; + narrow.wready = 1'b1; + #1; + if (!narrow.wvalid || narrow.wdata != data[63:0] || narrow.wstrb != strb[7:0] || + narrow.wlast || wide.wready) begin + $fatal(1, "lower split write beat mismatch"); + end + @(posedge clk_i); + @(negedge clk_i); + #1; + if (!narrow.wvalid || narrow.wdata != data[127:64] || narrow.wstrb != strb[15:8] || + narrow.wlast != wide_last || !wide.wready) begin + $fatal(1, "upper split write beat mismatch"); + end + @(posedge clk_i); + end + endtask + + // Drives one narrow read beat of a size-4 burst. Even beats are lower halves + // that must be buffered invisibly; odd beats complete a wide beat whose + // response keeps a non-OKAY lower half. hold_cycles > 0 applies wide.rready + // backpressure on the upper half before accepting it. + task automatic send_narrow_read_beat(input int beat, input int total_narrow, input logic [7:0] id, + input logic [1:0] response, input int hold_cycles); + logic [127:0] expected_data; + logic [ 1:0] expected_response; + logic expected_last; + begin + @(negedge clk_i); + narrow.rdata = narrow_read_data(beat); + narrow.rresp = response; + narrow.rlast = (beat == total_narrow - 1); + narrow.rvalid = 1'b1; + wide.rready = (hold_cycles == 0); + #1; + if (beat % 2 == 0) begin + last_lower_resp = response; + if (!narrow.rready) $fatal(1, "lower narrow read beat was not accepted"); + if (wide.rvalid) $fatal(1, "lower narrow read beat leaked to the wide side"); + @(posedge clk_i); + end else begin + expected_data = {narrow_read_data(beat), narrow_read_data(beat - 1)}; + expected_response = (last_lower_resp != `AXI4_RESP_OKAY) ? last_lower_resp : response; + expected_last = (beat == total_narrow - 1); + if (!wide.rvalid || wide.rdata != expected_data || wide.rresp != expected_response || + wide.rid != id || wide.rlast != expected_last) begin + $fatal(1, "wide read recombination mismatch"); + end + for (int h = 0; h < hold_cycles; h++) begin + if (narrow.rready) $fatal(1, "upper narrow read beat ignored wide backpressure"); + @(posedge clk_i); + @(negedge clk_i); + #1; + if (!wide.rvalid || wide.rdata != expected_data || wide.rresp != expected_response || + wide.rid != id || wide.rlast != expected_last) begin + $fatal(1, "wide read beat changed under backpressure"); + end + end + wide.rready = 1'b1; + #1; + if (!narrow.rready) $fatal(1, "upper narrow read beat was not accepted"); + @(posedge clk_i); + end + end + endtask + + // Runs one size-4 read burst (INCR or WRAP): the narrow burst doubles in + // length, every two narrow beats recombine into one wide beat, and the wide + // side raises rlast only on the final beat. error_beat/error_response inject + // a lower-half error, hold_wide_beat stalls one wide beat, and + // gap_after_narrow inserts a narrow.rvalid bubble; -1 disables each. + task automatic do_size4_read(input logic [31:0] address, input logic [7:0] length, + input logic [1:0] burst, input logic [7:0] id, input int error_beat, + input logic [1:0] error_response, input int hold_wide_beat, + input int gap_after_narrow); + int total_narrow; + logic [1:0] response; + begin + total_narrow = 2 * (length + 1); + accept_read(address, length, 3'd4, burst, id, 8'((length << 1) | 8'd1)); + for (int j = 0; j < total_narrow; j++) begin + response = (j == error_beat) ? error_response : `AXI4_RESP_OKAY; + send_narrow_read_beat(j, total_narrow, id, response, + (j % 2 == 1 && j / 2 == hold_wide_beat) ? 2 : 0); + if (j == gap_after_narrow) begin + @(negedge clk_i); + narrow.rvalid = 1'b0; + narrow.rlast = 1'b0; + wide.rready = 1'b0; + #1; + if (wide.rvalid) $fatal(1, "wide read beat appeared during a narrow gap"); + @(posedge clk_i); + end + end + @(negedge clk_i); + narrow.rvalid = 1'b0; + narrow.rlast = 1'b0; + wide.rready = 1'b0; + end + endtask + + // Runs one size-2 read burst: the geometry passes through unchanged and each + // narrow beat lands on the lane selected by address bit 3. + task automatic do_size2_read(input logic [31:0] address, input logic [7:0] length, + input logic [7:0] id); + logic [127:0] expected_data; + begin + accept_read(address, length, 3'd2, `AXI4_BURST_TYPE_INCR, id, length); + for (int j = 0; j <= length; j++) begin + @(negedge clk_i); + narrow.rdata = size2_read_data(j); + narrow.rresp = `AXI4_RESP_OKAY; + narrow.rlast = (j == length); + narrow.rvalid = 1'b1; + wide.rready = 1'b1; + #1; + expected_data = address[3] ? {size2_read_data(j), 64'd0} : {64'd0, size2_read_data(j)}; + if (!narrow.rready) $fatal(1, "32-bit read beat was not accepted"); + if (!wide.rvalid || wide.rdata != expected_data || wide.rid != id || + wide.rlast != (j == length) || wide.rresp != `AXI4_RESP_OKAY) begin + $fatal(1, "32-bit read lane mismatch"); + end + @(posedge clk_i); + end + @(negedge clk_i); + narrow.rvalid = 1'b0; + narrow.rlast = 1'b0; + wide.rready = 1'b0; + end + endtask + + // Runs one size-4 write burst: each wide beat splits into a lower and an + // upper narrow beat and the narrow burst ends on the upper half of the final + // wide beat. + task automatic do_size4_write(input logic [31:0] address, input logic [7:0] length, + input logic [7:0] id, input logic [1:0] response); + begin + accept_write(address, length, 3'd4, id, 8'((length << 1) | 8'd1)); + for (int i = 0; i <= length; i++) begin + send_wide_write_beat(wide_write_data(i), wide_write_strb(i), i == length); + end + @(negedge clk_i); + wide.wvalid = 1'b0; + narrow.wready = 1'b0; + return_write_response(id, response); + end + endtask + + // Runs one single-beat size-2 write; the narrow beat takes the half selected + // by address bit 3 and completes immediately. + task automatic do_size2_write(input logic [31:0] address, input logic [7:0] id); + logic [127:0] data; + logic [ 15:0] strb; + logic [ 63:0] expected_data; + logic [ 7:0] expected_strb; + begin + data = 128'hCAFE_0000_0000_0000_DEAD_0000_0000_0000; + strb = 16'hF00F; + accept_write(address, 8'd0, 3'd2, id, 8'd0); + @(negedge clk_i); + wide.wdata = data; + wide.wstrb = strb; + wide.wlast = 1'b1; + wide.wvalid = 1'b1; + narrow.wready = 1'b1; + #1; + expected_data = address[3] ? data[127:64] : data[63:0]; + expected_strb = address[3] ? strb[15:8] : strb[7:0]; + if (!narrow.wvalid || narrow.wdata != expected_data || narrow.wstrb != expected_strb || + !narrow.wlast || !wide.wready) begin + $fatal(1, "32-bit write lane mismatch"); + end + @(posedge clk_i); + @(negedge clk_i); + wide.wvalid = 1'b0; + narrow.wready = 1'b0; + return_write_response(id, `AXI4_RESP_OKAY); + end + endtask + + initial begin + init_bus(); + repeat (4) @(posedge clk_i); + rst_n_i = 1'b1; + + // Single-beat size-4 read: the lower-half SLVERR stays sticky in the + // recombined wide beat, which is held under wide.rready backpressure. + do_size4_read(32'h0000_0040, 8'd0, `AXI4_BURST_TYPE_INCR, 8'hA5, 0, `AXI4_RESP_SLAVE_ERROR, 0, + -1); + + // Four-beat size-4 INCR read: narrow arlen 7, wide rlast only on the final + // beat, mid-burst wide backpressure, and a narrow.rvalid bubble. + do_size4_read(32'h0000_0100, 8'd3, `AXI4_BURST_TYPE_INCR, 8'h10, -1, `AXI4_RESP_OKAY, 1, 4); + + // WRAP4 size-4 read: the narrow burst stays WRAP with doubled length. + do_size4_read(32'h0000_0300, 8'd3, `AXI4_BURST_TYPE_WRAP, 8'h11, -1, `AXI4_RESP_OKAY, -1, -1); + + // Size-2 reads: geometry passthrough and lane placement for address bit 3 + // clear (lower lane) and set (upper lane). + do_size2_read(32'h0000_0200, 8'd1, 8'h41); + do_size2_read(32'h0000_0208, 8'd0, 8'h42); + + // Two-beat size-4 INCR write: beat splitting, wstrb halves, narrow wlast + // only on the upper half of the final wide beat, and an error response. + do_size4_write(32'h0000_0400, 8'd1, 8'h20, `AXI4_RESP_SLAVE_ERROR); + + // Size-2 writes: lane placement for both address bit 3 alignments. + do_size2_write(32'h0000_0500, 8'h43); + do_size2_write(32'h0000_0508, 8'h44); + + $display("AXI4 128-to-64 downsizer test passed"); + $finish; + end +endmodule diff --git a/tests/rtl/axi4_mmio_demux_tb.sv b/tests/rtl/axi4_mmio_demux_tb.sv new file mode 100644 index 00000000..9ea702ad --- /dev/null +++ b/tests/rtl/axi4_mmio_demux_tb.sv @@ -0,0 +1,370 @@ +`timescale 1ns / 1ps + +`include "axi4_define.svh" + +module axi4_mmio_demux_tb; + logic clk_i = 1'b0; + logic rst_n_i = 1'b0; + + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(64), + .ID_WIDTH (3), + .USER_WIDTH(1) + ) source ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(64), + .ID_WIDTH (3), + .USER_WIDTH(1) + ) mem ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(64), + .ID_WIDTH (3), + .USER_WIDTH(1) + ) mmio ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + + always #5 clk_i = ~clk_i; + + axi4_mmio_demux u_dut ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .clear_i(1'b0), + .source (source), + .mem (mem), + .mmio (mmio) + ); + + function automatic logic [63:0] read_data(input logic [2:0] id, input int beat); + return {32'h5A00_0000 + 32'(id), 32'h0000_0000 + 32'(beat)}; + endfunction + + task automatic init_bus; + begin + source.awid = '0; + source.awaddr = '0; + source.awlen = '0; + source.awsize = `AXI4_BURST_SIZE_8BYTES; + source.awburst = `AXI4_BURST_TYPE_INCR; + source.awlock = `AXI4_LOCK_NORM; + source.awcache = `AXI4_CACHE_NO_BUF; + source.awprot = `AXI4_PROT_DATA; + source.awqos = `AXI4_QOS_NORMAL; + source.awregion = `AXI4_REGION_NORMAL; + source.awuser = '0; + source.awvalid = 1'b0; + source.wdata = '0; + source.wstrb = '0; + source.wlast = 1'b0; + source.wuser = '0; + source.wvalid = 1'b0; + source.bready = 1'b0; + source.arid = '0; + source.araddr = '0; + source.arlen = '0; + source.arsize = `AXI4_BURST_SIZE_8BYTES; + source.arburst = `AXI4_BURST_TYPE_INCR; + source.arlock = `AXI4_LOCK_NORM; + source.arcache = `AXI4_CACHE_NO_BUF; + source.arprot = `AXI4_PROT_DATA; + source.arqos = `AXI4_QOS_NORMAL; + source.arregion = `AXI4_REGION_NORMAL; + source.aruser = '0; + source.arvalid = 1'b0; + source.rready = 1'b0; + mem.awready = 1'b0; + mem.wready = 1'b0; + mem.bid = '0; + mem.bresp = `AXI4_RESP_OKAY; + mem.buser = '0; + mem.bvalid = 1'b0; + mem.arready = 1'b0; + mem.rid = '0; + mem.rdata = '0; + mem.rresp = `AXI4_RESP_OKAY; + mem.rlast = 1'b0; + mem.ruser = '0; + mem.rvalid = 1'b0; + mmio.awready = 1'b0; + mmio.wready = 1'b0; + mmio.bid = '0; + mmio.bresp = `AXI4_RESP_OKAY; + mmio.buser = '0; + mmio.bvalid = 1'b0; + mmio.arready = 1'b0; + mmio.rid = '0; + mmio.rdata = '0; + mmio.rresp = `AXI4_RESP_OKAY; + mmio.rlast = 1'b0; + mmio.ruser = '0; + mmio.rvalid = 1'b0; + end + endtask + + // Runs one read routed by address window: expect_mmio selects the target. + // Checks that the address only leaves on the selected port, that a ready on + // the wrong port cannot complete the source handshake, that wrong-port read + // data never leaks to the source, and that the selected response is held + // stable while source.rready is low on beat hold_beat (-1 disables). + task automatic do_read(input logic [31:0] address, input logic expect_mmio, input logic [2:0] id, + input logic [7:0] length, input int hold_beat); + logic [63:0] expected_data; + begin + @(negedge clk_i); + source.araddr = address; + source.arlen = length; + source.arsize = `AXI4_BURST_SIZE_8BYTES; + source.arburst = `AXI4_BURST_TYPE_INCR; + source.arid = id; + source.arvalid = 1'b1; + #1; + if (source.arready) $fatal(1, "read address accepted without target ready"); + if (expect_mmio) begin + if (!mmio.arvalid || mem.arvalid) $fatal(1, "read address leaked to the wrong port"); + end else begin + if (!mem.arvalid || mmio.arvalid) $fatal(1, "read address leaked to the wrong port"); + end + // A ready on the wrong port must not complete the source handshake. + if (expect_mmio) mem.arready = 1'b1; + else mmio.arready = 1'b1; + #1; + if (source.arready) $fatal(1, "read address used the wrong port ready"); + if (expect_mmio) mmio.arready = 1'b1; + else mem.arready = 1'b1; + #1; + if (!source.arready) $fatal(1, "read address was not forwarded to the selected port"); + if (expect_mmio) begin + if (mmio.arid != id || mmio.araddr != address || mmio.arlen != length || + mmio.arsize != `AXI4_BURST_SIZE_8BYTES) begin + $fatal(1, "read address fields changed on the mmio port"); + end + end else begin + if (mem.arid != id || mem.araddr != address || mem.arlen != length || + mem.arsize != `AXI4_BURST_SIZE_8BYTES) begin + $fatal(1, "read address fields changed on the mem port"); + end + end + @(posedge clk_i); + @(negedge clk_i); + source.arvalid = 1'b0; + mem.arready = 1'b0; + mmio.arready = 1'b0; + // A response on the wrong port must not reach the source. + if (expect_mmio) mem.rvalid = 1'b1; + else mmio.rvalid = 1'b1; + #1; + if (source.rvalid) $fatal(1, "wrong-port read data leaked to the source"); + if (expect_mmio) begin + if (mem.rready) $fatal(1, "read ready leaked to the wrong port"); + end else begin + if (mmio.rready) $fatal(1, "read ready leaked to the wrong port"); + end + @(posedge clk_i); + @(negedge clk_i); + mem.rvalid = 1'b0; + mmio.rvalid = 1'b0; + for (int j = 0; j <= length; j++) begin + @(negedge clk_i); + mem.rid = id; + mmio.rid = id; + mem.rdata = read_data(id, j); + mmio.rdata = read_data(id, j); + mem.rresp = `AXI4_RESP_OKAY; + mmio.rresp = `AXI4_RESP_OKAY; + mem.rlast = (j == length); + mmio.rlast = (j == length); + if (expect_mmio) mmio.rvalid = 1'b1; + else mem.rvalid = 1'b1; + source.rready = (j != hold_beat); + #1; + expected_data = read_data(id, j); + if (!source.rvalid || source.rid != id || source.rdata != expected_data || + source.rresp != `AXI4_RESP_OKAY || source.rlast != (j == length)) begin + $fatal(1, "read data return mismatch"); + end + if (j == hold_beat) begin + repeat (2) begin + if (expect_mmio) begin + if (mmio.rready) $fatal(1, "read beat ignored source backpressure"); + end else begin + if (mem.rready) $fatal(1, "read beat ignored source backpressure"); + end + @(posedge clk_i); + @(negedge clk_i); + #1; + if (!source.rvalid || source.rdata != expected_data || + source.rlast != (j == length)) begin + $fatal(1, "read data changed under backpressure"); + end + end + source.rready = 1'b1; + #1; + end + if (expect_mmio) begin + if (!mmio.rready || mem.rready) $fatal(1, "read ready routing mismatch"); + end else begin + if (!mem.rready || mmio.rready) $fatal(1, "read ready routing mismatch"); + end + @(posedge clk_i); + end + @(negedge clk_i); + mem.rvalid = 1'b0; + mmio.rvalid = 1'b0; + mem.rlast = 1'b0; + mmio.rlast = 1'b0; + source.rready = 1'b0; + end + endtask + + // Runs one single-beat write routed by address window: the W channel must + // follow the registered AW selection and the buffered response must be held + // stable while source.bready is low. + task automatic do_write(input logic [31:0] address, input logic expect_mmio, + input logic [2:0] id); + logic [63:0] data; + begin + data = {32'hD000_0000 + 32'(id), 32'h5EED_0000}; + @(negedge clk_i); + source.awaddr = address; + source.awlen = 8'd0; + source.awsize = `AXI4_BURST_SIZE_8BYTES; + source.awburst = `AXI4_BURST_TYPE_INCR; + source.awid = id; + source.awvalid = 1'b1; + #1; + if (source.awready) $fatal(1, "write address accepted without target ready"); + if (expect_mmio) begin + if (!mmio.awvalid || mem.awvalid) $fatal(1, "write address leaked to the wrong port"); + mmio.awready = 1'b1; + end else begin + if (!mem.awvalid || mmio.awvalid) $fatal(1, "write address leaked to the wrong port"); + mem.awready = 1'b1; + end + #1; + if (!source.awready) $fatal(1, "write address was not forwarded to the selected port"); + @(posedge clk_i); + @(negedge clk_i); + source.awvalid = 1'b0; + mem.awready = 1'b0; + mmio.awready = 1'b0; + // The W channel follows the registered AW selection. + source.wdata = data; + source.wstrb = 8'hA5; + source.wlast = 1'b1; + source.wvalid = 1'b1; + #1; + if (source.wready) $fatal(1, "write data accepted without target ready"); + if (expect_mmio) begin + if (!mmio.wvalid || mem.wvalid) $fatal(1, "write data leaked to the wrong port"); + end else begin + if (!mem.wvalid || mmio.wvalid) $fatal(1, "write data leaked to the wrong port"); + end + if (expect_mmio) mmio.wready = 1'b1; + else mem.wready = 1'b1; + #1; + if (!source.wready) $fatal(1, "write data was not forwarded to the selected port"); + if (expect_mmio) begin + if (mmio.wdata != data || mmio.wstrb != 8'hA5 || !mmio.wlast) begin + $fatal(1, "write data fields changed on the mmio port"); + end + end else begin + if (mem.wdata != data || mem.wstrb != 8'hA5 || !mem.wlast) begin + $fatal(1, "write data fields changed on the mem port"); + end + end + @(posedge clk_i); + @(negedge clk_i); + source.wvalid = 1'b0; + mem.wready = 1'b0; + mmio.wready = 1'b0; + // A response on the wrong port must not reach the source. + if (expect_mmio) mem.bvalid = 1'b1; + else mmio.bvalid = 1'b1; + #1; + if (source.bvalid) $fatal(1, "wrong-port write response leaked to the source"); + @(posedge clk_i); + @(negedge clk_i); + mem.bvalid = 1'b0; + mmio.bvalid = 1'b0; + // Selected response is held stable under source.bready backpressure. + mem.bid = id; + mmio.bid = id; + mem.bresp = `AXI4_RESP_OKAY; + mmio.bresp = `AXI4_RESP_OKAY; + if (expect_mmio) mmio.bvalid = 1'b1; + else mem.bvalid = 1'b1; + source.bready = 1'b0; + #1; + if (!source.bvalid || source.bid != id || source.bresp != `AXI4_RESP_OKAY) begin + $fatal(1, "write response return mismatch"); + end + if (expect_mmio) begin + if (mmio.bready || mem.bready) $fatal(1, "write ready leaked under backpressure"); + end else begin + if (mem.bready || mmio.bready) $fatal(1, "write ready leaked under backpressure"); + end + repeat (2) begin + @(posedge clk_i); + @(negedge clk_i); + #1; + if (!source.bvalid || source.bid != id) + $fatal(1, "write response changed under backpressure"); + end + source.bready = 1'b1; + #1; + if (expect_mmio) begin + if (!mmio.bready || mem.bready) $fatal(1, "write ready routing mismatch"); + end else begin + if (!mem.bready || mmio.bready) $fatal(1, "write ready routing mismatch"); + end + @(posedge clk_i); + @(negedge clk_i); + mem.bvalid = 1'b0; + mmio.bvalid = 1'b0; + source.bready = 1'b0; + #1; + if (source.bvalid) $fatal(1, "duplicate write response"); + end + endtask + + initial begin + init_bus(); + repeat (4) @(posedge clk_i); + rst_n_i = 1'b1; + + // Read routing: above the MMIO window goes to mem, inside goes to mmio. + do_read(32'h3800_0000, 1'b0, 3'h1, 8'd0, -1); + do_read(32'h1000_0000, 1'b1, 3'h2, 8'd0, -1); + + // Window boundaries: 0x01FFFFFF mem, 0x02000000 mmio, 0x2FFFFFFF mmio, + // 0x30000000 mem. + do_read(32'h01FF_FFFF, 1'b0, 3'h3, 8'd0, -1); + do_read(32'h0200_0000, 1'b1, 3'h4, 8'd0, -1); + do_read(32'h2FFF_FFFF, 1'b1, 3'h5, 8'd0, -1); + do_read(32'h3000_0000, 1'b0, 3'h6, 8'd0, -1); + + // Multi-beat reads with mid-burst source.rready backpressure, alternating + // targets so each transaction follows a completed one on the other port. + do_read(32'h1000_0100, 1'b1, 3'h7, 8'd3, 1); + do_read(32'h4000_0000, 1'b0, 3'h0, 8'd1, 0); + + // Write routing in both directions; the W channel follows AW. + do_write(32'h0200_0040, 1'b1, 3'h1); + do_write(32'h4000_0080, 1'b0, 3'h2); + do_write(32'h2FFF_FFF8, 1'b1, 3'h3); + do_write(32'h01FF_FFF8, 1'b0, 3'h4); + + $display("AXI4 MMIO demux test passed"); + $finish; + end +endmodule diff --git a/tests/rtl/ga2d_platform_tb.sv b/tests/rtl/ga2d_platform_tb.sv index 70c50527..c39b7306 100644 --- a/tests/rtl/ga2d_platform_tb.sv +++ b/tests/rtl/ga2d_platform_tb.sv @@ -175,7 +175,7 @@ module ga2d_platform_sram_target ( last_arid_o <= axi4.arid; seen_arid_mask_o[axi4.arid[6:0]] <= 1'b1; if (axi4.arid == 7'h40) saw_ga2d_o <= 1'b1; - if (axi4.arid == 7'h08) saw_legacy_o <= 1'b1; + if (axi4.arid == 7'h00) saw_legacy_o <= 1'b1; if (axi4.arid[6:3] == 4'd6) saw_jpeg_o <= 1'b1; end if (read_pending_q && !hold_response_i) begin @@ -527,16 +527,7 @@ module ga2d_platform_tb; .DATA_WIDTH(64), .ID_WIDTH (3), .USER_WIDTH(1) - ) hp_icache_axi4 ( - .aclk (clk_hp_i), - .aresetn(rst_hp_n_i) - ); - axi4_if #( - .ADDR_WIDTH(32), - .DATA_WIDTH(64), - .ID_WIDTH (3), - .USER_WIDTH(1) - ) hp_dcache_axi4 ( + ) hp_mem_axi4 ( .aclk (clk_hp_i), .aresetn(rst_hp_n_i) ); @@ -701,10 +692,9 @@ module ga2d_platform_tb; end always #13 clk_mem_i = ~clk_mem_i; - axi4_master_idle u_hp_icache_idle (.axi4(hp_icache_axi4)); // V13 competitor map: central DMA (master 2), APU/SDIO0/USB2 (master 3 via // the round-robin IO gateway A), and SDIO1 (master 4 via IO gateway B) are - // driven by deterministic BFMs; the HP dcache tasks below add the CPU-proxy + // driven by deterministic BFMs; the HP mem tasks below add the CPU-proxy // old-ID traffic and the JPEG tasks the master-6 traffic. spisd stays tied // off as the quiescent client of IO gateway B (driving it would only repeat // the master-4 path SDIO1 already exercises), and ext_h stays tied off @@ -844,8 +834,7 @@ module ga2d_platform_tb; .ext_h_read_limit_i (32'h4FFF_FFFF), .ext_h_write_base_i (32'h3000_0000), .ext_h_write_limit_i (32'h4FFF_FFFF), - .hp_icache_axi4 (hp_icache_axi4), - .hp_dcache_axi4 (hp_dcache_axi4), + .hp_mem_axi4 (hp_mem_axi4), .dma_axi4 (dma_axi4), .sdio0_axi4 (sdio0_axi4), .sdio1_axi4 (sdio1_axi4), @@ -1029,33 +1018,72 @@ module ga2d_platform_tb; task automatic issue_legacy_read(input logic [2:0] id, input logic [31:0] address); begin @(negedge clk_hp_i); - hp_dcache_axi4.arid = id; - hp_dcache_axi4.araddr = address; - hp_dcache_axi4.arlen = '0; - hp_dcache_axi4.arsize = 3'd3; - hp_dcache_axi4.arburst = 2'b01; - hp_dcache_axi4.arlock = 1'b0; - hp_dcache_axi4.arcache = '0; - hp_dcache_axi4.arprot = '0; - hp_dcache_axi4.arqos = '0; - hp_dcache_axi4.arregion = '0; - hp_dcache_axi4.aruser = '0; - hp_dcache_axi4.arvalid = 1'b1; - do @(posedge clk_hp_i); while (!hp_dcache_axi4.arready); + hp_mem_axi4.arid = id; + hp_mem_axi4.araddr = address; + hp_mem_axi4.arlen = '0; + hp_mem_axi4.arsize = 3'd3; + hp_mem_axi4.arburst = 2'b01; + hp_mem_axi4.arlock = 1'b0; + hp_mem_axi4.arcache = '0; + hp_mem_axi4.arprot = '0; + hp_mem_axi4.arqos = '0; + hp_mem_axi4.arregion = '0; + hp_mem_axi4.aruser = '0; + hp_mem_axi4.arvalid = 1'b1; + do @(posedge clk_hp_i); while (!hp_mem_axi4.arready); @(negedge clk_hp_i); - hp_dcache_axi4.arvalid = 1'b0; + hp_mem_axi4.arvalid = 1'b0; end endtask task automatic expect_legacy_read(input logic [2:0] id); begin - wait (hp_dcache_axi4.rvalid); - if ((hp_dcache_axi4.rid != id) || (hp_dcache_axi4.rresp != 2'b00)) begin + wait (hp_mem_axi4.rvalid); + if ((hp_mem_axi4.rid != id) || (hp_mem_axi4.rresp != 2'b00)) begin $fatal(1, "legacy response did not preserve its source ID"); end end endtask + task automatic issue_legacy_write(input logic [2:0] id, input logic [31:0] address, + input logic [63:0] data); + begin + @(negedge clk_hp_i); + hp_mem_axi4.awid = id; + hp_mem_axi4.awaddr = address; + hp_mem_axi4.awlen = '0; + hp_mem_axi4.awsize = 3'd3; + hp_mem_axi4.awburst = 2'b01; + hp_mem_axi4.awlock = 1'b0; + hp_mem_axi4.awcache = '0; + hp_mem_axi4.awprot = '0; + hp_mem_axi4.awqos = '0; + hp_mem_axi4.awregion = '0; + hp_mem_axi4.awuser = '0; + hp_mem_axi4.awvalid = 1'b1; + do @(posedge clk_hp_i); while (!hp_mem_axi4.awready); + @(negedge clk_hp_i); + hp_mem_axi4.awvalid = 1'b0; + hp_mem_axi4.wdata = data; + hp_mem_axi4.wstrb = 8'hFF; + hp_mem_axi4.wlast = 1'b1; + hp_mem_axi4.wuser = '0; + hp_mem_axi4.wvalid = 1'b1; + do @(posedge clk_hp_i); while (!hp_mem_axi4.wready); + @(negedge clk_hp_i); + hp_mem_axi4.wvalid = 1'b0; + end + endtask + + task automatic expect_legacy_write(input logic [2:0] id); + begin + wait (hp_mem_axi4.bvalid); + if ((hp_mem_axi4.bid != id) || (hp_mem_axi4.bresp != 2'b00)) begin + $fatal(1, "legacy write response did not preserve its source ID"); + end + end + endtask + task automatic issue_lp_read(input logic id, input logic [31:0] address); begin @(negedge clk_lp_i); @@ -1491,37 +1519,37 @@ module ga2d_platform_tb; jpeg_axi4.arvalid = 1'b0; jpeg_axi4.rready = 1'b1; - hp_dcache_axi4.awid = '0; - hp_dcache_axi4.awaddr = '0; - hp_dcache_axi4.awlen = '0; - hp_dcache_axi4.awsize = 3'd3; - hp_dcache_axi4.awburst = 2'b01; - hp_dcache_axi4.awlock = 1'b0; - hp_dcache_axi4.awcache = '0; - hp_dcache_axi4.awprot = '0; - hp_dcache_axi4.awqos = '0; - hp_dcache_axi4.awregion = '0; - hp_dcache_axi4.awuser = '0; - hp_dcache_axi4.awvalid = 1'b0; - hp_dcache_axi4.wdata = '0; - hp_dcache_axi4.wstrb = '0; - hp_dcache_axi4.wlast = 1'b1; - hp_dcache_axi4.wuser = '0; - hp_dcache_axi4.wvalid = 1'b0; - hp_dcache_axi4.bready = 1'b1; - hp_dcache_axi4.arid = '0; - hp_dcache_axi4.araddr = '0; - hp_dcache_axi4.arlen = '0; - hp_dcache_axi4.arsize = 3'd3; - hp_dcache_axi4.arburst = 2'b01; - hp_dcache_axi4.arlock = 1'b0; - hp_dcache_axi4.arcache = '0; - hp_dcache_axi4.arprot = '0; - hp_dcache_axi4.arqos = '0; - hp_dcache_axi4.arregion = '0; - hp_dcache_axi4.aruser = '0; - hp_dcache_axi4.arvalid = 1'b0; - hp_dcache_axi4.rready = 1'b1; + hp_mem_axi4.awid = '0; + hp_mem_axi4.awaddr = '0; + hp_mem_axi4.awlen = '0; + hp_mem_axi4.awsize = 3'd3; + hp_mem_axi4.awburst = 2'b01; + hp_mem_axi4.awlock = 1'b0; + hp_mem_axi4.awcache = '0; + hp_mem_axi4.awprot = '0; + hp_mem_axi4.awqos = '0; + hp_mem_axi4.awregion = '0; + hp_mem_axi4.awuser = '0; + hp_mem_axi4.awvalid = 1'b0; + hp_mem_axi4.wdata = '0; + hp_mem_axi4.wstrb = '0; + hp_mem_axi4.wlast = 1'b1; + hp_mem_axi4.wuser = '0; + hp_mem_axi4.wvalid = 1'b0; + hp_mem_axi4.bready = 1'b1; + hp_mem_axi4.arid = '0; + hp_mem_axi4.araddr = '0; + hp_mem_axi4.arlen = '0; + hp_mem_axi4.arsize = 3'd3; + hp_mem_axi4.arburst = 2'b01; + hp_mem_axi4.arlock = 1'b0; + hp_mem_axi4.arcache = '0; + hp_mem_axi4.arprot = '0; + hp_mem_axi4.arqos = '0; + hp_mem_axi4.arregion = '0; + hp_mem_axi4.aruser = '0; + hp_mem_axi4.arvalid = 1'b0; + hp_mem_axi4.rready = 1'b1; fabric_monitor_apb4.paddr = '0; fabric_monitor_apb4.pprot = '0; @@ -1582,6 +1610,23 @@ module ga2d_platform_tb; $fatal(1, "GA2D write did not preserve global ID 7'h40"); end + // The merged HP port must retain the retired HP data port's write credits: + // a write to SRAM followed by a readback with the returned data checked. + fork + issue_legacy_write(3'd1, 32'h3000_0100, 64'hA5A5_5A5A_0123_4567); + expect_legacy_write(3'd1); + join + fork + issue_legacy_read(3'd2, 32'h3000_0100); + begin + wait (hp_mem_axi4.rvalid); + if ((hp_mem_axi4.rid != 3'd2) || (hp_mem_axi4.rresp != 2'b00) || + (hp_mem_axi4.rdata != 64'hA5A5_5A5A_0123_4567)) begin + $fatal(1, "legacy readback did not return the data written through the HP port"); + end + end + join + wait (!flush_busy_o); block_new_i = 1'b1; repeat (2) @(posedge clk_hp_i); @@ -1832,7 +1877,7 @@ module ga2d_platform_tb; // GA2D-V13 contention window. The five BFMs (central DMA on master 2, // APU/SDIO0/USB2 sharing master 3, SDIO1 on master 4), the JPEG master-6 // loop, and the legacy HP-dcache loop (CPU proxy with old global ID - // 7'h08) run against the SRAM target while the GA2D battery executes + // 7'h00) run against the SRAM target while the GA2D battery executes // byte-checked jobs. Memory-refresh contention is not modelled here (no // SDRAM model exists in this TB); it is covered by the full-SoC ci_smoke // and benchmark runs against the real SDRAM controller. @@ -1914,9 +1959,9 @@ module ga2d_platform_tb; // Old/new global-ID alias check: every ID accepted by the SRAM target // must belong to the master that owns it. GA2D's IDs carry the new // seventh bit; if that bit were dropped anywhere, GA2D traffic would - // appear as 7'h00 and alias the (tied-off) HP icache master 0. + // appear as 7'h00 and alias the HP mem (CPU-proxy) master 0. expected_read_mask = '0; - expected_read_mask[7'h08] = 1'b1; + expected_read_mask[7'h00] = 1'b1; expected_read_mask[7'h10] = 1'b1; expected_read_mask[7'h11] = 1'b1; expected_read_mask[7'h18] = 1'b1; @@ -1945,12 +1990,12 @@ module ga2d_platform_tb; if ((sram_seen_awid_mask & ~expected_write_mask) != 128'd0) begin $fatal(1, "an unexpected global write ID reached the SRAM target"); end - if (!sram_seen_arid_mask[7'h40] || !sram_seen_arid_mask[7'h08] || + if (!sram_seen_arid_mask[7'h40] || !sram_seen_arid_mask[7'h00] || !sram_seen_arid_mask[7'h30]) begin $fatal(1, "old and new global read IDs were not interleaved during contention"); end - if (sram_seen_arid_mask[7'h00] || sram_seen_awid_mask[7'h00]) begin - $fatal(1, "GA2D traffic aliased onto the legacy master-0 ID space"); + if (sram_seen_arid_mask[7'h08] || sram_seen_awid_mask[7'h08]) begin + $fatal(1, "traffic aliased onto the retired HP master-1 ID space"); end // Fabric-monitor cross-check: bank 8 at 0x200 must have counted the GA2D // battery, and bank 2 the central-DMA competitor. @@ -2056,8 +2101,8 @@ module ga2d_platform_tb; end issue_legacy_read(3'd0, 32'h3000_0080); expect_legacy_read(3'd0); - if (sram_last_arid != 7'h08) begin - $fatal(1, "post-contention legacy read did not keep global ID 7'h08"); + if (sram_last_arid != 7'h00) begin + $fatal(1, "post-contention legacy read did not keep global ID 7'h00"); end issue_jpeg_read(3'd0, 32'h3000_00A0); expect_jpeg_read(3'd0); diff --git a/tests/rtl/hp_c906_boot_tb.sv b/tests/rtl/hp_c906_boot_tb.sv new file mode 100644 index 00000000..51fe726e --- /dev/null +++ b/tests/rtl/hp_c906_boot_tb.sv @@ -0,0 +1,356 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 + +// Focused OpenC906 boot test: runs the real HP smoke payload (hp_smoke.bin, +// preloaded at the 0x38000000 reset vector) on the hp_core_wrapper integration +// (C906 + tdt_dmi_top + axi4_downsizer_128to64 + axi4_mmio_demux) and drives +// the MMIO port through the same chain the SoC uses (axi4_downsizer_64to32, +// axi4_address_gate, axi4_async_bridge into the LP clock domain) to a 32-bit +// MMIO stub modelling UART1 TX and the HP mailbox registers. +// +// Passes when the payload prints HP_SMOKE_READY over UART1, posts the mailbox +// ready event, accepts the injected GA2D start command, and completes the +// GA2D phase (the GA2D engine itself is stubbed, so the expected result event +// is the payload's fail path). +// +// The payload binary is supplied as a byte-wide hex file via `HP_SMOKE_HEX`. + +`timescale 1ns / 1ps + +`include "axi4_define.svh" + +module hp_c906_boot_tb; + localparam logic [31:0] RamBase = 32'h3800_0000; + localparam int RamBytes = 128 * 1024; + localparam logic [31:0] Uart1Base = 32'h1001_8000; + localparam logic [31:0] MailboxBase = 32'h1001_9000; + localparam int MaxCycles = 4_000_000; + + logic clk_i = 1'b0; + logic clk_lp_i = 1'b0; + logic rst_n_i = 1'b0; + logic rst_lp_n_i = 1'b0; + logic core_reset_i = 1'b1; + logic [63:0] time_i = '0; + + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(64), + .ID_WIDTH (3), + .USER_WIDTH(1) + ) mem_axi4 ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(64), + .ID_WIDTH (3), + .USER_WIDTH(1) + ) mmio_axi4 ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_mmio_narrow_if ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_mmio_gated_if ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_mmio_lp_if ( + .aclk (clk_lp_i), + .aresetn(rst_lp_n_i) + ); + + always #5 clk_i = ~clk_i; + always #17 clk_lp_i = ~clk_lp_i; + always @(posedge clk_i) time_i <= time_i + 64'd1; + + hp_core_wrapper u_dut ( + .clk_i (clk_i), + .rst_n_i (rst_n_i), + .core_reset_i (core_reset_i), + .time_i (time_i), + .plic_src_i ('0), + .jtag_tck_i (1'b0), + .jtag_tms_i (1'b1), + .jtag_tdi_i (1'b0), + .jtag_trst_n_i (1'b1), + .jtag_tdo_o (), + .debug_reset_req_o(), + .mem_axi4 (mem_axi4), + .mmio_axi4 (mmio_axi4) + ); + + // The SoC MMIO chain: 64->32 downsizer, address gate, HP->LP CDC bridge. + axi4_downsizer_64to32 u_mmio_downsizer ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .clear_i(1'b0), + .wide (mmio_axi4), + .narrow (u_mmio_narrow_if) + ); + + axi4_address_gate u_mmio_gate ( + .clk_i (clk_i), + .rst_n_i (rst_n_i), + .block_new_i (1'b0), + .clear_i (1'b0), + .source (u_mmio_narrow_if), + .sink (u_mmio_gated_if), + .idle_o (), + .write_pending_o() + ); + + axi4_async_bridge #( + .DataWidth(32), + .IdWidth (1) + ) u_mmio_cdc ( + .src_clk_i (clk_i), + .src_rst_n_i (rst_n_i), + .dst_clk_i (clk_lp_i), + .dst_rst_n_i (rst_lp_n_i), + .clear_i (1'b0), + .clear_busy_o(), + .epoch_o (), + .src_axi4 (u_mmio_gated_if), + .dst_axi4 (u_mmio_lp_if) + ); + + // ---------------- 64-bit AXI4 RAM (mem port) ---------------- + // Single outstanding per channel matches the serializing downsizer. + logic [ 7:0] ram [RamBytes]; + logic [31:0] s_rd_addr_q; + logic [ 7:0] s_rd_len_q; + logic [ 1:0] s_rd_burst_q; + logic s_rd_active_q; + logic [31:0] s_wr_addr_q; + logic s_wr_active_q; + + assign mem_axi4.bid = '0; + assign mem_axi4.buser = '0; + assign mem_axi4.rid = '0; + assign mem_axi4.ruser = '0; + assign mem_axi4.rresp = `AXI4_RESP_OKAY; + assign mem_axi4.bresp = `AXI4_RESP_OKAY; + + function automatic logic [31:0] next_addr(input logic [31:0] addr, input logic [1:0] burst); + if (burst == `AXI4_BURST_TYPE_WRAP) begin + return (addr & ~32'd63) | ((addr + 32'd8) & 32'd63); + end + return addr + 32'd8; + endfunction + + always_ff @(posedge clk_i or negedge rst_n_i) begin + if (!rst_n_i) begin + mem_axi4.arready <= 1'b0; + mem_axi4.rvalid <= 1'b0; + mem_axi4.rlast <= 1'b0; + s_rd_active_q <= 1'b0; + mem_axi4.awready <= 1'b0; + mem_axi4.wready <= 1'b0; + mem_axi4.bvalid <= 1'b0; + s_wr_active_q <= 1'b0; + s_rd_addr_q <= '0; + s_rd_len_q <= '0; + s_rd_burst_q <= '0; + s_wr_addr_q <= '0; + end else begin + // Read address accept. + if (!s_rd_active_q && !mem_axi4.rvalid) begin + mem_axi4.arready <= 1'b1; + if (mem_axi4.arvalid && mem_axi4.arready) begin + s_rd_active_q <= 1'b1; + s_rd_addr_q <= mem_axi4.araddr; + s_rd_len_q <= mem_axi4.arlen; + s_rd_burst_q <= mem_axi4.arburst; + mem_axi4.arready <= 1'b0; + end + end + // Read data. + if (s_rd_active_q && !mem_axi4.rvalid) begin + for (int b = 0; b < 8; b++) begin + mem_axi4.rdata[b*8+:8] <= ram[s_rd_addr_q-RamBase+32'(b)]; + end + mem_axi4.rlast <= (s_rd_len_q == 8'd0); + mem_axi4.rvalid <= 1'b1; + end else if (mem_axi4.rvalid && mem_axi4.rready) begin + if (mem_axi4.rlast) begin + mem_axi4.rvalid <= 1'b0; + mem_axi4.rlast <= 1'b0; + s_rd_active_q <= 1'b0; + end else begin + s_rd_addr_q <= next_addr(s_rd_addr_q, s_rd_burst_q); + s_rd_len_q <= s_rd_len_q - 8'd1; + mem_axi4.rvalid <= 1'b0; + end + end + // Write address accept. + if (!s_wr_active_q && !mem_axi4.bvalid) begin + mem_axi4.awready <= 1'b1; + if (mem_axi4.awvalid && mem_axi4.awready) begin + s_wr_active_q <= 1'b1; + s_wr_addr_q <= mem_axi4.awaddr; + mem_axi4.awready <= 1'b0; + end + end + // Write data. + mem_axi4.wready <= s_wr_active_q; + if (s_wr_active_q && mem_axi4.wvalid && mem_axi4.wready) begin + for (int b = 0; b < 8; b++) begin + if (mem_axi4.wstrb[b]) ram[s_wr_addr_q-RamBase+32'(b)] <= mem_axi4.wdata[b*8+:8]; + end + if (mem_axi4.wlast) begin + s_wr_active_q <= 1'b0; + mem_axi4.bvalid <= 1'b1; + end else begin + s_wr_addr_q <= s_wr_addr_q + 32'd8; + end + end + if (mem_axi4.bvalid && mem_axi4.bready) mem_axi4.bvalid <= 1'b0; + end + end + + // ---------------- 32-bit MMIO stub (LP clock domain) ------------- + logic [31:0] s_mmio_wr_addr_q; + logic s_mmio_wr_active_q; + logic [ 7:0] s_mmio_rd_len_q; + logic s_saw_ready_q; + logic [31:0] s_result_event_q; + + assign u_mmio_lp_if.bid = '0; + assign u_mmio_lp_if.buser = '0; + assign u_mmio_lp_if.rid = '0; + assign u_mmio_lp_if.ruser = '0; + assign u_mmio_lp_if.rresp = `AXI4_RESP_OKAY; + assign u_mmio_lp_if.bresp = `AXI4_RESP_OKAY; + + always_ff @(posedge clk_lp_i or negedge rst_lp_n_i) begin + if (!rst_lp_n_i) begin + u_mmio_lp_if.arready <= 1'b0; + u_mmio_lp_if.rvalid <= 1'b0; + u_mmio_lp_if.rlast <= 1'b0; + u_mmio_lp_if.awready <= 1'b0; + u_mmio_lp_if.wready <= 1'b0; + u_mmio_lp_if.bvalid <= 1'b0; + s_mmio_wr_active_q <= 1'b0; + s_mmio_wr_addr_q <= '0; + s_mmio_rd_len_q <= '0; + s_saw_ready_q <= 1'b0; + s_result_event_q <= '0; + end else begin + if (!u_mmio_lp_if.rvalid) begin + u_mmio_lp_if.arready <= 1'b1; + if (u_mmio_lp_if.arvalid && u_mmio_lp_if.arready) begin + u_mmio_lp_if.arready <= 1'b0; + u_mmio_lp_if.rvalid <= 1'b1; + // UART1 STATUS reads report TX ready (all status bits clear). + u_mmio_lp_if.rdata <= '0; + if (s_saw_ready_q) begin + // Once the payload is ready, drive the LP-side GA2D start + // command into the mailbox read registers. + if (u_mmio_lp_if.araddr == (MailboxBase + 32'h18)) u_mmio_lp_if.rdata <= 32'd1; + if (u_mmio_lp_if.araddr == (MailboxBase + 32'h10)) u_mmio_lp_if.rdata <= 32'h4741_3250; + if (u_mmio_lp_if.araddr == (MailboxBase + 32'h14)) u_mmio_lp_if.rdata <= 32'h4741_3244; + end + // GA2D STATUS (0x10012014): done (bit 4), no error/busy. + if (u_mmio_lp_if.araddr == 32'h1001_2014) u_mmio_lp_if.rdata <= 32'h10; + s_mmio_rd_len_q <= u_mmio_lp_if.arlen; + u_mmio_lp_if.rlast <= (u_mmio_lp_if.arlen == 8'd0); + end + end else if (u_mmio_lp_if.rvalid && u_mmio_lp_if.rready) begin + if (u_mmio_lp_if.rlast) begin + u_mmio_lp_if.rvalid <= 1'b0; + u_mmio_lp_if.rlast <= 1'b0; + end else begin + s_mmio_rd_len_q <= s_mmio_rd_len_q - 8'd1; + u_mmio_lp_if.rlast <= (s_mmio_rd_len_q == 8'd1); + end + end + if (!s_mmio_wr_active_q && !u_mmio_lp_if.bvalid) begin + u_mmio_lp_if.awready <= 1'b1; + if (u_mmio_lp_if.awvalid && u_mmio_lp_if.awready) begin + s_mmio_wr_active_q <= 1'b1; + s_mmio_wr_addr_q <= u_mmio_lp_if.awaddr; + u_mmio_lp_if.awready <= 1'b0; + end + end + u_mmio_lp_if.wready <= s_mmio_wr_active_q; + if (s_mmio_wr_active_q && u_mmio_lp_if.wvalid && u_mmio_lp_if.wready) begin + if (s_mmio_wr_addr_q == (Uart1Base + 32'h10)) begin + $write("%c", 8'(u_mmio_lp_if.wdata[7:0])); + end + if ((s_mmio_wr_addr_q == (MailboxBase + 32'h24)) && + (u_mmio_lp_if.wdata == 32'h4c4e_5801)) begin + s_saw_ready_q <= 1'b1; + end + // HP_EVENT writes (MailboxBase+0x20): the first event is the ready + // notification; any later event is a GA2D-phase result (2=pass, + // 3=fail, 4=cache). + if (s_saw_ready_q && (s_mmio_wr_addr_q == (MailboxBase + 32'h20)) && + (u_mmio_lp_if.wdata != 32'd1)) begin + s_result_event_q <= u_mmio_lp_if.wdata; + end + if (u_mmio_lp_if.wlast) begin + s_mmio_wr_active_q <= 1'b0; + u_mmio_lp_if.bvalid <= 1'b1; + end + end + if (u_mmio_lp_if.bvalid && u_mmio_lp_if.bready) u_mmio_lp_if.bvalid <= 1'b0; + end + end + + // ---------------- sequence ---------------- + int s_cycle; + logic s_done; + initial begin +`ifdef HP_SMOKE_HEX + $readmemh(`HP_SMOKE_HEX, ram, 0); +`else + $fatal(1, "HP_SMOKE_HEX define missing"); +`endif + s_done = 1'b0; + repeat (20) @(posedge clk_i); + rst_n_i = 1'b1; + rst_lp_n_i = 1'b1; + repeat (20) @(posedge clk_i); + core_reset_i = 1'b0; + for (s_cycle = 0; s_cycle < MaxCycles; s_cycle++) begin + @(posedge clk_i); + if (s_saw_ready_q && (s_result_event_q != 32'd0)) begin + s_done = 1'b1; + break; + end + end + if (s_done) begin + $display("\nC906 booted the HP smoke payload: HP_SMOKE_READY printed,"); + $display("the mailbox ready event was posted, the GA2D start command was"); + $display("accepted, and the payload completed the GA2D phase with event %0d", + s_result_event_q); + $display("(the TB stubs the GA2D engine, so a fail event is expected here)"); + $display("HP_C906_BOOT_TEST_PASS"); + end else if (s_saw_ready_q) begin + $fatal(1, "payload stalled between ready and the GA2D-phase result event"); + end else begin + $fatal(1, "timeout waiting for the HP smoke ready mailbox event"); + end + $finish; + end +endmodule diff --git a/tests/test_axi4.py b/tests/test_axi4.py index 8a8f85f3..0694afa3 100644 --- a/tests/test_axi4.py +++ b/tests/test_axi4.py @@ -133,6 +133,90 @@ def test_axi4_downsizer_preserves_bursts_lanes_and_backpressure( assert "AXI4 64-to-32 downsizer test passed" in result.stdout +def test_axi4_downsizer_128to64_recombines_lanes_and_backpressure( + tmp_path: Path, +) -> None: + verilator = shutil.which("verilator") + if verilator is None: + return + + output = tmp_path / "axi4_downsizer_128to64_tb" + ccache_tmp = tmp_path / "ccache" + ccache_tmp.mkdir() + subprocess.run( + [ + verilator, + "--binary", + "--timing", + "-Wno-fatal", + "--top-module", + "axi4_downsizer_128to64_tb", + "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"), + "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"), + str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), + str(ROOT / "rtl/mini/top/axi4_downsizer_128to64.sv"), + str(ROOT / "tests/rtl/axi4_downsizer_128to64_tb.sv"), + "-Mdir", + str(tmp_path / "obj"), + "-o", + str(output), + ], + check=True, + text=True, + capture_output=True, + env={ + **os.environ, + "CCACHE_DIR": str(ccache_tmp), + "CCACHE_TEMPDIR": str(ccache_tmp), + }, + ) + result = subprocess.run([output], check=True, text=True, capture_output=True) + assert "AXI4 128-to-64 downsizer test passed" in result.stdout + + +def test_axi4_mmio_demux_routes_by_address_window_and_backpressure( + tmp_path: Path, +) -> None: + verilator = shutil.which("verilator") + if verilator is None: + return + + output = tmp_path / "axi4_mmio_demux_tb" + ccache_tmp = tmp_path / "ccache" + ccache_tmp.mkdir() + subprocess.run( + [ + verilator, + "--binary", + "--timing", + "-Wno-fatal", + "--top-module", + "axi4_mmio_demux_tb", + "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"), + "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"), + str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), + str(ROOT / "rtl/mini/top/axi4_mmio_demux.sv"), + str(ROOT / "tests/rtl/axi4_mmio_demux_tb.sv"), + "-Mdir", + str(tmp_path / "obj"), + "-o", + str(output), + ], + check=True, + text=True, + capture_output=True, + env={ + **os.environ, + "CCACHE_DIR": str(ccache_tmp), + "CCACHE_TEMPDIR": str(ccache_tmp), + }, + ) + result = subprocess.run([output], check=True, text=True, capture_output=True) + assert "AXI4 MMIO demux test passed" in result.stdout + + def test_axi4_word_bridge_supports_bursts_backpressure_and_errors(tmp_path: Path) -> None: verilator = shutil.which("verilator") if verilator is None: diff --git a/tests/test_ga2d_platform.py b/tests/test_ga2d_platform.py index 7854314c..9ac773b6 100644 --- a/tests/test_ga2d_platform.py +++ b/tests/test_ga2d_platform.py @@ -39,14 +39,14 @@ def test_ga2d_p5_preserves_the_real_private_axi64_master_and_irq_route() -> None "user_access": "none", } assert topology["apb4_periph_targets"][-2] == { - "slot": 28, + "slot": 26, "name": "ga2d", "timed_interface": "u_ga2d_apb4_if", "pure_interface": "u_ga2d_apb4_pure_if", "region": "APB4_GA2D", } assert topology["apb4_periph_targets"][-1] == { - "slot": 29, + "slot": 27, "name": "npu", "timed_interface": "u_npu_apb4_if", "pure_interface": "u_npu_apb4_pure_if", diff --git a/tests/test_hp_platform.py b/tests/test_hp_platform.py index b8be842a..7c5640d0 100644 --- a/tests/test_hp_platform.py +++ b/tests/test_hp_platform.py @@ -3,6 +3,7 @@ from __future__ import annotations import json +import os import shutil import subprocess from pathlib import Path @@ -18,33 +19,46 @@ ROOT = Path(__file__).resolve().parents[1] def test_hp_profile_and_locked_generator_contract() -> None: lock = json.loads((ROOT / "dependencies/dependencies.lock.json").read_text(encoding="utf-8")) - vexii = lock["sources"]["vexiiriscv"] - assert vexii["revision"] == "ef7da4134ff11ec6a681d0632123b232b853b046" - assert vexii["recursive"] is True - assert vexii["destination"].startswith(".cache/") + openc906 = lock["sources"]["openc906"] + assert openc906["url"] == "https://github.com/XUANTIE-RV/openc906.git" + assert len(openc906["revision"]) == 40 + assert openc906["destination"].startswith(".cache/") + assert openc906["license"] == "Apache-2.0" profile = (ROOT / "configs/ci/ihp130-hp.mk").read_text(encoding="utf-8") assert "HAVE_HP" in profile and "YES" in profile - assert "rv64imafdc_zicbom_max" in profile + assert "HP_CONFIG" not in profile assert "APP" in profile and "hp_boot" in profile assert "LINK_TYPE" in profile and "ld2_all_sram" in profile - generator = (ROOT / "scripts/vexiiriscv/GenerateRetroSocHp.scala").read_text( - encoding="utf-8" - ) + generator = (ROOT / "scripts/generate_openc906.py").read_text(encoding="utf-8") for requirement in ( - "param.xlen = 64", - "param.physicalWidth = 32", - 'param.addISA("m", "a", "f", "d", "c", "s", "u", "zicbom", "zicntr", "zihpm")', - "param.decoders = 2", - "param.lanes = 2", - "param.fetchL1Ways = 4", - "param.lsuL1Ways = 4", - "param.resetVector = 0x38000000L", - "param.plugins(hartId = 1)", + 'GENERATED_MODULE = "openC906"', + '"C906_RTL_FACTORY/gen_rtl/cpu/rtl/aq_sysio_kid.v"', + '"C906_RTL_FACTORY/gen_rtl/mmu/rtl/sysmap.h"', + "C906_asic_rtl.fl", + "tdt_dmi_top_rtl.fl", ): assert requirement in generator + # The Mini LP/HP contract keeps the HP core at hart 1; upstream hardwires + # mhartid to 0, so the build substitutes a reviewed override file. + override = (ROOT / "rtl/mini/ip_overrides/aq_sysio_kid.v").read_text(encoding="utf-8") + assert "assign sysio_core_hartid[2:0] = 3'd1;" in override + assert "b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f" in override + + # The sysmap override marks the Mini MMIO window (and the core-internal + # CLINT/PLIC window) strong-order non-cacheable per the C906 user manual. + sysmap = (ROOT / "rtl/mini/ip_overrides/sysmap.h").read_text(encoding="utf-8") + assert "`define SYSMAP_BASE_ADDR1 28'h30000" in sysmap + assert "`define SYSMAP_FLG1 5'b10011" in sysmap + + wrapper = (ROOT / "rtl/mini/top/hp_core_wrapper.sv").read_text(encoding="utf-8") + assert "HpResetVector = 40'h00_3800_0000" in wrapper + assert "HpApbBase = 40'h00_0800_0000" in wrapper + assert "openC906 u_openc906" in wrapper + assert "tdt_dmi_top u_tdt_dmi_top" in wrapper + def test_makefile_uses_path_resolved_sbt() -> None: makefile = (ROOT / "Makefile").read_text(encoding="utf-8") @@ -77,8 +91,13 @@ def test_hp_address_and_sysctrl_contract() -> None: (ROOT / "rtl/mini/address_map/memory_map.json").read_text(encoding="utf-8") ) regions = {region["symbol"]: region for region in document["regions"]} - assert regions["HP_ACLINT"]["base"] == "0x02000000" - assert regions["HP_PLIC"]["base"] == "0x0C000000" + # The C906 internal CLINT/PLIC window is decoded inside the core BIU and + # never reaches the SoC fabric; the map records it as reserved. + assert "HP_ACLINT" not in regions + assert "HP_PLIC" not in regions + assert regions["HP_C906_SYS"]["base"] == "0x08000000" + assert regions["HP_C906_SYS"]["size"] == "0x08000000" + assert regions["HP_C906_SYS"]["kind"] == "reserved" assert regions["APB4_UART1"]["base"] == "0x10018000" assert regions["APB4_HP_MAILBOX"]["base"] == "0x10019000" assert regions["APB4_RESOURCE_CTRL"]["base"] == "0x2000A000" @@ -89,15 +108,141 @@ def test_hp_address_and_sysctrl_contract() -> None: assert registers["DEBUG_SELECT"] == "0xAC" -def test_generated_vexii_rtl_is_not_tracked() -> None: +def test_generated_hp_core_rtl_is_not_tracked() -> None: tracked = subprocess.run( - ["git", "ls-files", "*vexii_riscv_hp_generated*"], + ["git", "ls-files", "*vexiiriscv_std_generated*", "*vexii_riscv_hp_generated*"], cwd=ROOT, check=True, capture_output=True, text=True, ).stdout assert tracked == "" + tracked = subprocess.run( + ["git", "ls-files", "*generated/openc906*"], + cwd=ROOT, + check=True, + capture_output=True, + text=True, + ).stdout + assert tracked == "" + + +def test_c906_boots_smoke_payload_in_focused_tb(tmp_path: Path) -> None: + """Boot the real HP smoke payload on the hp_core_wrapper integration.""" + verilator = shutil.which("verilator") + openc906 = ROOT / ".cache/retrosoc/sources/openc906" + if verilator is None or not (openc906 / "C906_RTL_FACTORY").is_dir(): + return + try: + cross = subprocess.run( + ["python3", str(ROOT / "scripts/hp_tools.py"), "--root", str(ROOT)], + check=True, + capture_output=True, + text=True, + ).stdout.strip() + except subprocess.CalledProcessError: + return + if not Path(cross + "gcc").is_file(): + return + + payload_dir = tmp_path / "payload" + subprocess.run( + [ + "python3", + str(ROOT / "scripts/build_hp_smoke.py"), + "--source", + str(ROOT / "app/ports/linux/smoke/start.S"), + "--linker", + str(ROOT / "app/ports/linux/smoke/linker.ld"), + "--output", + str(payload_dir), + "--cross", + cross, + ], + check=True, + capture_output=True, + text=True, + ) + payload = payload_dir / "images/hp_smoke.bin" + assert payload.is_file() + + generated = tmp_path / "generated" + subprocess.run( + [ + "python3", + str(ROOT / "scripts/generate_openc906.py"), + "--root", + str(ROOT), + "--source", + str(openc906), + "--output", + str(generated), + "--manifest", + str(generated / "manifest.json"), + "--lock", + str(ROOT / "dependencies/dependencies.lock.json"), + ], + check=True, + capture_output=True, + text=True, + ) + hex_image = tmp_path / "hp_smoke.hex" + hex_image.write_text( + "".join(f"{byte:02x}\n" for byte in payload.read_bytes()), encoding="utf-8" + ) + + common = ROOT / "rtl/managed/clusterip/common/rtl" + output = tmp_path / "hp_c906_boot_tb" + ccache_tmp = tmp_path / "ccache" + ccache_tmp.mkdir() + subprocess.run( + [ + verilator, + "--binary", + "--timing", + "-Wno-fatal", + "--top-module", + "hp_c906_boot_tb", + "-I" + str(common / "interface"), + "-I" + str(common / "utils"), + "-I" + str(common), + "-I" + str(common / "cdc"), + "-I" + str(ROOT / "rtl/mini/top"), + f"+define+HP_SMOKE_HEX=\"{hex_image}\"", + str(common / "interface/axi4_if.sv"), + str(common / "interface/axi4_addr_gen.sv"), + str(common / "utils/register.sv"), + str(common / "utils/xchecker.sv"), + str(common / "utils/spill_register.sv"), + str(common / "utils/bin2gray.sv"), + str(common / "utils/gray2bin.sv"), + str(common / "cdc/cdc_sync.sv"), + str(common / "cdc/cdc_rst_ctrlr.sv"), + str(common / "cdc/cdc_2phase.sv"), + str(common / "clkrst/rst_sync.sv"), + str(common / "clkrst/clk_int_div.sv"), + str(ROOT / "rtl/ip/util/soc_common_cdc.sv"), + str(ROOT / "rtl/mini/top/axi4_downsizer_128to64.sv"), + str(ROOT / "rtl/mini/top/axi4_mmio_demux.sv"), + str(ROOT / "rtl/mini/top/axi4_downsizer_64to32.sv"), + str(ROOT / "rtl/mini/top/axi4_address_gate.sv"), + str(ROOT / "rtl/mini/top/axi4_async_bridge.sv"), + str(ROOT / "rtl/mini/top/hp_core_wrapper.sv"), + "-f", + str(generated / "openc906.fl"), + str(ROOT / "tests/rtl/hp_c906_boot_tb.sv"), + "-Mdir", + str(tmp_path / "obj"), + "-o", + str(output), + ], + check=True, + text=True, + capture_output=True, + env={**os.environ, "CCACHE_DIR": str(ccache_tmp), "CCACHE_TEMPDIR": str(ccache_tmp)}, + ) + result = subprocess.run([output], check=True, text=True, capture_output=True) + assert "HP_C906_BOOT_TEST_PASS" in result.stdout def test_hp_smoke_payload_uses_hart1_platform_abi() -> None: @@ -108,8 +253,9 @@ def test_hp_smoke_payload_uses_hart1_platform_abi() -> None: assert "HP_SMOKE_READY" in source assert "0x10012000" in source assert "0x2000a000" in source.lower() - assert "cbo.clean" in source - assert "cbo.inval" in source + # C906 cache maintenance: custom-0 dcache.cva/dcache.iva (no Zicbom). + assert ".insn r 0x0b, 0x0, 0x01, x0, a0, x5" in source + assert ".insn r 0x0b, 0x0, 0x01, x0, a0, x6" in source assert source.count(".balign 64") >= 4 for marker in ("HP_GA2D_START", "HP_GA2D_PASS", "HP_GA2D_FAIL", "HP_GA2D_CACHE"): assert marker in source @@ -128,7 +274,7 @@ def test_hp_smoke_p5_npu_payload_has_stack_cache_and_polling_plan() -> None: assert "rs_npu_irq_enable(0U)" in acceptance assert "rs_npu_irq_ack(RS_NPU_IRQ_ALL)" in acceptance assert '"--extra-source"' in builder and '"--include"' in builder - assert '"-march=rv64imafdc_zicbom_zicsr_zifencei"' in builder + assert '"-march=rv64imafdc_zicsr_zifencei"' in builder assert '"-mabi=lp64d"' in builder assert "require_rv64_elf(elf)" in builder assert 'images / "hp_smoke.bin"' in builder @@ -140,8 +286,8 @@ def test_hp_apu_profile_and_payload_use_the_rv64_product_contract() -> None: builder = (ROOT / "scripts/build_hp_apu.py").read_text(encoding="utf-8") makefile = (ROOT / "Makefile").read_text(encoding="utf-8") - assert "HP_CONFIG := rv64imafdc_zicbom_max" in profile - assert '"-march=rv64imafdc_zicbom_zicsr_zifencei"' in builder + assert "HP_CONFIG" not in profile + assert '"-march=rv64imafdc_zicsr_zifencei"' in builder assert '"-mabi=lp64d"' in builder assert "require_rv64_elf(elf)" in builder assert 'images / "rootfs.cpio"' in builder @@ -161,7 +307,7 @@ def test_hp_apu_profile_and_payload_use_the_rv64_product_contract() -> None: check=False, ) assert completed.returncode == 0, completed.stdout + completed.stderr - assert "HP_CONFIG rv64imafdc_zicbom_max" in completed.stdout + assert "HP_CONFIG" not in completed.stdout def test_hp_smoke_simulation_requires_ga2d_result_and_cache_lifecycle_markers() -> None: @@ -219,7 +365,8 @@ def test_linux_build_uses_external_opensbi_platform_and_actual_initrd_end() -> N ).read_text(encoding="utf-8") assert "s_hart_index_to_id[] = {1U}" in platform assert "RETROSOC_HP_UART_BASE" in platform - assert "aclint_mtimer_cold_init" in platform + assert "retrosoc-hp-c906-clint" in platform + assert "aclint_mswi_cold_init" in platform def test_hp_linux_effective_config_is_fail_closed(tmp_path: Path) -> None: @@ -287,5 +434,6 @@ def test_hp_linux_device_tree_compiles_and_can_patch_initrd_end(tmp_path: Path) ).splitlines() assert "no-map" in properties dts = (ROOT / "app/ports/linux/linux/retrosoc_hp.dts").read_text(encoding="utf-8") - assert '"zicbom"' in dts - assert "riscv,cbom-block-size = <64>;" in dts + assert '"thead,c906"' in dts + assert '"thead,c900-plic"' in dts + assert '"thead,c900-clint"' in dts diff --git a/tests/test_mgmt_core_spec.py b/tests/test_mgmt_core_spec.py index 823b1937..5b59d11f 100644 --- a/tests/test_mgmt_core_spec.py +++ b/tests/test_mgmt_core_spec.py @@ -10,7 +10,7 @@ SOFTWARE_MAKE = ROOT / "rtl/mk/software.mk" MGMT_CORE = ROOT / "rtl/ip/core/mgmt_core_wrapper.sv" MGMT_DEBUG = ROOT / "rtl/ip/core/mgmt_debug_wrapper.sv" AHBL_TO_AXI4 = ROOT / "rtl/ip/interconnect/ahbl2axi4.sv" -VEXII_CONFIG = ROOT / "scripts/vexiiriscv/GenerateRetroSocHp.scala" +VEXII_CONFIG = ROOT / "scripts/vexiiriscv/GenerateRetroSocStd.scala" def test_booter_prints_the_fixed_hazard3_specification() -> None: @@ -75,34 +75,24 @@ def test_booter_prints_the_fixed_hazard3_specification() -> None: def test_booter_prints_present_hp_core_specification() -> None: booter = BOOTER.read_text(encoding="utf-8") - vexii_config = VEXII_CONFIG.read_text(encoding="utf-8") for text in ( "High-Performance-Core Specification:", - "Core: VexiiRiscv(hart 1), dual-issue in-order", - "Base: RV64IMAFDC_Zicbom_Zicntr_Zihpm", - "Mode: M/S/U; Sv39 MMU, 9-bit ASID", - "Protection: 16 PMP regions, 4 KiB granularity", - "L1: separate 16 KiB, 4-way instruction and data caches", - "Maintenance: 64-byte Zicbom CBO; no hardware coherency", - "Bus: native AXI64 I/D/MMIO; MMIO downsized to AXI32", - "Embedded RISC-V JTAG, 4 triggers", + "Core: T-Head OpenC906(hart 1), dual-issue in-order", + "Base: RV64IMAFDC_Zicsr_Zifencei (RV64GC)", + "Mode: M/S/U; Sv39 MMU", + "IRQ: internal CLINT/PLIC (T-Head c900 layout)", + "PLIC: 0x08000000; SoC external source n -> ID n+16", + "CLINT: 0x0c000000; MSIP/MTIMECMP/SSIP/STIMECMP", + "No MMIO mtime; software reads the time CSR", + "LP->HP notification: mailbox doorbell (PLIC ID 18)", + "Bus: AXI4 via core BIU; MMIO downsized to AXI32", ): assert text in booter assert "rs_sysctrl_get_hp_status(&status)" in booter assert "!status.present" in booter - for parameter in ( - 'param.addISA("m", "a", "f", "d", "c", "s", "u", "zicbom", "zicntr", "zihpm")', - "param.asidWidth = 9", - "param.decoders = 2", - "param.lanes = 2", - "param.fetchL1Sets = 64", - "param.fetchL1Ways = 4", - "param.lsuL1Sets = 64", - "param.lsuL1Ways = 4", - "param.pmpParam.pmpSize = 16", - "param.pmpParam.granularity = 4096", - "param.privParam.debugTriggers = 4", - ): - assert parameter in vexii_config + + # The retired VexiiRiscv Mini configuration is preserved as the frozen + # Std-series generator asset (covered by tests/test_std_vexiiriscv.py). + assert VEXII_CONFIG.is_file() diff --git a/tests/test_npu_p6.py b/tests/test_npu_p6.py index d91bc324..846a6f40 100644 --- a/tests/test_npu_p6.py +++ b/tests/test_npu_p6.py @@ -32,7 +32,8 @@ def test_p6_shard_parser_invalidates_image_before_header_and_payload_reads() -> runner = (ROOT / "app/benchmark/npu/npu_p6_runner.c").read_text(encoding="utf-8") assert "rs_npu_p6_invalidate_range(image, RS_NPU_P6_HEADER_BYTES);" in runner assert "rs_npu_p6_invalidate_range(&image[RS_NPU_P6_HEADER_BYTES], payload_bytes);" in runner - assert '"cbo.inval 0(%0)"' in runner + # C906 cache maintenance: custom-0 dcache.iva (replaces the Zicbom cbo.inval). + assert '".insn r 0x0b, 0x0, 0x01, x0, %0, x6"' in runner def test_p6_first_case_has_bounded_stage_markers_without_changing_case_schema() -> None: @@ -156,7 +157,6 @@ def test_verilator_report_uses_matching_variant_manifests(tmp_path: Path) -> Non "MINI_MODE": "PRODUCT", "APP": "hp_boot", "SIMU": "VERILATOR", - "HP_CONFIG": "rv64imafdc_zicbom_max", "EXT_CLK_HZ": "72000000", } for variant in variants.values(): @@ -170,7 +170,7 @@ def test_verilator_report_uses_matching_variant_manifests(tmp_path: Path) -> Non "EXT_CLK_HZ": 72_000_000, } - mismatched = {**configuration, "HP_CONFIG": "rv32imafdc_zicbom_max"} + mismatched = {**configuration, "APP": "shell"} (variants["vww"] / "meta/manifest.json").write_text( json.dumps({"configuration": mismatched}), encoding="utf-8" ) diff --git a/tests/test_publication_dev_snapshot.py b/tests/test_publication_dev_snapshot.py index ba44f9e3..82030317 100644 --- a/tests/test_publication_dev_snapshot.py +++ b/tests/test_publication_dev_snapshot.py @@ -26,7 +26,9 @@ def test_refrozen_structure_covers_ga2d_without_duplicate_register_ownership(dat assert contract["ip_ids"].index("ga2d") == contract["ip_ids"].index("jpeg") + 1 assert contract["ip_ids"].index("apu") == contract["ip_ids"].index("ga2d") + 1 assert contract["ip_ids"].index("npu") == contract["ip_ids"].index("apu") + 1 - assert sum(len(group["items"]) for group in data["overview_groups"]) == 45 + # HP ACLINT/HP PLIC left the inventory with the OpenC906 migration: both are + # core-internal units, not separately owned SoC register windows. + assert sum(len(group["items"]) for group in data["overview_groups"]) == 43 ga2d = next(row for row in data["regions"] if row["symbol"] == "APB4_GA2D") assert (ga2d["base"], ga2d["size"], ga2d["kind"]) == (0x10012000, 4096, "active") assert len(data["policies"]) == 10 diff --git a/tests/test_publication_diagrams.py b/tests/test_publication_diagrams.py index 720a464b..73c1ab92 100644 --- a/tests/test_publication_diagrams.py +++ b/tests/test_publication_diagrams.py @@ -82,7 +82,7 @@ def test_protocol_field_order_is_checked_even_with_complete_coverage(data): ("rtl/ip/serial/uart_reg.sv", "TxFifoDepth = 64", "TxFifoDepth = 32"), ("scripts/apu_isa.py", "(self.dst, 4, 48)", "(self.dst, 4, 47)"), ("scripts/apu_isa.py", "APUMC_MAX_INSTRUCTIONS = APUMC_MAX_INSTRUCTIONS_V1", "APUMC_MAX_INSTRUCTIONS = 4096"), - ("app/ports/linux/linux/retrosoc_hp.dts", "riscv,cbom-block-size = <64>", "riscv,cbom-block-size = <128>"), + ("app/ports/linux/smoke/start.S", ".insn r 0x0b, 0x0, 0x01, x0, a0, x5", ".insn r 0x0b, 0x0, 0x02, x0, a0, x5"), ("rtl/ip/security/apb4_crypto.sv", "logic [31:0] s_wdata;", "logic [63:0] s_wdata;"), ]) def test_source_drift_requires_diagram_review(source_tree, data, relative, old, new): diff --git a/tests/test_publication_implementation.py b/tests/test_publication_implementation.py index 82b285bb..eb0efe81 100644 --- a/tests/test_publication_implementation.py +++ b/tests/test_publication_implementation.py @@ -26,11 +26,13 @@ def test_cpu_configuration_does_not_substitute_firmware_flags(spec): assert result["lp"]["CSR_M_MANDATORY"] == "1" assert result["build"]["ISA"] == "RV32IM" and result["build"]["HAVE_CSR"] == "NO" assert result["lp"]["PMP_REGIONS"] == "0" - assert result["hp"]["pmpParam.pmpSize"] == "16" - assert result["hp"]["fetchL1Sets"] == "64" and result["hp"]["fetchL1Ways"] == "4" - assert result["hp_cache_capacity"].startswith("Unconfirmed") - sram_pma = next(row for row in result["pma"] if row["base"] == "0x30000000") - assert sram_pma["bytes"] == 128 * 1024 # Attribute envelope, not fitted SRAM capacity. + assert result["hp"]["resetVector"] == "0x38000000" + assert result["hp"]["sysWindowBase"] == "0x08000000" + assert result["hp"]["coreAxiDataWidth"] == "128" and result["hp"]["fabricAxiDataWidth"] == "64" + assert result["hp"]["hartId"] == "1" and result["hp"]["externalInterruptSources"] == "16" + assert result["hp_isa_base"] == "rv64i" and result["hp_mmu"] == "sv39" + assert "zicbom" not in result["hp_isa"] + assert "32 KiB" in result["hp_cache_capacity"] @pytest.mark.parametrize("text", [ @@ -50,8 +52,9 @@ def test_lp_parameters_ignore_commented_out_instance(): def test_duplicate_hp_assignment_is_rejected(): + wrapper = "localparam logic [39:0] HpResetVector = 40'h00_3800_0000;\n" * 2 with pytest.raises(ValueError, match="duplicate HP"): - ir.hp_parameters('param.xlen = 32\nparam.xlen = 64\nparam.addISA("m")') + ir.hp_parameters(wrapper, "") def test_required_processor_parameter_cannot_disappear(spec): diff --git a/tests/test_publication_programming.py b/tests/test_publication_programming.py index ff91ba4b..a9b8c235 100644 --- a/tests/test_publication_programming.py +++ b/tests/test_publication_programming.py @@ -31,7 +31,9 @@ def test_complete_dma_routes_and_native_credit_boundary(spec): assert [r["number"] for r in result["dma_routes"]] == list(range(14)) assert [r["number"] for r in result["channels"]] == list(range(8)) assert result["read_credits"] == [4, 4, 4, 2, 2, 1, 1, 4, 1, 1] - assert result["write_credits"] == [0, 2, 2, 1, 1, 1, 1, 2, 1, 1] + # The merged HP port (slot 0) holds the retired data port's two write + # credits; the retired slot 1 holds none. + assert result["write_credits"] == [2, 0, 2, 1, 1, 1, 1, 2, 1, 1] def test_jpeg_bounded_admission_publication_facts_match_executable_credits(spec): diff --git a/tests/test_publication_registers.py b/tests/test_publication_registers.py index 396c9843..022f4293 100644 --- a/tests/test_publication_registers.py +++ b/tests/test_publication_registers.py @@ -52,9 +52,9 @@ def test_repeated_banks_keep_their_real_instance_ranges(reference): 0x40, 16, ) - clint = {g["id"]: g for g in reference["aclint"]["groups"]} - assert clint["compare"]["count"] == 2 - assert clint["compare"]["stride"] == 8 + pwm = {g["id"]: g for g in reference["pwm"]["groups"]} + assert pwm["channel"]["count"] == 4 + assert pwm["channel"]["stride"] == 64 def test_gpio_windows_are_not_collapsed_into_one_register_table(reference): diff --git a/tests/test_publication_retrieval.py b/tests/test_publication_retrieval.py index 3ced38cb..c0bb84a8 100644 --- a/tests/test_publication_retrieval.py +++ b/tests/test_publication_retrieval.py @@ -51,9 +51,9 @@ def test_array_addresses_include_group_base_exactly_once(data): assert row["first"] == 0x1000A128 assert row["last"] == 0x1000A4A8 assert (row["stride"], row["count"], row["offset_hex"]) == (0x80, 8, "0x128") - plic = bank(result, "HP_PLIC") - claim = next(r for r in plic["rows"] if r["key"] == "context.CLAIM_COMPLETE") - assert (claim["first"], claim["last"]) == (0x0C200004, 0x0C201004) + usb2 = bank(result, "APB4_USB2") + channel = next(r for r in usb2["rows"] if r["key"] == "channel.CFG") + assert (channel["first"], channel["last"]) == (0x10016500, 0x100168C0) def test_gpio_common_discovery_decode_and_mpw_scope(data): diff --git a/tests/test_publication_software.py b/tests/test_publication_software.py index 87e8dec7..781f8e21 100644 --- a/tests/test_publication_software.py +++ b/tests/test_publication_software.py @@ -136,7 +136,7 @@ def test_unreviewed_return_expression_is_not_silently_omitted(source_tree): def test_linux_platform_uses_source_values_and_order(): data = sr.linux_platform(ROOT) - assert (data["hart_id"], data["timebase_hz"], data["cbom_bytes"]) == (1, 1000000, 64) + assert (data["hart_id"], data["timebase_hz"]) == (1, 1000000) assert data["initrd_start"] == data["initrd_template_end"] == 0x39000000 assert data["ready_writes"][-1] == { "address": "0x1001902C", "value": "0x00000001", @@ -148,7 +148,7 @@ def test_linux_platform_uses_source_values_and_order(): @pytest.mark.parametrize("relative,old,new", [ ("app/ports/linux/linux/retrosoc_hp.dts", "cpu@1", "cpu@0"), ("app/ports/linux/linux/retrosoc_hp.dts", "linux,initrd-end = <0x39000000>", "linux,initrd-end = <0x39100000>"), - ("app/ports/linux/opensbi/retrosoc_hp/platform.c", ".mtime_freq = 1000000UL", ".mtime_freq = 2000000UL"), + ("app/ports/linux/opensbi/retrosoc_hp/platform.c", ".timer_freq = 1000000UL", ".timer_freq = 2000000UL"), ("app/ports/linux/hp_ready.c", "0x4C4E5801", "0x4C4E5802"), ]) def test_linux_consistency_and_ready_event_drift_fail(source_tree, relative, old, new): diff --git a/tests/test_soc_topology.py b/tests/test_soc_topology.py index b82c86d7..7e78791d 100644 --- a/tests/test_soc_topology.py +++ b/tests/test_soc_topology.py @@ -80,7 +80,7 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) - ).read_text(encoding="utf-8") filelist = (tmp_path / "soc_topology.fl").read_text(encoding="utf-8") - assert interfaces.count("apb4_if u_") == 28 + assert interfaces.count("apb4_if u_") == 26 assert "nmi_if" not in interfaces assert "soc_nmi" not in interfaces assert "assign s_psel_comb[17] = `SOC_ADDR_IS_APB4_I2C1(s_decode_addr);" in routes @@ -93,12 +93,10 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) - assert "assign s_psel_comb[20] = `SOC_ADDR_IS_APB4_USB2(s_decode_addr);" in routes assert "assign s_psel_comb[22] = `SOC_ADDR_IS_APB4_UART1(s_decode_addr);" in routes assert "assign s_psel_comb[23] = `SOC_ADDR_IS_APB4_HP_MAILBOX(s_decode_addr);" in routes - assert "assign s_psel_comb[24] = `SOC_ADDR_IS_HP_ACLINT(s_decode_addr);" in routes - assert "assign s_psel_comb[25] = `SOC_ADDR_IS_HP_PLIC(s_decode_addr);" in routes - assert "assign s_psel_comb[26] = `SOC_ADDR_IS_APB4_JPEG(s_decode_addr);" in routes - assert "assign s_psel_comb[27] = `SOC_ADDR_IS_APB4_APU(s_decode_addr);" in routes - assert "assign s_psel_comb[28] = `SOC_ADDR_IS_APB4_GA2D(s_decode_addr);" in routes - assert "assign s_psel_comb[29] = `SOC_ADDR_IS_APB4_NPU(s_decode_addr);" in routes + assert "assign s_psel_comb[24] = `SOC_ADDR_IS_APB4_JPEG(s_decode_addr);" in routes + assert "assign s_psel_comb[25] = `SOC_ADDR_IS_APB4_APU(s_decode_addr);" in routes + assert "assign s_psel_comb[26] = `SOC_ADDR_IS_APB4_GA2D(s_decode_addr);" in routes + assert "assign s_psel_comb[27] = `SOC_ADDR_IS_APB4_NPU(s_decode_addr);" in routes assert "apb4_if u_ga2d_apb4_if (clk_i, rst_n_i);" in interfaces assert "apb4_if u_npu_apb4_if (clk_i, rst_n_i);" in interfaces assert gpio.count("// GPIO") == 64 @@ -204,8 +202,8 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) - assert "SOC_DATA_POLICY_WRITE_TARGET_MASK" in data_policy assert "SOC_DATA_POLICY_ALLOW_INSTRUCTION" in data_policy assert "SOC_DATA_POLICY_REQUIRE_NONCACHEABLE" in data_policy - assert "`define SOC_DATA_POLICY_READ_TARGET_MASK 50'b11111111111111111111111111111111111111111111111111" in data_policy - assert "`define SOC_DATA_POLICY_WRITE_TARGET_MASK 50'b01111011110111101111011110111101111011110111100000" in data_policy + assert "`define SOC_DATA_POLICY_READ_TARGET_MASK 50'b11111111111111111111111111111111111111110000011111" in data_policy + assert "`define SOC_DATA_POLICY_WRITE_TARGET_MASK 50'b01111011110111101111011110111101111011110000001111" in data_policy assert "`define SOC_DATA_POLICY_ALLOW_INSTRUCTION 10'b0000000001" in data_policy assert "`define SOC_DATA_POLICY_REQUIRE_NONCACHEABLE 10'b1111111100" in data_policy assert "RS_SOC_IRQ_VECTOR_WIDTH UINT32_C(64)" in irq_metadata @@ -276,8 +274,8 @@ def test_ga2d_p4_topology_preserves_the_private_master_policy_and_active_shell() policies = document["data_master_policies"] assert [policy["name"] for policy in policies] == [ - "hp_icache", - "hp_dcache", + "hp_mem", + "hp_retired", "dma", "io_gateway_a", "io_gateway_b", @@ -305,10 +303,10 @@ def test_ga2d_p4_topology_preserves_the_private_master_policy_and_active_shell() "require_noncacheable": True, } assert document["apb4_periph_targets"][-2]["name"] == "ga2d" - assert document["apb4_periph_targets"][-2]["slot"] == 28 + assert document["apb4_periph_targets"][-2]["slot"] == 26 assert document["apb4_periph_targets"][-2]["region"] == "APB4_GA2D" assert document["apb4_periph_targets"][-1]["name"] == "npu" - assert document["apb4_periph_targets"][-1]["slot"] == 29 + assert document["apb4_periph_targets"][-1]["slot"] == 27 assert document["apb4_periph_targets"][-1]["region"] == "APB4_NPU" assert document["interrupts"][-2]["name"] == "ga2d" assert document["interrupts"][-2]["group_bit"] == 24 @@ -331,9 +329,9 @@ def test_apu_p1_fixed_resource_and_hp_irq_allocations() -> None: assert "s_hp_plic_source[12] = resource_irq_hp_i[8];" in periph assert "s_ga2d_irq_raw," in periph assert ".ResourceCount(10)" in system - assert ".apu_owner_i (s_resource_owner[7])" in top - assert ".apu_quiesce_i (s_resource_quiesce[7])" in top - assert ".apu_reset_i (s_resource_reset[7])" in top + assert ".apu_owner_i (s_resource_owner[7])" in top + assert ".apu_quiesce_i (s_resource_quiesce[7])" in top + assert ".apu_reset_i (s_resource_reset[7])" in top compact_top = "".join(top.split()) assert ".ga2d_quiesce_i(s_resource_quiesce[8])" in compact_top assert ".ga2d_reset_i(s_resource_reset[8])" in compact_top diff --git a/tests/test_std_vexiiriscv.py b/tests/test_std_vexiiriscv.py new file mode 100644 index 00000000..aef90614 --- /dev/null +++ b/tests/test_std_vexiiriscv.py @@ -0,0 +1,52 @@ +"""Std-series VexiiRiscv generator preservation contract tests.""" + +from __future__ import annotations + +import json +import re +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[1] +GENERATOR = ROOT / "scripts/vexiiriscv/GenerateRetroSocStd.scala" +DRIVER = ROOT / "scripts/generate_vexiiriscv.py" +LOCK = ROOT / "dependencies/dependencies.lock.json" + + +def test_std_generator_scala_preserves_the_frozen_hp_configuration() -> None: + assert GENERATOR.is_file() + generator = GENERATOR.read_text(encoding="utf-8") + + assert "object GenerateRetroSocStd extends App" in generator + assert 'setDefinitionName("vexiiriscv_std_generated")' in generator + assert "param.resetVector = 0x38000000L" in generator + assert "param.plugins(hartId = 1)" in generator + assert "param.xlen = 64" in generator + + for base, size in ( + ("0x00000000L", "0x01000000L"), + ("0x02000000L", "0x2E000000L"), + ("0x30000000L", "0x00020000L"), + ("0x38000000L", "0x04000000L"), + ("0x40000000L", "0x02000000L"), + ("0x48000000L", "0x08000000L"), + ): + assert f"SizeMapping({base}, {size})" in generator + + +def test_std_driver_pins_the_std_generator_and_module_names() -> None: + driver = DRIVER.read_text(encoding="utf-8") + + assert 'GENERATOR_CLASS = "vexiiriscv.GenerateRetroSocStd"' in driver + assert 'GENERATED_MODULE = "vexiiriscv_std_generated"' in driver + assert '"configuration": "rv64imafdc_zicbom_max"' in driver + assert '"product": "std"' in driver + assert "GenerateRetroSocStd.scala" in driver + + +def test_vexiiriscv_lock_entry_remains_a_locked_std_asset() -> None: + lock = json.loads(LOCK.read_text(encoding="utf-8")) + vexii = lock["sources"]["vexiiriscv"] + + assert re.fullmatch(r"[0-9a-f]{40}", vexii["revision"]) + assert vexii["destination"].startswith(".cache/") From ef8f7459a3b158c736ded730448c9d92351fade2 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 10 Oct 2026 16:16:11 +0800 Subject: [PATCH 02/31] feat: add HP release window transaction retention test and update documentation --- docs/lp-hp-architecture.md | 8 +- tests/rtl/hp_release_window_tb.sv | 392 ++++++++++++++++++++++++++++++ tests/test_axi4.py | 40 +++ 3 files changed, 439 insertions(+), 1 deletion(-) create mode 100644 tests/rtl/hp_release_window_tb.sv diff --git a/docs/lp-hp-architecture.md b/docs/lp-hp-architecture.md index e01c0968..578aa816 100644 --- a/docs/lp-hp-architecture.md +++ b/docs/lp-hp-architecture.md @@ -215,7 +215,13 @@ files remain available only for optional PLL experiments. ## Evidence boundary Behavioral RTL, firmware, directed data-plane/lifecycle/clock tests, manifest -parity, and quality checks are the evidence for this implementation. HP stop +parity, and quality checks are the evidence for this implementation. The +directed `tests/rtl/hp_release_window_tb.sv` composes the exact release path +(AON lifecycle controller, HP-domain CDC synchronizers, MMIO address gate, and +HP-to-LP async bridge) and proves that same-cycle release-window writes and +reads complete intact, that a full stop/re-release cycle leaves the chain +clean, and that a gate-held transaction during drain is dropped without +contaminating the next release window. HP stop implements a pre-drain cache request/ACK window, drain, coordinated flush, actual-release status, and bounded forced reset. OpenC906 uses 64-byte cache lines with T-Head custom-0 `dcache.cva`/`dcache.iva` maintenance instructions diff --git a/tests/rtl/hp_release_window_tb.sv b/tests/rtl/hp_release_window_tb.sv new file mode 100644 index 00000000..2e960056 --- /dev/null +++ b/tests/rtl/hp_release_window_tb.sv @@ -0,0 +1,392 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 + +// HP lifecycle release-window transaction retention test. Composes the exact +// release path used by retrosoc.sv: the AON lifecycle controller, the two +// cdc_sync chains into the HP domain, the MMIO address gate and the HP-to-LP +// async bridge, and proves that writes/reads issued in the same HP cycle as +// the release completes intact, that a full stop/re-release cycle leaves the +// chain clean, and that a transaction held at the gate during drain is +// dropped without corrupting the next release window. + +`timescale 1ns / 1ps + +`include "axi4_define.svh" + +module hp_release_window_tb; + logic clk_hp_i = 1'b0; + logic clk_lp_i = 1'b0; + logic clk_aon_i = 1'b0; + logic rst_hp_n_i = 1'b0; + logic rst_lp_n_i = 1'b0; + logic rst_aon_n_i = 1'b0; + + logic release_req_i = 1'b0; + logic hp_idle_i = 1'b1; + logic flush_busy_i; + logic cache_clean_i = 1'b0; + logic s_cdc_clear_busy; + + logic s_release_aon; + logic s_block_aon; + logic s_flush_aon; + logic s_hp_release_hp; + logic s_hp_block_hp; + logic s_hp_recovery_hp; + logic s_hp_flush_hp; + + always #5 clk_hp_i = ~clk_hp_i; + always #17 clk_lp_i = ~clk_lp_i; + always #40 clk_aon_i = ~clk_aon_i; + + // As in the SoC, the lifecycle controller's flush-busy input tracks the + // bridge's clear-busy report: flush stays asserted until the bridge has + // fully cycled its warm flush. + assign flush_busy_i = s_cdc_clear_busy; + + // The exact lifecycle wiring from retrosoc.sv. + hp_lifecycle_controller u_dut_lifecycle ( + .clk_i (clk_aon_i), + .rst_n_i (rst_aon_n_i), + .release_req_i (release_req_i), + .hp_idle_i (hp_idle_i), + .flush_busy_i (flush_busy_i), + .cache_clean_i (cache_clean_i), + .timeout_i (16'd64), + .hp_release_o (s_release_aon), + .block_new_o (s_block_aon), + .flush_o (s_flush_aon), + .cache_request_o(), + .draining_o (), + .forced_fault_o () + ); + + cdc_sync #( + .STAGE (2), + .DATA_WIDTH(1) + ) u_hp_release_sync ( + .clk_i (clk_hp_i), + .rst_n_i(rst_hp_n_i), + .dat_i (s_release_aon), + .dat_o (s_hp_release_hp) + ); + + cdc_sync #( + .STAGE (2), + .DATA_WIDTH(3) + ) u_hp_lifecycle_control_sync ( + .clk_i (clk_hp_i), + .rst_n_i(rst_hp_n_i), + .dat_i ({s_block_aon, 1'b0, s_flush_aon}), + .dat_o ({s_hp_block_hp, s_hp_recovery_hp, s_hp_flush_hp}) + ); + + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_gate_src_if ( + .aclk (clk_hp_i), + .aresetn(rst_hp_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_gate_sink_if ( + .aclk (clk_hp_i), + .aresetn(rst_hp_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_lp_if ( + .aclk (clk_lp_i), + .aresetn(rst_lp_n_i) + ); + + axi4_address_gate u_dut_gate ( + .clk_i (clk_hp_i), + .rst_n_i (rst_hp_n_i), + .block_new_i (s_hp_block_hp), + .clear_i (s_hp_flush_hp), + .source (u_gate_src_if), + .sink (u_gate_sink_if), + .idle_o (), + .write_pending_o() + ); + + axi4_async_bridge #( + .DataWidth(32), + .IdWidth (1) + ) u_dut_cdc ( + .src_clk_i (clk_hp_i), + .src_rst_n_i (rst_hp_n_i), + .dst_clk_i (clk_lp_i), + .dst_rst_n_i (rst_lp_n_i), + .clear_i (s_hp_flush_hp), + .clear_busy_o(s_cdc_clear_busy), + .epoch_o (), + .src_axi4 (u_gate_sink_if), + .dst_axi4 (u_lp_if) + ); + + // ---------------- LP-side slave stub ---------------- + logic [31:0] s_stub_writes [8]; + int s_stub_write_count; + logic s_wr_active_q; + logic [31:0] s_wr_addr_q; + logic s_rd_active_q; + logic [31:0] s_rd_addr_q; + + assign u_lp_if.bid = '0; + assign u_lp_if.buser = '0; + assign u_lp_if.bresp = `AXI4_RESP_OKAY; + assign u_lp_if.rid = '0; + assign u_lp_if.ruser = '0; + assign u_lp_if.rresp = `AXI4_RESP_OKAY; + + always_ff @(posedge clk_lp_i or negedge rst_lp_n_i) begin + if (!rst_lp_n_i) begin + u_lp_if.awready <= 1'b0; + u_lp_if.wready <= 1'b0; + u_lp_if.bvalid <= 1'b0; + u_lp_if.arready <= 1'b0; + u_lp_if.rvalid <= 1'b0; + u_lp_if.rlast <= 1'b0; + u_lp_if.rdata <= '0; + s_wr_active_q <= 1'b0; + s_wr_addr_q <= '0; + s_rd_active_q <= 1'b0; + s_rd_addr_q <= '0; + s_stub_write_count <= 0; + end else begin + if (!s_wr_active_q && !u_lp_if.bvalid) begin + u_lp_if.awready <= 1'b1; + if (u_lp_if.awvalid && u_lp_if.awready) begin + s_wr_active_q <= 1'b1; + s_wr_addr_q <= u_lp_if.awaddr; + u_lp_if.awready <= 1'b0; + end + end + u_lp_if.wready <= s_wr_active_q; + if (s_wr_active_q && u_lp_if.wvalid && u_lp_if.wready) begin + if (s_stub_write_count < 8) begin + s_stub_writes[s_stub_write_count] <= {s_wr_addr_q[15:0], u_lp_if.wdata[15:0]}; + s_stub_write_count <= s_stub_write_count + 1; + end + if (u_lp_if.wlast) begin + s_wr_active_q <= 1'b0; + u_lp_if.bvalid <= 1'b1; + end + end + if (u_lp_if.bvalid && u_lp_if.bready) u_lp_if.bvalid <= 1'b0; + + if (!s_rd_active_q && !u_lp_if.rvalid) begin + u_lp_if.arready <= 1'b1; + if (u_lp_if.arvalid && u_lp_if.arready) begin + s_rd_active_q <= 1'b1; + s_rd_addr_q <= u_lp_if.araddr; + u_lp_if.arready <= 1'b0; + u_lp_if.rvalid <= 1'b1; + u_lp_if.rdata <= 32'hC0DE_0000 ^ u_lp_if.araddr; + u_lp_if.rlast <= (u_lp_if.arlen == 8'd0); + end + end else if (u_lp_if.rvalid && u_lp_if.rready) begin + if (u_lp_if.rlast) begin + u_lp_if.rvalid <= 1'b0; + u_lp_if.rlast <= 1'b0; + s_rd_active_q <= 1'b0; + end else begin + s_rd_addr_q <= s_rd_addr_q + 32'd4; + u_lp_if.rdata <= 32'hC0DE_0000 ^ (s_rd_addr_q + 32'd4); + u_lp_if.rlast <= '0; + end + end + end + end + + // ---------------- HP-side BFM ---------------- + logic s_bvalid_seen; + logic [31:0] s_last_rdata; + logic [31:0] s_last_rdata_addr; + + task automatic bfm_idle; + begin + u_gate_src_if.awid = '0; + u_gate_src_if.awaddr = '0; + u_gate_src_if.awlen = '0; + u_gate_src_if.awsize = 3'd2; + u_gate_src_if.awburst = `AXI4_BURST_TYPE_INCR; + u_gate_src_if.awlock = '0; + u_gate_src_if.awcache = '0; + u_gate_src_if.awprot = '0; + u_gate_src_if.awqos = '0; + u_gate_src_if.awregion = '0; + u_gate_src_if.awuser = '0; + u_gate_src_if.awvalid = 1'b0; + u_gate_src_if.wdata = '0; + u_gate_src_if.wstrb = '0; + u_gate_src_if.wlast = 1'b0; + u_gate_src_if.wuser = '0; + u_gate_src_if.wvalid = 1'b0; + u_gate_src_if.bready = 1'b0; + u_gate_src_if.arid = '0; + u_gate_src_if.araddr = '0; + u_gate_src_if.arlen = '0; + u_gate_src_if.arsize = 3'd2; + u_gate_src_if.arburst = `AXI4_BURST_TYPE_INCR; + u_gate_src_if.arlock = '0; + u_gate_src_if.arcache = '0; + u_gate_src_if.arprot = '0; + u_gate_src_if.arqos = '0; + u_gate_src_if.arregion = '0; + u_gate_src_if.aruser = '0; + u_gate_src_if.arvalid = 1'b0; + u_gate_src_if.rready = 1'b0; + end + endtask + + task automatic bfm_write(input logic [31:0] addr, input logic [31:0] data); + begin + @(negedge clk_hp_i); + u_gate_src_if.awaddr = addr; + u_gate_src_if.awvalid = 1'b1; + u_gate_src_if.wdata = data; + u_gate_src_if.wstrb = 4'hF; + u_gate_src_if.wlast = 1'b1; + u_gate_src_if.wvalid = 1'b1; + u_gate_src_if.bready = 1'b1; + do @(posedge clk_hp_i); while (!u_gate_src_if.awready); + @(negedge clk_hp_i); + u_gate_src_if.awvalid = 1'b0; + do @(posedge clk_hp_i); while (!u_gate_src_if.wready); + @(negedge clk_hp_i); + u_gate_src_if.wvalid = 1'b0; + wait (u_gate_src_if.bvalid); + if (u_gate_src_if.bresp != `AXI4_RESP_OKAY) $fatal(1, "write response not OKAY"); + @(negedge clk_hp_i); + u_gate_src_if.bready = 1'b0; + end + endtask + + task automatic bfm_read(input logic [31:0] addr); + begin + @(negedge clk_hp_i); + u_gate_src_if.araddr = addr; + u_gate_src_if.arvalid = 1'b1; + u_gate_src_if.rready = 1'b1; + do @(posedge clk_hp_i); while (!u_gate_src_if.arready); + @(negedge clk_hp_i); + u_gate_src_if.arvalid = 1'b0; + wait (u_gate_src_if.rvalid); + if (!u_gate_src_if.rlast || u_gate_src_if.rresp != `AXI4_RESP_OKAY) begin + $fatal(1, "read response malformed"); + end + s_last_rdata = u_gate_src_if.rdata; + s_last_rdata_addr = addr; + @(negedge clk_hp_i); + u_gate_src_if.rready = 1'b0; + end + endtask + + task automatic complete_stop; + begin + // Drive the exact lifecycle stop handshake: the flush-busy level comes + // from the bridge's clear-busy report, as on the SoC data plane. + @(negedge clk_aon_i); + release_req_i = 1'b0; + wait (!s_release_aon); + end + endtask + + // Watchdog: the whole test must complete well within this budget. + initial begin + #5_000_000; + $fatal(1, "global timeout"); + end + + initial begin + bfm_idle(); + s_stub_write_count = 0; + repeat (4) @(posedge clk_hp_i); + rst_hp_n_i = 1'b1; + rst_lp_n_i = 1'b1; + rst_aon_n_i = 1'b1; + repeat (4) @(posedge clk_aon_i); + + // Scenario a+b: write and read issued in the same HP cycle that the + // synced release asserts. + release_req_i = 1'b1; + wait (s_hp_release_hp); + fork + bfm_write(32'h1001_9000, 32'hA5A5_0001); + bfm_read(32'h1001_8000); + join + if (s_last_rdata != (32'hC0DE_0000 ^ 32'h1001_8000)) + $fatal(1, "release-window read data mismatch"); + repeat (4) @(posedge clk_lp_i); + if (s_stub_write_count != 1 || s_stub_writes[0] != 32'h9000_0001) begin + $fatal(1, "release-window write did not reach the LP side intact"); + end + + // Full stop, then re-release; the chain must be clean. + complete_stop(); + repeat (2) @(posedge clk_aon_i); + release_req_i = 1'b1; + wait (s_hp_release_hp); + fork + bfm_write(32'h1001_9004, 32'h5A5A_0002); + bfm_read(32'h1001_8004); + join + if (s_last_rdata != (32'hC0DE_0000 ^ 32'h1001_8004)) begin + $fatal(1, "post-stop release-window read data mismatch"); + end + repeat (4) @(posedge clk_lp_i); + if (s_stub_write_count != 2 || s_stub_writes[1] != 32'h9004_0002) begin + $fatal(1, "post-stop release-window write did not reach the LP side intact"); + end + + // Scenario c: a write presented while the gate blocks (drain phase) is + // held, then dropped by flush; the BFM withdraws it when the HP re-holds, + // and the next release window still works. + release_req_i = 1'b1; + wait (s_hp_release_hp); + @(negedge clk_aon_i); + release_req_i = 1'b0; + wait (s_hp_block_hp); + @(negedge clk_hp_i); + u_gate_src_if.awaddr = 32'h1001_9008; + u_gate_src_if.awvalid = 1'b1; + u_gate_src_if.wdata = 32'hDEAD_BEEF; + u_gate_src_if.wstrb = 4'hF; + u_gate_src_if.wlast = 1'b1; + u_gate_src_if.wvalid = 1'b1; + repeat (4) @(posedge clk_hp_i); + if (u_gate_src_if.awready) $fatal(1, "gate accepted a new write while blocking"); + // Complete the drain handshake so the lifecycle can re-hold the HP; the + // flush-busy level is driven by the bridge's clear-busy report. + wait (!s_hp_release_hp); + @(negedge clk_hp_i); + u_gate_src_if.awvalid = 1'b0; + u_gate_src_if.wvalid = 1'b0; + repeat (4) @(posedge clk_aon_i); + release_req_i = 1'b1; + wait (s_hp_release_hp); + bfm_write(32'h1001_900C, 32'h1234_5678); + repeat (4) @(posedge clk_lp_i); + if (s_stub_write_count != 3 || s_stub_writes[2] != 32'h900C_5678) begin + $fatal(1, "third release-window write did not reach the LP side intact"); + end + if (s_stub_writes[2] == 32'h9008_BEEF) begin + $fatal(1, "the drain-held write leaked into the next release window"); + end + + $display("HP release window transaction retention test passed"); + $finish; + end +endmodule diff --git a/tests/test_axi4.py b/tests/test_axi4.py index 0694afa3..ccd27709 100644 --- a/tests/test_axi4.py +++ b/tests/test_axi4.py @@ -90,6 +90,46 @@ def test_axi4_async_bridge_transfers_and_warm_flushes(tmp_path: Path) -> None: assert "AXI4 async bridge transfer and warm flush test passed" in result.stdout +def test_hp_release_window_retains_transactions(tmp_path: Path) -> None: + verilator = shutil.which("verilator") + if verilator is None: + return + output = tmp_path / "hp_release_window_tb" + ccache_tmp = tmp_path / "ccache" + ccache_tmp.mkdir() + subprocess.run( + [ + verilator, "--binary", "--timing", "-Wno-fatal", "--top-module", + "hp_release_window_tb", + "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"), + "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/cdc"), + "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"), + str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/utils/xchecker.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/utils/bin2gray.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/utils/gray2bin.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"), + str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv"), + str(ROOT / "rtl/ip/util/soc_common_cdc.sv"), + str(ROOT / "rtl/mini/top/axi4_address_gate.sv"), + str(ROOT / "rtl/mini/top/axi4_async_bridge.sv"), + str(ROOT / "rtl/mini/top/hp_lifecycle_controller.sv"), + str(ROOT / "tests/rtl/hp_release_window_tb.sv"), + "-Mdir", str(tmp_path / "obj"), "-o", str(output), + ], + check=True, + text=True, + capture_output=True, + env={**os.environ, "CCACHE_DIR": str(ccache_tmp), "CCACHE_TEMPDIR": str(ccache_tmp)}, + ) + result = subprocess.run([output], check=True, text=True, capture_output=True) + assert "HP release window transaction retention test passed" in result.stdout + + def test_axi4_downsizer_preserves_bursts_lanes_and_backpressure( tmp_path: Path, ) -> None: From 489ff284e1c6453f0b4cc10bba681a613ab4c350 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sun, 11 Oct 2026 08:14:57 +0800 Subject: [PATCH 03/31] fix(axi4): correct WRAP burst handling for mid-line and page-edge fills The OpenC906 is the first master to issue WRAP bursts (cache line fills start at the critical word). Two latent path bugs made every such fill fail or corrupt data: - sdram_axi4 reconstructed the WRAP wrap-back address from the decrementing remaining-beat count, which cannot reproduce the wrap boundary; mid-line starts read the second half from wrong addresses. Beat stepping now uses the registered original geometry through the proven shared axi4_addr_gen, on both the read and write paths. - axi4_data_crossbar burst_legal computed a WRAP burst's last address as if it were INCR, so fills starting in the last 64 bytes of a 4 KiB page were faulted as FaultProtocol and answered with DECERR. The WRAP last address is now computed from the wrap boundary. Locked by new directed cases: mid-line WRAP read/write with address-encoded data in tests/rtl/sdram_data_tb.sv and a page-edge WRAP read routing case in tests/rtl/axi4_data_crossbar_tb.sv. Both fail on the pre-fix RTL and pass after; full test_axi4/test_sdram (17/17), hp-smoke-sim, hp-rtthread-sim and the PR ci_smoke all pass with the fix. --- rtl/ip/memory/sdram_axi4.sv | 64 +++++++++++++++----- rtl/mini/top/axi4_data_crossbar.sv | 7 ++- tests/rtl/axi4_data_crossbar_tb.sv | 73 +++++++++++++++++++++++ tests/rtl/sdram_data_tb.sv | 93 ++++++++++++++++++++++++++++++ 4 files changed, 220 insertions(+), 17 deletions(-) diff --git a/rtl/ip/memory/sdram_axi4.sv b/rtl/ip/memory/sdram_axi4.sv index b276bf71..c8f54294 100644 --- a/rtl/ip/memory/sdram_axi4.sv +++ b/rtl/ip/memory/sdram_axi4.sv @@ -128,6 +128,11 @@ module sdram_axi4 ( logic s_rd_id_d; logic [ 1:0] s_rd_resp_q; logic [ 1:0] s_rd_resp_d; + // Original burst length, registered at accept: WRAP stepping needs the + // total geometry, which the decrementing remaining-beat count cannot + // reconstruct. + logic [ 7:0] s_rd_len_q; + logic [ 7:0] s_rd_len_d; sdram_wr_state_e s_wr_state_q; sdram_wr_state_e s_wr_state_d; @@ -145,6 +150,8 @@ module sdram_axi4 ( logic s_wr_id_d; logic [ 1:0] s_wr_resp_q; logic [ 1:0] s_wr_resp_d; + logic [ 7:0] s_wr_len_q; + logic [ 7:0] s_wr_len_d; logic s_rd_err_event_d; logic s_wr_err_event_d; @@ -307,6 +314,31 @@ module sdram_axi4 ( assign error_code_o = s_err_code_q; assign error_addr_o = s_err_addr_q; + // Per-beat address stepping uses the registered original burst geometry so + // WRAP boundaries survive mid-burst: the previous remaining-beats-based + // mask arithmetic produced wrong wrap-back addresses for mid-line starts. + logic [31:0] s_rd_step_addr; + logic [31:0] s_wr_step_addr; + + axi4_addr_gen #( + .ADDR_WIDTH(32) + ) u_rd_addr_gen ( + .alen_i (s_rd_len_q), + .asize_i (s_rd_size_q), + .aburst_i(s_rd_burst_q), + .addr_i (s_rd_addr_q), + .addr_o (s_rd_step_addr) + ); + axi4_addr_gen #( + .ADDR_WIDTH(32) + ) u_wr_addr_gen ( + .alen_i (s_wr_len_q), + .asize_i (s_wr_size_q), + .aburst_i(s_wr_burst_q), + .addr_i (s_wr_addr_q), + .addr_o (s_wr_step_addr) + ); + fifo #( .DATA_WIDTH (CmdWidth), .BUFFER_DEPTH(2) @@ -396,6 +428,7 @@ module sdram_axi4 ( s_rd_frag_d = s_rd_frag_q; s_rd_size_d = s_rd_size_q; s_rd_burst_d = s_rd_burst_q; + s_rd_len_d = s_rd_len_q; s_rd_id_d = s_rd_id_q; s_rd_resp_d = s_rd_resp_q; s_ar_pop = 1'b0; @@ -436,6 +469,7 @@ module sdram_axi4 ( s_rd_left_d = s_ar_len + 8'd1; s_rd_size_d = s_ar_size; s_rd_burst_d = s_ar_burst; + s_rd_len_d = s_ar_len; s_rd_id_d = s_ar_id; rd_frag = fragment_beats(s_ar_addr, s_ar_len + 8'd1, s_ar_len, s_ar_size, s_ar_burst); s_rd_frag_d = rd_frag; @@ -461,19 +495,11 @@ module sdram_axi4 ( end s_r_push = 1'b1; s_r_push_data = {rd_data_rdata_i, (s_rd_left_q == 8'd1), s_rd_resp_d, s_rd_id_q}; - if (s_rd_burst_q == `AXI4_BURST_TYPE_FIXED) begin - next_rd_addr = s_rd_addr_q; - end else begin - next_rd_addr = s_rd_addr_q + (32'd1 << s_rd_size_q); - if ((s_rd_burst_q == `AXI4_BURST_TYPE_WRAP) && (beats_to_wrap( - s_rd_addr_q, s_rd_left_q - 8'd1, s_rd_size_q, s_rd_burst_q - ) == 8'd1)) begin - next_rd_addr = s_rd_addr_q & ~((32'd1 << s_rd_size_q) - 1'b1); - next_rd_addr = next_rd_addr - (((32'(s_rd_left_q) - 32'd1) << s_rd_size_q)); - end - end - s_rd_addr_d = next_rd_addr; - s_rd_left_d = s_rd_left_q - 8'd1; + // Step with the original geometry: FIXED holds, INCR increments, + // WRAP wraps at the total-burst boundary (mid-line starts included). + next_rd_addr = s_rd_step_addr; + s_rd_addr_d = next_rd_addr; + s_rd_left_d = s_rd_left_q - 8'd1; if (s_rd_frag_q != 4'd0) begin s_rd_frag_d = s_rd_frag_q - 4'd1; end else if (s_rd_left_q == 8'd1) begin @@ -512,6 +538,7 @@ module sdram_axi4 ( s_wr_frag_d = s_wr_frag_q; s_wr_size_d = s_wr_size_q; s_wr_burst_d = s_wr_burst_q; + s_wr_len_d = s_wr_len_q; s_wr_id_d = s_wr_id_q; s_wr_resp_d = s_wr_resp_q; s_aw_pop = 1'b0; @@ -553,6 +580,7 @@ module sdram_axi4 ( s_wr_left_d = s_aw_len + 8'd1; s_wr_size_d = s_aw_size; s_wr_burst_d = s_aw_burst; + s_wr_len_d = s_aw_len; s_wr_id_d = s_aw_id; wr_frag = fragment_beats(s_aw_addr, s_aw_len + 8'd1, s_aw_len, s_aw_size, s_aw_burst); s_wr_frag_d = wr_frag; @@ -574,9 +602,9 @@ module sdram_axi4 ( if (s_w_data[0] != (s_wr_left_q == 8'd1)) begin s_wr_resp_d = `AXI4_RESP_SLAVE_ERROR; end - if (s_wr_burst_q != `AXI4_BURST_TYPE_FIXED) begin - s_wr_addr_d = s_wr_addr_q + (32'd1 << s_wr_size_q); - end + // Step with the original geometry; this also gives WRAP writes a + // correct wrap-back instead of running past the boundary. + s_wr_addr_d = s_wr_step_addr; s_wr_left_d = s_wr_left_q - 8'd1; if (s_wr_frag_q != 4'd0) begin s_wr_frag_d = s_wr_frag_q - 4'd1; @@ -632,6 +660,7 @@ module sdram_axi4 ( s_rd_frag_q <= '0; s_rd_size_q <= '0; s_rd_burst_q <= '0; + s_rd_len_q <= '0; s_rd_id_q <= '0; s_rd_resp_q <= `AXI4_RESP_OKAY; s_wr_state_q <= WrIdle; @@ -640,6 +669,7 @@ module sdram_axi4 ( s_wr_frag_q <= '0; s_wr_size_q <= '0; s_wr_burst_q <= '0; + s_wr_len_q <= '0; s_wr_id_q <= '0; s_wr_resp_q <= `AXI4_RESP_OKAY; s_err_event_q <= 1'b0; @@ -652,6 +682,7 @@ module sdram_axi4 ( s_rd_frag_q <= s_rd_frag_d; s_rd_size_q <= s_rd_size_d; s_rd_burst_q <= s_rd_burst_d; + s_rd_len_q <= s_rd_len_d; s_rd_id_q <= s_rd_id_d; s_rd_resp_q <= s_rd_resp_d; s_wr_state_q <= s_wr_state_d; @@ -660,6 +691,7 @@ module sdram_axi4 ( s_wr_frag_q <= s_wr_frag_d; s_wr_size_q <= s_wr_size_d; s_wr_burst_q <= s_wr_burst_d; + s_wr_len_q <= s_wr_len_d; s_wr_id_q <= s_wr_id_d; s_wr_resp_q <= s_wr_resp_d; s_err_event_q <= s_rd_err_event_d || s_wr_err_event_d; diff --git a/rtl/mini/top/axi4_data_crossbar.sv b/rtl/mini/top/axi4_data_crossbar.sv index cbc3e6e1..ec5c9f5c 100644 --- a/rtl/mini/top/axi4_data_crossbar.sv +++ b/rtl/mini/top/axi4_data_crossbar.sv @@ -282,12 +282,17 @@ module axi4_data_crossbar #( logic [32:0] beat_bytes; logic [32:0] burst_bytes; logic [32:0] last_addr; + logic [32:0] wrap_base; logic [32:0] window_limit; beat_bytes = 33'd1 << size; burst_bytes = beat_bytes * ({25'd0, len} + 1'b1); + // WRAP bursts end at their wrap boundary, not at addr + burst_bytes: a + // mid-line start otherwise overshoots and fails the 4 KiB page check. + wrap_base = {1'b0, addr} & ~(burst_bytes - 1'b1); last_addr = (burst == 2'b00) ? ({1'b0, addr} + beat_bytes - 1'b1) : - ({1'b0, addr} + burst_bytes - 1'b1); + ((burst == 2'b10) ? (wrap_base + burst_bytes - 1'b1) : + ({1'b0, addr} + burst_bytes - 1'b1)); window_limit = {1'b0, addr[31:12], 12'd0} + 33'd4096; return !lock && (size <= 3'd3) && ((burst == 2'b00) || (burst == 2'b01) || diff --git a/tests/rtl/axi4_data_crossbar_tb.sv b/tests/rtl/axi4_data_crossbar_tb.sv index fa1e36cb..e7a0041a 100644 --- a/tests/rtl/axi4_data_crossbar_tb.sv +++ b/tests/rtl/axi4_data_crossbar_tb.sv @@ -940,6 +940,79 @@ module axi4_data_crossbar_tb; join end + // C906 cache fills issue WRAP bursts whose critical word can start near + // the end of a 4 KiB page: the burst must be routed to SDRAM with its + // real (wrapped) last address, not faulted by an INCR-style overshoot. + wrap_page_edge_read : begin + logic collect_done; + logic seen_sdram_ar; + logic seen_error_ar; + logic seen_fault; + logic [31:0] seen_addr; + logic [ 7:0] seen_len; + logic [ 1:0] seen_burst; + collect_done = 1'b0; + seen_sdram_ar = 1'b0; + seen_error_ar = 1'b0; + seen_fault = 1'b0; + seen_addr = '0; + seen_len = '0; + seen_burst = '0; + fork + begin + @(negedge clk_i); + masters[1].arid = 7'h09; + masters[1].araddr = 32'h3800_0FF0; + masters[1].arlen = 8'd7; + masters[1].arsize = 3'd3; + masters[1].arburst = 2'b10; + masters[1].arvalid = 1'b1; + do @(posedge clk_i); while (!masters[1].arready); + @(negedge clk_i); + masters[1].arvalid = 1'b0; + masters[1].arlen = '0; + masters[1].arburst = 2'b01; + end + begin + while (!collect_done) begin + @(posedge clk_i); + if (targets[1].arvalid && targets[1].arready) begin + seen_sdram_ar = 1'b1; + seen_addr = targets[1].araddr; + seen_len = targets[1].arlen; + seen_burst = targets[1].arburst; + end + if (targets[5].arvalid && targets[5].arready) seen_error_ar = 1'b1; + if (fault_valid_o) seen_fault = 1'b1; + end + end + return_target1_burst(7'h09, 64'hACE0_5555_0000_0000); + begin + for (int beat = 0; beat < 8; beat++) begin + do @(posedge clk_i); while (!masters[1].rvalid); + if (masters[1].rid != 7'h09) + $fatal(1, "WRAP page-edge read beat %0d ID mismatch", beat); + if (masters[1].rdata !== (64'hACE0_5555_0000_0000 + 64'(beat))) begin + $fatal(1, "WRAP page-edge read beat %0d data mismatch", beat); + end + if (masters[1].rresp !== 2'b00) $fatal(1, "WRAP page-edge read beat %0d faulted", beat); + if (masters[1].rlast !== (beat == 7)) begin + $fatal(1, "WRAP page-edge read beat %0d RLAST mismatch", beat); + end + @(negedge clk_i); + end + collect_done = 1'b1; + end + join + if (!seen_sdram_ar || seen_error_ar || seen_fault) begin + $fatal(1, "WRAP page-edge read was not cleanly routed to SDRAM"); + end + if ((seen_addr != 32'h3800_0FF0) || (seen_len != 8'd7) || (seen_burst != 2'b10)) begin + $fatal(1, "WRAP page-edge read metadata was not forwarded intact"); + end + $display("AXI4 data crossbar WRAP page-edge read routed to SDRAM intact"); + end + @(negedge clk_i); if (!idle_o || (outstanding_read_o != 8'd0) || (outstanding_write_o != 8'd0)) begin $fatal(1, "ACL and QoS transactions did not drain the crossbar"); diff --git a/tests/rtl/sdram_data_tb.sv b/tests/rtl/sdram_data_tb.sv index 4af486f6..bc78d86a 100644 --- a/tests/rtl/sdram_data_tb.sv +++ b/tests/rtl/sdram_data_tb.sv @@ -264,6 +264,87 @@ module sdram_data_tb; end endtask + // Byte address of beat `beat` in a 4-byte WRAP burst starting mid-line. + function automatic logic [31:0] wrap_beat_addr(input logic [31:0] start, input integer beat, + input logic [7:0] length); + logic [31:0] burst_bytes; + logic [31:0] wrap_base; + logic [31:0] addr; + begin + burst_bytes = ({24'd0, length} + 32'd1) * 32'd4; + wrap_base = start & ~(burst_bytes - 32'd1); + addr = start + (32'(beat) * 32'd4); + if (addr >= (wrap_base + burst_bytes)) addr = addr - burst_bytes; + return addr; + end + endfunction + + // WRAP write starting mid-line; beat data encodes the beat's own byte + // address so a plain sequential INCR readback catches any wrap-back error. + task automatic write_wrap(input logic [31:0] address, input logic [7:0] length); + integer beat; + begin + @(negedge clk_i); + axi4.awaddr = address; + axi4.awlen = length; + axi4.awburst = `AXI4_BURST_TYPE_WRAP; + axi4.awvalid = 1'b1; + do @(posedge clk_i); while (!axi4.awready); + @(negedge clk_i); + axi4.awvalid = 1'b0; + for (beat = 0; beat <= length; beat++) begin + axi4.wdata = 32'h1000_0000 + wrap_beat_addr(address, beat, length); + axi4.wstrb = 4'hF; + axi4.wlast = (beat == length); + axi4.wvalid = 1'b1; + do @(posedge clk_i); while (!axi4.wready); + @(negedge clk_i); + end + axi4.wvalid = 1'b0; + axi4.wlast = 1'b0; + axi4.bready = 1'b1; + do @(posedge clk_i); while (!axi4.bvalid); + if (axi4.bresp != `AXI4_RESP_OKAY) begin + $fatal(1, "AXI4 SDRAM WRAP write failed at %08x", address); + end + @(negedge clk_i); + axi4.bready = 1'b0; + end + endtask + + // WRAP read starting mid-line; every beat must carry the data of its own + // wrap-ordered byte address, with RLAST only on the final beat. + task automatic read_wrap(input logic [31:0] address, input logic [7:0] length); + integer beat; + logic [31:0] beat_addr; + begin + @(negedge clk_i); + axi4.araddr = address; + axi4.arlen = length; + axi4.arburst = `AXI4_BURST_TYPE_WRAP; + axi4.arvalid = 1'b1; + do @(posedge clk_i); while (!axi4.arready); + @(negedge clk_i); + axi4.arvalid = 1'b0; + axi4.rready = 1'b1; + for (beat = 0; beat <= length; beat++) begin + beat_addr = wrap_beat_addr(address, beat, length); + do @(posedge clk_i); while (!axi4.rvalid); + if (axi4.rdata !== (32'h1000_0000 + beat_addr)) begin + $fatal(1, "WRAP read mismatch beat %0d addr %08x got %08x", beat, beat_addr, axi4.rdata); + end + if (axi4.rresp != `AXI4_RESP_OKAY) begin + $fatal(1, "WRAP read SLVERR beat %0d", beat); + end + if (axi4.rlast !== (beat == length)) begin + $fatal(1, "WRAP RLAST mismatch beat %0d", beat); + end + @(negedge clk_i); + end + axi4.rready = 1'b0; + end + endtask + initial begin #2_000_000; $fatal(1, "simulation timeout"); @@ -324,6 +405,18 @@ module sdram_data_tb; write_incr(`SOC_ADDR_SDRAM_BASE + 32'h300, 8'd15); read_incr(`SOC_ADDR_SDRAM_BASE + 32'h300, 8'd15); + // C906 cache fills issue WRAP bursts whose critical word can start + // mid-line: cover a 64-byte line entered at +0x30 in both directions. + write_incr(`SOC_ADDR_SDRAM_BASE + 32'h400, 8'd15); + read_wrap(`SOC_ADDR_SDRAM_BASE + 32'h430, 8'd15); + write_wrap(`SOC_ADDR_SDRAM_BASE + 32'h530, 8'd15); + read_incr(`SOC_ADDR_SDRAM_BASE + 32'h500, 8'd15); + // A second mid-line offset guards against offset-dependent mask math. + write_incr(`SOC_ADDR_SDRAM_BASE + 32'h600, 8'd15); + read_wrap(`SOC_ADDR_SDRAM_BASE + 32'h610, 8'd15); + write_wrap(`SOC_ADDR_SDRAM_BASE + 32'h720, 8'd15); + read_incr(`SOC_ADDR_SDRAM_BASE + 32'h700, 8'd15); + @(negedge clk_i); axi4.araddr = `SOC_ADDR_SDRAM_BASE; axi4.arlen = 8'd0; From 269edc43a6163e59a9351f6509f4ebab1e3f8e37 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sun, 11 Oct 2026 08:15:12 +0800 Subject: [PATCH 04/31] fix(hp): run the C906 mcor/mhcr init sequence before any real work The C906 resets with caches and the BPU disabled (mhcr=0) and does not initialize the cache/predictor RAMs (aq_cp0_ext_csr.v). The upstream reference crt0 (openc906 smart_run/tests/lib/crt0.s) invalidates them via mcor before enabling mhcr; skipping mcor makes the core execute through uninitialized predictor/cache state (wild control flow with no trap), and leaving caches off makes SDRAM execution ~100x slower, which livelocked the RT-Thread 1 kHz tick ISR before the first selftest marker. Apply the upstream sequence at the earliest point of both HP boot paths: RT-Thread start.S and the OpenSBI platform early_init. MMIO windows stay strong-order non-cacheable via the sysmap override, so enabling the D-cache is safe. hp-rtthread-sim now passes with all selftest markers (6,373,952 cycles in 542 s). --- app/ports/linux/opensbi/retrosoc_hp/platform.c | 13 +++++++++++++ app/ports/rtthread/start.S | 11 +++++++++++ 2 files changed, 24 insertions(+) diff --git a/app/ports/linux/opensbi/retrosoc_hp/platform.c b/app/ports/linux/opensbi/retrosoc_hp/platform.c index 43640474..bb17c4c0 100644 --- a/app/ports/linux/opensbi/retrosoc_hp/platform.c +++ b/app/ports/linux/opensbi/retrosoc_hp/platform.c @@ -32,6 +32,16 @@ #define RETROSOC_HP_UART_FIFO_FLUSH 0x03U #define RETROSOC_HP_UART_ERROR_ALL 0x7FU +/* C906 resets with caches and the BPU disabled (mhcr=0) and does not + * initialize the cache/predictor RAMs; the upstream reference crt0 + * (smart_run/tests/lib/crt0.s) invalidates them via mcor before enabling + * mhcr. Uncached SDRAM execution is ~100x slower. MMIO windows stay + * strong-order non-cacheable via the sysmap override. */ +#define RETROSOC_HP_CSR_MCOR 0x7c2U +#define RETROSOC_HP_MCOR_INVALIDATE_ALL 0x30013UL /* BTB|BHT|DCACHE|ICACHE */ +#define RETROSOC_HP_CSR_MHCR 0x7c1U +#define RETROSOC_HP_MHCR_CACHES_BPU 0x7fUL /* IE|DE|WA|RSE|BPE|BTBE */ + static const u32 s_hart_index_to_id[] = {1U}; static struct aclint_mswi_data s_mswi = { @@ -107,6 +117,9 @@ static int retrosoc_hp_early_init(bool cold_boot) { return 0; } + csr_write(RETROSOC_HP_CSR_MCOR, RETROSOC_HP_MCOR_INVALIDATE_ALL); + csr_write(RETROSOC_HP_CSR_MHCR, RETROSOC_HP_MHCR_CACHES_BPU); + retrosoc_hp_uart_write(RETROSOC_HP_UART_CTRL_REG, 0U); retrosoc_hp_uart_write(RETROSOC_HP_UART_FIFO_CTRL_REG, RETROSOC_HP_UART_FIFO_FLUSH); retrosoc_hp_uart_write(RETROSOC_HP_UART_ERROR_REG, RETROSOC_HP_UART_ERROR_ALL); diff --git a/app/ports/rtthread/start.S b/app/ports/rtthread/start.S index e6c8858f..1e168dd3 100644 --- a/app/ports/rtthread/start.S +++ b/app/ports/rtthread/start.S @@ -5,6 +5,17 @@ _start: csrw satp, zero li t0, 0x6000 csrw mstatus, t0 + # C906 resets with caches and the BPU disabled (mhcr=0) and does not + # initialize the cache/predictor RAMs; the upstream reference crt0 + # (smart_run/tests/lib/crt0.s) invalidates them via mcor before enabling + # mhcr, otherwise the core fetches/stores through stale state. + li t0, 0x30013 + csrs 0x7c2, t0 # mcor: invalidate BTB/BHT/D-cache/I-cache + li t0, 0x7f + csrs 0x7c1, t0 # mhcr: IE|DE|WA|RSE|BPE|BTBE + # Uncached SDRAM execution is ~100x slower otherwise, and the 1 kHz tick + # ISR round-trip then exceeds the tick period (livelock). MMIO windows + # stay strong-order non-cacheable via the sysmap override. .option push .option norelax la gp, __global_pointer$ From 473e249125e396c79a9fa45e762917de368d7dee Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sun, 11 Oct 2026 08:15:27 +0800 Subject: [PATCH 05/31] docs: retire stale Zicbom/VexiiRiscv wording after the OpenC906 swap The Mini HP core is the locked OpenC906 with T-Head XTheadCmo custom-0 dcache maintenance; the former rv64imafdc_zicbom_max VexiiRiscv configuration survives only as the frozen Std-series generator asset. Sweep the leftover wording: - scripts/README.md gains the missing setup_openc906.py and generate_openc906.py entries (locked source install; sha256-pinned overrides; single compilation unit below build/). - configs/README.md and app/README.md describe the OpenC906 core and XTheadCmo maintenance instead of VexiiRiscv RTL generation and Zicbom. - The npu-p5-hp-sim help line and the npu_p5_report.py emitted HP evidence mode now say polling-xtheadcmo, matching the payload's actual dcache.cva/iva mechanism. --- Makefile | 2 +- app/README.md | 4 ++-- configs/README.md | 13 ++++++++----- scripts/README.md | 10 ++++++++++ scripts/npu_p5_report.py | 2 +- 5 files changed, 22 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index 72d1ab2b..f38c1217 100644 --- a/Makefile +++ b/Makefile @@ -576,7 +576,7 @@ help: ' npu-p5-host run compiler, generated-C, executor, and ABI tests' \ ' npu-p5-rtl run frozen model inputs through Icarus and Verilator' \ ' npu-p5-lp-sim run LP interrupt bare-metal NPU acceptance' \ - ' npu-p5-hp-sim run HP polling/Zicbom bare-metal NPU acceptance' \ + ' npu-p5-hp-sim run HP polling/XTheadCmo bare-metal NPU acceptance' \ ' npu-p5-report validate and assemble retained P5 evidence' \ ' npu-p6-corpus build deterministic 100-case qualification shards' \ ' npu-p6-formal close DMA, context, and control bounded proofs' \ diff --git a/app/README.md b/app/README.md index fae63e58..e627db77 100644 --- a/app/README.md +++ b/app/README.md @@ -33,7 +33,7 @@ The build selects an application with `APP=`. The supported profiles are: | `coremark` | SRAM-resident Hazard3 CoreMark measurement; use the committed quick or standard profile. | | `debug` | Minimal SRAM image used only by the Hazard3 OpenOCD/GDB acceptance flow. | | `hp_boot` | SRAM-resident LP loader that validates typed V2 Linux, smoke or RT-Thread bundles, loads SDRAM, releases HP, and monitors the workload-specific mailbox verdict. | -| `apu_release` | PSRAM-resident LP/HP APU evidence flow: LP-only microcode/KWS model load, ownership handoff to RV64 HP, HP-submitted WAV/KWS jobs with Zicbom maintenance, and LP-only register fault probe. | +| `apu_release` | PSRAM-resident LP/HP APU evidence flow: LP-only microcode/KWS model load, ownership handoff to RV64 HP, HP-submitted WAV/KWS jobs with T-Head XTheadCmo dcache maintenance, and LP-only register fault probe. | | `shell` | Interactive application that adds shell services, board drivers, media, FatFs, CoreMark, and UserIP integration. | | `xpi_flash_loader` | SRAM-resident, GDB-called service image for sector-preserving JTAG programming of the qualified NSS0 NOR. | @@ -46,7 +46,7 @@ NPU-P5 acceptance extends existing compositions rather than adding an APP. of the reproducible variant key. The LP path links the generated KWS plan into `ci_smoke`, uses the real LP completion interrupt, and writes the normal SYSCTRL verdict. The RV64 HP smoke bundle assigns resource 9 to hart 1, runs -the same plan with polling and 64-byte Zicbom maintenance, then returns +the same plan with polling and 64-byte T-Head XTheadCmo dcache maintenance, then returns ownership before LP publishes the final verdict. The option defaults to `NO`, preserving normal PR firmware size and behavior. diff --git a/configs/README.md b/configs/README.md index c0f19a12..403283bc 100644 --- a/configs/README.md +++ b/configs/README.md @@ -22,10 +22,10 @@ and retained logs under `build/ihp130-2026-10-01-10-30-b2e490436ac7/npu/p6/`. `ci/ihp130-hp.mk` is the asymmetric Linux application profile. It starts HP from the external 72 MHz safe clock and LP from REF24, runs `hp_boot` entirely -from 32 KiB on-chip SRAM, enables VexiiRiscv `Zicbom` with 64-byte blocks, and -generates VexiiRiscv RTL only below the selected build variant. It is not part -of the supported PR matrix until Linux boot, HP performance, synthesis, and -timing evidence are qualified. +from 32 KiB on-chip SRAM, and uses the locked pre-generated OpenC906 HP core +(RV64GC, hart 1) whose combined RTL is emitted only below the selected build +variant. It is not part of the supported PR matrix until Linux boot, HP +performance, synthesis, and timing evidence are qualified. `ci/ihp130-rtthread.mk` selects the same RV64 HP hardware and LP loader for the pinned RT-Thread M-mode selftest. Run `make setup-hp-rtthread`, then `make CONFIG=configs/ci/ihp130-rtthread.mk SIMU=VERILATOR hp-rtthread-sim`. @@ -34,7 +34,10 @@ the pinned RT-Thread M-mode selftest. Run `make setup-hp-rtthread`, then SDRAM, performs the LP-only image loads, hands APU ownership to HP, and checks HP-submitted WAV/KWS jobs plus the LP-only register fault probe in the full-SoC Verilator simulation via `hp-apu-sim`. -All PRODUCT profiles use `rv64imafdc_zicbom_max`; LP compiler/ISA remain RV32. +Mini PRODUCT profiles use the locked OpenC906 HP core (RV64GC); HP images +compile as `rv64imafdc_zicsr_zifencei`/`lp64d`, and the former +`rv64imafdc_zicbom_max` VexiiRiscv configuration is preserved as the +Std-series generator asset. LP compiler/ISA remain RV32. `ci/ihp130-xpi-flash-loader.mk` builds the SRAM-only XPI NOR service image used by GDB/OpenOCD; it is a programming utility, not a normal boot application. Start builds from a committed profile rather than setting an unreviewed mix of diff --git a/scripts/README.md b/scripts/README.md index 44b9e027..d905f607 100644 --- a/scripts/README.md +++ b/scripts/README.md @@ -125,6 +125,16 @@ SRAM CoreMark quick report into `meta/coremark.json`; it requires one valid `COREMARK_RESULT` record and `COREMARK_PASS`. Both reports complement, rather than replace, the common `SIM_TEST_PASS` simulation verdict. +`setup_openc906.py` installs or updates (`--update`) the locked OpenC906 +source used by Mini product profiles and verifies the checked-out revision; +the vendored checkout is never modified. `generate_openc906.py` resolves the +upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes +the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1 +`aq_sysio_kid.v` and the strong-order MMIO-window `sysmap.h`, each pinned to +the upstream file's SHA-256 so a locked-revision move forces review), and +emits the single compilation unit `openc906_combined.v` below `build/`; +generated RTL is never tracked. + `generate_vexiiriscv.py` verifies the locked VexiiRiscv revision, rejects local source changes before and after generation, and generates the fixed Std-series core (preserved from the retired Mini HP configuration) below `build/`; generated diff --git a/scripts/npu_p5_report.py b/scripts/npu_p5_report.py index 67d3a032..5d56f187 100644 --- a/scripts/npu_p5_report.py +++ b/scripts/npu_p5_report.py @@ -450,7 +450,7 @@ def main() -> int: "softmax_cycles": int(marker.group(4)), **lp_evidence}, "hp": {"result": str(args.hp_result), "check": str(args.hp_check), - "command": hp["command"], "mode": "polling-zicbom", + "command": hp["command"], "mode": "polling-xtheadcmo", **hp_evidence}, "summary": { "required_checks": 47, From dcdb7d378247a1f28d4430fcad865476ca56c4bf Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sun, 11 Oct 2026 08:15:41 +0800 Subject: [PATCH 06/31] docs: record OpenC906 RT-Thread and bounded Linux bring-up evidence hp-rtthread-sim now passes on the OpenC906 HP core with all selftest markers (6,373,952 cycles in 542 s), exercising the internal CLINT timer/MSWI and the internal PLIC mailbox doorbell. The RT-Thread bring-up root-cause chain (mcor/mhcr init, sdram_axi4 and crossbar WRAP handling) is recorded with its regression locks. hp-linux-sim ran with a bounded 4 h wall budget (158.7 M cycles): OpenSBI v1.9 completes on the repo-owned retrosoc_hp platform and hands off to the kernel correctly; the kernel enters S-mode with Sv39 but stalls in the S-mode fault path after the __cpu_online_mask store page fault (A/D-bit emulation fixup loop), which is the current bring-up frontier. The target stays unqualified; the synthesis-dependent gates remain deferred to the SRAM macro swap round. Also records the latent gap that OpenSBI never initializes the C906-internal PLIC (no .irqchip_init), harmless for the current minimal acceptance. --- docs/hp-rv64-validation.md | 45 ++++++++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index bfb41ab2..9a6581e1 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -34,6 +34,38 @@ qualification. Current evidence requires, at minimum: 128-to-64 downsizer and MMIO demux, the mailbox protocol, the GA2D engine through the HP data path, and the T-Head `dcache.cva`/`dcache.iva` cache lifecycle handshake. +- `hp-rtthread-sim` on `configs/ci/ihp130-rtthread.mk` (Verilator): all + selftest markers (`RTTHREAD_RV64_PASS`, `RTTHREAD_TIMEOUT_PASS`, + `RTTHREAD_PREEMPT_PASS`, `RTTHREAD_CONTEXT_PASS`, `RTTHREAD_IPC_PASS`, + `RTTHREAD_MAILBOX_IRQ_PASS`, `RTTHREAD_TEST_PASS`) plus `HP_RTTHREAD_PASS` + and `SIM_TEST_PASS code=0`; 6,373,952 cycles in 542 s. This exercises the + C906 internal CLINT timer tick and MSIP IPI, the internal PLIC mailbox + doorbell (MEIP), and the full cached SDRAM fill path. +- `hp-linux-sim` on `configs/ci/ihp130-hp.mk` (Verilator, bounded 4 h wall, + 158.7 M cycles): OpenSBI v1.9 completes fully on the C906 with the + repo-owned platform (custom timer device reading the `time` CSR plus + internal-CLINT MSWI IPI, custom UART1 console), and `fw_jump` hands off to + the kernel Image at `0x38400000` with the DTB at `0x38080000` (bundle + segments byte-identical to the built images, CRC-checked). The kernel + enters S-mode, brings Sv39 up and executes, but does not reach its first + console print: a temporary retire-PC/trap probe shows it cycling through + the S-mode fault path (`handle_exception`/`do_trap_break`) after a store + page fault on the `__cpu_online_mask` AMO, i.e. the A/D-bit emulation + fixup path is the current bring-up frontier. The target stays unqualified. +- The RT-Thread bring-up exposed and fixed three latent issues, each locked + by directed regression. (a) The C906 resets with caches and the BPU + disabled and does not initialize the cache/predictor RAMs: HP payloads must + run the upstream `mcor` invalidate-then-`mhcr` enable sequence + (`app/ports/rtthread/start.S`, OpenSBI `early_init`). Without it the 1 kHz + tick ISR livelocked the uncached core, and enabling caches without + invalidating first produced wild control flow. (b) `sdram_axi4` computed + WRAP wrap-back addresses from the decrementing remaining-beat count, + corrupting every cache-line fill starting mid-line (locked by WRAP cases in + `tests/rtl/sdram_data_tb.sv`). (c) The data crossbar's `burst_legal` + computed a WRAP burst's last address as if it were INCR, faulting fills + that start in the last 64 bytes of a 4 KiB page (locked by the page-edge + case in `tests/rtl/axi4_data_crossbar_tb.sv`). No previous master issued + WRAP bursts, so (b) and (c) predated the swap. - Focused `hp_c906_boot_tb` (pytest `test_hp_platform.py`): the real smoke payload runs on `hp_core_wrapper` plus the production MMIO chain (64-to-32 downsizer, address gate, HP-to-LP CDC bridge) and completes the @@ -48,14 +80,19 @@ qualification. Current evidence requires, at minimum: core-internal CLINT/PLIC windows strong-order non-cacheable per the user manual. -`hp-rtthread-sim`, `hp-linux-sim`, and the synthesis-dependent gates remain -unrun this round (synthesis waits for the SRAM macro swap); they stay required -evidence for qualification. +`hp-linux-sim` was run with a bounded wall-clock budget this round and its +current frontier is recorded above; the synthesis-dependent gates remain +unrun (synthesis waits for the SRAM macro swap). Both stay required evidence +for qualification. Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT (scan/mbist tied off), the debug SBA AXI master (unconnected), ASIC memory-macro replacement for the behavioral FPGA SRAM models, and HP Linux -re-qualification timing/performance evidence. +re-qualification timing/performance evidence. The repo-owned OpenSBI platform +deliberately registers no `.irqchip_init`, so the C906-internal PLIC is not +initialized by OpenSBI: harmless for the current minimal Linux acceptance +(`hvc0` console, SBI TIME timer, polled mailbox), but Linux S-mode +external-interrupt consumers will need an `fdt_irqchip_init(true)` wrapper. ## Historical VexiiRiscv evidence (pre-swap) From 160d4e35f0145a479a340235d211cae6072ccc7d Mon Sep 17 00:00:00 2001 From: maksyuki Date: Mon, 12 Oct 2026 03:18:54 +0800 Subject: [PATCH 07/31] fix(hp/linux): initialize the C906-internal PLIC through OpenSBI The retrosoc_hp platform registered no irqchip_init hook, so the C906-internal PLIC (thead,c900-plic, decoded by the core BIU rather than the SoC fabric) was never initialized before the kernel probed it. Select FDT_IRQCHIP_PLIC and register fdt_irqchip_init: OpenSBI v1.9's thead,c900-plic match applies the T-Head M-to-S delegation quirk that S-mode external-interrupt delivery requires. Verified by nm on the rebuilt fw_jump.elf (fdt_irqchip_init/fdt_irqchip_plic linked in). --- app/ports/linux/opensbi/retrosoc_hp/Kconfig | 3 +++ app/ports/linux/opensbi/retrosoc_hp/platform.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/app/ports/linux/opensbi/retrosoc_hp/Kconfig b/app/ports/linux/opensbi/retrosoc_hp/Kconfig index b6261b9b..b39c362b 100644 --- a/app/ports/linux/opensbi/retrosoc_hp/Kconfig +++ b/app/ports/linux/opensbi/retrosoc_hp/Kconfig @@ -2,5 +2,8 @@ config PLATFORM_RETROSOC_HP bool + select FDT + select FDT_IRQCHIP + select FDT_IRQCHIP_PLIC select IPI_MSWI default y diff --git a/app/ports/linux/opensbi/retrosoc_hp/platform.c b/app/ports/linux/opensbi/retrosoc_hp/platform.c index bb17c4c0..f596f67c 100644 --- a/app/ports/linux/opensbi/retrosoc_hp/platform.c +++ b/app/ports/linux/opensbi/retrosoc_hp/platform.c @@ -8,6 +8,7 @@ #include #include #include +#include /* Internal C906 CLINT (thead,c900-clint), decoded by the core BIU. */ #define RETROSOC_HP_CLINT_BASE 0x0C000000UL @@ -140,6 +141,10 @@ static int retrosoc_hp_timer_init(void) { static const struct sbi_platform_operations s_platform_operations = { .early_init = retrosoc_hp_early_init, + /* Initialize the C906-internal PLIC from the boot FDT: the thead,c900-plic + * match applies the T-Head M-to-S delegation quirk that S-mode interrupt + * delivery requires. */ + .irqchip_init = fdt_irqchip_init, .timer_init = retrosoc_hp_timer_init, }; From 31ea1a275405f5a89a3f45e796770f96d008827b Mon Sep 17 00:00:00 2001 From: maksyuki Date: Mon, 12 Oct 2026 03:19:21 +0800 Subject: [PATCH 08/31] fix(hp/linux): clear OpenC906 mxstatus.MAEE in OpenSBI early init The OpenC906 user manual states mxstatus.MAEE resets to 0, but the RTL (aq_cp0_ext_csr.v) resets it to 1. With MAEE set, S-mode page attributes come from the T-Head extended PTE bits [63:59], which a stock mainline kernel never programs, so every translated page is non-cacheable; the C906 then raises a store/AMO access fault (cause 7) for any AMO on such a page (aq_lsu_ag.v: !mmu_ca && ag_pipe_amo). The first victim was set_cpu_online()'s amoor.d.aqrl on __cpu_online_mask, after which the kernel entered the do_trap_break storm before its first console print. Bare-metal Sv39 payloads proved independently that page-table walks, loads/stores, and the bus fill path are correct (4 KiB three-level, 2 MiB megapage, high-half canonical VAs, cold fills from SDRAM after D$ eviction); the failure was purely the AMO-on-non-cacheable rule, and no bus error response or PMP denial was observed on probes. early_init now clears mxstatus.MAEE so translated accesses follow the sysmap override (RAM cacheable, MMIO strong-order device) and the stock kernel needs no T-Head PBMT errata. Evidence: directed payload passes the full AMO battery (amoor/amoadd/amoswap/lr-sc, cold-line and high-half-VA variants); hp-linux-sim (bounded 2 h wall) boots past set_cpu_online, prints 'Linux version 6.12.105+', and keeps retiring into meminit with no further traps. Userspace acceptance continues on a longer bounded run; the target stays unqualified until it completes. --- .../linux/opensbi/retrosoc_hp/platform.c | 13 +++++ docs/hp-rv64-validation.md | 50 +++++++++++++------ 2 files changed, 48 insertions(+), 15 deletions(-) diff --git a/app/ports/linux/opensbi/retrosoc_hp/platform.c b/app/ports/linux/opensbi/retrosoc_hp/platform.c index f596f67c..6d35c315 100644 --- a/app/ports/linux/opensbi/retrosoc_hp/platform.c +++ b/app/ports/linux/opensbi/retrosoc_hp/platform.c @@ -43,6 +43,18 @@ #define RETROSOC_HP_CSR_MHCR 0x7c1U #define RETROSOC_HP_MHCR_CACHES_BPU 0x7fUL /* IE|DE|WA|RSE|BPE|BTBE */ +/* The OpenC906 RTL resets mxstatus.MAEE (bit 21) to 1, contrary to the user + * manual's stated reset value of 0 (aq_cp0_ext_csr.v). With MAEE set, S-mode + * page attributes come from the T-Head extended PTE bits [63:59], which a + * stock mainline kernel never programs: every translated page becomes + * non-cacheable and the C906 raises a store/AMO access fault (cause 7) for + * any AMO on such a page (aq_lsu_ag.v: !mmu_ca && ag_pipe_amo), e.g. the + * kernel's first set_cpu_online amoor.d. Clearing MAEE makes translated + * accesses follow the sysmap override (RAM cacheable, MMIO strong-order + * device), so the stock kernel works without T-Head PBMT errata. */ +#define RETROSOC_HP_CSR_MXSTATUS 0x7c0U +#define RETROSOC_HP_MXSTATUS_MAEE (1UL << 21) + static const u32 s_hart_index_to_id[] = {1U}; static struct aclint_mswi_data s_mswi = { @@ -120,6 +132,7 @@ static int retrosoc_hp_early_init(bool cold_boot) { csr_write(RETROSOC_HP_CSR_MCOR, RETROSOC_HP_MCOR_INVALIDATE_ALL); csr_write(RETROSOC_HP_CSR_MHCR, RETROSOC_HP_MHCR_CACHES_BPU); + csr_clear(RETROSOC_HP_CSR_MXSTATUS, RETROSOC_HP_MXSTATUS_MAEE); retrosoc_hp_uart_write(RETROSOC_HP_UART_CTRL_REG, 0U); retrosoc_hp_uart_write(RETROSOC_HP_UART_FIFO_CTRL_REG, RETROSOC_HP_UART_FIFO_FLUSH); diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index 9a6581e1..76a5a313 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -41,17 +41,37 @@ qualification. Current evidence requires, at minimum: and `SIM_TEST_PASS code=0`; 6,373,952 cycles in 542 s. This exercises the C906 internal CLINT timer tick and MSIP IPI, the internal PLIC mailbox doorbell (MEIP), and the full cached SDRAM fill path. -- `hp-linux-sim` on `configs/ci/ihp130-hp.mk` (Verilator, bounded 4 h wall, - 158.7 M cycles): OpenSBI v1.9 completes fully on the C906 with the - repo-owned platform (custom timer device reading the `time` CSR plus - internal-CLINT MSWI IPI, custom UART1 console), and `fw_jump` hands off to - the kernel Image at `0x38400000` with the DTB at `0x38080000` (bundle - segments byte-identical to the built images, CRC-checked). The kernel - enters S-mode, brings Sv39 up and executes, but does not reach its first - console print: a temporary retire-PC/trap probe shows it cycling through - the S-mode fault path (`handle_exception`/`do_trap_break`) after a store - page fault on the `__cpu_online_mask` AMO, i.e. the A/D-bit emulation - fixup path is the current bring-up frontier. The target stays unqualified. +- `hp-linux-sim` on `configs/ci/ihp130-hp.mk` (Verilator, bounded 2 h wall, + 83.5 M emulator cycles / 41.8 M HP cycles): OpenSBI v1.9 completes fully on + the C906 with the repo-owned platform (custom timer device reading the + `time` CSR plus internal-CLINT MSWI IPI, custom UART1 console), and + `fw_jump` hands off to the kernel Image at `0x38400000` with the DTB at + `0x38080000` (bundle segments byte-identical to the built images, + CRC-checked). The kernel enters S-mode, brings Sv39 up, executes past + `set_cpu_online()`'s first AMO, and prints `Linux version 6.12.105+` on the + SBI console: the earlier boot blocker is fixed (see the MAEE entry below). + The run ends on the wall-clock budget while the kernel is mid-`meminit` + (`Initmem setup node 0`), retiring steadily with no further traps; userspace + acceptance (`HP_LINUX_READY`) is continued on a longer bounded run. The + target stays unqualified until that acceptance completes. +- The Linux boot blocker was a doc/RTL mismatch in OpenC906, root-caused with + bare-metal MMU payloads and locked by simulation evidence: the user manual + states `mxstatus.MAEE` resets to 0, but the RTL (`aq_cp0_ext_csr.v`) resets + it to 1. With MAEE set, S-mode page attributes come from the T-Head + extended PTE bits [63:59], which a stock mainline kernel never programs, so + every translated page is non-cacheable; the C906 then raises a store/AMO + access fault (cause 7) for any AMO on such a page (`aq_lsu_ag.v`: + `!mmu_ca && ag_pipe_amo`). The first victim is `set_cpu_online()`'s + `amoor.d.aqrl` on `__cpu_online_mask`, after which the kernel enters the + `do_trap_break` storm. Loads/stores and full Sv39 page-table walks + (4 KiB three-level, 2 MiB megapage, high-half canonical VAs, cold fills from + SDRAM after D$ eviction) were proven correct independently: the failure was + purely the AMO-on-non-cacheable rule. The OpenSBI platform `early_init` now + clears `mxstatus.MAEE` (`app/ports/linux/opensbi/retrosoc_hp/platform.c`), + making translated accesses follow the sysmap override (RAM cacheable, MMIO + strong-order device) so the stock kernel needs no T-Head PBMT errata. A + directed payload then passes the full AMO battery (amoor/amoadd/amoswap/ + lr-sc, cold-line and high-half-VA variants). - The RT-Thread bring-up exposed and fixed three latent issues, each locked by directed regression. (a) The C906 resets with caches and the BPU disabled and does not initialize the cache/predictor RAMs: HP payloads must @@ -89,10 +109,10 @@ Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT (scan/mbist tied off), the debug SBA AXI master (unconnected), ASIC memory-macro replacement for the behavioral FPGA SRAM models, and HP Linux re-qualification timing/performance evidence. The repo-owned OpenSBI platform -deliberately registers no `.irqchip_init`, so the C906-internal PLIC is not -initialized by OpenSBI: harmless for the current minimal Linux acceptance -(`hvc0` console, SBI TIME timer, polled mailbox), but Linux S-mode -external-interrupt consumers will need an `fdt_irqchip_init(true)` wrapper. +registers `fdt_irqchip_init` (v1.9 supports the `thead,c900-plic` match with +T-Head delegation fixups), so the C906-internal PLIC is initialized by +OpenSBI before the kernel probes it; the minimal Linux acceptance uses the +`hvc0` console, the SBI TIME timer, and the polled mailbox path. ## Historical VexiiRiscv evidence (pre-swap) From cec7949e8b791dbc3c8579678857270c4083666b Mon Sep 17 00:00:00 2001 From: maksyuki Date: Mon, 12 Oct 2026 03:19:32 +0800 Subject: [PATCH 09/31] feat(hp/boot): add HP_JTAG_DEBUG pre-release JTAG select knob Select the HP (OpenC906) JTAG target before the LP releases it, for HP bring-up debug sessions. Behavior-neutral when off. The knob deliberately stays out of the variant key: debug runs are not qualification evidence, and enabling it should not force a full Linux-bundle rebuild. --- Makefile | 6 ++++++ app/apps/hp_boot/main.c | 7 +++++++ rtl/mk/software.mk | 3 +++ 3 files changed, 16 insertions(+) diff --git a/Makefile b/Makefile index f38c1217..9d259c11 100644 --- a/Makefile +++ b/Makefile @@ -86,6 +86,11 @@ SW_LTO ?= NO WS2812_P3_ACCEPTANCE ?= NO COREMARK_MODE ?= quick NPU_P5_ACCEPTANCE ?= NO +# Select the HP (OpenC906) JTAG target before the LP releases it; debug aid +# for HP bring-up sessions, behavior-neutral when off. Debug runs are not +# qualification evidence, so the knob deliberately stays out of the variant +# key; rebuilds require touching the app source. +HP_JTAG_DEBUG ?= NO NPU_P6_ACCEPTANCE ?= NO NPU_P6_WORKLOAD ?= kws HP_PERF_MIN_RATIO ?= 2.5 @@ -279,6 +284,7 @@ $(call validate_value,APP,$(VALID_APP)) $(call validate_value,LINK_TYPE,$(VALID_LINK_TYPE)) $(call validate_value,COREMARK_MODE,$(VALID_COREMARK_MODE)) $(call validate_value,NPU_P5_ACCEPTANCE,$(VALID_BOOL)) +$(call validate_value,HP_JTAG_DEBUG,$(VALID_BOOL)) $(call validate_value,NPU_P6_ACCEPTANCE,$(VALID_BOOL)) $(call validate_value,NPU_P6_WORKLOAD,kws vww) $(call validate_value,SW_ISA_PROFILE,COMPAT TINY_PERF) diff --git a/app/apps/hp_boot/main.c b/app/apps/hp_boot/main.c index f2ac9461..a3d4d0ec 100644 --- a/app/apps/hp_boot/main.c +++ b/app/apps/hp_boot/main.c @@ -299,6 +299,13 @@ int main(void) { } #endif __asm__ volatile("fence rw, rw" ::: "memory"); +#ifdef RS_HP_JTAG_DEBUG + /* Select the HP (C906) JTAG target before release; the select register is + * writable only while the HP is held. Used by HP debug sessions. */ + if (rs_sysctrl_select_hp_debug(true) != RS_OK) { + rs_hp_boot_fail(UINT8_C(20)); + } +#endif if ((rs_hp_mailbox_clear_lp_interrupt() != RS_OK) || (rs_sysctrl_set_hp_release(true) != RS_OK) || (rs_sysctrl_get_hp_status(&hp_status) != RS_OK) || !hp_status.released) { diff --git a/rtl/mk/software.mk b/rtl/mk/software.mk index 6ab91f17..c5611759 100644 --- a/rtl/mk/software.mk +++ b/rtl/mk/software.mk @@ -88,6 +88,9 @@ endif ifeq ($(NPU_P5_ACCEPTANCE),YES) DEF_VAL += -DRS_NPU_P5_ACCEPTANCE endif +ifeq ($(HP_JTAG_DEBUG),YES) +DEF_VAL += -DRS_HP_JTAG_DEBUG +endif ifeq ($(NPU_P6_ACCEPTANCE),YES) DEF_VAL += -DRS_NPU_P6_ACCEPTANCE endif From ec0adc0fd8d3ea89271a71a2ef229bf0405b910c Mon Sep 17 00:00:00 2001 From: maksyuki Date: Mon, 12 Oct 2026 03:20:46 +0800 Subject: [PATCH 10/31] docs: register the HP_JTAG_DEBUG knob in the app composition guide --- app/README.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/app/README.md b/app/README.md index e627db77..8ebe3f1b 100644 --- a/app/README.md +++ b/app/README.md @@ -50,6 +50,13 @@ the same plan with polling and 64-byte T-Head XTheadCmo dcache maintenance, then ownership before LP publishes the final verdict. The option defaults to `NO`, preserving normal PR firmware size and behavior. +`HP_JTAG_DEBUG=YES` is an `hp_boot` debug aid: the LP selects the HP +(OpenC906) JTAG target before releasing the HP core, so a debugger can attach +from the first HP instruction. It defaults to `NO` and is behavior-neutral +when off. It is deliberately excluded from the variant key because debug runs +are not qualification evidence; toggling it requires touching an app source +to trigger a rebuild. + NPU-P6 likewise reuses `APP=hp_boot`; it does not add an application profile or public ABI. `NPU_P6_ACCEPTANCE=YES` selects a private qualification payload, and `NPU_P6_WORKLOAD=kws|vww` selects one frozen generated plan. The payload From 4ce34734ce492a1c2aeba2c111c34a50d5bdf20e Mon Sep 17 00:00:00 2001 From: maksyuki Date: Mon, 12 Oct 2026 22:32:26 +0800 Subject: [PATCH 11/31] fix(hp/linux): park the C906 internal-CLINT STIMECMP at cold boot The C906 ORs the internal CLINT's hardware supervisor-timer line into mip.STIP (aq_cp0_trap_csr.v: st_int && CLINTEE || stip_reg) and the RTL resets mxstatus.CLINTEE to 1. Nothing ever programmed STIMECMP, and the compare registers' 0xFFFF_FFFF reset values are not guaranteed to be applied (the HP hold-reset produces no async negedge in Verilator, so the regs stay zero), so st_int fires from the first cycle: the moment the kernel enables sie.STIE in time_init, it falls into an infinite supervisor-timer storm and the boot thread starves right after the sched_clock print. (M-mode firmware is immune, which is why RT-Thread and OpenSBI were unaffected.) Probe evidence after the fix: MTIMECMP arms exactly one jiffy out (mtime+3979 at HZ=250) and MTIP fires exactly at the compare value on a healthy 288K-cycle cadence; the kernel boots through console init, BogoMIPS, devtmpfs, and switches to the riscv_clocksource. Park both compare registers explicitly at cold boot so the state is deterministic on silicon and in simulation. --- app/ports/linux/opensbi/retrosoc_hp/platform.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/app/ports/linux/opensbi/retrosoc_hp/platform.c b/app/ports/linux/opensbi/retrosoc_hp/platform.c index 6d35c315..6c346569 100644 --- a/app/ports/linux/opensbi/retrosoc_hp/platform.c +++ b/app/ports/linux/opensbi/retrosoc_hp/platform.c @@ -14,6 +14,8 @@ #define RETROSOC_HP_CLINT_BASE 0x0C000000UL #define RETROSOC_HP_CLINT_MTIMECMP_LO 0x4000UL #define RETROSOC_HP_CLINT_MTIMECMP_HI 0x4004UL +#define RETROSOC_HP_CLINT_STIMECMP_LO 0xD000UL +#define RETROSOC_HP_CLINT_STIMECMP_HI 0xD004UL #define RETROSOC_HP_UART_BASE 0x10018000UL #define RETROSOC_HP_UART_BAUD_INT 78U #define RETROSOC_HP_UART_BAUD_FRAC 32U @@ -134,6 +136,18 @@ static int retrosoc_hp_early_init(bool cold_boot) { csr_write(RETROSOC_HP_CSR_MHCR, RETROSOC_HP_MHCR_CACHES_BPU); csr_clear(RETROSOC_HP_CSR_MXSTATUS, RETROSOC_HP_MXSTATUS_MAEE); + /* Park both internal-CLINT compare registers. The C906 ORs the hardware + * supervisor-timer line into mip.STIP (aq_cp0_trap_csr.v: st_int && CLINTEE, + * and the RTL resets CLINTEE to 1), so an unparked STIMECMP wedges S-mode + * with an infinite supervisor-timer interrupt the moment the kernel enables + * sie.STIE. The compare registers' 0xFFFF_FFFF reset values are not + * guaranteed to be applied (the hold-reset produces no async negedge in + * Verilator), so park them explicitly at cold boot. */ + retrosoc_hp_mtimecmp_write(~0ULL); + writel_relaxed((u32)-1, (void *)(RETROSOC_HP_CLINT_BASE + RETROSOC_HP_CLINT_STIMECMP_LO)); + writel_relaxed((u32)-1, (void *)(RETROSOC_HP_CLINT_BASE + RETROSOC_HP_CLINT_STIMECMP_HI)); + writel_relaxed((u32)-1, (void *)(RETROSOC_HP_CLINT_BASE + RETROSOC_HP_CLINT_STIMECMP_LO)); + retrosoc_hp_uart_write(RETROSOC_HP_UART_CTRL_REG, 0U); retrosoc_hp_uart_write(RETROSOC_HP_UART_FIFO_CTRL_REG, RETROSOC_HP_UART_FIFO_FLUSH); retrosoc_hp_uart_write(RETROSOC_HP_UART_ERROR_REG, RETROSOC_HP_UART_ERROR_ALL); From e6774d0f69e67197d51923397e8e01e2f3296d14 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Mon, 12 Oct 2026 22:34:03 +0800 Subject: [PATCH 12/31] docs: record the STIMECMP supervisor-timer storm root cause --- docs/hp-rv64-validation.md | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index 76a5a313..db6f759d 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -50,9 +50,10 @@ qualification. Current evidence requires, at minimum: CRC-checked). The kernel enters S-mode, brings Sv39 up, executes past `set_cpu_online()`'s first AMO, and prints `Linux version 6.12.105+` on the SBI console: the earlier boot blocker is fixed (see the MAEE entry below). - The run ends on the wall-clock budget while the kernel is mid-`meminit` - (`Initmem setup node 0`), retiring steadily with no further traps; userspace - acceptance (`HP_LINUX_READY`) is continued on a longer bounded run. The + A longer bounded run (8 h wall) with the STIMECMP fix additionally boots + the kernel through console init, BogoMIPS calibration, devtmpfs, and the + switch to the riscv_clocksource with a healthy periodic tick; userspace + acceptance (`HP_LINUX_READY`) evidence is collected on that run. The target stays unqualified until that acceptance completes. - The Linux boot blocker was a doc/RTL mismatch in OpenC906, root-caused with bare-metal MMU payloads and locked by simulation evidence: the user manual @@ -72,6 +73,21 @@ qualification. Current evidence requires, at minimum: strong-order device) so the stock kernel needs no T-Head PBMT errata. A directed payload then passes the full AMO battery (amoor/amoadd/amoswap/ lr-sc, cold-line and high-half-VA variants). +- The post-`sched_clock` stall was a second doc/RTL trap of the same family: + the C906 ORs the internal CLINT's hardware supervisor-timer line into + `mip.STIP` (`aq_cp0_trap_csr.v`: `st_int && CLINTEE || stip_reg`) and the + RTL resets `CLINTEE` to 1. Nobody parked the internal STIMECMP, and the + compare registers' `0xFFFF_FFFF` reset values are not guaranteed to be + applied (the HP hold-reset produces no async negedge in Verilator, leaving + them at zero), so the hardware S-timer line fired continuously: the first + `sie.STIE` enable in the kernel's `time_init` dropped it into an infinite + supervisor-timer storm and starved the boot thread. M-mode firmware + (RT-Thread, OpenSBI) is immune, which is why earlier targets were + unaffected. The OpenSBI `early_init` now parks both internal-CLINT compare + registers at cold boot, making the state deterministic on silicon and in + simulation; probe evidence shows MTIMECMP armed exactly one jiffy out and + MTIP firing exactly at the compare value on a healthy 288 kHz-cycle + cadence. - The RT-Thread bring-up exposed and fixed three latent issues, each locked by directed regression. (a) The C906 resets with caches and the BPU disabled and does not initialize the cache/predictor RAMs: HP payloads must From dd3ee032b2c201151e63958ab648f514625e41b7 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Wed, 14 Oct 2026 16:33:35 +0800 Subject: [PATCH 13/31] feat(hp): swap the OpenC906 SRAM wrappers to PDK-selectable macros Implement the memory replacement required by chapter 3 of the OpenC906 integration manual for the Mini HP core. The eight aq_spsram_* single-port SRAM wrappers (BHT, ICache data/tag, DCache data/dirty/tag, JTLB data/tag) gain reviewed overrides in rtl/mini/ip_overrides/, registered in scripts/generate_openc906.py with sha256 pins on the vendored files at the locked revision b0c06eb1. Each override keeps the upstream behavioral aq_f_spsram_* instance byte-identical by default; only PDK_IHP130 + HAVE_SRAM_MACRO without PDK_BEHAV instantiates IHP130 RM_IHPSG13_1P_* macros, stacked per manual section 3.1.5 (depth stacks with a read-registered bank select, width stacks, zero-padded unused write-mask bits). Macro ports map CEN/GWEN/WEN onto A_MEN/A_WEN/A_REN/A_BM with A_DLY tied high and BIST pins tied off, matching the tc_sram.sv convention. Committed CI profiles keep PDK_BEHAV=YES, so their simulation results are unchanged. The Makefile also lists the new overrides as prerequisites of the generated-filelist stamp so editing one forces regeneration. Evidence: directed 8-wrapper equivalence TB (behavioral vs macro, Icarus) and the manual section 3.2 MEM_INTF suite adapted to Icarus both pass on the macro path. --- Makefile | 10 +- rtl/mini/ip_overrides/aq_spsram_1024x16.v | 138 +++++++++++++++++ rtl/mini/ip_overrides/aq_spsram_1024x64.v | 156 +++++++++++++++++++ rtl/mini/ip_overrides/aq_spsram_128x8.v | 175 ++++++++++++++++++++++ rtl/mini/ip_overrides/aq_spsram_2048x32.v | 169 +++++++++++++++++++++ rtl/mini/ip_overrides/aq_spsram_256x59.v | 157 +++++++++++++++++++ rtl/mini/ip_overrides/aq_spsram_64x58.v | 137 +++++++++++++++++ rtl/mini/ip_overrides/aq_spsram_64x88.v | 162 ++++++++++++++++++++ rtl/mini/ip_overrides/aq_spsram_64x98.v | 162 ++++++++++++++++++++ scripts/generate_openc906.py | 38 +++++ 10 files changed, 1303 insertions(+), 1 deletion(-) create mode 100644 rtl/mini/ip_overrides/aq_spsram_1024x16.v create mode 100644 rtl/mini/ip_overrides/aq_spsram_1024x64.v create mode 100644 rtl/mini/ip_overrides/aq_spsram_128x8.v create mode 100644 rtl/mini/ip_overrides/aq_spsram_2048x32.v create mode 100644 rtl/mini/ip_overrides/aq_spsram_256x59.v create mode 100644 rtl/mini/ip_overrides/aq_spsram_64x58.v create mode 100644 rtl/mini/ip_overrides/aq_spsram_64x88.v create mode 100644 rtl/mini/ip_overrides/aq_spsram_64x98.v diff --git a/Makefile b/Makefile index 9d259c11..6504b975 100644 --- a/Makefile +++ b/Makefile @@ -1112,7 +1112,15 @@ npu-p5-lp-sim: firmware sim ifeq ($(HAVE_HP),YES) $(HP_GENERATED_STAMP): $(ROOT_PATH)/scripts/generate_openc906.py \ $(ROOT_PATH)/rtl/mini/ip_overrides/aq_sysio_kid.v \ - $(ROOT_PATH)/rtl/mini/ip_overrides/sysmap.h $(LOCK_FILE) + $(ROOT_PATH)/rtl/mini/ip_overrides/sysmap.h \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_1024x16.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_2048x32.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_256x59.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_1024x64.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_128x8.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x58.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x88.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x98.v $(LOCK_FILE) python3 $(ROOT_PATH)/scripts/generate_openc906.py \ --root $(ROOT_PATH) --source $(OPENC906_ROOT) --output $(HP_GENERATED_DIR) \ --manifest $(HP_GENERATED_MANIFEST) --lock $(LOCK_FILE) diff --git a/rtl/mini/ip_overrides/aq_spsram_1024x16.v b/rtl/mini/ip_overrides/aq_spsram_1024x16.v new file mode 100644 index 00000000..ec5e2167 --- /dev/null +++ b/rtl/mini/ip_overrides/aq_spsram_1024x16.v @@ -0,0 +1,138 @@ +// retroSoC controlled override of the vendored OpenC906 aq_spsram_1024x16.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_1024x16.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with +// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 1024x16 BHT RAM is +// built from one RM_IHPSG13_1P_1024x32_c2_bm_bist macro; only the low 16 +// bits are used and the upper mask bits are tied off so they are never +// written. Every other configuration keeps the upstream behavioral +// aq_f_spsram_1024x16 instance byte-identical. Keep in sync when the lock +// revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module aq_spsram_1024x16( + A, + CEN, + CLK, + D, + GWEN, + Q, + WEN +); + +// &Ports; @23 +input [9 :0] A; +input CEN; +input CLK; +input [15:0] D; +input GWEN; +input [15:0] WEN; +output [15:0] Q; + +// &Regs; @24 + +// &Wires; @25 +wire [9 :0] A; +wire CEN; +wire CLK; +wire [15:0] D; +wire GWEN; +wire [15:0] Q; +wire [15:0] WEN; + + +//********************************************************** +// Parameter Definition +//********************************************************** +parameter ADDR_WIDTH = 10; +parameter DATA_WIDTH = 16; +parameter WE_WIDTH = 16; + +// &Force("bus","Q",DATA_WIDTH-1,0); @34 +// &Force("bus","WEN",WE_WIDTH-1,0); @35 +// &Force("bus","A",ADDR_WIDTH-1,0); @36 +// &Force("bus","D",DATA_WIDTH-1,0); @37 + +`ifdef PDK_IHP130 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_1024X16_IHP130_ +`endif +`endif +`endif + +`ifdef _AQ_SPSRAM_1024X16_IHP130_ + //******************************************************** + //* IHP130 SRAM macro * + //******************************************************** +// One 1024x32 macro supplies the 1024x16 BHT RAM; the upper 16 bits are +// masked off so they are never written. +wire [31:0] s_dout; +wire [15:0] s_dout_unused; + +assign Q = s_dout[15:0]; +assign s_dout_unused = s_dout[31:16]; + +RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem ( + .A_CLK (CLK ), + .A_ADDR (A ), + .A_BM ({16'b0, ~WEN} ), + .A_MEN (~CEN ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN ({16'b0, D} ), + .A_DOUT (s_dout ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(10'b0 ), + .A_BIST_DIN (32'b0 ), + .A_BIST_BM (32'b0 ) +); +`else + //******************************************************** + //* FPGA memory * + //******************************************************** +// &Instance("aq_f_spsram_1024x16"); @43 +aq_f_spsram_1024x16 x_aq_f_spsram_1024x16 ( + .A (A ), + .CEN (CEN ), + .CLK (CLK ), + .D (D ), + .GWEN (GWEN), + .Q (Q ), + .WEN (WEN ) +); +`endif + +`ifdef _AQ_SPSRAM_1024X16_IHP130_ +`undef _AQ_SPSRAM_1024X16_IHP130_ +`endif + +// &Instance("aq_tsmc_spsram_1024x16"); @49 +// &Instance("aq_umc_spsram_1024x16"); @61 + +// &ModuleEnd; @65 +endmodule diff --git a/rtl/mini/ip_overrides/aq_spsram_1024x64.v b/rtl/mini/ip_overrides/aq_spsram_1024x64.v new file mode 100644 index 00000000..ce7c853e --- /dev/null +++ b/rtl/mini/ip_overrides/aq_spsram_1024x64.v @@ -0,0 +1,156 @@ +// retroSoC controlled override of the vendored OpenC906 aq_spsram_1024x64.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_1024x64.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with +// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 1024x64 DCache data +// RAM is built from two RM_IHPSG13_1P_1024x32_c2_bm_bist macros in a width +// stack: one macro holds the low 32 bits, the other the high 32 bits (manual +// section 3.1.5 stacking). Every other configuration keeps the upstream +// behavioral aq_f_spsram_1024x64 instance byte-identical. Keep in sync when +// the lock revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module aq_spsram_1024x64( + A, + CEN, + CLK, + D, + GWEN, + Q, + WEN +); + +// &Ports; @23 +input [9 :0] A; +input CEN; +input CLK; +input [63:0] D; +input GWEN; +input [63:0] WEN; +output [63:0] Q; + +// &Regs; @24 + +// &Wires; @25 +wire [9 :0] A; +wire CEN; +wire CLK; +wire [63:0] D; +wire GWEN; +wire [63:0] Q; +wire [63:0] WEN; + + +//********************************************************** +// Parameter Definition +//********************************************************** +parameter ADDR_WIDTH = 10; +parameter DATA_WIDTH = 64; +parameter WE_WIDTH = 64; + +// &Force("bus","Q",DATA_WIDTH-1,0); @34 +// &Force("bus","WEN",WE_WIDTH-1,0); @35 +// &Force("bus","A",ADDR_WIDTH-1,0); @36 +// &Force("bus","D",DATA_WIDTH-1,0); @37 + +`ifdef PDK_IHP130 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_1024X64_IHP130_ +`endif +`endif +`endif + +`ifdef _AQ_SPSRAM_1024X64_IHP130_ + //******************************************************** + //* IHP130 SRAM macro * + //******************************************************** +// Two 1024x32 macros are width-stacked into 1024x64: the low and high 32 +// bits each get one macro sharing address and control. +wire [31:0] s_q_lo; +wire [31:0] s_q_hi; + +assign Q = {s_q_hi, s_q_lo}; + +RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_lo ( + .A_CLK (CLK ), + .A_ADDR (A ), + .A_BM (~WEN[31:0] ), + .A_MEN (~CEN ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN (D[31:0] ), + .A_DOUT (s_q_lo ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(10'b0 ), + .A_BIST_DIN (32'b0 ), + .A_BIST_BM (32'b0 ) +); + +RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_hi ( + .A_CLK (CLK ), + .A_ADDR (A ), + .A_BM (~WEN[63:32] ), + .A_MEN (~CEN ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN (D[63:32] ), + .A_DOUT (s_q_hi ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(10'b0 ), + .A_BIST_DIN (32'b0 ), + .A_BIST_BM (32'b0 ) +); +`else +// //******************************************************** +// //* FPGA memory * +// //******************************************************** +// &Instance("aq_f_spsram_1024x64"); @43 +aq_f_spsram_1024x64 x_aq_f_spsram_1024x64 ( + .A (A ), + .CEN (CEN ), + .CLK (CLK ), + .D (D ), + .GWEN (GWEN), + .Q (Q ), + .WEN (WEN ) +); +`endif + +`ifdef _AQ_SPSRAM_1024X64_IHP130_ +`undef _AQ_SPSRAM_1024X64_IHP130_ +`endif + +// &Instance("aq_umc_spsram_1024x64"); @49 +// &Instance("aq_tsmc_spsram_1024x64"); @55 +// &ModuleEnd; @58 +endmodule diff --git a/rtl/mini/ip_overrides/aq_spsram_128x8.v b/rtl/mini/ip_overrides/aq_spsram_128x8.v new file mode 100644 index 00000000..16d6f997 --- /dev/null +++ b/rtl/mini/ip_overrides/aq_spsram_128x8.v @@ -0,0 +1,175 @@ +// retroSoC controlled override of the vendored OpenC906 aq_spsram_128x8.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_128x8.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with +// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 128x8 DCache dirty +// RAM is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a depth +// stack: A[6] selects the bank, only the low 8 bits of each macro are used +// (upper mask bits tied off so they are never written), and the read-data +// mux uses the bank select registered on read transactions (manual section +// 3.1.5 stacking). Every other configuration keeps the upstream behavioral +// aq_f_spsram_128x8 instance byte-identical. Keep in sync when the lock +// revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module aq_spsram_128x8( + A, + CEN, + CLK, + D, + GWEN, + Q, + WEN +); + +// &Ports; @23 +input [6:0] A; +input CEN; +input CLK; +input [7:0] D; +input GWEN; +input [7:0] WEN; +output [7:0] Q; + +// &Regs; @24 + +// &Wires; @25 +wire [6:0] A; +wire CEN; +wire CLK; +wire [7:0] D; +wire GWEN; +wire [7:0] Q; +wire [7:0] WEN; + + +//********************************************************** +// Parameter Definition +//********************************************************** +parameter ADDR_WIDTH = 7; +parameter DATA_WIDTH = 8; +parameter WE_WIDTH = 8; + +// &Force("bus","Q",DATA_WIDTH-1,0); @34 +// &Force("bus","WEN",WE_WIDTH-1,0); @35 +// &Force("bus","A",ADDR_WIDTH-1,0); @36 +// &Force("bus","D",DATA_WIDTH-1,0); @37 + +`ifdef PDK_IHP130 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_128X8_IHP130_ +`endif +`endif +`endif + +`ifdef _AQ_SPSRAM_128X8_IHP130_ + //******************************************************** + //* IHP130 SRAM macro * + //******************************************************** +// Two 64x64 macros are depth-stacked into 128x8: A[6] chip-selects the bank, +// the upper 56 data/mask bits of each macro are tied off so they are never +// written, and the read-data mux uses the bank select registered on reads. +wire [63:0] s_din; +wire [63:0] s_bm; +wire [63:0] s_q_lo; +wire [63:0] s_q_hi; +wire [55:0] s_q_lo_unused; +wire [55:0] s_q_hi_unused; +reg s_rd_sel_q; + +assign s_din = {56'b0, D}; +assign s_bm = {56'b0, ~WEN}; + +always @(posedge CLK) begin + if (!CEN && GWEN) begin + s_rd_sel_q <= A[6]; + end +end + +assign Q = s_rd_sel_q ? s_q_hi[7:0] : s_q_lo[7:0]; +assign s_q_lo_unused = s_q_lo[63:8]; +assign s_q_hi_unused = s_q_hi[63:8]; + +RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_lo ( + .A_CLK (CLK ), + .A_ADDR (A[5:0] ), + .A_BM (s_bm ), + .A_MEN (~CEN & ~A[6] ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN (s_din ), + .A_DOUT (s_q_lo ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(6'b0 ), + .A_BIST_DIN (64'b0 ), + .A_BIST_BM (64'b0 ) +); + +RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_hi ( + .A_CLK (CLK ), + .A_ADDR (A[5:0] ), + .A_BM (s_bm ), + .A_MEN (~CEN & A[6] ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN (s_din ), + .A_DOUT (s_q_hi ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(6'b0 ), + .A_BIST_DIN (64'b0 ), + .A_BIST_BM (64'b0 ) +); +`else +// //******************************************************** +// //* FPGA memory * +// //******************************************************** +// &Instance("aq_f_spsram_128x8"); @43 +aq_f_spsram_128x8 x_aq_f_spsram_128x8 ( + .A (A ), + .CEN (CEN ), + .CLK (CLK ), + .D (D ), + .GWEN (GWEN), + .Q (Q ), + .WEN (WEN ) +); +`endif + +`ifdef _AQ_SPSRAM_128X8_IHP130_ +`undef _AQ_SPSRAM_128X8_IHP130_ +`endif + +// &Instance("aq_umc_spsram_128x8"); @49 +// &Instance("aq_tsmc_spsram_128x8"); @55 +// &ModuleEnd; @58 +endmodule diff --git a/rtl/mini/ip_overrides/aq_spsram_2048x32.v b/rtl/mini/ip_overrides/aq_spsram_2048x32.v new file mode 100644 index 00000000..466c6461 --- /dev/null +++ b/rtl/mini/ip_overrides/aq_spsram_2048x32.v @@ -0,0 +1,169 @@ +// retroSoC controlled override of the vendored OpenC906 aq_spsram_2048x32.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_2048x32.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with +// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 2048x32 ICache data +// RAM is built from two RM_IHPSG13_1P_1024x32_c2_bm_bist macros in a depth +// stack: A[10] selects the bank and the read-data mux uses the bank select +// registered on read transactions (manual section 3.1.5 stacking). Every +// other configuration keeps the upstream behavioral aq_f_spsram_2048x32 +// instance byte-identical. Keep in sync when the lock revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module aq_spsram_2048x32( + A, + CEN, + CLK, + D, + GWEN, + Q, + WEN +); + +// &Ports; @23 +input [10:0] A; +input CEN; +input CLK; +input [31:0] D; +input GWEN; +input [31:0] WEN; +output [31:0] Q; + +// &Regs; @24 + +// &Wires; @25 +wire [10:0] A; +wire CEN; +wire CLK; +wire [31:0] D; +wire GWEN; +wire [31:0] Q; +wire [31:0] WEN; + + +//********************************************************** +// Parameter Definition +//********************************************************** +parameter ADDR_WIDTH = 11; +parameter DATA_WIDTH = 32; +parameter WE_WIDTH = 32; + +// &Force("bus","Q",DATA_WIDTH-1,0); @34 +// &Force("bus","WEN",WE_WIDTH-1,0); @35 +// &Force("bus","A",ADDR_WIDTH-1,0); @36 +// &Force("bus","D",DATA_WIDTH-1,0); @37 + +`ifdef PDK_IHP130 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_2048X32_IHP130_ +`endif +`endif +`endif + +`ifdef _AQ_SPSRAM_2048X32_IHP130_ + //******************************************************** + //* IHP130 SRAM macro * + //******************************************************** +// Two 1024x32 macros are depth-stacked into 2048x32: A[10] chip-selects the +// bank, and the read-data mux uses the bank select registered on reads. +wire s_en_lo; +wire s_en_hi; +wire [31:0] s_q_lo; +wire [31:0] s_q_hi; +reg s_rd_sel_q; + +assign s_en_lo = ~CEN & ~A[10]; +assign s_en_hi = ~CEN & A[10]; + +always @(posedge CLK) begin + if (!CEN && GWEN) begin + s_rd_sel_q <= A[10]; + end +end + +assign Q = s_rd_sel_q ? s_q_hi : s_q_lo; + +RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_lo ( + .A_CLK (CLK ), + .A_ADDR (A[9:0] ), + .A_BM (~WEN ), + .A_MEN (s_en_lo ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN (D ), + .A_DOUT (s_q_lo ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(10'b0 ), + .A_BIST_DIN (32'b0 ), + .A_BIST_BM (32'b0 ) +); + +RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_hi ( + .A_CLK (CLK ), + .A_ADDR (A[9:0] ), + .A_BM (~WEN ), + .A_MEN (s_en_hi ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN (D ), + .A_DOUT (s_q_hi ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(10'b0 ), + .A_BIST_DIN (32'b0 ), + .A_BIST_BM (32'b0 ) +); +`else + //******************************************************** + //* FPGA memory * + //******************************************************** +// &Instance("aq_f_spsram_2048x32"); @43 +aq_f_spsram_2048x32 x_aq_f_spsram_2048x32 ( + .A (A ), + .CEN (CEN ), + .CLK (CLK ), + .D (D ), + .GWEN (GWEN), + .Q (Q ), + .WEN (WEN ) +); +`endif + +`ifdef _AQ_SPSRAM_2048X32_IHP130_ +`undef _AQ_SPSRAM_2048X32_IHP130_ +`endif + +// &Instance("aq_tsmc_spsram_2048x32"); @49 +// &Instance("aq_umc_spsram_2048x32"); @61 + +// &ModuleEnd; @65 +endmodule diff --git a/rtl/mini/ip_overrides/aq_spsram_256x59.v b/rtl/mini/ip_overrides/aq_spsram_256x59.v new file mode 100644 index 00000000..f7ec3cd8 --- /dev/null +++ b/rtl/mini/ip_overrides/aq_spsram_256x59.v @@ -0,0 +1,157 @@ +// retroSoC controlled override of the vendored OpenC906 aq_spsram_256x59.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_256x59.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with +// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 256x59 ICache tag +// RAM is built from four RM_IHPSG13_1P_64x64_c2_bm_bist macros in a depth +// stack: A[7:6] selects the bank, only the low 59 bits of each macro are +// used (upper mask bits tied off so they are never written), and the +// read-data mux uses the bank select registered on read transactions +// (manual section 3.1.5 stacking). Every other configuration keeps the +// upstream behavioral aq_f_spsram_256x59 instance byte-identical. Keep in +// sync when the lock revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module aq_spsram_256x59( + A, + CEN, + CLK, + D, + GWEN, + Q, + WEN +); + +// &Ports; @23 +input [7 :0] A; +input CEN; +input CLK; +input [58:0] D; +input GWEN; +input [58:0] WEN; +output [58:0] Q; + +// &Regs; @24 + +// &Wires; @25 +wire [7 :0] A; +wire CEN; +wire CLK; +wire [58:0] D; +wire GWEN; +wire [58:0] Q; +wire [58:0] WEN; + + +//********************************************************** +// Parameter Definition +//********************************************************** +parameter ADDR_WIDTH = 8; +parameter DATA_WIDTH = 59; +parameter WE_WIDTH = 59; + +// &Force("bus","Q",DATA_WIDTH-1,0); @34 +// &Force("bus","WEN",WE_WIDTH-1,0); @35 +// &Force("bus","A",ADDR_WIDTH-1,0); @36 +// &Force("bus","D",DATA_WIDTH-1,0); @37 + +`ifdef PDK_IHP130 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_256X59_IHP130_ +`endif +`endif +`endif + +`ifdef _AQ_SPSRAM_256X59_IHP130_ + //******************************************************** + //* IHP130 SRAM macro * + //******************************************************** +// Four 64x64 macros are depth-stacked into 256x59: A[7:6] chip-selects the +// bank, the upper 5 data/mask bits of each macro are tied off so they are +// never written, and the read-data mux uses the bank select registered on +// reads. +wire [63:0] s_din; +wire [63:0] s_bm; +wire [255:0] s_dout; +reg [1:0] s_rd_sel_q; +genvar g_bank; + +assign s_din = {5'b0, D}; +assign s_bm = {5'b0, ~WEN}; + +always @(posedge CLK) begin + if (!CEN && GWEN) begin + s_rd_sel_q <= A[7:6]; + end +end + +assign Q = s_dout[s_rd_sel_q*64 +: 59]; + +generate + for (g_bank = 0; g_bank < 4; g_bank = g_bank + 1) begin : gen_bank + RM_IHPSG13_1P_64x64_c2_bm_bist u_mem ( + .A_CLK (CLK ), + .A_ADDR (A[5:0] ), + .A_BM (s_bm ), + .A_MEN (~CEN & (A[7:6] == g_bank) ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN (s_din ), + .A_DOUT (s_dout[g_bank*64 +: 64] ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(6'b0 ), + .A_BIST_DIN (64'b0 ), + .A_BIST_BM (64'b0 ) + ); + end +endgenerate +`else + //******************************************************** + //* FPGA memory * + //******************************************************** +// &Instance("aq_f_spsram_256x59"); @43 +aq_f_spsram_256x59 x_aq_f_spsram_256x59 ( + .A (A ), + .CEN (CEN ), + .CLK (CLK ), + .D (D ), + .GWEN (GWEN), + .Q (Q ), + .WEN (WEN ) +); +`endif + +`ifdef _AQ_SPSRAM_256X59_IHP130_ +`undef _AQ_SPSRAM_256X59_IHP130_ +`endif + +// &Instance("aq_tsmc_spsram_256x59"); @49 +// &Instance("aq_umc_spsram_256x59"); @61 + +// &ModuleEnd; @65 +endmodule diff --git a/rtl/mini/ip_overrides/aq_spsram_64x58.v b/rtl/mini/ip_overrides/aq_spsram_64x58.v new file mode 100644 index 00000000..c7b1f25a --- /dev/null +++ b/rtl/mini/ip_overrides/aq_spsram_64x58.v @@ -0,0 +1,137 @@ +// retroSoC controlled override of the vendored OpenC906 aq_spsram_64x58.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_64x58.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with +// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 64x58 DCache tag RAM +// is built from one RM_IHPSG13_1P_64x64_c2_bm_bist macro; only the low 58 +// bits are used and the upper mask bits are tied off so they are never +// written. Every other configuration keeps the upstream behavioral +// aq_f_spsram_64x58 instance byte-identical. Keep in sync when the lock +// revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module aq_spsram_64x58( + A, + CEN, + CLK, + D, + GWEN, + Q, + WEN +); + +// &Ports; @23 +input [5 :0] A; +input CEN; +input CLK; +input [57:0] D; +input GWEN; +input [57:0] WEN; +output [57:0] Q; + +// &Regs; @24 + +// &Wires; @25 +wire [5 :0] A; +wire CEN; +wire CLK; +wire [57:0] D; +wire GWEN; +wire [57:0] Q; +wire [57:0] WEN; + + +//********************************************************** +// Parameter Definition +//********************************************************** +parameter ADDR_WIDTH = 6; +parameter DATA_WIDTH = 58; +parameter WE_WIDTH = 58; + +// &Force("bus","Q",DATA_WIDTH-1,0); @34 +// &Force("bus","WEN",WE_WIDTH-1,0); @35 +// &Force("bus","A",ADDR_WIDTH-1,0); @36 +// &Force("bus","D",DATA_WIDTH-1,0); @37 + +`ifdef PDK_IHP130 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_64X58_IHP130_ +`endif +`endif +`endif + +`ifdef _AQ_SPSRAM_64X58_IHP130_ + //******************************************************** + //* IHP130 SRAM macro * + //******************************************************** +// One 64x64 macro supplies the 64x58 DCache tag RAM; the upper 6 bits are +// masked off so they are never written. +wire [63:0] s_dout; +wire [5:0] s_dout_unused; + +assign Q = s_dout[57:0]; +assign s_dout_unused = s_dout[63:58]; + +RM_IHPSG13_1P_64x64_c2_bm_bist u_mem ( + .A_CLK (CLK ), + .A_ADDR (A ), + .A_BM ({6'b0, ~WEN} ), + .A_MEN (~CEN ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN ({6'b0, D} ), + .A_DOUT (s_dout ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(6'b0 ), + .A_BIST_DIN (64'b0 ), + .A_BIST_BM (64'b0 ) +); +`else +// //******************************************************** +// //* FPGA memory * +// //******************************************************** +// &Instance("aq_f_spsram_64x58"); @43 +aq_f_spsram_64x58 x_aq_f_spsram_64x58 ( + .A (A ), + .CEN (CEN ), + .CLK (CLK ), + .D (D ), + .GWEN (GWEN), + .Q (Q ), + .WEN (WEN ) +); +`endif + +`ifdef _AQ_SPSRAM_64X58_IHP130_ +`undef _AQ_SPSRAM_64X58_IHP130_ +`endif + +// &Instance("aq_umc_spsram_64x58"); @49 +// &Instance("aq_tsmc_spsram_64x58"); @55 +// &ModuleEnd; @58 +endmodule diff --git a/rtl/mini/ip_overrides/aq_spsram_64x88.v b/rtl/mini/ip_overrides/aq_spsram_64x88.v new file mode 100644 index 00000000..5d7a13fb --- /dev/null +++ b/rtl/mini/ip_overrides/aq_spsram_64x88.v @@ -0,0 +1,162 @@ +// retroSoC controlled override of the vendored OpenC906 aq_spsram_64x88.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/mmu/rtl/aq_spsram_64x88.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with +// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 64x88 JTLB data RAM +// is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a width stack: +// one macro holds the low 64 bits, the other the high 24 bits with its upper +// mask bits tied off so they are never written (manual section 3.1.5 +// stacking). Every other configuration keeps the upstream behavioral +// aq_f_spsram_64x88 instance byte-identical. Keep in sync when the lock +// revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module aq_spsram_64x88( + A, + CEN, + CLK, + D, + GWEN, + Q, + WEN +); + +// &Ports; @23 +input [5 :0] A; +input CEN; +input CLK; +input [87:0] D; +input GWEN; +input [87:0] WEN; +output [87:0] Q; + +// &Regs; @24 + +// &Wires; @25 +wire [5 :0] A; +wire CEN; +wire CLK; +wire [87:0] D; +wire GWEN; +wire [87:0] Q; +wire [87:0] WEN; + + +//********************************************************** +// Parameter Definition +//********************************************************** +parameter ADDR_WIDTH = 6; +parameter DATA_WIDTH = 88; +parameter WE_WIDTH = 88; + +// &Force("bus","Q",DATA_WIDTH-1,0); @34 +// &Force("bus","WEN",WE_WIDTH-1,0); @35 +// &Force("bus","A",ADDR_WIDTH-1,0); @36 +// &Force("bus","D",DATA_WIDTH-1,0); @37 + +`ifdef PDK_IHP130 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_64X88_IHP130_ +`endif +`endif +`endif + +`ifdef _AQ_SPSRAM_64X88_IHP130_ + //******************************************************** + //* IHP130 SRAM macro * + //******************************************************** +// Two 64x64 macros are width-stacked into 64x88: the low 64 bits get one +// macro, the high 24 bits get another with its upper 40 mask bits tied off +// so they are never written; both share address and control. +wire [63:0] s_q_lo; +wire [63:0] s_q_hi; +wire [39:0] s_q_hi_unused; + +assign Q = {s_q_hi[23:0], s_q_lo}; +assign s_q_hi_unused = s_q_hi[63:24]; + +RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_lo ( + .A_CLK (CLK ), + .A_ADDR (A ), + .A_BM (~WEN[63:0] ), + .A_MEN (~CEN ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN (D[63:0] ), + .A_DOUT (s_q_lo ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(6'b0 ), + .A_BIST_DIN (64'b0 ), + .A_BIST_BM (64'b0 ) +); + +RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_hi ( + .A_CLK (CLK ), + .A_ADDR (A ), + .A_BM ({40'b0, ~WEN[87:64]}), + .A_MEN (~CEN ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN ({40'b0, D[87:64]} ), + .A_DOUT (s_q_hi ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(6'b0 ), + .A_BIST_DIN (64'b0 ), + .A_BIST_BM (64'b0 ) +); +`else + //******************************************************** + //* FPGA memory * + //******************************************************** + //{WEN[135:132],WEN[131:99],WEN[98:66],WEN[65:33],WEN[32:0]} +// &Instance("aq_f_spsram_64x88"); @44 +aq_f_spsram_64x88 x_aq_f_spsram_64x88 ( + .A (A ), + .CEN (CEN ), + .CLK (CLK ), + .D (D ), + .GWEN (GWEN), + .Q (Q ), + .WEN (WEN ) +); +`endif + +`ifdef _AQ_SPSRAM_64X88_IHP130_ +`undef _AQ_SPSRAM_64X88_IHP130_ +`endif + +// &Instance("aq_tsmc_spsram_64x88"); @50 +// &Instance("aq_umc_spsram_64x88"); @62 + +// &ModuleEnd; @66 +endmodule diff --git a/rtl/mini/ip_overrides/aq_spsram_64x98.v b/rtl/mini/ip_overrides/aq_spsram_64x98.v new file mode 100644 index 00000000..c3b64b77 --- /dev/null +++ b/rtl/mini/ip_overrides/aq_spsram_64x98.v @@ -0,0 +1,162 @@ +// retroSoC controlled override of the vendored OpenC906 aq_spsram_64x98.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/mmu/rtl/aq_spsram_64x98.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 SRAM swap): with +// PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 64x98 JTLB tag RAM +// is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a width stack: +// one macro holds the low 64 bits, the other the high 34 bits with its upper +// mask bits tied off so they are never written (manual section 3.1.5 +// stacking). Every other configuration keeps the upstream behavioral +// aq_f_spsram_64x98 instance byte-identical. Keep in sync when the lock +// revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module aq_spsram_64x98( + A, + CEN, + CLK, + D, + GWEN, + Q, + WEN +); + +// &Ports; @23 +input [5 :0] A; +input CEN; +input CLK; +input [97:0] D; +input GWEN; +input [97:0] WEN; +output [97:0] Q; + +// &Regs; @24 + +// &Wires; @25 +wire [5 :0] A; +wire CEN; +wire CLK; +wire [97:0] D; +wire GWEN; +wire [97:0] Q; +wire [97:0] WEN; + + +//********************************************************** +// Parameter Definition +//********************************************************** +parameter ADDR_WIDTH = 6; +parameter DATA_WIDTH = 98; +parameter WE_WIDTH = 98; + +// &Force("bus","Q",DATA_WIDTH-1,0); @34 +// &Force("bus","WEN",WE_WIDTH-1,0); @35 +// &Force("bus","A",ADDR_WIDTH-1,0); @36 +// &Force("bus","D",DATA_WIDTH-1,0); @37 + +`ifdef PDK_IHP130 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_64X98_IHP130_ +`endif +`endif +`endif + +`ifdef _AQ_SPSRAM_64X98_IHP130_ + //******************************************************** + //* IHP130 SRAM macro * + //******************************************************** +// Two 64x64 macros are width-stacked into 64x98: the low 64 bits get one +// macro, the high 34 bits get another with its upper 30 mask bits tied off +// so they are never written; both share address and control. +wire [63:0] s_q_lo; +wire [63:0] s_q_hi; +wire [29:0] s_q_hi_unused; + +assign Q = {s_q_hi[33:0], s_q_lo}; +assign s_q_hi_unused = s_q_hi[63:34]; + +RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_lo ( + .A_CLK (CLK ), + .A_ADDR (A ), + .A_BM (~WEN[63:0] ), + .A_MEN (~CEN ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN (D[63:0] ), + .A_DOUT (s_q_lo ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(6'b0 ), + .A_BIST_DIN (64'b0 ), + .A_BIST_BM (64'b0 ) +); + +RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_hi ( + .A_CLK (CLK ), + .A_ADDR (A ), + .A_BM ({30'b0, ~WEN[97:64]}), + .A_MEN (~CEN ), + .A_WEN (~GWEN ), + .A_REN (GWEN ), + .A_DIN ({30'b0, D[97:64]} ), + .A_DOUT (s_q_hi ), + .A_DLY (1'b1 ), + .A_BIST_CLK (1'b0 ), + .A_BIST_EN (1'b0 ), + .A_BIST_MEN (1'b0 ), + .A_BIST_WEN (1'b0 ), + .A_BIST_REN (1'b0 ), + .A_BIST_ADDR(6'b0 ), + .A_BIST_DIN (64'b0 ), + .A_BIST_BM (64'b0 ) +); +`else + //******************************************************** + //* FPGA memory * + //******************************************************** + //{WEN[111:56],WEN[55:0]} +// &Instance("aq_f_spsram_64x98"); @44 +aq_f_spsram_64x98 x_aq_f_spsram_64x98 ( + .A (A ), + .CEN (CEN ), + .CLK (CLK ), + .D (D ), + .GWEN (GWEN), + .Q (Q ), + .WEN (WEN ) +); +`endif + +`ifdef _AQ_SPSRAM_64X98_IHP130_ +`undef _AQ_SPSRAM_64X98_IHP130_ +`endif + +// &Instance("aq_tsmc_spsram_64x98"); @50 +// &Instance("aq_umc_spsram_64x98"); @62 + +// &ModuleEnd; @66 +endmodule diff --git a/scripts/generate_openc906.py b/scripts/generate_openc906.py index a3bd7af7..8f790a68 100644 --- a/scripts/generate_openc906.py +++ b/scripts/generate_openc906.py @@ -14,6 +14,12 @@ for their vendored counterparts: window cacheable/bufferable; the override maps the Mini address map with the MMIO window (including the core-internal CLINT/PLIC window) as strong-order non-cacheable, as the OpenC906 user manual requires. +- ``aq_spsram_*.v``: the eight single-port SRAM wrappers (OpenC906 + integration manual chapter 3 memory swap). Each override keeps the upstream + behavioral ``aq_f_spsram_*`` instance by default and substitutes IHP130 + ``RM_IHPSG13_1P_*`` macro combinations (depth/width stacking per manual + section 3.1.5) only when the build defines ``PDK_IHP130`` and + ``HAVE_SRAM_MACRO`` without ``PDK_BEHAV``. All sources are concatenated into a single compilation unit (``openc906_combined.v``) because gen_rtl relies on header macros being @@ -50,6 +56,38 @@ OVERRIDES = { "sysmap.h", "0389089a42ef762768e57bbb4fdcbe6b95f33ab650b5bacc0de8122e0d8711d5", ), + "C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_1024x16.v": ( + "aq_spsram_1024x16.v", + "8969cdfd73933ff4ca105d562e31283e16433f90e4ceaa4339759e6df7ba34d9", + ), + "C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_2048x32.v": ( + "aq_spsram_2048x32.v", + "3f4aa927be7d16a0bcd0d3a0f973d93e5cd1b0912f310981bf24656711964abd", + ), + "C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_256x59.v": ( + "aq_spsram_256x59.v", + "6760517965692f1c94c31be295696d7c016f138d697c3495184a6bb14ce482f3", + ), + "C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_1024x64.v": ( + "aq_spsram_1024x64.v", + "695c054d66f673cc863e2eaea0ec53845c45f83797acb7abe9d08e59dfc9d0bb", + ), + "C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_128x8.v": ( + "aq_spsram_128x8.v", + "7a8e963c4539f5ecfb29b147e5bc1b1e66fffd3cb5ee72923db7199092a15f38", + ), + "C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_spsram_64x58.v": ( + "aq_spsram_64x58.v", + "f4b5457d06d2e97ae158432cb7c265242c05c9f96ffeb8c68083d8cee941bd96", + ), + "C906_RTL_FACTORY/gen_rtl/mmu/rtl/aq_spsram_64x88.v": ( + "aq_spsram_64x88.v", + "0a38b7ffc18c2b837e7a253d7ba7b40fc88a172f1b94ed552470614927d7fee8", + ), + "C906_RTL_FACTORY/gen_rtl/mmu/rtl/aq_spsram_64x98.v": ( + "aq_spsram_64x98.v", + "99680fb11271eee6cfe6ff7aaa95cbdd04ef4f78d7b0e23a18c17ef064a8bedf", + ), } From 7ca1a1a746d760962a9c6f2e45f8b002ad66623d Mon Sep 17 00:00:00 2001 From: maksyuki Date: Wed, 14 Oct 2026 16:33:46 +0800 Subject: [PATCH 14/31] test(hp): boot the C906 smoke payload on IHP130 SRAM macros Factor the focused hp_core_wrapper boot testbench into a shared helper and add test_c906_boots_smoke_payload_with_ihp130_sram_macros, which rebuilds the same real smoke payload run with +define+PDK_IHP130/+HAVE_SRAM_MACRO/ +FUNCTIONAL and the committed RM_IHPSG13_1P_* models. The payload's cache maintenance and GA2D data movement exercise all eight replaced SRAMs (BHT/ICache/DCache/JTLB) for real; both modes must reach HP_C906_BOOT_TEST_PASS. Evidence: pytest tests/test_hp_platform.py -k boots_smoke_payload passes in both modes (2 passed); a whole-SoC macro-mode run via 'make CONFIG=configs/ci/ihp130-hp.mk PDK_BEHAV=NO SIMU=VERILATOR hp-smoke-sim' passes with SIM_TEST_PASS code=0 and the HP_LINUX_READY/HP_GA2D_PASS/HP_GA2D_CACHE_CLEAN markers. --- tests/test_hp_platform.py | 113 ++++++++++++++++++++++++-------------- 1 file changed, 71 insertions(+), 42 deletions(-) diff --git a/tests/test_hp_platform.py b/tests/test_hp_platform.py index 7c5640d0..47ca76c2 100644 --- a/tests/test_hp_platform.py +++ b/tests/test_hp_platform.py @@ -127,8 +127,8 @@ def test_generated_hp_core_rtl_is_not_tracked() -> None: assert tracked == "" -def test_c906_boots_smoke_payload_in_focused_tb(tmp_path: Path) -> None: - """Boot the real HP smoke payload on the hp_core_wrapper integration.""" +def _run_c906_boot_tb(tmp_path: Path, *, sram_macros: bool) -> None: + """Build and run the focused hp_core_wrapper boot testbench.""" verilator = shutil.which("verilator") openc906 = ROOT / ".cache/retrosoc/sources/openc906" if verilator is None or not (openc906 / "C906_RTL_FACTORY").is_dir(): @@ -195,47 +195,66 @@ def test_c906_boots_smoke_payload_in_focused_tb(tmp_path: Path) -> None: output = tmp_path / "hp_c906_boot_tb" ccache_tmp = tmp_path / "ccache" ccache_tmp.mkdir() + command = [ + verilator, + "--binary", + "--timing", + "-Wno-fatal", + "--top-module", + "hp_c906_boot_tb", + "-I" + str(common / "interface"), + "-I" + str(common / "utils"), + "-I" + str(common), + "-I" + str(common / "cdc"), + "-I" + str(ROOT / "rtl/mini/top"), + f"+define+HP_SMOKE_HEX=\"{hex_image}\"", + ] + if sram_macros: + # IHP130 macro path for the eight C906 SRAM wrappers (integration + # manual chapter 3): the override files select RM_IHPSG13_1P_* macros + # when PDK_IHP130+HAVE_SRAM_MACRO are defined without PDK_BEHAV, and + # FUNCTIONAL puts the macro models in zero-delay functional mode. + sram_verilog = ( + ROOT / "physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog" + ) + command += [ + "+define+PDK_IHP130", + "+define+HAVE_SRAM_MACRO", + "+define+FUNCTIONAL", + str(sram_verilog / "RM_IHPSG13_1P_core_behavioral_bm_bist.v"), + str(sram_verilog / "RM_IHPSG13_1P_1024x32_c2_bm_bist.v"), + str(sram_verilog / "RM_IHPSG13_1P_64x64_c2_bm_bist.v"), + ] + command += [ + str(common / "interface/axi4_if.sv"), + str(common / "interface/axi4_addr_gen.sv"), + str(common / "utils/register.sv"), + str(common / "utils/xchecker.sv"), + str(common / "utils/spill_register.sv"), + str(common / "utils/bin2gray.sv"), + str(common / "utils/gray2bin.sv"), + str(common / "cdc/cdc_sync.sv"), + str(common / "cdc/cdc_rst_ctrlr.sv"), + str(common / "cdc/cdc_2phase.sv"), + str(common / "clkrst/rst_sync.sv"), + str(common / "clkrst/clk_int_div.sv"), + str(ROOT / "rtl/ip/util/soc_common_cdc.sv"), + str(ROOT / "rtl/mini/top/axi4_downsizer_128to64.sv"), + str(ROOT / "rtl/mini/top/axi4_mmio_demux.sv"), + str(ROOT / "rtl/mini/top/axi4_downsizer_64to32.sv"), + str(ROOT / "rtl/mini/top/axi4_address_gate.sv"), + str(ROOT / "rtl/mini/top/axi4_async_bridge.sv"), + str(ROOT / "rtl/mini/top/hp_core_wrapper.sv"), + "-f", + str(generated / "openc906.fl"), + str(ROOT / "tests/rtl/hp_c906_boot_tb.sv"), + "-Mdir", + str(tmp_path / "obj"), + "-o", + str(output), + ] subprocess.run( - [ - verilator, - "--binary", - "--timing", - "-Wno-fatal", - "--top-module", - "hp_c906_boot_tb", - "-I" + str(common / "interface"), - "-I" + str(common / "utils"), - "-I" + str(common), - "-I" + str(common / "cdc"), - "-I" + str(ROOT / "rtl/mini/top"), - f"+define+HP_SMOKE_HEX=\"{hex_image}\"", - str(common / "interface/axi4_if.sv"), - str(common / "interface/axi4_addr_gen.sv"), - str(common / "utils/register.sv"), - str(common / "utils/xchecker.sv"), - str(common / "utils/spill_register.sv"), - str(common / "utils/bin2gray.sv"), - str(common / "utils/gray2bin.sv"), - str(common / "cdc/cdc_sync.sv"), - str(common / "cdc/cdc_rst_ctrlr.sv"), - str(common / "cdc/cdc_2phase.sv"), - str(common / "clkrst/rst_sync.sv"), - str(common / "clkrst/clk_int_div.sv"), - str(ROOT / "rtl/ip/util/soc_common_cdc.sv"), - str(ROOT / "rtl/mini/top/axi4_downsizer_128to64.sv"), - str(ROOT / "rtl/mini/top/axi4_mmio_demux.sv"), - str(ROOT / "rtl/mini/top/axi4_downsizer_64to32.sv"), - str(ROOT / "rtl/mini/top/axi4_address_gate.sv"), - str(ROOT / "rtl/mini/top/axi4_async_bridge.sv"), - str(ROOT / "rtl/mini/top/hp_core_wrapper.sv"), - "-f", - str(generated / "openc906.fl"), - str(ROOT / "tests/rtl/hp_c906_boot_tb.sv"), - "-Mdir", - str(tmp_path / "obj"), - "-o", - str(output), - ], + command, check=True, text=True, capture_output=True, @@ -245,6 +264,16 @@ def test_c906_boots_smoke_payload_in_focused_tb(tmp_path: Path) -> None: assert "HP_C906_BOOT_TEST_PASS" in result.stdout +def test_c906_boots_smoke_payload_in_focused_tb(tmp_path: Path) -> None: + """Boot the real HP smoke payload on the hp_core_wrapper integration.""" + _run_c906_boot_tb(tmp_path, sram_macros=False) + + +def test_c906_boots_smoke_payload_with_ihp130_sram_macros(tmp_path: Path) -> None: + """Boot the same payload with the C906 SRAM wrappers on IHP130 macros.""" + _run_c906_boot_tb(tmp_path, sram_macros=True) + + def test_hp_smoke_payload_uses_hart1_platform_abi() -> None: source = (ROOT / "app/ports/linux/smoke/start.S").read_text(encoding="utf-8") assert "0x10018000" in source From 06e90bdb93a700233268fda7480720738ae687b2 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Wed, 14 Oct 2026 16:33:55 +0800 Subject: [PATCH 15/31] docs: record the OpenC906 SRAM macro swap and its evidence Move the chapter 3 memory swap from deferred to simulation-validated in docs/ip/hp-platform.md (mechanism, define gating, and the stacking table) and docs/hp-rv64-validation.md (macro-mode boot TB and SoC macro-sim evidence, with the remaining synthesis/netlist/STA/LEC gates called out). Extend the override inventories in rtl/README.md and scripts/README.md to cover the eight aq_spsram_* wrappers. The chapter 3 ICG replacement and physical qualification stay explicitly deferred. --- docs/hp-rv64-validation.md | 21 +++++++++++++++---- docs/ip/hp-platform.md | 41 ++++++++++++++++++++++++++++++++------ rtl/README.md | 7 +++++-- scripts/README.md | 4 +++- 4 files changed, 60 insertions(+), 13 deletions(-) diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index db6f759d..d378add9 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -115,15 +115,28 @@ qualification. Current evidence requires, at minimum: the C906 store buffer; `rtl/mini/ip_overrides/sysmap.h` marks the MMIO and core-internal CLINT/PLIC windows strong-order non-cacheable per the user manual. +- The integration manual chapter 3 SRAM swap is validated in simulation: the + eight `rtl/mini/ip_overrides/aq_spsram_*.v` overrides select IHP130 + `RM_IHPSG13_1P_*` macro combinations under `PDK_IHP130`+`HAVE_SRAM_MACRO` + without `PDK_BEHAV`, and the focused boot testbench variant + `test_c906_boots_smoke_payload_with_ihp130_sram_macros` boots the real + smoke payload (cache maintenance plus GA2D data movement, which exercises + the BHT/ICache/DCache/JTLB RAMs for real) on the macro path with the same + `HP_C906_BOOT_TEST_PASS` verdict as the behavioral run. `hp-linux-sim` was run with a bounded wall-clock budget this round and its current frontier is recorded above; the synthesis-dependent gates remain -unrun (synthesis waits for the SRAM macro swap). Both stay required evidence -for qualification. +unrun (synthesis, netlist simulation, STA, and the physical/LEC qualification +of the macro path). The SoC-level macro-mode simulation now has passing +evidence: `make CONFIG=configs/ci/ihp130-hp.mk PDK_BEHAV=NO SIMU=VERILATOR +hp-smoke-sim` builds the whole SoC (C906 `aq_spsram_*` wrappers and +`tc_sram`) on the IHP130 macro models and passes with +`SIM_TEST_PASS code=0` plus the `HP_LINUX_READY`/`HP_GA2D_PASS`/ +`HP_GA2D_CACHE_CLEAN` markers. All stay required evidence for qualification. Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT -(scan/mbist tied off), the debug SBA AXI master (unconnected), ASIC -memory-macro replacement for the behavioral FPGA SRAM models, and HP Linux +(scan/mbist tied off), the debug SBA AXI master (unconnected), the chapter 3 +ICG (`gated_clk_cell`) replacement, and HP Linux re-qualification timing/performance evidence. The repo-owned OpenSBI platform registers `fdt_irqchip_init` (v1.9 supports the `thead,c900-plic` match with T-Head delegation fixups), so the C906-internal PLIC is initialized by diff --git a/docs/ip/hp-platform.md b/docs/ip/hp-platform.md index fa6fe41a..6258acc5 100644 --- a/docs/ip/hp-platform.md +++ b/docs/ip/hp-platform.md @@ -44,11 +44,36 @@ and would mark the Mini peripheral window cacheable/bufferable) with the Mini address map: the MMIO window `0x02000000`-`0x2FFFFFFF` — including the core-internal CLINT/PLIC window — is strong-order/non-cacheable device memory as the OpenC906 user manual requires; SRAM/SDRAM/PSRAM/OPI and the flash/XIP -windows stay cacheable. The vendored checkout is never modified. Deferred -this phase: low-power support +windows stay cacheable. The vendored checkout is never modified. + +The OpenC906 integration manual chapter 3 memory swap is implemented for +simulation: the eight C906 single-port SRAM wrappers have reviewed overrides +in `rtl/mini/ip_overrides/aq_spsram_*.v`. With `PDK_IHP130` + +`HAVE_SRAM_MACRO` and without `PDK_BEHAV` each wrapper instantiates IHP130 +`RM_IHPSG13_1P_*` macros (BIST pins tied off, `A_DLY=1`), stacked per manual +section 3.1.5: + +| Wrapper | Macro combination | Stacking | +| --- | --- | --- | +| `aq_spsram_1024x16` (BHT) | 1x `RM_IHPSG13_1P_1024x32_c2_bm_bist` | low 16 bits used | +| `aq_spsram_2048x32` (ICache data) | 2x `RM_IHPSG13_1P_1024x32_c2_bm_bist` | depth, `A[10]` chip-select | +| `aq_spsram_256x59` (ICache tag) | 4x `RM_IHPSG13_1P_64x64_c2_bm_bist` | depth, `A[7:6]` chip-select | +| `aq_spsram_1024x64` (DCache data) | 2x `RM_IHPSG13_1P_1024x32_c2_bm_bist` | width, low/high 32 bits | +| `aq_spsram_128x8` (DCache dirty) | 2x `RM_IHPSG13_1P_64x64_c2_bm_bist` | depth, `A[6]` chip-select | +| `aq_spsram_64x58` (DCache tag) | 1x `RM_IHPSG13_1P_64x64_c2_bm_bist` | low 58 bits used | +| `aq_spsram_64x88` (JTLB data) | 2x `RM_IHPSG13_1P_64x64_c2_bm_bist` | width, low 64 + high 24 bits | +| `aq_spsram_64x98` (JTLB tag) | 2x `RM_IHPSG13_1P_64x64_c2_bm_bist` | width, low 64 + high 34 bits | + +Depth stacks register the bank select on read transactions and mux the bank +outputs one cycle later (manual section 3.1.4 timing); unused upper +write-mask bits are tied off so unimplemented bits are never written. Every +other configuration — including the committed `PDK_BEHAV=YES` CI profiles — +compiles the upstream behavioral `aq_f_spsram_*` instance byte-identically. +Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT (scan/mbist tied off), the debug SBA AXI -master (unconnected), ASIC memory-macro replacement for the behavioral FPGA -SRAM models, and HP Linux re-qualification timing/performance evidence. +master (unconnected), the chapter 3 ICG (`gated_clk_cell`) replacement, +physical/LEC qualification of the macro path (synthesis mapping, STA), and +HP Linux re-qualification timing/performance evidence. ### Boot bundle V2 @@ -136,8 +161,12 @@ separate run logs and structured results; an interrupted or ongoing run cannot reuse an old pass. Run affected host/Python/C/RTL checks and IHP130 behavioral regressions. Synthesis, netlist simulation, STA, and synthesis-dependent metrics are -explicitly deferred by user instruction, as are SRAM macro replacement, -CDC/RDC/physical signoff and commercial qualification. No PPA claim is made. +explicitly deferred by user instruction, as are CDC/RDC/physical signoff and +commercial qualification. No PPA claim is made. The SRAM macro swap is no +longer deferred at simulation level: the `aq_spsram_*` overrides described +above run the IHP130 macro path in the focused boot testbench (see +[HP RV64 Validation](../hp-rv64-validation.md)); physical macro integration +remains deferred. Reference boundaries: [RT-Thread v5.3.0](https://github.com/RT-Thread/rt-thread/releases/tag/v5.3.0) supplies the OS/CPU port; the repository owns board integration. The C906 diff --git a/rtl/README.md b/rtl/README.md index 3aba7527..79b32e2f 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -18,8 +18,11 @@ downsizer with an MMIO demux, the C906 internal CLINT/PLIC, mailbox, UART1, and SYSCTRL lifecycle signals. `make setup-openc906` (part of `make setup`) restores the locked checkout and `make openc906-prepare` emits the generated filelist and manifest below `build//generated/openc906/`; the OpenC906 -sources are an external lint boundary. The reviewed hart-ID and sysmap -address-attribute overrides live in `rtl/mini/ip_overrides/` and are applied +sources are an external lint boundary. The reviewed hart-ID, sysmap +address-attribute, and SRAM wrapper overrides live in `rtl/mini/ip_overrides/` +(the `aq_spsram_*.v` overrides implement the integration manual chapter 3 +memory swap and select IHP130 `RM_IHPSG13_1P_*` macros only under +`PDK_IHP130`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`) and are applied by filelist generation, never by editing the vendored checkout. The former VexiiRiscv HP generator is preserved only as the frozen Std-series asset (`make std-vexii-generate`). See diff --git a/scripts/README.md b/scripts/README.md index d905f607..e713268a 100644 --- a/scripts/README.md +++ b/scripts/README.md @@ -130,7 +130,9 @@ source used by Mini product profiles and verifies the checked-out revision; the vendored checkout is never modified. `generate_openc906.py` resolves the upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1 -`aq_sysio_kid.v` and the strong-order MMIO-window `sysmap.h`, each pinned to +`aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, and the eight +`aq_spsram_*.v` SRAM wrappers whose IHP130 macro path is gated on +`PDK_IHP130`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, each pinned to the upstream file's SHA-256 so a locked-revision move forces review), and emits the single compilation unit `openc906_combined.v` below `build/`; generated RTL is never tracked. From 2583f138287b96a5eb72bf3efd4839fa657ac310 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 02:42:13 +0800 Subject: [PATCH 16/31] build(pdk): lock the eight C906 ICS55 SRAM macro releases Register the eight exact-geometry OpenECOS ICS55 SRAM macros for the Mini HP core (1024x16_m8, 2048x32_m8, 256x59_m4, 1024x64_m8, 128x8_m8, 64x58_m4, 64x88_m4, 64x98_m4) as locked archives in dependencies.lock.json, each pinned to its GitHub release URL and tarball SHA-256. Extend the setup.py materialization list so 'make setup-pdk' downloads and extracts them below .cache/retrosoc/pdk/ics55/sram/, and list the new core models in the ICS55 Icarus/Verilator filelists (stub entries in the Yosys filelist for cross-file consistency; the synthesis macro binding itself remains Liberty-side physical collateral). Evidence: dependency_lock.py validates the updated lock; setup-pdk materializes all eight macros with verified checksums. --- dependencies/dependencies.lock.json | 48 +++++++++++++++++++++++++++++ physical/pdk/setup.py | 8 +++++ rtl/filelist/pdk_ics55.fl | 8 +++++ rtl/filelist/pdk_ics55_verilator.fl | 8 +++++ rtl/filelist/pdk_ics55_yosys.fl | 8 +++++ 5 files changed, 80 insertions(+) diff --git a/dependencies/dependencies.lock.json b/dependencies/dependencies.lock.json index 37b9ebc3..861772be 100644 --- a/dependencies/dependencies.lock.json +++ b/dependencies/dependencies.lock.json @@ -299,6 +299,54 @@ "destination": ".cache/retrosoc/downloads/pdk/ics55/ics55_ecos_sram_1024x32_m8.tar.gz", "license": "NOASSERTION" }, + "pdk_ics55_sram_1024x16_m8": { + "url": "https://github.com/openecos-projects/ics55_ecos_sram/releases/download/sram-v1-7aee4a4c686eb3d2cd8e86b7a62a5a5c065996fef8b25e8d535be5846cf52313/ics55_ecos_sram_1024x16_m8.tar.gz", + "sha256": "2873728b20faa2a28b892c3833a930399d3ec5bb443441004026483bc6acdfd0", + "destination": ".cache/retrosoc/downloads/pdk/ics55/ics55_ecos_sram_1024x16_m8.tar.gz", + "license": "NOASSERTION" + }, + "pdk_ics55_sram_2048x32_m8": { + "url": "https://github.com/openecos-projects/ics55_ecos_sram/releases/download/sram-v1-74bf8d8151ec0d2ecba03c6feb004b83df1a4d7878bcca780ddf82160b371e94/ics55_ecos_sram_2048x32_m8.tar.gz", + "sha256": "e5d0554155084c3624a16aff5e6df5f89ce3367274aeeff469b74ff443e0c1c0", + "destination": ".cache/retrosoc/downloads/pdk/ics55/ics55_ecos_sram_2048x32_m8.tar.gz", + "license": "NOASSERTION" + }, + "pdk_ics55_sram_256x59_m4": { + "url": "https://github.com/openecos-projects/ics55_ecos_sram/releases/download/sram-v1-a82938d52971739e36dfda702b892ebd21b17bdf308859761cb52be0207919a8/ics55_ecos_sram_256x59_m4.tar.gz", + "sha256": "c59da66a16d95f13d22b350cbba185dcdbaed243c15211d48eba2b6afd0e8977", + "destination": ".cache/retrosoc/downloads/pdk/ics55/ics55_ecos_sram_256x59_m4.tar.gz", + "license": "NOASSERTION" + }, + "pdk_ics55_sram_1024x64_m8": { + "url": "https://github.com/openecos-projects/ics55_ecos_sram/releases/download/sram-v1-b9994f07f8e68e6c6387b433ca8421401a2b7e1a1aa5a29f7de1ce62691832f7/ics55_ecos_sram_1024x64_m8.tar.gz", + "sha256": "0e11c6ef5715d20adc76a2fa5044c06cddb2b48315b2fac5b8b99ceeccd0515d", + "destination": ".cache/retrosoc/downloads/pdk/ics55/ics55_ecos_sram_1024x64_m8.tar.gz", + "license": "NOASSERTION" + }, + "pdk_ics55_sram_128x8_m8": { + "url": "https://github.com/openecos-projects/ics55_ecos_sram/releases/download/sram-v1-ad751361962b34a6d63346196ae8a35f7332486a08b16f3473b30488a3ebc931/ics55_ecos_sram_128x8_m8.tar.gz", + "sha256": "f8187a4d19636602cede59cad17bf77810834ec53748c96235f38eadbd037580", + "destination": ".cache/retrosoc/downloads/pdk/ics55/ics55_ecos_sram_128x8_m8.tar.gz", + "license": "NOASSERTION" + }, + "pdk_ics55_sram_64x58_m4": { + "url": "https://github.com/openecos-projects/ics55_ecos_sram/releases/download/sram-v1-d4783a521fb52872d51a3661cdec3eb394723e44501307f31817e7c1e92fc240/ics55_ecos_sram_64x58_m4.tar.gz", + "sha256": "df9fe1726d140c610ff2a96270226a6f2a4140ce5c3462065e97557d99d74c2f", + "destination": ".cache/retrosoc/downloads/pdk/ics55/ics55_ecos_sram_64x58_m4.tar.gz", + "license": "NOASSERTION" + }, + "pdk_ics55_sram_64x88_m4": { + "url": "https://github.com/openecos-projects/ics55_ecos_sram/releases/download/sram-v1-5754982b8e6208f88e2eb2e0ba6e474e9e4eecd2d38dcfe8467ee10b3d6b7e4e/ics55_ecos_sram_64x88_m4.tar.gz", + "sha256": "6b69114c28557b00be71b3f822780872d1ce1eef46ca81f626f176f6d4f85d6c", + "destination": ".cache/retrosoc/downloads/pdk/ics55/ics55_ecos_sram_64x88_m4.tar.gz", + "license": "NOASSERTION" + }, + "pdk_ics55_sram_64x98_m4": { + "url": "https://github.com/openecos-projects/ics55_ecos_sram/releases/download/sram-v1-9bf1f08b87901ff376fae7d81d6ada10047012b7bde2c226a545d9df73eef6d3/ics55_ecos_sram_64x98_m4.tar.gz", + "sha256": "19932ac06e4a6d4ecd92a2ec36968494a435a624b79158a0e4e4cc1a601c8871", + "destination": ".cache/retrosoc/downloads/pdk/ics55/ics55_ecos_sram_64x98_m4.tar.gz", + "license": "NOASSERTION" + }, "pdk_ics55_sram_4096x32_m8": { "url": "https://github.com/openecos-projects/ics55_ecos_sram/releases/download/sram-v1-5ea91275df77176fa7e0469a94c75d7ed6468de0569a3f89fac519f09c319a17/ics55_ecos_sram_4096x32_m8.tar.gz", "sha256": "5d168d0c7c26281bd7ab0e58493033e65823e5ea6b320c897d65ed079ee4de6e", diff --git a/physical/pdk/setup.py b/physical/pdk/setup.py index 6b8df534..a01b4008 100644 --- a/physical/pdk/setup.py +++ b/physical/pdk/setup.py @@ -208,6 +208,14 @@ def main() -> int: for sram_name, directory_name in ( ("pdk_ics55_sram_1024x32_m8", "ics55_ecos_sram_1024x32_m8"), ("pdk_ics55_sram_4096x32_m8", "ics55_ecos_sram_4096x32_m8"), + ("pdk_ics55_sram_1024x16_m8", "ics55_ecos_sram_1024x16_m8"), + ("pdk_ics55_sram_2048x32_m8", "ics55_ecos_sram_2048x32_m8"), + ("pdk_ics55_sram_256x59_m4", "ics55_ecos_sram_256x59_m4"), + ("pdk_ics55_sram_1024x64_m8", "ics55_ecos_sram_1024x64_m8"), + ("pdk_ics55_sram_128x8_m8", "ics55_ecos_sram_128x8_m8"), + ("pdk_ics55_sram_64x58_m4", "ics55_ecos_sram_64x58_m4"), + ("pdk_ics55_sram_64x88_m4", "ics55_ecos_sram_64x88_m4"), + ("pdk_ics55_sram_64x98_m4", "ics55_ecos_sram_64x98_m4"), ): sram = archive(sram_name) sram_archive = ROOT / sram["destination"] diff --git a/rtl/filelist/pdk_ics55.fl b/rtl/filelist/pdk_ics55.fl index ac995b06..a139e53b 100644 --- a/rtl/filelist/pdk_ics55.fl +++ b/rtl/filelist/pdk_ics55.fl @@ -3,3 +3,11 @@ /physical/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v /cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_1024x32_m8/verilog/ics55_ecos_sram_1024x32_m8_core.v /cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_4096x32_m8/verilog/ics55_ecos_sram_4096x32_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_1024x16_m8/verilog/ics55_ecos_sram_1024x16_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_2048x32_m8/verilog/ics55_ecos_sram_2048x32_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_256x59_m4/verilog/ics55_ecos_sram_256x59_m4_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_1024x64_m8/verilog/ics55_ecos_sram_1024x64_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_128x8_m8/verilog/ics55_ecos_sram_128x8_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_64x58_m4/verilog/ics55_ecos_sram_64x58_m4_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_64x88_m4/verilog/ics55_ecos_sram_64x88_m4_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_64x98_m4/verilog/ics55_ecos_sram_64x98_m4_core.v diff --git a/rtl/filelist/pdk_ics55_verilator.fl b/rtl/filelist/pdk_ics55_verilator.fl index 087d16c8..126fe466 100644 --- a/rtl/filelist/pdk_ics55_verilator.fl +++ b/rtl/filelist/pdk_ics55_verilator.fl @@ -4,3 +4,11 @@ /tech/ics55_io_sim_cells.sv /cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_1024x32_m8/verilog/ics55_ecos_sram_1024x32_m8_core.v /cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_4096x32_m8/verilog/ics55_ecos_sram_4096x32_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_1024x16_m8/verilog/ics55_ecos_sram_1024x16_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_2048x32_m8/verilog/ics55_ecos_sram_2048x32_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_256x59_m4/verilog/ics55_ecos_sram_256x59_m4_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_1024x64_m8/verilog/ics55_ecos_sram_1024x64_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_128x8_m8/verilog/ics55_ecos_sram_128x8_m8_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_64x58_m4/verilog/ics55_ecos_sram_64x58_m4_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_64x88_m4/verilog/ics55_ecos_sram_64x88_m4_core.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_64x98_m4/verilog/ics55_ecos_sram_64x98_m4_core.v diff --git a/rtl/filelist/pdk_ics55_yosys.fl b/rtl/filelist/pdk_ics55_yosys.fl index aa0b85d7..73daa21d 100644 --- a/rtl/filelist/pdk_ics55_yosys.fl +++ b/rtl/filelist/pdk_ics55_yosys.fl @@ -1,3 +1,11 @@ # ICS55 technology cells are supplied by the locked Liberty views in Yosys. /cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_1024x32_m8/verilog/ics55_ecos_sram_1024x32_m8_stub.v /cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_4096x32_m8/verilog/ics55_ecos_sram_4096x32_m8_stub.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_1024x16_m8/verilog/ics55_ecos_sram_1024x16_m8_stub.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_2048x32_m8/verilog/ics55_ecos_sram_2048x32_m8_stub.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_256x59_m4/verilog/ics55_ecos_sram_256x59_m4_stub.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_1024x64_m8/verilog/ics55_ecos_sram_1024x64_m8_stub.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_128x8_m8/verilog/ics55_ecos_sram_128x8_m8_stub.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_64x58_m4/verilog/ics55_ecos_sram_64x58_m4_stub.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_64x88_m4/verilog/ics55_ecos_sram_64x88_m4_stub.v +/cache/retrosoc/pdk/ics55/sram/ics55_ecos_sram_64x98_m4/verilog/ics55_ecos_sram_64x98_m4_stub.v From 64c62f8cfb418099067247cf6ab43c84b2f2750d Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 02:42:22 +0800 Subject: [PATCH 17/31] feat(hp): add the ICS55 macro path to the OpenC906 SRAM wrappers Extend each of the eight aq_spsram_* overrides with a PDK_ICS55+HAVE_SRAM_MACRO (without PDK_BEHAV) branch that instantiates the matching exact-geometry ics55_ecos_sram_* macro. The ICS55 interface polarity (CEB/GWEB/WEB active-low, per-bit WEB) matches the wrappers exactly, so the branch is a single direct instantiation with MARE/MAR tied off; no inversion, stacking, or padding is needed. Priority order is PDK_BEHAV behavioral, then IHP130 macros, then ICS55 macros, else the upstream behavioral model; the behavioral and IHP130 paths are bit-identical. The committed ICS55 CI/cluster profiles (HAVE_HP=YES, HAVE_SRAM_MACRO=YES, PDK_BEHAV unset) now compile the macro path automatically. Evidence: directed 8-wrapper equivalence TB and the manual section 3.2 MEM_INTF adaptation (Icarus) pass on the ICS55 path; the CI-flavored ics55 profile simulation passes with SIM_TEST_PASS code=0. --- rtl/mini/ip_overrides/aq_spsram_1024x16.v | 36 ++++++++++++++++++++-- rtl/mini/ip_overrides/aq_spsram_1024x64.v | 36 ++++++++++++++++++++-- rtl/mini/ip_overrides/aq_spsram_128x8.v | 36 ++++++++++++++++++++-- rtl/mini/ip_overrides/aq_spsram_2048x32.v | 37 +++++++++++++++++++++-- rtl/mini/ip_overrides/aq_spsram_256x59.v | 37 +++++++++++++++++++++-- rtl/mini/ip_overrides/aq_spsram_64x58.v | 36 ++++++++++++++++++++-- rtl/mini/ip_overrides/aq_spsram_64x88.v | 36 ++++++++++++++++++++-- rtl/mini/ip_overrides/aq_spsram_64x98.v | 36 ++++++++++++++++++++-- 8 files changed, 266 insertions(+), 24 deletions(-) diff --git a/rtl/mini/ip_overrides/aq_spsram_1024x16.v b/rtl/mini/ip_overrides/aq_spsram_1024x16.v index ec5e2167..ba7e63e7 100644 --- a/rtl/mini/ip_overrides/aq_spsram_1024x16.v +++ b/rtl/mini/ip_overrides/aq_spsram_1024x16.v @@ -9,9 +9,11 @@ // PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 1024x16 BHT RAM is // built from one RM_IHPSG13_1P_1024x32_c2_bm_bist macro; only the low 16 // bits are used and the upper mask bits are tied off so they are never -// written. Every other configuration keeps the upstream behavioral -// aq_f_spsram_1024x16 instance byte-identical. Keep in sync when the lock -// revision changes. +// written. With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the +// exact-geometry ics55_ecos_sram_1024x16_m8 macro replaces it directly +// (identical active-low polarity, no stacking or padding). Every other +// configuration keeps the upstream behavioral aq_f_spsram_1024x16 instance +// byte-identical. Keep in sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -80,6 +82,14 @@ parameter WE_WIDTH = 16; `endif `endif +`ifdef PDK_ICS55 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_1024X16_ICS55_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_1024X16_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -111,6 +121,22 @@ RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem ( .A_BIST_DIN (32'b0 ), .A_BIST_BM (32'b0 ) ); +`elsif _AQ_SPSRAM_1024X16_ICS55_ + //******************************************************** + //* ICS55 SRAM macro * + //******************************************************** +// Exact-geometry macro; polarities match the wrapper, direct connection. +ics55_ecos_sram_1024x16_m8 u_mem ( + .A (A ), + .CEB (CEN ), + .CLK (CLK ), + .D (D ), + .GWEB (GWEN), + .MARE (1'b0), + .MAR (4'b0), + .WEB (WEN ), + .Q (Q ) +); `else //******************************************************** //* FPGA memory * @@ -131,6 +157,10 @@ aq_f_spsram_1024x16 x_aq_f_spsram_1024x16 ( `undef _AQ_SPSRAM_1024X16_IHP130_ `endif +`ifdef _AQ_SPSRAM_1024X16_ICS55_ +`undef _AQ_SPSRAM_1024X16_ICS55_ +`endif + // &Instance("aq_tsmc_spsram_1024x16"); @49 // &Instance("aq_umc_spsram_1024x16"); @61 diff --git a/rtl/mini/ip_overrides/aq_spsram_1024x64.v b/rtl/mini/ip_overrides/aq_spsram_1024x64.v index ce7c853e..a21b583a 100644 --- a/rtl/mini/ip_overrides/aq_spsram_1024x64.v +++ b/rtl/mini/ip_overrides/aq_spsram_1024x64.v @@ -9,9 +9,11 @@ // PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 1024x64 DCache data // RAM is built from two RM_IHPSG13_1P_1024x32_c2_bm_bist macros in a width // stack: one macro holds the low 32 bits, the other the high 32 bits (manual -// section 3.1.5 stacking). Every other configuration keeps the upstream -// behavioral aq_f_spsram_1024x64 instance byte-identical. Keep in sync when -// the lock revision changes. +// section 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without +// PDK_BEHAV, the exact-geometry ics55_ecos_sram_1024x64_m8 macro replaces it +// directly (identical active-low polarity, no stacking or padding). Every +// other configuration keeps the upstream behavioral aq_f_spsram_1024x64 +// instance byte-identical. Keep in sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -80,6 +82,14 @@ parameter WE_WIDTH = 64; `endif `endif +`ifdef PDK_ICS55 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_1024X64_ICS55_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_1024X64_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -130,6 +140,22 @@ RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_hi ( .A_BIST_DIN (32'b0 ), .A_BIST_BM (32'b0 ) ); +`elsif _AQ_SPSRAM_1024X64_ICS55_ + //******************************************************** + //* ICS55 SRAM macro * + //******************************************************** +// Exact-geometry macro; polarities match the wrapper, direct connection. +ics55_ecos_sram_1024x64_m8 u_mem ( + .A (A ), + .CEB (CEN ), + .CLK (CLK ), + .D (D ), + .GWEB (GWEN), + .MARE (1'b0), + .MAR (4'b0), + .WEB (WEN ), + .Q (Q ) +); `else // //******************************************************** // //* FPGA memory * @@ -150,6 +176,10 @@ aq_f_spsram_1024x64 x_aq_f_spsram_1024x64 ( `undef _AQ_SPSRAM_1024X64_IHP130_ `endif +`ifdef _AQ_SPSRAM_1024X64_ICS55_ +`undef _AQ_SPSRAM_1024X64_ICS55_ +`endif + // &Instance("aq_umc_spsram_1024x64"); @49 // &Instance("aq_tsmc_spsram_1024x64"); @55 // &ModuleEnd; @58 diff --git a/rtl/mini/ip_overrides/aq_spsram_128x8.v b/rtl/mini/ip_overrides/aq_spsram_128x8.v index 16d6f997..be08e091 100644 --- a/rtl/mini/ip_overrides/aq_spsram_128x8.v +++ b/rtl/mini/ip_overrides/aq_spsram_128x8.v @@ -11,9 +11,11 @@ // stack: A[6] selects the bank, only the low 8 bits of each macro are used // (upper mask bits tied off so they are never written), and the read-data // mux uses the bank select registered on read transactions (manual section -// 3.1.5 stacking). Every other configuration keeps the upstream behavioral -// aq_f_spsram_128x8 instance byte-identical. Keep in sync when the lock -// revision changes. +// 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, +// the exact-geometry ics55_ecos_sram_128x8_m8 macro replaces it directly +// (identical active-low polarity, no stacking or padding). Every other +// configuration keeps the upstream behavioral aq_f_spsram_128x8 instance +// byte-identical. Keep in sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -82,6 +84,14 @@ parameter WE_WIDTH = 8; `endif `endif +`ifdef PDK_ICS55 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_128X8_ICS55_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_128X8_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -149,6 +159,22 @@ RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_hi ( .A_BIST_DIN (64'b0 ), .A_BIST_BM (64'b0 ) ); +`elsif _AQ_SPSRAM_128X8_ICS55_ + //******************************************************** + //* ICS55 SRAM macro * + //******************************************************** +// Exact-geometry macro; polarities match the wrapper, direct connection. +ics55_ecos_sram_128x8_m8 u_mem ( + .A (A ), + .CEB (CEN ), + .CLK (CLK ), + .D (D ), + .GWEB (GWEN), + .MARE (1'b0), + .MAR (4'b0), + .WEB (WEN ), + .Q (Q ) +); `else // //******************************************************** // //* FPGA memory * @@ -169,6 +195,10 @@ aq_f_spsram_128x8 x_aq_f_spsram_128x8 ( `undef _AQ_SPSRAM_128X8_IHP130_ `endif +`ifdef _AQ_SPSRAM_128X8_ICS55_ +`undef _AQ_SPSRAM_128X8_ICS55_ +`endif + // &Instance("aq_umc_spsram_128x8"); @49 // &Instance("aq_tsmc_spsram_128x8"); @55 // &ModuleEnd; @58 diff --git a/rtl/mini/ip_overrides/aq_spsram_2048x32.v b/rtl/mini/ip_overrides/aq_spsram_2048x32.v index 466c6461..a4cd951b 100644 --- a/rtl/mini/ip_overrides/aq_spsram_2048x32.v +++ b/rtl/mini/ip_overrides/aq_spsram_2048x32.v @@ -9,9 +9,12 @@ // PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 2048x32 ICache data // RAM is built from two RM_IHPSG13_1P_1024x32_c2_bm_bist macros in a depth // stack: A[10] selects the bank and the read-data mux uses the bank select -// registered on read transactions (manual section 3.1.5 stacking). Every -// other configuration keeps the upstream behavioral aq_f_spsram_2048x32 -// instance byte-identical. Keep in sync when the lock revision changes. +// registered on read transactions (manual section 3.1.5 stacking). With +// PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the exact-geometry +// ics55_ecos_sram_2048x32_m8 macro replaces it directly (identical +// active-low polarity, no stacking or padding). Every other configuration +// keeps the upstream behavioral aq_f_spsram_2048x32 instance byte-identical. +// Keep in sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -80,6 +83,14 @@ parameter WE_WIDTH = 32; `endif `endif +`ifdef PDK_ICS55 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_2048X32_ICS55_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_2048X32_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -142,6 +153,22 @@ RM_IHPSG13_1P_1024x32_c2_bm_bist u_mem_hi ( .A_BIST_DIN (32'b0 ), .A_BIST_BM (32'b0 ) ); +`elsif _AQ_SPSRAM_2048X32_ICS55_ + //******************************************************** + //* ICS55 SRAM macro * + //******************************************************** +// Exact-geometry macro; polarities match the wrapper, direct connection. +ics55_ecos_sram_2048x32_m8 u_mem ( + .A (A ), + .CEB (CEN ), + .CLK (CLK ), + .D (D ), + .GWEB (GWEN), + .MARE (1'b0), + .MAR (4'b0), + .WEB (WEN ), + .Q (Q ) +); `else //******************************************************** //* FPGA memory * @@ -162,6 +189,10 @@ aq_f_spsram_2048x32 x_aq_f_spsram_2048x32 ( `undef _AQ_SPSRAM_2048X32_IHP130_ `endif +`ifdef _AQ_SPSRAM_2048X32_ICS55_ +`undef _AQ_SPSRAM_2048X32_ICS55_ +`endif + // &Instance("aq_tsmc_spsram_2048x32"); @49 // &Instance("aq_umc_spsram_2048x32"); @61 diff --git a/rtl/mini/ip_overrides/aq_spsram_256x59.v b/rtl/mini/ip_overrides/aq_spsram_256x59.v index f7ec3cd8..e3d0330b 100644 --- a/rtl/mini/ip_overrides/aq_spsram_256x59.v +++ b/rtl/mini/ip_overrides/aq_spsram_256x59.v @@ -11,9 +11,12 @@ // stack: A[7:6] selects the bank, only the low 59 bits of each macro are // used (upper mask bits tied off so they are never written), and the // read-data mux uses the bank select registered on read transactions -// (manual section 3.1.5 stacking). Every other configuration keeps the -// upstream behavioral aq_f_spsram_256x59 instance byte-identical. Keep in -// sync when the lock revision changes. +// (manual section 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and +// without PDK_BEHAV, the exact-geometry ics55_ecos_sram_256x59_m4 macro +// replaces it directly (identical active-low polarity, no stacking or +// padding). Every other configuration keeps the upstream behavioral +// aq_f_spsram_256x59 instance byte-identical. Keep in sync when the lock +// revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -82,6 +85,14 @@ parameter WE_WIDTH = 59; `endif `endif +`ifdef PDK_ICS55 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_256X59_ICS55_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_256X59_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -130,6 +141,22 @@ generate ); end endgenerate +`elsif _AQ_SPSRAM_256X59_ICS55_ + //******************************************************** + //* ICS55 SRAM macro * + //******************************************************** +// Exact-geometry macro; polarities match the wrapper, direct connection. +ics55_ecos_sram_256x59_m4 u_mem ( + .A (A ), + .CEB (CEN ), + .CLK (CLK ), + .D (D ), + .GWEB (GWEN), + .MARE (1'b0), + .MAR (4'b0), + .WEB (WEN ), + .Q (Q ) +); `else //******************************************************** //* FPGA memory * @@ -150,6 +177,10 @@ aq_f_spsram_256x59 x_aq_f_spsram_256x59 ( `undef _AQ_SPSRAM_256X59_IHP130_ `endif +`ifdef _AQ_SPSRAM_256X59_ICS55_ +`undef _AQ_SPSRAM_256X59_ICS55_ +`endif + // &Instance("aq_tsmc_spsram_256x59"); @49 // &Instance("aq_umc_spsram_256x59"); @61 diff --git a/rtl/mini/ip_overrides/aq_spsram_64x58.v b/rtl/mini/ip_overrides/aq_spsram_64x58.v index c7b1f25a..7f0c7e17 100644 --- a/rtl/mini/ip_overrides/aq_spsram_64x58.v +++ b/rtl/mini/ip_overrides/aq_spsram_64x58.v @@ -9,9 +9,11 @@ // PDK_IHP130+HAVE_SRAM_MACRO and without PDK_BEHAV, the 64x58 DCache tag RAM // is built from one RM_IHPSG13_1P_64x64_c2_bm_bist macro; only the low 58 // bits are used and the upper mask bits are tied off so they are never -// written. Every other configuration keeps the upstream behavioral -// aq_f_spsram_64x58 instance byte-identical. Keep in sync when the lock -// revision changes. +// written. With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the +// exact-geometry ics55_ecos_sram_64x58_m4 macro replaces it directly +// (identical active-low polarity, no stacking or padding). Every other +// configuration keeps the upstream behavioral aq_f_spsram_64x58 instance +// byte-identical. Keep in sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -80,6 +82,14 @@ parameter WE_WIDTH = 58; `endif `endif +`ifdef PDK_ICS55 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_64X58_ICS55_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_64X58_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -111,6 +121,22 @@ RM_IHPSG13_1P_64x64_c2_bm_bist u_mem ( .A_BIST_DIN (64'b0 ), .A_BIST_BM (64'b0 ) ); +`elsif _AQ_SPSRAM_64X58_ICS55_ + //******************************************************** + //* ICS55 SRAM macro * + //******************************************************** +// Exact-geometry macro; polarities match the wrapper, direct connection. +ics55_ecos_sram_64x58_m4 u_mem ( + .A (A ), + .CEB (CEN ), + .CLK (CLK ), + .D (D ), + .GWEB (GWEN), + .MARE (1'b0), + .MAR (4'b0), + .WEB (WEN ), + .Q (Q ) +); `else // //******************************************************** // //* FPGA memory * @@ -131,6 +157,10 @@ aq_f_spsram_64x58 x_aq_f_spsram_64x58 ( `undef _AQ_SPSRAM_64X58_IHP130_ `endif +`ifdef _AQ_SPSRAM_64X58_ICS55_ +`undef _AQ_SPSRAM_64X58_ICS55_ +`endif + // &Instance("aq_umc_spsram_64x58"); @49 // &Instance("aq_tsmc_spsram_64x58"); @55 // &ModuleEnd; @58 diff --git a/rtl/mini/ip_overrides/aq_spsram_64x88.v b/rtl/mini/ip_overrides/aq_spsram_64x88.v index 5d7a13fb..6d0a6754 100644 --- a/rtl/mini/ip_overrides/aq_spsram_64x88.v +++ b/rtl/mini/ip_overrides/aq_spsram_64x88.v @@ -10,9 +10,11 @@ // is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a width stack: // one macro holds the low 64 bits, the other the high 24 bits with its upper // mask bits tied off so they are never written (manual section 3.1.5 -// stacking). Every other configuration keeps the upstream behavioral -// aq_f_spsram_64x88 instance byte-identical. Keep in sync when the lock -// revision changes. +// stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the +// exact-geometry ics55_ecos_sram_64x88_m4 macro replaces it directly +// (identical active-low polarity, no stacking or padding). Every other +// configuration keeps the upstream behavioral aq_f_spsram_64x88 instance +// byte-identical. Keep in sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -81,6 +83,14 @@ parameter WE_WIDTH = 88; `endif `endif +`ifdef PDK_ICS55 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_64X88_ICS55_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_64X88_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -134,6 +144,22 @@ RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_hi ( .A_BIST_DIN (64'b0 ), .A_BIST_BM (64'b0 ) ); +`elsif _AQ_SPSRAM_64X88_ICS55_ + //******************************************************** + //* ICS55 SRAM macro * + //******************************************************** +// Exact-geometry macro; polarities match the wrapper, direct connection. +ics55_ecos_sram_64x88_m4 u_mem ( + .A (A ), + .CEB (CEN ), + .CLK (CLK ), + .D (D ), + .GWEB (GWEN), + .MARE (1'b0), + .MAR (4'b0), + .WEB (WEN ), + .Q (Q ) +); `else //******************************************************** //* FPGA memory * @@ -155,6 +181,10 @@ aq_f_spsram_64x88 x_aq_f_spsram_64x88 ( `undef _AQ_SPSRAM_64X88_IHP130_ `endif +`ifdef _AQ_SPSRAM_64X88_ICS55_ +`undef _AQ_SPSRAM_64X88_ICS55_ +`endif + // &Instance("aq_tsmc_spsram_64x88"); @50 // &Instance("aq_umc_spsram_64x88"); @62 diff --git a/rtl/mini/ip_overrides/aq_spsram_64x98.v b/rtl/mini/ip_overrides/aq_spsram_64x98.v index c3b64b77..b379d2aa 100644 --- a/rtl/mini/ip_overrides/aq_spsram_64x98.v +++ b/rtl/mini/ip_overrides/aq_spsram_64x98.v @@ -10,9 +10,11 @@ // is built from two RM_IHPSG13_1P_64x64_c2_bm_bist macros in a width stack: // one macro holds the low 64 bits, the other the high 34 bits with its upper // mask bits tied off so they are never written (manual section 3.1.5 -// stacking). Every other configuration keeps the upstream behavioral -// aq_f_spsram_64x98 instance byte-identical. Keep in sync when the lock -// revision changes. +// stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the +// exact-geometry ics55_ecos_sram_64x98_m4 macro replaces it directly +// (identical active-low polarity, no stacking or padding). Every other +// configuration keeps the upstream behavioral aq_f_spsram_64x98 instance +// byte-identical. Keep in sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -81,6 +83,14 @@ parameter WE_WIDTH = 98; `endif `endif +`ifdef PDK_ICS55 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_64X98_ICS55_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_64X98_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -134,6 +144,22 @@ RM_IHPSG13_1P_64x64_c2_bm_bist u_mem_hi ( .A_BIST_DIN (64'b0 ), .A_BIST_BM (64'b0 ) ); +`elsif _AQ_SPSRAM_64X98_ICS55_ + //******************************************************** + //* ICS55 SRAM macro * + //******************************************************** +// Exact-geometry macro; polarities match the wrapper, direct connection. +ics55_ecos_sram_64x98_m4 u_mem ( + .A (A ), + .CEB (CEN ), + .CLK (CLK ), + .D (D ), + .GWEB (GWEN), + .MARE (1'b0), + .MAR (4'b0), + .WEB (WEN ), + .Q (Q ) +); `else //******************************************************** //* FPGA memory * @@ -155,6 +181,10 @@ aq_f_spsram_64x98 x_aq_f_spsram_64x98 ( `undef _AQ_SPSRAM_64X98_IHP130_ `endif +`ifdef _AQ_SPSRAM_64X98_ICS55_ +`undef _AQ_SPSRAM_64X98_ICS55_ +`endif + // &Instance("aq_tsmc_spsram_64x98"); @50 // &Instance("aq_umc_spsram_64x98"); @62 From b33c57fae2f2190ab875621f7e803194c4e63cc6 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 02:42:36 +0800 Subject: [PATCH 18/31] test(hp): boot the C906 smoke payload on ICS55 SRAM macros Generalize the focused boot testbench helper from a boolean to a macro mode selector (behavioral / ihp130 / ics55) and add test_c906_boots_smoke_payload_with_ics55_sram_macros, which runs the same real smoke payload with +define+PDK_ICS55/+HAVE_SRAM_MACRO and the eight materialized ics55_ecos_sram_* core models; the test skips when the macros are not materialized. The ICS55 models need no FUNCTIONAL define. Evidence: all three boot testbench modes pass with HP_C906_BOOT_TEST_PASS; a whole-SoC macro-mode run via 'make CONFIG=configs/ci/ihp130-hp.mk PDK=ICS55 PDK_BEHAV=NO SIMU=VERILATOR hp-smoke-sim' passes with SIM_TEST_PASS code=0 and the GA2D cache lifecycle markers. --- tests/test_hp_platform.py | 50 ++++++++++++++++++++++++++++++--------- 1 file changed, 39 insertions(+), 11 deletions(-) diff --git a/tests/test_hp_platform.py b/tests/test_hp_platform.py index 47ca76c2..08cf365e 100644 --- a/tests/test_hp_platform.py +++ b/tests/test_hp_platform.py @@ -127,7 +127,7 @@ def test_generated_hp_core_rtl_is_not_tracked() -> None: assert tracked == "" -def _run_c906_boot_tb(tmp_path: Path, *, sram_macros: bool) -> None: +def _run_c906_boot_tb(tmp_path: Path, *, sram_macros: str | None) -> None: """Build and run the focused hp_core_wrapper boot testbench.""" verilator = shutil.which("verilator") openc906 = ROOT / ".cache/retrosoc/sources/openc906" @@ -209,7 +209,7 @@ def _run_c906_boot_tb(tmp_path: Path, *, sram_macros: bool) -> None: "-I" + str(ROOT / "rtl/mini/top"), f"+define+HP_SMOKE_HEX=\"{hex_image}\"", ] - if sram_macros: + if sram_macros == "ihp130": # IHP130 macro path for the eight C906 SRAM wrappers (integration # manual chapter 3): the override files select RM_IHPSG13_1P_* macros # when PDK_IHP130+HAVE_SRAM_MACRO are defined without PDK_BEHAV, and @@ -217,14 +217,37 @@ def _run_c906_boot_tb(tmp_path: Path, *, sram_macros: bool) -> None: sram_verilog = ( ROOT / "physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog" ) - command += [ - "+define+PDK_IHP130", - "+define+HAVE_SRAM_MACRO", - "+define+FUNCTIONAL", - str(sram_verilog / "RM_IHPSG13_1P_core_behavioral_bm_bist.v"), - str(sram_verilog / "RM_IHPSG13_1P_1024x32_c2_bm_bist.v"), - str(sram_verilog / "RM_IHPSG13_1P_64x64_c2_bm_bist.v"), + macro_defines = ["+define+PDK_IHP130", "+define+HAVE_SRAM_MACRO", "+define+FUNCTIONAL"] + macro_models = [ + sram_verilog / "RM_IHPSG13_1P_core_behavioral_bm_bist.v", + sram_verilog / "RM_IHPSG13_1P_1024x32_c2_bm_bist.v", + sram_verilog / "RM_IHPSG13_1P_64x64_c2_bm_bist.v", ] + elif sram_macros == "ics55": + # ICS55 macro path: the override files select the exact-geometry + # ics55_ecos_sram_* macros when PDK_ICS55+HAVE_SRAM_MACRO are defined + # without PDK_BEHAV; these models need no FUNCTIONAL define. + ics55_names = ( + "ics55_ecos_sram_1024x16_m8", + "ics55_ecos_sram_2048x32_m8", + "ics55_ecos_sram_256x59_m4", + "ics55_ecos_sram_1024x64_m8", + "ics55_ecos_sram_128x8_m8", + "ics55_ecos_sram_64x58_m4", + "ics55_ecos_sram_64x88_m4", + "ics55_ecos_sram_64x98_m4", + ) + macro_defines = ["+define+PDK_ICS55", "+define+HAVE_SRAM_MACRO"] + macro_models = [ + ROOT / ".cache/retrosoc/pdk/ics55/sram" / name / "verilog" / f"{name}_core.v" + for name in ics55_names + ] + else: + macro_defines = [] + macro_models = [] + if any(not model.is_file() for model in macro_models): + return + command += [*macro_defines, *(str(model) for model in macro_models)] command += [ str(common / "interface/axi4_if.sv"), str(common / "interface/axi4_addr_gen.sv"), @@ -266,12 +289,17 @@ def _run_c906_boot_tb(tmp_path: Path, *, sram_macros: bool) -> None: def test_c906_boots_smoke_payload_in_focused_tb(tmp_path: Path) -> None: """Boot the real HP smoke payload on the hp_core_wrapper integration.""" - _run_c906_boot_tb(tmp_path, sram_macros=False) + _run_c906_boot_tb(tmp_path, sram_macros=None) def test_c906_boots_smoke_payload_with_ihp130_sram_macros(tmp_path: Path) -> None: """Boot the same payload with the C906 SRAM wrappers on IHP130 macros.""" - _run_c906_boot_tb(tmp_path, sram_macros=True) + _run_c906_boot_tb(tmp_path, sram_macros="ihp130") + + +def test_c906_boots_smoke_payload_with_ics55_sram_macros(tmp_path: Path) -> None: + """Boot the same payload with the C906 SRAM wrappers on ICS55 macros.""" + _run_c906_boot_tb(tmp_path, sram_macros="ics55") def test_hp_smoke_payload_uses_hart1_platform_abi() -> None: From 6fba349894b2d8407e0a8661e3e1b080f17131aa Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 02:42:48 +0800 Subject: [PATCH 19/31] docs: record the ICS55 SRAM macro path and its evidence Extend the chapter 3 SRAM swap documentation to the ICS55 exact-geometry macros: hp-platform.md describes the direct-replacement mapping and gating next to the IHP130 stacking table, hp-rv64-validation.md records the ICS55 boot-TB, MEM_INTF, and SoC macro-sim evidence along with the precise remaining gaps (Yosys smoke synth needs Liberty registration for the new macros; STA/LEC stay deferred), and the two READMEs generalize the override wording to the PDK-selectable IHP130/ICS55 paths. --- docs/hp-rv64-validation.md | 25 +++++++++++++++++++++++-- docs/ip/hp-platform.md | 19 ++++++++++++++++--- rtl/README.md | 5 +++-- scripts/README.md | 6 ++++-- 4 files changed, 46 insertions(+), 9 deletions(-) diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index d378add9..b32384ee 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -123,16 +123,37 @@ qualification. Current evidence requires, at minimum: smoke payload (cache maintenance plus GA2D data movement, which exercises the BHT/ICache/DCache/JTLB RAMs for real) on the macro path with the same `HP_C906_BOOT_TEST_PASS` verdict as the behavioral run. +- The wrappers also have an ICS55 macro path: under `PDK_ICS55`+ + `HAVE_SRAM_MACRO` without `PDK_BEHAV` each wrapper directly instantiates + its exact-geometry `ics55_ecos_sram__m4/m8` macro (locked + `openecos-projects/ics55_ecos_sram` release assets materialized by + `make setup-pdk`; polarity-identical ports, no stacking or padding). The + focused boot testbench variant + `test_c906_boots_smoke_payload_with_ics55_sram_macros` passes with the same + verdict, the vendored MEM_INTF memory suite (manual section 3.2, adapted + to Icarus) passes on the ICS55 path as well, and the `ics55.mk` CI profile + smoke simulation (`APP=ci_smoke`, Verilator) passes with the macro path + compiled into the SoC. `hp-linux-sim` was run with a bounded wall-clock budget this round and its current frontier is recorded above; the synthesis-dependent gates remain unrun (synthesis, netlist simulation, STA, and the physical/LEC qualification -of the macro path). The SoC-level macro-mode simulation now has passing +of the macro path; on Yosys the C906 ICS55 macros additionally need their +Liberty views registered in `physical/smoke/syn/yosys/script/init_tech.tcl`, +and the ICS55 smoke synthesis is already red without this work because +`npu_scheduler.sv` hard-codes IHP130 `sg13g2_dlygate4sd3_1` delay cells under +plain `SYNTHESIS`). The SoC-level macro-mode simulation now has passing evidence: `make CONFIG=configs/ci/ihp130-hp.mk PDK_BEHAV=NO SIMU=VERILATOR hp-smoke-sim` builds the whole SoC (C906 `aq_spsram_*` wrappers and `tc_sram`) on the IHP130 macro models and passes with `SIM_TEST_PASS code=0` plus the `HP_LINUX_READY`/`HP_GA2D_PASS`/ -`HP_GA2D_CACHE_CLEAN` markers. All stay required evidence for qualification. +`HP_GA2D_CACHE_CLEAN` markers. The same SoC smoke passes on the ICS55 macro +path (`PDK=ICS55 PDK_BEHAV=NO`, 3.64M cycles, `SIM_TEST_PASS code=0` with the +full GA2D cache-lifecycle marker sequence); the default 300 s +`HP_SMOKE_SIM_TIME` is only enough when the run is uncontended, and the bare +`ics55.mk` profile-default `sim` (no fast-flash) exceeds its 180 s default +budget in this environment, so both were run with the CI-sized time budgets. +All stay required evidence for qualification. Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT (scan/mbist tied off), the debug SBA AXI master (unconnected), the chapter 3 diff --git a/docs/ip/hp-platform.md b/docs/ip/hp-platform.md index 6258acc5..9439fa27 100644 --- a/docs/ip/hp-platform.md +++ b/docs/ip/hp-platform.md @@ -66,9 +66,22 @@ section 3.1.5: Depth stacks register the bank select on read transactions and mux the bank outputs one cycle later (manual section 3.1.4 timing); unused upper -write-mask bits are tied off so unimplemented bits are never written. Every -other configuration — including the committed `PDK_BEHAV=YES` CI profiles — -compiles the upstream behavioral `aq_f_spsram_*` instance byte-identically. +write-mask bits are tied off so unimplemented bits are never written. + +With `PDK_ICS55` + `HAVE_SRAM_MACRO` and without `PDK_BEHAV`, each wrapper +instead instantiates its exact-geometry ICS55 OpenECOS macro +(`ics55_ecos_sram_1024x16_m8`, `_2048x32_m8`, `_256x59_m4`, `_1024x64_m8`, +`_128x8_m8`, `_64x58_m4`, `_64x88_m4`, `_64x98_m4`), materialized by +`make setup-pdk` from the locked `openecos-projects/ics55_ecos_sram` release +assets (`dependencies.lock.json` `pdk_ics55_sram_` entries). The macro +interface matches the wrapper polarity exactly (`CEB`/`GWEB`/per-bit `WEB` +are active-low at identical widths), so the replacement is a direct +connection with no inversion, padding, or stacking; `MARE`/`MAR` are tied +off as in `tc_sram.sv`. + +Every other configuration — including the committed `PDK_BEHAV=YES` CI +profiles — compiles the upstream behavioral `aq_f_spsram_*` instance +byte-identically. Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT (scan/mbist tied off), the debug SBA AXI master (unconnected), the chapter 3 ICG (`gated_clk_cell`) replacement, diff --git a/rtl/README.md b/rtl/README.md index 79b32e2f..e8921ca7 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -21,8 +21,9 @@ filelist and manifest below `build//generated/openc906/`; the OpenC906 sources are an external lint boundary. The reviewed hart-ID, sysmap address-attribute, and SRAM wrapper overrides live in `rtl/mini/ip_overrides/` (the `aq_spsram_*.v` overrides implement the integration manual chapter 3 -memory swap and select IHP130 `RM_IHPSG13_1P_*` macros only under -`PDK_IHP130`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`) and are applied +memory swap and select IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 +`ics55_ecos_sram_*` macros only under `PDK_IHP130`/`PDK_ICS55` + +`HAVE_SRAM_MACRO` without `PDK_BEHAV`) and are applied by filelist generation, never by editing the vendored checkout. The former VexiiRiscv HP generator is preserved only as the frozen Std-series asset (`make std-vexii-generate`). See diff --git a/scripts/README.md b/scripts/README.md index e713268a..6fb63e30 100644 --- a/scripts/README.md +++ b/scripts/README.md @@ -131,8 +131,10 @@ the vendored checkout is never modified. `generate_openc906.py` resolves the upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1 `aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, and the eight -`aq_spsram_*.v` SRAM wrappers whose IHP130 macro path is gated on -`PDK_IHP130`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, each pinned to +`aq_spsram_*.v` SRAM wrappers whose PDK-selectable macro path — stacked +IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 `ics55_ecos_sram_*` — is +gated on `PDK_IHP130`/`PDK_ICS55`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, +each pinned to the upstream file's SHA-256 so a locked-revision move forces review), and emits the single compilation unit `openc906_combined.v` below `build/`; generated RTL is never tracked. From 65b1794a20a5444c4c9bdd401cb9d473a3a84c89 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 14:05:33 +0800 Subject: [PATCH 20/31] fix(hp): hold the C906 ICG scan enable during reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Real clock-gating cells deadlocked the C906 boot in two-state Verilator: a reset held low from t=0 never fires an async-reset flop's reset branch, and the DTM sleeps at boot (dmactive=0), so the gated dm_pclk never edges and dm_core_rstn (reset value 1) kept its zero-init 0, holding the core in reset forever. Drive pad_yy_icg_scan_en/pad_tdt_icg_scan_en with the inverted core/APB reset so every gate is transparent while in reset and async-reset flops initialize on running-clock edges — the standard POR clock-force pattern silicon gets from the held level. Pass-through (default/PDK_BEHAV) builds ignore SE entirely; the default ihp130-hp smoke run stays cycle-identical (3,644,186 cycles), proving the change is inert until real ICG cells are compiled in. --- rtl/mini/top/hp_core_wrapper.sv | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/rtl/mini/top/hp_core_wrapper.sv b/rtl/mini/top/hp_core_wrapper.sv index f0054d59..91948ab4 100644 --- a/rtl/mini/top/hp_core_wrapper.sv +++ b/rtl/mini/top/hp_core_wrapper.sv @@ -156,7 +156,13 @@ module hp_core_wrapper ( .pad_tdt_dm_rvalid (1'b0), .pad_tdt_dm_wready (1'b0), .pad_yy_dft_clk_rst_b (rst_n_i), - .pad_yy_icg_scan_en (1'b0), + // Hold the ICG scan enable asserted while the core is in reset so the + // gated clocks stay transparent and every async-reset flop behind a + // clock gate still initializes on running-clock edges. Two-state + // simulators otherwise never apply a held async-reset level when the + // gate is closed (the DTM sleeps at boot and would hold hartreset + // low). Pass-through builds ignore SE, keeping them bit-identical. + .pad_yy_icg_scan_en (!s_core_rst_b), .pad_yy_mbist_mode (1'b0), .pad_yy_scan_enable (1'b0), .pad_yy_scan_mode (1'b0), @@ -209,7 +215,10 @@ module hp_core_wrapper ( .pad_tdt_dtm_tdi (jtag_tdi_i), .pad_tdt_dtm_tms_i (jtag_tms_i), .pad_tdt_dtm_trst_b (jtag_trst_n_i), - .pad_tdt_icg_scan_en (1'b0), + // Same ICG transparency while the DTM/APB reset is held (see the + // pad_yy_icg_scan_en note above); the debug module sleeps at boot and + // its async-reset flops still need clock edges to initialize. + .pad_tdt_icg_scan_en (!s_sys_apb_rst_b), .pad_yy_scan_mode (1'b0), .pad_yy_scan_rst_b (1'b1), .sys_apb_clk (s_sys_apb_clk), From 65c19e7005c3687e18dacd17fefa3af3ffb35761 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 14:05:46 +0800 Subject: [PATCH 21/31] feat(hp): replace the OpenC906 clock-gating cells with per-PDK ICGs Complete the integration manual chapter 3 cell swap (the ICG half; the SRAM half landed earlier). Three new reviewed overrides, registered in generate_openc906.py with sha256 pins on the vendored files and added to the generated-filelist stamp prerequisites: - gated_clk_cell.v (216 CPU instances) and tdt_gated_clk_cell.v (DTM): pass-through upstream by default; with PDK_IHP130/PDK_ICS55/PDK_SKY130/ PDK_GF180 and without PDK_BEHAV they instantiate the process ICG cell (sg13g2_slgcp_1 with SCE, ICGX1H7R with the scan enable ORed into E because the ICS55 cell has no TE pin, sky130_fd_sc_hd__sdlclkp_1 with SCE, gf180mcu_fd_sc_mcu7t5v0__icgtp_1 with TE and notifier tied off). - BUFGCE.v (PLIC/CLINT div-2 gate): the upstream behavioral latch model stays byte-identical by default; the same four PDK branches substitute the process cell with the scan input tied off. The GF180 branch uses a repo-owned icgtp_1 functional model in rtl/tech/gf180_seq_sim_cells.v (following the file's dff precedent) because the vendor functional model references a UDP latch primitive that the locked gf180mcu-pdk checkout never ships. SKY130 picks up the vendor sdlclkp model through pdk_sky130.fl, following the existing cell pattern. ASIC CI profiles with PDK_BEHAV unset now compile real clock gating; PDK_BEHAV=YES profiles are bit-identical. Evidence: the manual's MEM_INTF c906_icg_test_tb passes on all four PDK cell paths (Icarus adaptation); the five-mode boot testbench suite passes on top of this change. --- Makefile | 5 +- rtl/filelist/pdk_sky130.fl | 2 + rtl/mini/ip_overrides/BUFGCE.v | 114 +++++++++++++ rtl/mini/ip_overrides/gated_clk_cell.v | 131 ++++++++++++++ rtl/mini/ip_overrides/tdt_gated_clk_cell.v | 190 +++++++++++++++++++++ rtl/tech/gf180_seq_sim_cells.v | 18 ++ scripts/generate_openc906.py | 22 ++- 7 files changed, 480 insertions(+), 2 deletions(-) create mode 100644 rtl/mini/ip_overrides/BUFGCE.v create mode 100644 rtl/mini/ip_overrides/gated_clk_cell.v create mode 100644 rtl/mini/ip_overrides/tdt_gated_clk_cell.v diff --git a/Makefile b/Makefile index 7510e603..15466355 100644 --- a/Makefile +++ b/Makefile @@ -1132,7 +1132,10 @@ $(HP_GENERATED_STAMP): $(ROOT_PATH)/scripts/generate_openc906.py \ $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_128x8.v \ $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x58.v \ $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x88.v \ - $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x98.v $(LOCK_FILE) + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_64x98.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/gated_clk_cell.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/tdt_gated_clk_cell.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/BUFGCE.v $(LOCK_FILE) python3 $(ROOT_PATH)/scripts/generate_openc906.py \ --root $(ROOT_PATH) --source $(OPENC906_ROOT) --output $(HP_GENERATED_DIR) \ --manifest $(HP_GENERATED_MANIFEST) --lock $(LOCK_FILE) diff --git a/rtl/filelist/pdk_sky130.fl b/rtl/filelist/pdk_sky130.fl index 968acc51..cddc467d 100644 --- a/rtl/filelist/pdk_sky130.fl +++ b/rtl/filelist/pdk_sky130.fl @@ -5,6 +5,7 @@ +incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv +incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2 +incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/xor2 ++incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp /tech/sky130_io_sim_cells.v /clusterip/common/rtl/tech/ram.sv /tech/sky130_sram_sim_cells.sv @@ -12,3 +13,4 @@ /physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_1.v /physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v /physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/xor2/sky130_fd_sc_hd__xor2_1.v +/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_1.v diff --git a/rtl/mini/ip_overrides/BUFGCE.v b/rtl/mini/ip_overrides/BUFGCE.v new file mode 100644 index 00000000..792f8c7c --- /dev/null +++ b/rtl/mini/ip_overrides/BUFGCE.v @@ -0,0 +1,114 @@ +// retroSoC controlled override of the vendored OpenC906 BUFGCE.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/common/rtl/BUFGCE.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 ICG swap): with a +// PDK define and without PDK_BEHAV, the clock buffer-gate feeding the +// PLIC/CLINT divide-by-2 domain (aq_mp_clk_top.v apb_clk_buf) uses the +// process integrated clock-gating cell (same selection as +// gated_clk_cell.v; there is no scan enable on this instance, so SCE/TE are +// tied off). PDK_BEHAV and PDK-less builds keep the upstream behavioral +// latch-based gate byte-identical. Keep in sync when the lock revision +// changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +module BUFGCE( + I, + CE, + O +); + +input I; +input CE ; +output O; + +`ifndef PDK_BEHAV +`ifdef PDK_IHP130 +`define _AQ_BUFGCE_IHP130_ +`endif +`ifdef PDK_ICS55 +`define _AQ_BUFGCE_ICS55_ +`endif +`ifdef PDK_SKY130 +`define _AQ_BUFGCE_SKY130_ +`endif +`ifdef PDK_GF180 +`define _AQ_BUFGCE_GF180_ +`endif +`endif + +`ifdef _AQ_BUFGCE_IHP130_ +sg13g2_slgcp_1 u_icg ( + .CLK (I), + .GATE (CE), + .SCE (1'b0), + .GCLK (O) +); +`elsif _AQ_BUFGCE_ICS55_ +ICGX1H7R u_icg ( + .CK (I), + .E (CE), + .ECK (O) +); +`elsif _AQ_BUFGCE_SKY130_ +sky130_fd_sc_hd__sdlclkp_1 u_icg ( + .CLK (I), + .GATE (CE), + .SCE (1'b0), + .GCLK (O) +); +`elsif _AQ_BUFGCE_GF180_ +gf180mcu_fd_sc_mcu7t5v0__icgtp_1 u_icg ( + .CLK (I), + .E (CE), + .TE (1'b0), + .Q (O), + .notifier (1'b0) +); +`else +reg clk_en_af_latch; +always @(I or CE) +begin + if(!I) + clk_en_af_latch <= CE; +end + +reg clk_en ; +always @ (clk_en_af_latch ) +begin + clk_en <= clk_en_af_latch; +end +assign O = I && clk_en ; +`endif + +`ifdef _AQ_BUFGCE_IHP130_ +`undef _AQ_BUFGCE_IHP130_ +`endif +`ifdef _AQ_BUFGCE_ICS55_ +`undef _AQ_BUFGCE_ICS55_ +`endif +`ifdef _AQ_BUFGCE_SKY130_ +`undef _AQ_BUFGCE_SKY130_ +`endif +`ifdef _AQ_BUFGCE_GF180_ +`undef _AQ_BUFGCE_GF180_ +`endif + +endmodule diff --git a/rtl/mini/ip_overrides/gated_clk_cell.v b/rtl/mini/ip_overrides/gated_clk_cell.v new file mode 100644 index 00000000..0afbed70 --- /dev/null +++ b/rtl/mini/ip_overrides/gated_clk_cell.v @@ -0,0 +1,131 @@ +// retroSoC controlled override of the vendored OpenC906 gated_clk_cell.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 ICG swap): with a +// PDK define and without PDK_BEHAV, the upstream pass-through clock gate is +// replaced by the process integrated clock-gating cell: +// PDK_IHP130 -> sg13g2_slgcp_1 (GATE=enable, SCE=scan enable) +// PDK_ICS55 -> ICGX1H7R (no test-enable pin; the scan enable is ORed +// into E so scan mode forces the clock on) +// PDK_SKY130 -> sky130_fd_sc_hd__sdlclkp_1 (GATE=enable, SCE=scan enable) +// PDK_GF180 -> gf180mcu_fd_sc_mcu7t5v0__icgtp_1 (E=enable, TE=scan enable) +// PDK_BEHAV and PDK-less builds keep the upstream pass-through +// byte-identical. Keep in sync when the lock revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +module gated_clk_cell( + clk_in, + global_en, + module_en, + local_en, + external_en, + pad_yy_icg_scan_en, + clk_out +); + +input clk_in; +input global_en; +input module_en; +input local_en; +input external_en; +input pad_yy_icg_scan_en; +output clk_out; + +wire clk_en_bf_latch; +wire SE; + +assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ; + +// SE driven from primary input, held constant +assign SE = pad_yy_icg_scan_en; + +`ifndef PDK_BEHAV +`ifdef PDK_IHP130 +`define _AQ_GATED_CLK_CELL_IHP130_ +`endif +`ifdef PDK_ICS55 +`define _AQ_GATED_CLK_CELL_ICS55_ +`endif +`ifdef PDK_SKY130 +`define _AQ_GATED_CLK_CELL_SKY130_ +`endif +`ifdef PDK_GF180 +`define _AQ_GATED_CLK_CELL_GF180_ +`endif +`endif + +`ifdef _AQ_GATED_CLK_CELL_IHP130_ +sg13g2_slgcp_1 u_icg ( + .CLK (clk_in), + .GATE (clk_en_bf_latch), + .SCE (SE), + .GCLK (clk_out) +); +`elsif _AQ_GATED_CLK_CELL_ICS55_ +// ICGX1H7R has no test-enable pin; OR the scan enable into the enable input. +wire s_en_se; + +assign s_en_se = clk_en_bf_latch | SE; + +ICGX1H7R u_icg ( + .CK (clk_in), + .E (s_en_se), + .ECK (clk_out) +); +`elsif _AQ_GATED_CLK_CELL_SKY130_ +sky130_fd_sc_hd__sdlclkp_1 u_icg ( + .CLK (clk_in), + .GATE (clk_en_bf_latch), + .SCE (SE), + .GCLK (clk_out) +); +`elsif _AQ_GATED_CLK_CELL_GF180_ +gf180mcu_fd_sc_mcu7t5v0__icgtp_1 u_icg ( + .CLK (clk_in), + .E (clk_en_bf_latch), + .TE (SE), + .Q (clk_out), + .notifier (1'b0) +); +`else +// // &Connect( .clk_in (clk_in), @50 +// // .SE (SE), @51 +// // .external_en (clk_en_bf_latch), @52 +// // .clk_out (clk_out) @53 +// // ) ; @54 + +assign clk_out = clk_in; +`endif + +`ifdef _AQ_GATED_CLK_CELL_IHP130_ +`undef _AQ_GATED_CLK_CELL_IHP130_ +`endif +`ifdef _AQ_GATED_CLK_CELL_ICS55_ +`undef _AQ_GATED_CLK_CELL_ICS55_ +`endif +`ifdef _AQ_GATED_CLK_CELL_SKY130_ +`undef _AQ_GATED_CLK_CELL_SKY130_ +`endif +`ifdef _AQ_GATED_CLK_CELL_GF180_ +`undef _AQ_GATED_CLK_CELL_GF180_ +`endif + +endmodule diff --git a/rtl/mini/ip_overrides/tdt_gated_clk_cell.v b/rtl/mini/ip_overrides/tdt_gated_clk_cell.v new file mode 100644 index 00000000..f3e9fbd3 --- /dev/null +++ b/rtl/mini/ip_overrides/tdt_gated_clk_cell.v @@ -0,0 +1,190 @@ +// retroSoC controlled override of the vendored OpenC906 tdt_gated_clk_cell.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/tdt/rtl/common/tdt_gated_clk_cell.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (OpenC906 integration manual chapter 3 ICG swap): the +// upstream `ifdef TDT_GATED_CELL branch is preserved verbatim; with a PDK +// define and without PDK_BEHAV the debug module clock gate uses the process +// integrated clock-gating cell (same selection as gated_clk_cell.v; +// ICGX1H7R has no test-enable pin, so the scan enable is ORed into E). +// PDK_BEHAV and PDK-less builds keep the upstream pass-through +// byte-identical. Keep in sync when the lock revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +module tdt_gated_clk_cell( + clk_in, + global_en, + module_en, + local_en, + external_en, + pad_yy_icg_scan_en, + clk_out +); + +input clk_in; +input global_en; +input module_en; +input local_en; +input external_en; +input pad_yy_icg_scan_en; +output clk_out; + +wire clk_en_bf_latch; +wire SE; + +assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ; + +// SE driven from primary input, held constant +assign SE = pad_yy_icg_scan_en; + +`ifndef PDK_BEHAV +`ifdef PDK_IHP130 +`define _TDT_GATED_CLK_CELL_IHP130_ +`endif +`ifdef PDK_ICS55 +`define _TDT_GATED_CLK_CELL_ICS55_ +`endif +`ifdef PDK_SKY130 +`define _TDT_GATED_CLK_CELL_SKY130_ +`endif +`ifdef PDK_GF180 +`define _TDT_GATED_CLK_CELL_GF180_ +`endif +`endif + +`ifdef TDT_GATED_CELL +tdt_gated_cell x_tdt_gated_cell( + .clk_in (clk_in), + .external_en (clk_en_bf_latch), + .SE (SE), + .clk_out (clk_out) + ); +//`ifdef TDT_SMIC +// `ifdef TDT_PROCESS55LL +//HVT_CLKLANQHDV8 x_gated_clk_cell( +//.CK(clk_in), +// `endif +//.TE(SE), +//.E(clk_en_bf_latch), +//.Q(clk_out)); +//`endif +//`ifdef TDT_TSMC +// `ifdef TDT_PROCESS40LP +//CKLNQD1BWP x_gated_clk_cell( +//.CP(clk_in), +//.TE(SE), +//.E(clk_en_bf_latch), +//.Q(clk_out)); +// `endif +// `ifdef TDT_PROCESS28HPC +// CKLNQD8BWP35P140 x_gated_clk_cell ( +// .CP (clk_in), +// .TE (SE), +// .E (clk_en_bf_latch), +// .Q (clk_out) +// ); +// `endif +//`endif +//`ifdef TDT_GSMC +// `ifdef TDT_PROCESS130 +//CLKGTPHD8X x_gated_clk_cell( +//.CK(clk_in), +// `endif +//.TE(SE), +//.E(clk_en_bf_latch), +//.Z(clk_out)); +//`endif +// +//`ifdef TDT_UMC +// `ifdef TDT_PROCESS28HDE +// PREICG_X4B_A9PP140ZTR_C30 x_gated_clk_cell ( +// .CK(clk_in), +// .SE(SE), +// .E(clk_en_bf_latch), +// .ECK(clk_out) +// ); +// `endif +// `ifdef TDT_PROCESS22HDE +// PREICG_X4B_A9PP140ZTS_C30 x_gated_clk_cell ( +// .CK(clk_in), +// .SE(SE), +// .E(clk_en_bf_latch), +// .ECK(clk_out) +// ); +// +// `endif +//`endif +`elsif _TDT_GATED_CLK_CELL_IHP130_ +sg13g2_slgcp_1 u_icg ( + .CLK (clk_in), + .GATE (clk_en_bf_latch), + .SCE (SE), + .GCLK (clk_out) +); +`elsif _TDT_GATED_CLK_CELL_ICS55_ +// ICGX1H7R has no test-enable pin; OR the scan enable into the enable input. +wire s_en_se; + +assign s_en_se = clk_en_bf_latch | SE; + +ICGX1H7R u_icg ( + .CK (clk_in), + .E (s_en_se), + .ECK (clk_out) +); +`elsif _TDT_GATED_CLK_CELL_SKY130_ +sky130_fd_sc_hd__sdlclkp_1 u_icg ( + .CLK (clk_in), + .GATE (clk_en_bf_latch), + .SCE (SE), + .GCLK (clk_out) +); +`elsif _TDT_GATED_CLK_CELL_GF180_ +gf180mcu_fd_sc_mcu7t5v0__icgtp_1 u_icg ( + .CLK (clk_in), + .E (clk_en_bf_latch), + .TE (SE), + .Q (clk_out), + .notifier (1'b0) +); +`else +//STN_CKGTPLT_V5_1 x_gated_clk_cell ( +// .CK (clk_in), +// .SE (SE), +// .EN (clk_en_bf_latch), +// .Q (clk_out) +//); +assign clk_out = clk_in; +`endif + +`ifdef _TDT_GATED_CLK_CELL_IHP130_ +`undef _TDT_GATED_CLK_CELL_IHP130_ +`endif +`ifdef _TDT_GATED_CLK_CELL_ICS55_ +`undef _TDT_GATED_CLK_CELL_ICS55_ +`endif +`ifdef _TDT_GATED_CLK_CELL_SKY130_ +`undef _TDT_GATED_CLK_CELL_SKY130_ +`endif +`ifdef _TDT_GATED_CLK_CELL_GF180_ +`undef _TDT_GATED_CLK_CELL_GF180_ +`endif + +endmodule diff --git a/rtl/tech/gf180_seq_sim_cells.v b/rtl/tech/gf180_seq_sim_cells.v index 3ee75618..5fd851df 100644 --- a/rtl/tech/gf180_seq_sim_cells.v +++ b/rtl/tech/gf180_seq_sim_cells.v @@ -53,3 +53,21 @@ module gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 ( else Q <= D; end endmodule + +// The upstream icgtp functional model references a UDP latch primitive +// (UDP_GF018hv5v_mcu_sc7_TT_1P8V_25C_verilog_nonpg_MGM_N_IQ_LATCH_UDP) that +// is not shipped anywhere in the locked GF180 checkout, so the vendor model +// cannot elaborate; this functional model retains the PDK cell interface. +module gf180mcu_fd_sc_mcu7t5v0__icgtp_1 ( + input wire TE, + input wire E, + input wire CLK, + output wire Q, + input wire notifier +); + reg s_en_latch; + always @(CLK or E or TE) begin + if (!CLK) s_en_latch <= E | TE; + end + assign Q = CLK & s_en_latch; +endmodule diff --git a/scripts/generate_openc906.py b/scripts/generate_openc906.py index 8f790a68..87736308 100644 --- a/scripts/generate_openc906.py +++ b/scripts/generate_openc906.py @@ -18,8 +18,16 @@ for their vendored counterparts: integration manual chapter 3 memory swap). Each override keeps the upstream behavioral ``aq_f_spsram_*`` instance by default and substitutes IHP130 ``RM_IHPSG13_1P_*`` macro combinations (depth/width stacking per manual - section 3.1.5) only when the build defines ``PDK_IHP130`` and + section 3.1.5) or exact-geometry ICS55 ``ics55_ecos_sram_*`` macros only + when the build defines ``PDK_IHP130``/``PDK_ICS55`` and ``HAVE_SRAM_MACRO`` without ``PDK_BEHAV``. +- ``gated_clk_cell.v`` / ``tdt_gated_clk_cell.v`` / ``BUFGCE.v``: the + clock-gating cells (manual chapter 3 ICG swap). Each override keeps the + upstream default (pass-through for the two ``*_gated_clk_cell`` wrappers, + behavioral latch gate for ``BUFGCE``) unless a PDK define is set without + ``PDK_BEHAV``, in which case the process ICG cell is instantiated + (``sg13g2_slgcp_1`` / ``ICGX1H7R`` / ``sky130_fd_sc_hd__sdlclkp_1`` / + ``gf180mcu_fd_sc_mcu7t5v0__icgtp_1``). All sources are concatenated into a single compilation unit (``openc906_combined.v``) because gen_rtl relies on header macros being @@ -88,6 +96,18 @@ OVERRIDES = { "aq_spsram_64x98.v", "99680fb11271eee6cfe6ff7aaa95cbdd04ef4f78d7b0e23a18c17ef064a8bedf", ), + "C906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v": ( + "gated_clk_cell.v", + "22a4a5f41c7733bd4935adc8a036870a110a8e2f2a70f1f3cf64476b7a49eb9e", + ), + "C906_RTL_FACTORY/gen_rtl/tdt/rtl/common/tdt_gated_clk_cell.v": ( + "tdt_gated_clk_cell.v", + "9c38f1d71a3aaa64e00d2aa7d5a43f5836080c604f245dd414a85935241d26bd", + ), + "C906_RTL_FACTORY/gen_rtl/common/rtl/BUFGCE.v": ( + "BUFGCE.v", + "b0907982b81c64494756d7f62a3a35bf961f6cbf7d54241460a476dde36a333a", + ), } From f83fc3c1c477a8e0ba8616790a373d88d149942c Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 14:05:56 +0800 Subject: [PATCH 22/31] test(hp): boot the C906 smoke payload with per-PDK ICG cells The ihp130/ics55 macro-mode boot testbenches define PDK_IHP130/PDK_ICS55, so they now also compile the ICG branches: extend their model sets with sg13g2_udp.v+sg13g2_stdcell.v and ics55_h7cr_functional.v respectively (the latter with +define+functional, mirroring pdk_ics55.fl). Add test_c906_boots_smoke_payload_with_sky130_icg and ..._gf180_icg covering the two PDKs whose SRAM wrappers intentionally stay behavioral (mixed-mode coverage); both skip when the PDK checkout is not materialized. Evidence: all five boot testbench modes pass with HP_C906_BOOT_TEST_PASS (5 passed, 634s); whole-SoC macro+ICG runs pass for IHP130 and ICS55 (hp-smoke-sim, SIM_TEST_PASS code=0 with the GA2D lifecycle markers), and the CI-flavored sky130/gf180 profile simulations pass at 26.46M cycles. --- tests/test_hp_platform.py | 64 ++++++++++++++++++++++++++++++++------- 1 file changed, 53 insertions(+), 11 deletions(-) diff --git a/tests/test_hp_platform.py b/tests/test_hp_platform.py index 08cf365e..60838f92 100644 --- a/tests/test_hp_platform.py +++ b/tests/test_hp_platform.py @@ -209,24 +209,28 @@ def _run_c906_boot_tb(tmp_path: Path, *, sram_macros: str | None) -> None: "-I" + str(ROOT / "rtl/mini/top"), f"+define+HP_SMOKE_HEX=\"{hex_image}\"", ] + macro_incdirs: list[Path] = [] if sram_macros == "ihp130": # IHP130 macro path for the eight C906 SRAM wrappers (integration # manual chapter 3): the override files select RM_IHPSG13_1P_* macros # when PDK_IHP130+HAVE_SRAM_MACRO are defined without PDK_BEHAV, and - # FUNCTIONAL puts the macro models in zero-delay functional mode. - sram_verilog = ( - ROOT / "physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog" - ) + # FUNCTIONAL puts the macro models in zero-delay functional mode. The + # ICG overrides select sg13g2_slgcp_1, which needs the standard-cell + # and UDP model files (mirrors pdk_ihp130.fl). + ihp130 = ROOT / "physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref" macro_defines = ["+define+PDK_IHP130", "+define+HAVE_SRAM_MACRO", "+define+FUNCTIONAL"] macro_models = [ - sram_verilog / "RM_IHPSG13_1P_core_behavioral_bm_bist.v", - sram_verilog / "RM_IHPSG13_1P_1024x32_c2_bm_bist.v", - sram_verilog / "RM_IHPSG13_1P_64x64_c2_bm_bist.v", + ihp130 / "sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v", + ihp130 / "sg13g2_sram/verilog/RM_IHPSG13_1P_1024x32_c2_bm_bist.v", + ihp130 / "sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v", + ihp130 / "sg13g2_stdcell/verilog/sg13g2_udp.v", + ihp130 / "sg13g2_stdcell/verilog/sg13g2_stdcell.v", ] elif sram_macros == "ics55": # ICS55 macro path: the override files select the exact-geometry # ics55_ecos_sram_* macros when PDK_ICS55+HAVE_SRAM_MACRO are defined - # without PDK_BEHAV; these models need no FUNCTIONAL define. + # without PDK_BEHAV; the ICG overrides select ICGX1H7R from the H7CR + # functional cell models. Mirrors pdk_ics55.fl (+define+functional). ics55_names = ( "ics55_ecos_sram_1024x16_m8", "ics55_ecos_sram_2048x32_m8", @@ -237,17 +241,45 @@ def _run_c906_boot_tb(tmp_path: Path, *, sram_macros: str | None) -> None: "ics55_ecos_sram_64x88_m4", "ics55_ecos_sram_64x98_m4", ) - macro_defines = ["+define+PDK_ICS55", "+define+HAVE_SRAM_MACRO"] + macro_defines = ["+define+PDK_ICS55", "+define+HAVE_SRAM_MACRO", "+define+functional"] macro_models = [ - ROOT / ".cache/retrosoc/pdk/ics55/sram" / name / "verilog" / f"{name}_core.v" - for name in ics55_names + ROOT / ".cache/retrosoc/pdk/ics55/ics55_h7cr_functional.v", + *( + ROOT / ".cache/retrosoc/pdk/ics55/sram" / name / "verilog" / f"{name}_core.v" + for name in ics55_names + ), ] + elif sram_macros == "sky130": + # ICG-only path (manual chapter 3): PDK_SKY130 without PDK_BEHAV + # selects sky130_fd_sc_hd__sdlclkp_1 for the clock-gating cells; the + # SRAM wrappers have no SKY130 branch and stay behavioral. Mirrors + # pdk_sky130.fl (+define+FUNCTIONAL); the cell dir incdir resolves + # the wrapper's `include chain (base module and UDP model). + sdlclkp_dir = ( + ROOT / "physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest" + / "cells/sdlclkp" + ) + macro_defines = ["+define+PDK_SKY130", "+define+HAVE_SRAM_MACRO", "+define+FUNCTIONAL"] + macro_models = [sdlclkp_dir / "sky130_fd_sc_hd__sdlclkp_1.v"] + macro_incdirs = [sdlclkp_dir] + elif sram_macros == "gf180": + # ICG-only path: PDK_GF180 without PDK_BEHAV selects + # gf180mcu_fd_sc_mcu7t5v0__icgtp_1; the SRAM wrappers stay + # behavioral. The sim model is repo-owned (rtl/tech/ + # gf180_seq_sim_cells.v) because the vendor icgtp functional model + # references a UDP primitive that the locked GF180 checkout does not + # ship. + macro_defines = ["+define+PDK_GF180", "+define+HAVE_SRAM_MACRO"] + macro_models = [ROOT / "rtl/tech/gf180_seq_sim_cells.v"] + macro_incdirs = [] else: macro_defines = [] macro_models = [] + macro_incdirs = [] if any(not model.is_file() for model in macro_models): return command += [*macro_defines, *(str(model) for model in macro_models)] + command += ["-I" + str(incdir) for incdir in macro_incdirs] command += [ str(common / "interface/axi4_if.sv"), str(common / "interface/axi4_addr_gen.sv"), @@ -302,6 +334,16 @@ def test_c906_boots_smoke_payload_with_ics55_sram_macros(tmp_path: Path) -> None _run_c906_boot_tb(tmp_path, sram_macros="ics55") +def test_c906_boots_smoke_payload_with_sky130_icg(tmp_path: Path) -> None: + """Boot the same payload with the C906 clock gates on SKY130 ICG cells.""" + _run_c906_boot_tb(tmp_path, sram_macros="sky130") + + +def test_c906_boots_smoke_payload_with_gf180_icg(tmp_path: Path) -> None: + """Boot the same payload with the C906 clock gates on GF180 ICG cells.""" + _run_c906_boot_tb(tmp_path, sram_macros="gf180") + + def test_hp_smoke_payload_uses_hart1_platform_abi() -> None: source = (ROOT / "app/ports/linux/smoke/start.S").read_text(encoding="utf-8") assert "0x10018000" in source From 7070be96c9e9ecad1c9d43ce61cfe0c2df1a9135 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 14:06:08 +0800 Subject: [PATCH 23/31] docs: record the ICG replacement and its evidence Close out the chapter 3 documentation: hp-platform.md gains the ICG section (three override points, per-PDK cell table, the ICS55 SE-into-E note, and the two-state reset rationale), leaving only physical/STA qualification deferred; hp-rv64-validation.md records the MEM_INTF ICG results, the five boot testbench modes, and the four SoC-level runs with the remaining gaps; the two READMEs extend the override inventory to hart-ID + sysmap + SRAM wrappers + clock-gating cells. --- docs/hp-rv64-validation.md | 32 ++++++++++++++++++++++++++------ docs/ip/hp-platform.md | 32 ++++++++++++++++++++++++++++++-- rtl/README.md | 8 ++++++-- scripts/README.md | 6 ++++-- 4 files changed, 66 insertions(+), 12 deletions(-) diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index b32384ee..7208424a 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -134,6 +134,23 @@ qualification. Current evidence requires, at minimum: to Icarus) passes on the ICS55 path as well, and the `ics55.mk` CI profile smoke simulation (`APP=ci_smoke`, Verilator) passes with the macro path compiled into the SoC. +- The chapter 3 ICG swap is validated in simulation on all four PDKs: the + `gated_clk_cell.v`/`tdt_gated_clk_cell.v`/`BUFGCE.v` overrides select + `sg13g2_slgcp_1` (IHP130), `ICGX1H7R` (ICS55, scan enable ORed into `E`), + `sky130_fd_sc_hd__sdlclkp_1` (SKY130), or + `gf180mcu_fd_sc_mcu7t5v0__icgtp_1` (GF180; repo-owned sim model in + `rtl/tech/gf180_seq_sim_cells.v` because the locked checkout never ships + the vendor latch UDP the cell model references) under a `PDK_*` define + without `PDK_BEHAV`. The vendored MEM_INTF `c906_icg_test_tb` gate sequence + passes on all four cell paths (Icarus adaptation; the pass-through default + fails it by design since it never gates). The focused boot testbench passes + with real clock gating for all four PDKs — the IHP130/ICS55 modes run SRAM + macros and ICG together, the SKY130/GF180 modes run ICG with behavioral + SRAMs. One integration fix was required for two-state simulators: + `hp_core_wrapper` asserts the C906/DTM ICG scan-enable while the core is + held in reset, so flops behind closed gates initialize on running-clock + edges (the DTM sleeps at boot and otherwise holds `hartreset_n` low); + pass-through modes ignore the scan-enable input and stay bit-identical. `hp-linux-sim` was run with a bounded wall-clock budget this round and its current frontier is recorded above; the synthesis-dependent gates remain @@ -147,17 +164,20 @@ evidence: `make CONFIG=configs/ci/ihp130-hp.mk PDK_BEHAV=NO SIMU=VERILATOR hp-smoke-sim` builds the whole SoC (C906 `aq_spsram_*` wrappers and `tc_sram`) on the IHP130 macro models and passes with `SIM_TEST_PASS code=0` plus the `HP_LINUX_READY`/`HP_GA2D_PASS`/ -`HP_GA2D_CACHE_CLEAN` markers. The same SoC smoke passes on the ICS55 macro -path (`PDK=ICS55 PDK_BEHAV=NO`, 3.64M cycles, `SIM_TEST_PASS code=0` with the -full GA2D cache-lifecycle marker sequence); the default 300 s +`HP_GA2D_CACHE_CLEAN` markers; with the ICG overrides the same run also +exercises the real `sg13g2_slgcp_1` clock gates. The same SoC smoke passes on +the ICS55 macro+ICG path (`PDK=ICS55 PDK_BEHAV=NO`, 3.64M cycles, +`SIM_TEST_PASS code=0` with the full GA2D cache-lifecycle marker sequence), +and the `sky130.mk` and `gf180.mk` CI profile smokes (`APP=ci_smoke`, +Verilator) pass with the `sky130_fd_sc_hd__sdlclkp_1` / +`gf180mcu_fd_sc_mcu7t5v0__icgtp_1` ICG compiled in. The default 300 s `HP_SMOKE_SIM_TIME` is only enough when the run is uncontended, and the bare `ics55.mk` profile-default `sim` (no fast-flash) exceeds its 180 s default -budget in this environment, so both were run with the CI-sized time budgets. +budget in this environment, so these were run with CI-sized time budgets. All stay required evidence for qualification. Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT -(scan/mbist tied off), the debug SBA AXI master (unconnected), the chapter 3 -ICG (`gated_clk_cell`) replacement, and HP Linux +(scan/mbist tied off), the debug SBA AXI master (unconnected), and HP Linux re-qualification timing/performance evidence. The repo-owned OpenSBI platform registers `fdt_irqchip_init` (v1.9 supports the `thead,c900-plic` match with T-Head delegation fixups), so the C906-internal PLIC is initialized by diff --git a/docs/ip/hp-platform.md b/docs/ip/hp-platform.md index 9439fa27..f59f2755 100644 --- a/docs/ip/hp-platform.md +++ b/docs/ip/hp-platform.md @@ -82,10 +82,38 @@ off as in `tc_sram.sv`. Every other configuration — including the committed `PDK_BEHAV=YES` CI profiles — compiles the upstream behavioral `aq_f_spsram_*` instance byte-identically. + +The chapter 3 ICG swap is implemented alongside: `gated_clk_cell.v` (the 216 +CPU clock gates), `tdt_gated_clk_cell.v` (the debug module gate), and +`BUFGCE.v` (the PLIC/CLINT divide-by-2 gate in `aq_mp_clk_top.v`) have +reviewed overrides in `rtl/mini/ip_overrides/`. With a PDK define and without +`PDK_BEHAV` — no `HAVE_SRAM_MACRO` knob, the ICG is a base cell — each +override instantiates the process clock-gating cell: + +| PDK | ICG cell | Enable/scan mapping | +| --- | --- | --- | +| IHP130 | `sg13g2_slgcp_1` | `GATE`=enable, `SCE`=scan enable | +| ICS55 | `ICGX1H7R` | no test-enable pin: scan enable ORed into `E` | +| SKY130 | `sky130_fd_sc_hd__sdlclkp_1` | `GATE`=enable, `SCE`=scan enable | +| GF180 | `gf180mcu_fd_sc_mcu7t5v0__icgtp_1` | `E`=enable, `TE`=scan enable | + +`BUFGCE` has no scan enable upstream, so SCE/TE tie off there. The GF180 +vendor model cannot elaborate (its UDP latch primitive is not shipped in the +locked checkout), so its simulation model is repo-owned in +`rtl/tech/gf180_seq_sim_cells.v`, following the existing `dffq` precedent. +Because two-state simulators only apply an async-reset flop's reset value on +a real reset edge, `hp_core_wrapper` asserts `pad_yy_icg_scan_en`/ +`pad_tdt_icg_scan_en` while the core/DTM is held in reset, keeping the gated +clocks transparent so flops behind closed gates initialize (the DTM sleeps at +boot and would otherwise hold `hartreset_n` low forever). `PDK_BEHAV` and +PDK-less builds keep the upstream defaults byte-identical (pass-through for +the two `*_gated_clk_cell`, the behavioral latch gate for `BUFGCE`), and +pass-through ignores the scan-enable input entirely. Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT (scan/mbist tied off), the debug SBA AXI -master (unconnected), the chapter 3 ICG (`gated_clk_cell`) replacement, -physical/LEC qualification of the macro path (synthesis mapping, STA), and +master (unconnected), +physical/LEC qualification of the macro and ICG paths (synthesis mapping, +STA), and HP Linux re-qualification timing/performance evidence. ### Boot bundle V2 diff --git a/rtl/README.md b/rtl/README.md index e8921ca7..8ee06b5a 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -19,11 +19,15 @@ SYSCTRL lifecycle signals. `make setup-openc906` (part of `make setup`) restores the locked checkout and `make openc906-prepare` emits the generated filelist and manifest below `build//generated/openc906/`; the OpenC906 sources are an external lint boundary. The reviewed hart-ID, sysmap -address-attribute, and SRAM wrapper overrides live in `rtl/mini/ip_overrides/` +address-attribute, SRAM wrapper, and clock-gate (ICG) overrides live in +`rtl/mini/ip_overrides/` (the `aq_spsram_*.v` overrides implement the integration manual chapter 3 memory swap and select IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 `ics55_ecos_sram_*` macros only under `PDK_IHP130`/`PDK_ICS55` + -`HAVE_SRAM_MACRO` without `PDK_BEHAV`) and are applied +`HAVE_SRAM_MACRO` without `PDK_BEHAV`; the `gated_clk_cell.v`, +`tdt_gated_clk_cell.v`, and `BUFGCE.v` overrides implement the chapter 3 ICG +swap and select the process clock-gating cell under a `PDK_*` define without +`PDK_BEHAV`) and are applied by filelist generation, never by editing the vendored checkout. The former VexiiRiscv HP generator is preserved only as the frozen Std-series asset (`make std-vexii-generate`). See diff --git a/scripts/README.md b/scripts/README.md index 6fb63e30..08b23619 100644 --- a/scripts/README.md +++ b/scripts/README.md @@ -130,10 +130,12 @@ source used by Mini product profiles and verifies the checked-out revision; the vendored checkout is never modified. `generate_openc906.py` resolves the upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1 -`aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, and the eight +`aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, the eight `aq_spsram_*.v` SRAM wrappers whose PDK-selectable macro path — stacked IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 `ics55_ecos_sram_*` — is -gated on `PDK_IHP130`/`PDK_ICS55`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, +gated on `PDK_IHP130`/`PDK_ICS55`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, and +the `gated_clk_cell.v`/`tdt_gated_clk_cell.v`/`BUFGCE.v` clock-gate overrides +that select the process ICG cell under a `PDK_*` define without `PDK_BEHAV`), each pinned to the upstream file's SHA-256 so a locked-revision move forces review), and emits the single compilation unit `openc906_combined.v` below `build/`; From e5819d0a273e0a6befa8e40556e1b1fcc00d0826 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 15:54:01 +0800 Subject: [PATCH 24/31] feat(tech): add the GF180 64/128/256x8 SRAM functional models Extend gf180_sram_sim_cells.sv with pin-compatible functional models for gf180mcu_fd_ip_sram__sram{64,128,256}x8m8wm1, matching the existing 512x8 model's style and behavior (registered read, per-bit active-low WEN, VDD/VSS sanity checks). All four geometries ship vendor collateral in the locked gf180mcu-pdk checkout; the repo-owned models keep simulation self-contained per the existing convention. No filelist change: the file is already listed in pdk_gf180.fl. --- rtl/tech/gf180_sram_sim_cells.sv | 99 +++++++++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 1 deletion(-) diff --git a/rtl/tech/gf180_sram_sim_cells.sv b/rtl/tech/gf180_sram_sim_cells.sv index 440af9a5..9ea08a22 100644 --- a/rtl/tech/gf180_sram_sim_cells.sv +++ b/rtl/tech/gf180_sram_sim_cells.sv @@ -8,7 +8,8 @@ // MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. // See the Mulan PSL v2 for more details. -// Pin-compatible functional model for the GF180 512x8 bit-write SRAM macro. +// Pin-compatible functional models for the GF180 bit-write SRAM macros +// (512x8 for the SoC SRAM, 64/128/256x8 for the C906 SRAM tiles). /* verilator lint_off DECLFILENAME */ module gf180mcu_fd_ip_sram__sram512x8m8wm1 ( // verilog_format: off -- preserve the PDK memory interface columns @@ -40,3 +41,99 @@ module gf180mcu_fd_ip_sram__sram512x8m8wm1 ( end endmodule /* verilator lint_on DECLFILENAME */ + +/* verilator lint_off DECLFILENAME */ +module gf180mcu_fd_ip_sram__sram256x8m8wm1 ( + // verilog_format: off -- preserve the PDK memory interface columns + input logic CLK, + input logic CEN, + input logic GWEN, + input logic [7:0] WEN, + input logic [7:0] A, + input logic [7:0] D, + output logic [7:0] Q, + inout wire VDD, + inout wire VSS + // verilog_format: on +); + logic [7:0] s_storage_q[0:255]; + + always_ff @(posedge CLK) begin + if (!CEN && (VDD !== 1'b0) && (VSS !== 1'b1)) begin + if (GWEN) begin + Q <= s_storage_q[A]; + end else begin + for (int unsigned bit_index = 0; bit_index < 8; bit_index++) begin + if (!WEN[bit_index]) begin + s_storage_q[A][bit_index] <= D[bit_index]; + end + end + end + end + end +endmodule +/* verilator lint_on DECLFILENAME */ + +/* verilator lint_off DECLFILENAME */ +module gf180mcu_fd_ip_sram__sram128x8m8wm1 ( + // verilog_format: off -- preserve the PDK memory interface columns + input logic CLK, + input logic CEN, + input logic GWEN, + input logic [7:0] WEN, + input logic [6:0] A, + input logic [7:0] D, + output logic [7:0] Q, + inout wire VDD, + inout wire VSS + // verilog_format: on +); + logic [7:0] s_storage_q[0:127]; + + always_ff @(posedge CLK) begin + if (!CEN && (VDD !== 1'b0) && (VSS !== 1'b1)) begin + if (GWEN) begin + Q <= s_storage_q[A]; + end else begin + for (int unsigned bit_index = 0; bit_index < 8; bit_index++) begin + if (!WEN[bit_index]) begin + s_storage_q[A][bit_index] <= D[bit_index]; + end + end + end + end + end +endmodule +/* verilator lint_on DECLFILENAME */ + +/* verilator lint_off DECLFILENAME */ +module gf180mcu_fd_ip_sram__sram64x8m8wm1 ( + // verilog_format: off -- preserve the PDK memory interface columns + input logic CLK, + input logic CEN, + input logic GWEN, + input logic [7:0] WEN, + input logic [5:0] A, + input logic [7:0] D, + output logic [7:0] Q, + inout wire VDD, + inout wire VSS + // verilog_format: on +); + logic [7:0] s_storage_q[0:63]; + + always_ff @(posedge CLK) begin + if (!CEN && (VDD !== 1'b0) && (VSS !== 1'b1)) begin + if (GWEN) begin + Q <= s_storage_q[A]; + end else begin + for (int unsigned bit_index = 0; bit_index < 8; bit_index++) begin + if (!WEN[bit_index]) begin + s_storage_q[A][bit_index] <= D[bit_index]; + end + end + end + end + end +endmodule +/* verilator lint_on DECLFILENAME */ From a8c897d475cb1ff35da3e249ff0a34a7504c4978 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 15:54:42 +0800 Subject: [PATCH 25/31] feat(hp): add the GF180 SRAM macro path to the OpenC906 wrappers Add a PDK_GF180+HAVE_SRAM_MACRO (without PDK_BEHAV) branch to each of the eight aq_spsram_* overrides, tiling the 8-bit GF180 macros (sram{64,128,256,512}x8m8wm1, per-bit active-low WEN, matching polarity so no inversion is needed): 512x8 tiles with registered read-mux depth stacking for 1024x16/2048x32/1024x64, width stacks of depth-exact 256x8 and 64x8 tiles for 256x59/64x58/64x88/64x98 (partial top tiles tie unused WEN bits inactive), and a single exact 128x8 tile for the dirty array. VDD/VSS follow the tc_sram.sv GF180 convention. The GF180 CI profile (HAVE_HP=YES, HAVE_SRAM_MACRO=YES, PDK_BEHAV unset) now compiles the macro path automatically. Behavioral, IHP130, and ICS55 paths are bit-identical. SKY130 intentionally stays behavioral: the locked OpenRAM macro offers only byte-granular wmask0 while six of the eight C906 arrays require per-bit writes (BHT one-hot, 29/44/48-bit field groups, single-bit dirty updates). Evidence: directed 8-wrapper equivalence TB and the MEM_INTF adaptation pass on the GF180 path; the gf180 boot testbench and the GF180 SoC hp-smoke-sim both pass (SIM_TEST_PASS code=0, 3,644,186 cycles, identical to every other macro mode). --- rtl/mini/ip_overrides/aq_spsram_1024x16.v | 65 ++++++++++++++++++++- rtl/mini/ip_overrides/aq_spsram_1024x64.v | 65 ++++++++++++++++++++- rtl/mini/ip_overrides/aq_spsram_128x8.v | 50 +++++++++++++++- rtl/mini/ip_overrides/aq_spsram_2048x32.v | 69 ++++++++++++++++++++++- rtl/mini/ip_overrides/aq_spsram_256x59.v | 64 ++++++++++++++++++++- rtl/mini/ip_overrides/aq_spsram_64x58.v | 65 ++++++++++++++++++++- rtl/mini/ip_overrides/aq_spsram_64x88.v | 58 ++++++++++++++++++- rtl/mini/ip_overrides/aq_spsram_64x98.v | 65 ++++++++++++++++++++- 8 files changed, 481 insertions(+), 20 deletions(-) diff --git a/rtl/mini/ip_overrides/aq_spsram_1024x16.v b/rtl/mini/ip_overrides/aq_spsram_1024x16.v index ba7e63e7..83c046d8 100644 --- a/rtl/mini/ip_overrides/aq_spsram_1024x16.v +++ b/rtl/mini/ip_overrides/aq_spsram_1024x16.v @@ -11,7 +11,11 @@ // bits are used and the upper mask bits are tied off so they are never // written. With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the // exact-geometry ics55_ecos_sram_1024x16_m8 macro replaces it directly -// (identical active-low polarity, no stacking or padding). Every other +// (identical active-low polarity, no stacking or padding). With +// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, GF180 +// gf180mcu_fd_ip_sram__sram512x8m8wm1 tiles build it (two deep selected by +// A[9] with a registered read mux, times two wide; the repo-owned functional +// models live in rtl/tech/gf180_sram_sim_cells.sv). Every other // configuration keeps the upstream behavioral aq_f_spsram_1024x16 instance // byte-identical. Keep in sync when the lock revision changes. @@ -90,6 +94,14 @@ parameter WE_WIDTH = 16; `endif `endif +`ifdef PDK_GF180 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_1024X16_GF180_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_1024X16_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -137,6 +149,53 @@ ics55_ecos_sram_1024x16_m8 u_mem ( .WEB (WEN ), .Q (Q ) ); +`elsif _AQ_SPSRAM_1024X16_GF180_ + //******************************************************** + //* GF180 SRAM macro * + //******************************************************** +// Four 512x8 tiles: two deep selected by A[9] with the bank select +// registered on read transactions, times two wide. +`ifndef SYNTHESIS +wire s_vdd; +wire s_vss; + +assign s_vdd = 1'b1; +assign s_vss = 1'b0; +`endif +wire [31:0] s_q; +reg s_rd_sel_q; +genvar g_d; +genvar g_w; + +always @(posedge CLK) begin + if (!CEN && GWEN) begin + s_rd_sel_q <= A[9]; + end +end + +assign Q = s_rd_sel_q ? s_q[31:16] : s_q[15:0]; + +generate + for (g_d = 0; g_d < 2; g_d = g_d + 1) begin : gen_depth + for (g_w = 0; g_w < 2; g_w = g_w + 1) begin : gen_width + gf180mcu_fd_ip_sram__sram512x8m8wm1 u_mem ( + .CLK (CLK ), + .CEN (~(~CEN & (A[9] == g_d)) ), + .GWEN (GWEN ), + .WEN (WEN[g_w*8 +: 8] ), + .A (A[8:0] ), + .D (D[g_w*8 +: 8] ), +`ifndef SYNTHESIS + .Q (s_q[g_d*16 + g_w*8 +: 8] ), + .VDD (s_vdd ), + .VSS (s_vss ) +`else + .Q (s_q[g_d*16 + g_w*8 +: 8] ) +`endif + ); + end + end +endgenerate `else //******************************************************** //* FPGA memory * @@ -161,6 +220,10 @@ aq_f_spsram_1024x16 x_aq_f_spsram_1024x16 ( `undef _AQ_SPSRAM_1024X16_ICS55_ `endif +`ifdef _AQ_SPSRAM_1024X16_GF180_ +`undef _AQ_SPSRAM_1024X16_GF180_ +`endif + // &Instance("aq_tsmc_spsram_1024x16"); @49 // &Instance("aq_umc_spsram_1024x16"); @61 diff --git a/rtl/mini/ip_overrides/aq_spsram_1024x64.v b/rtl/mini/ip_overrides/aq_spsram_1024x64.v index a21b583a..aec43611 100644 --- a/rtl/mini/ip_overrides/aq_spsram_1024x64.v +++ b/rtl/mini/ip_overrides/aq_spsram_1024x64.v @@ -11,7 +11,11 @@ // stack: one macro holds the low 32 bits, the other the high 32 bits (manual // section 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without // PDK_BEHAV, the exact-geometry ics55_ecos_sram_1024x64_m8 macro replaces it -// directly (identical active-low polarity, no stacking or padding). Every +// directly (identical active-low polarity, no stacking or padding). With +// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, GF180 +// gf180mcu_fd_ip_sram__sram512x8m8wm1 tiles build it (two deep selected by +// A[9] with a registered read mux, times eight wide; the repo-owned +// functional models live in rtl/tech/gf180_sram_sim_cells.sv). Every // other configuration keeps the upstream behavioral aq_f_spsram_1024x64 // instance byte-identical. Keep in sync when the lock revision changes. @@ -90,6 +94,14 @@ parameter WE_WIDTH = 64; `endif `endif +`ifdef PDK_GF180 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_1024X64_GF180_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_1024X64_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -156,6 +168,53 @@ ics55_ecos_sram_1024x64_m8 u_mem ( .WEB (WEN ), .Q (Q ) ); +`elsif _AQ_SPSRAM_1024X64_GF180_ + //******************************************************** + //* GF180 SRAM macro * + //******************************************************** +// Sixteen 512x8 tiles: two deep selected by A[9] with the bank select +// registered on read transactions, times eight wide. +`ifndef SYNTHESIS +wire s_vdd; +wire s_vss; + +assign s_vdd = 1'b1; +assign s_vss = 1'b0; +`endif +wire [127:0] s_q; +reg s_rd_sel_q; +genvar g_d; +genvar g_w; + +always @(posedge CLK) begin + if (!CEN && GWEN) begin + s_rd_sel_q <= A[9]; + end +end + +assign Q = s_q[s_rd_sel_q*64 +: 64]; + +generate + for (g_d = 0; g_d < 2; g_d = g_d + 1) begin : gen_depth + for (g_w = 0; g_w < 8; g_w = g_w + 1) begin : gen_width + gf180mcu_fd_ip_sram__sram512x8m8wm1 u_mem ( + .CLK (CLK ), + .CEN (~(~CEN & (A[9] == g_d)) ), + .GWEN (GWEN ), + .WEN (WEN[g_w*8 +: 8] ), + .A (A[8:0] ), + .D (D[g_w*8 +: 8] ), +`ifndef SYNTHESIS + .Q (s_q[g_d*64 + g_w*8 +: 8] ), + .VDD (s_vdd ), + .VSS (s_vss ) +`else + .Q (s_q[g_d*64 + g_w*8 +: 8] ) +`endif + ); + end + end +endgenerate `else // //******************************************************** // //* FPGA memory * @@ -180,6 +239,10 @@ aq_f_spsram_1024x64 x_aq_f_spsram_1024x64 ( `undef _AQ_SPSRAM_1024X64_ICS55_ `endif +`ifdef _AQ_SPSRAM_1024X64_GF180_ +`undef _AQ_SPSRAM_1024X64_GF180_ +`endif + // &Instance("aq_umc_spsram_1024x64"); @49 // &Instance("aq_tsmc_spsram_1024x64"); @55 // &ModuleEnd; @58 diff --git a/rtl/mini/ip_overrides/aq_spsram_128x8.v b/rtl/mini/ip_overrides/aq_spsram_128x8.v index be08e091..b0a10bf7 100644 --- a/rtl/mini/ip_overrides/aq_spsram_128x8.v +++ b/rtl/mini/ip_overrides/aq_spsram_128x8.v @@ -13,9 +13,13 @@ // mux uses the bank select registered on read transactions (manual section // 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, // the exact-geometry ics55_ecos_sram_128x8_m8 macro replaces it directly -// (identical active-low polarity, no stacking or padding). Every other -// configuration keeps the upstream behavioral aq_f_spsram_128x8 instance -// byte-identical. Keep in sync when the lock revision changes. +// (identical active-low polarity, no stacking or padding). With +// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, one exact-geometry GF180 +// gf180mcu_fd_ip_sram__sram128x8m8wm1 tile replaces it directly (the +// repo-owned functional models live in rtl/tech/gf180_sram_sim_cells.sv). +// Every other configuration keeps the upstream behavioral +// aq_f_spsram_128x8 instance byte-identical. Keep in sync when the lock +// revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -92,6 +96,14 @@ parameter WE_WIDTH = 8; `endif `endif +`ifdef PDK_GF180 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_128X8_GF180_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_128X8_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -175,6 +187,34 @@ ics55_ecos_sram_128x8_m8 u_mem ( .WEB (WEN ), .Q (Q ) ); +`elsif _AQ_SPSRAM_128X8_GF180_ + //******************************************************** + //* GF180 SRAM macro * + //******************************************************** +// One exact 128x8 tile; identical active-low polarity, direct connection. +`ifndef SYNTHESIS +wire s_vdd; +wire s_vss; + +assign s_vdd = 1'b1; +assign s_vss = 1'b0; +`endif + +gf180mcu_fd_ip_sram__sram128x8m8wm1 u_mem ( + .CLK (CLK ), + .CEN (CEN ), + .GWEN (GWEN ), + .WEN (WEN ), + .A (A ), + .D (D ), +`ifndef SYNTHESIS + .Q (Q ), + .VDD (s_vdd), + .VSS (s_vss) +`else + .Q (Q ) +`endif +); `else // //******************************************************** // //* FPGA memory * @@ -199,6 +239,10 @@ aq_f_spsram_128x8 x_aq_f_spsram_128x8 ( `undef _AQ_SPSRAM_128X8_ICS55_ `endif +`ifdef _AQ_SPSRAM_128X8_GF180_ +`undef _AQ_SPSRAM_128X8_GF180_ +`endif + // &Instance("aq_umc_spsram_128x8"); @49 // &Instance("aq_tsmc_spsram_128x8"); @55 // &ModuleEnd; @58 diff --git a/rtl/mini/ip_overrides/aq_spsram_2048x32.v b/rtl/mini/ip_overrides/aq_spsram_2048x32.v index a4cd951b..6dd90919 100644 --- a/rtl/mini/ip_overrides/aq_spsram_2048x32.v +++ b/rtl/mini/ip_overrides/aq_spsram_2048x32.v @@ -12,9 +12,13 @@ // registered on read transactions (manual section 3.1.5 stacking). With // PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the exact-geometry // ics55_ecos_sram_2048x32_m8 macro replaces it directly (identical -// active-low polarity, no stacking or padding). Every other configuration -// keeps the upstream behavioral aq_f_spsram_2048x32 instance byte-identical. -// Keep in sync when the lock revision changes. +// active-low polarity, no stacking or padding). With PDK_GF180+ +// HAVE_SRAM_MACRO and without PDK_BEHAV, GF180 +// gf180mcu_fd_ip_sram__sram512x8m8wm1 tiles build it (four deep selected by +// A[10:9] with a registered read mux, times four wide; the repo-owned +// functional models live in rtl/tech/gf180_sram_sim_cells.sv). Every other +// configuration keeps the upstream behavioral aq_f_spsram_2048x32 instance +// byte-identical. Keep in sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -91,6 +95,14 @@ parameter WE_WIDTH = 32; `endif `endif +`ifdef PDK_GF180 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_2048X32_GF180_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_2048X32_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -169,6 +181,53 @@ ics55_ecos_sram_2048x32_m8 u_mem ( .WEB (WEN ), .Q (Q ) ); +`elsif _AQ_SPSRAM_2048X32_GF180_ + //******************************************************** + //* GF180 SRAM macro * + //******************************************************** +// Sixteen 512x8 tiles: four deep selected by A[10:9] with the bank select +// registered on read transactions, times four wide. +`ifndef SYNTHESIS +wire s_vdd; +wire s_vss; + +assign s_vdd = 1'b1; +assign s_vss = 1'b0; +`endif +wire [127:0] s_q; +reg [1:0] s_rd_sel_q; +genvar g_d; +genvar g_w; + +always @(posedge CLK) begin + if (!CEN && GWEN) begin + s_rd_sel_q <= A[10:9]; + end +end + +assign Q = s_q[s_rd_sel_q*32 +: 32]; + +generate + for (g_d = 0; g_d < 4; g_d = g_d + 1) begin : gen_depth + for (g_w = 0; g_w < 4; g_w = g_w + 1) begin : gen_width + gf180mcu_fd_ip_sram__sram512x8m8wm1 u_mem ( + .CLK (CLK ), + .CEN (~(~CEN & (A[10:9] == g_d))), + .GWEN (GWEN ), + .WEN (WEN[g_w*8 +: 8] ), + .A (A[8:0] ), + .D (D[g_w*8 +: 8] ), +`ifndef SYNTHESIS + .Q (s_q[g_d*32 + g_w*8 +: 8] ), + .VDD (s_vdd ), + .VSS (s_vss ) +`else + .Q (s_q[g_d*32 + g_w*8 +: 8] ) +`endif + ); + end + end +endgenerate `else //******************************************************** //* FPGA memory * @@ -193,6 +252,10 @@ aq_f_spsram_2048x32 x_aq_f_spsram_2048x32 ( `undef _AQ_SPSRAM_2048X32_ICS55_ `endif +`ifdef _AQ_SPSRAM_2048X32_GF180_ +`undef _AQ_SPSRAM_2048X32_GF180_ +`endif + // &Instance("aq_tsmc_spsram_2048x32"); @49 // &Instance("aq_umc_spsram_2048x32"); @61 diff --git a/rtl/mini/ip_overrides/aq_spsram_256x59.v b/rtl/mini/ip_overrides/aq_spsram_256x59.v index e3d0330b..0e50b4bb 100644 --- a/rtl/mini/ip_overrides/aq_spsram_256x59.v +++ b/rtl/mini/ip_overrides/aq_spsram_256x59.v @@ -14,9 +14,12 @@ // (manual section 3.1.5 stacking). With PDK_ICS55+HAVE_SRAM_MACRO and // without PDK_BEHAV, the exact-geometry ics55_ecos_sram_256x59_m4 macro // replaces it directly (identical active-low polarity, no stacking or -// padding). Every other configuration keeps the upstream behavioral -// aq_f_spsram_256x59 instance byte-identical. Keep in sync when the lock -// revision changes. +// padding). With PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, eight +// GF180 gf180mcu_fd_ip_sram__sram256x8m8wm1 tiles width-stack it (the top +// tile's upper 5 bits are tied inactive; the repo-owned functional models +// live in rtl/tech/gf180_sram_sim_cells.sv). Every other configuration +// keeps the upstream behavioral aq_f_spsram_256x59 instance byte-identical. +// Keep in sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -93,6 +96,14 @@ parameter WE_WIDTH = 59; `endif `endif +`ifdef PDK_GF180 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_256X59_GF180_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_256X59_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -157,6 +168,49 @@ ics55_ecos_sram_256x59_m4 u_mem ( .WEB (WEN ), .Q (Q ) ); +`elsif _AQ_SPSRAM_256X59_GF180_ + //******************************************************** + //* GF180 SRAM macro * + //******************************************************** +// Eight 256x8 tiles width-stack the 59-bit word; the top tile's upper 5 +// bits are tied inactive so they are never written. +`ifndef SYNTHESIS +wire s_vdd; +wire s_vss; + +assign s_vdd = 1'b1; +assign s_vss = 1'b0; +`endif +wire [63:0] s_din_ext; +wire [63:0] s_wen_ext; +wire [63:0] s_q; +wire [4:0] s_q_unused; +genvar g_w; + +assign s_din_ext = {5'b00000, D}; +assign s_wen_ext = {5'b11111, WEN}; +assign Q = s_q[58:0]; +assign s_q_unused = s_q[63:59]; + +generate + for (g_w = 0; g_w < 8; g_w = g_w + 1) begin : gen_width + gf180mcu_fd_ip_sram__sram256x8m8wm1 u_mem ( + .CLK (CLK ), + .CEN (CEN ), + .GWEN (GWEN ), + .WEN (s_wen_ext[g_w*8 +: 8] ), + .A (A ), + .D (s_din_ext[g_w*8 +: 8] ), +`ifndef SYNTHESIS + .Q (s_q[g_w*8 +: 8] ), + .VDD (s_vdd ), + .VSS (s_vss ) +`else + .Q (s_q[g_w*8 +: 8] ) +`endif + ); + end +endgenerate `else //******************************************************** //* FPGA memory * @@ -181,6 +235,10 @@ aq_f_spsram_256x59 x_aq_f_spsram_256x59 ( `undef _AQ_SPSRAM_256X59_ICS55_ `endif +`ifdef _AQ_SPSRAM_256X59_GF180_ +`undef _AQ_SPSRAM_256X59_GF180_ +`endif + // &Instance("aq_tsmc_spsram_256x59"); @49 // &Instance("aq_umc_spsram_256x59"); @61 diff --git a/rtl/mini/ip_overrides/aq_spsram_64x58.v b/rtl/mini/ip_overrides/aq_spsram_64x58.v index 7f0c7e17..40d4d41a 100644 --- a/rtl/mini/ip_overrides/aq_spsram_64x58.v +++ b/rtl/mini/ip_overrides/aq_spsram_64x58.v @@ -11,9 +11,13 @@ // bits are used and the upper mask bits are tied off so they are never // written. With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the // exact-geometry ics55_ecos_sram_64x58_m4 macro replaces it directly -// (identical active-low polarity, no stacking or padding). Every other -// configuration keeps the upstream behavioral aq_f_spsram_64x58 instance -// byte-identical. Keep in sync when the lock revision changes. +// (identical active-low polarity, no stacking or padding). With +// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, eight GF180 +// gf180mcu_fd_ip_sram__sram64x8m8wm1 tiles width-stack it (the top tile's +// upper 6 bits are tied inactive; the repo-owned functional models live in +// rtl/tech/gf180_sram_sim_cells.sv). Every other configuration keeps the +// upstream behavioral aq_f_spsram_64x58 instance byte-identical. Keep in +// sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -90,6 +94,14 @@ parameter WE_WIDTH = 58; `endif `endif +`ifdef PDK_GF180 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_64X58_GF180_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_64X58_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -137,6 +149,49 @@ ics55_ecos_sram_64x58_m4 u_mem ( .WEB (WEN ), .Q (Q ) ); +`elsif _AQ_SPSRAM_64X58_GF180_ + //******************************************************** + //* GF180 SRAM macro * + //******************************************************** +// Eight 64x8 tiles width-stack the 58-bit word; the top tile's upper 6 +// bits are tied inactive so they are never written. +`ifndef SYNTHESIS +wire s_vdd; +wire s_vss; + +assign s_vdd = 1'b1; +assign s_vss = 1'b0; +`endif +wire [63:0] s_din_ext; +wire [63:0] s_wen_ext; +wire [63:0] s_q; +wire [5:0] s_q_unused; +genvar g_w; + +assign s_din_ext = {6'b000000, D}; +assign s_wen_ext = {6'b111111, WEN}; +assign Q = s_q[57:0]; +assign s_q_unused = s_q[63:58]; + +generate + for (g_w = 0; g_w < 8; g_w = g_w + 1) begin : gen_width + gf180mcu_fd_ip_sram__sram64x8m8wm1 u_mem ( + .CLK (CLK ), + .CEN (CEN ), + .GWEN (GWEN ), + .WEN (s_wen_ext[g_w*8 +: 8] ), + .A (A ), + .D (s_din_ext[g_w*8 +: 8] ), +`ifndef SYNTHESIS + .Q (s_q[g_w*8 +: 8] ), + .VDD (s_vdd ), + .VSS (s_vss ) +`else + .Q (s_q[g_w*8 +: 8] ) +`endif + ); + end +endgenerate `else // //******************************************************** // //* FPGA memory * @@ -161,6 +216,10 @@ aq_f_spsram_64x58 x_aq_f_spsram_64x58 ( `undef _AQ_SPSRAM_64X58_ICS55_ `endif +`ifdef _AQ_SPSRAM_64X58_GF180_ +`undef _AQ_SPSRAM_64X58_GF180_ +`endif + // &Instance("aq_umc_spsram_64x58"); @49 // &Instance("aq_tsmc_spsram_64x58"); @55 // &ModuleEnd; @58 diff --git a/rtl/mini/ip_overrides/aq_spsram_64x88.v b/rtl/mini/ip_overrides/aq_spsram_64x88.v index 6d0a6754..408e5438 100644 --- a/rtl/mini/ip_overrides/aq_spsram_64x88.v +++ b/rtl/mini/ip_overrides/aq_spsram_64x88.v @@ -12,9 +12,13 @@ // mask bits tied off so they are never written (manual section 3.1.5 // stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the // exact-geometry ics55_ecos_sram_64x88_m4 macro replaces it directly -// (identical active-low polarity, no stacking or padding). Every other -// configuration keeps the upstream behavioral aq_f_spsram_64x88 instance -// byte-identical. Keep in sync when the lock revision changes. +// (identical active-low polarity, no stacking or padding). With +// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, eleven GF180 +// gf180mcu_fd_ip_sram__sram64x8m8wm1 tiles width-stack it exactly (the +// repo-owned functional models live in rtl/tech/gf180_sram_sim_cells.sv). +// Every other configuration keeps the upstream behavioral +// aq_f_spsram_64x88 instance byte-identical. Keep in sync when the lock +// revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -91,6 +95,14 @@ parameter WE_WIDTH = 88; `endif `endif +`ifdef PDK_GF180 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_64X88_GF180_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_64X88_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -160,6 +172,42 @@ ics55_ecos_sram_64x88_m4 u_mem ( .WEB (WEN ), .Q (Q ) ); +`elsif _AQ_SPSRAM_64X88_GF180_ + //******************************************************** + //* GF180 SRAM macro * + //******************************************************** +// Eleven 64x8 tiles width-stack the 88-bit word exactly. +`ifndef SYNTHESIS +wire s_vdd; +wire s_vss; + +assign s_vdd = 1'b1; +assign s_vss = 1'b0; +`endif +wire [87:0] s_q; +genvar g_w; + +assign Q = s_q; + +generate + for (g_w = 0; g_w < 11; g_w = g_w + 1) begin : gen_width + gf180mcu_fd_ip_sram__sram64x8m8wm1 u_mem ( + .CLK (CLK ), + .CEN (CEN ), + .GWEN (GWEN ), + .WEN (WEN[g_w*8 +: 8] ), + .A (A ), + .D (D[g_w*8 +: 8] ), +`ifndef SYNTHESIS + .Q (s_q[g_w*8 +: 8] ), + .VDD (s_vdd ), + .VSS (s_vss ) +`else + .Q (s_q[g_w*8 +: 8] ) +`endif + ); + end +endgenerate `else //******************************************************** //* FPGA memory * @@ -185,6 +233,10 @@ aq_f_spsram_64x88 x_aq_f_spsram_64x88 ( `undef _AQ_SPSRAM_64X88_ICS55_ `endif +`ifdef _AQ_SPSRAM_64X88_GF180_ +`undef _AQ_SPSRAM_64X88_GF180_ +`endif + // &Instance("aq_tsmc_spsram_64x88"); @50 // &Instance("aq_umc_spsram_64x88"); @62 diff --git a/rtl/mini/ip_overrides/aq_spsram_64x98.v b/rtl/mini/ip_overrides/aq_spsram_64x98.v index b379d2aa..5a19b1e5 100644 --- a/rtl/mini/ip_overrides/aq_spsram_64x98.v +++ b/rtl/mini/ip_overrides/aq_spsram_64x98.v @@ -12,9 +12,13 @@ // mask bits tied off so they are never written (manual section 3.1.5 // stacking). With PDK_ICS55+HAVE_SRAM_MACRO and without PDK_BEHAV, the // exact-geometry ics55_ecos_sram_64x98_m4 macro replaces it directly -// (identical active-low polarity, no stacking or padding). Every other -// configuration keeps the upstream behavioral aq_f_spsram_64x98 instance -// byte-identical. Keep in sync when the lock revision changes. +// (identical active-low polarity, no stacking or padding). With +// PDK_GF180+HAVE_SRAM_MACRO and without PDK_BEHAV, thirteen GF180 +// gf180mcu_fd_ip_sram__sram64x8m8wm1 tiles width-stack it (the top tile's +// upper 6 bits are tied inactive; the repo-owned functional models live in +// rtl/tech/gf180_sram_sim_cells.sv). Every other configuration keeps the +// upstream behavioral aq_f_spsram_64x98 instance byte-identical. Keep in +// sync when the lock revision changes. /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. @@ -91,6 +95,14 @@ parameter WE_WIDTH = 98; `endif `endif +`ifdef PDK_GF180 +`ifdef HAVE_SRAM_MACRO +`ifndef PDK_BEHAV +`define _AQ_SPSRAM_64X98_GF180_ +`endif +`endif +`endif + `ifdef _AQ_SPSRAM_64X98_IHP130_ //******************************************************** //* IHP130 SRAM macro * @@ -160,6 +172,49 @@ ics55_ecos_sram_64x98_m4 u_mem ( .WEB (WEN ), .Q (Q ) ); +`elsif _AQ_SPSRAM_64X98_GF180_ + //******************************************************** + //* GF180 SRAM macro * + //******************************************************** +// Thirteen 64x8 tiles width-stack the 98-bit word; the top tile's upper 6 +// bits are tied inactive so they are never written. +`ifndef SYNTHESIS +wire s_vdd; +wire s_vss; + +assign s_vdd = 1'b1; +assign s_vss = 1'b0; +`endif +wire [103:0] s_din_ext; +wire [103:0] s_wen_ext; +wire [103:0] s_q; +wire [5:0] s_q_unused; +genvar g_w; + +assign s_din_ext = {6'b000000, D}; +assign s_wen_ext = {6'b111111, WEN}; +assign Q = s_q[97:0]; +assign s_q_unused = s_q[103:98]; + +generate + for (g_w = 0; g_w < 13; g_w = g_w + 1) begin : gen_width + gf180mcu_fd_ip_sram__sram64x8m8wm1 u_mem ( + .CLK (CLK ), + .CEN (CEN ), + .GWEN (GWEN ), + .WEN (s_wen_ext[g_w*8 +: 8] ), + .A (A ), + .D (s_din_ext[g_w*8 +: 8] ), +`ifndef SYNTHESIS + .Q (s_q[g_w*8 +: 8] ), + .VDD (s_vdd ), + .VSS (s_vss ) +`else + .Q (s_q[g_w*8 +: 8] ) +`endif + ); + end +endgenerate `else //******************************************************** //* FPGA memory * @@ -185,6 +240,10 @@ aq_f_spsram_64x98 x_aq_f_spsram_64x98 ( `undef _AQ_SPSRAM_64X98_ICS55_ `endif +`ifdef _AQ_SPSRAM_64X98_GF180_ +`undef _AQ_SPSRAM_64X98_GF180_ +`endif + // &Instance("aq_tsmc_spsram_64x98"); @50 // &Instance("aq_umc_spsram_64x98"); @62 From 7da9a7efb8c9be2dc80f26a0b96013f5ceb4f56b Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 15:55:01 +0800 Subject: [PATCH 26/31] test(hp): cover the GF180 SRAM+ICG macro path in the boot testbench The gf180 boot testbench mode defines PDK_GF180 and therefore now compiles the SRAM macro branches alongside the ICG cells: add the repo-owned gf180_sram_sim_cells.sv to its model list and rename the test to test_c906_boots_smoke_payload_with_gf180_macros. Both GF180 models are repo-owned, so the mode no longer depends on the PDK checkout. Evidence: tests/test_hp_platform.py passes 20/20 with all five boot modes (behavioral, ihp130, ics55, sky130-icg, gf180); the CI-flavored gf180 profile simulation passes at 26,462,456 cycles with SIM_TEST_PASS code=0. --- tests/test_hp_platform.py | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/tests/test_hp_platform.py b/tests/test_hp_platform.py index 60838f92..2bc414b2 100644 --- a/tests/test_hp_platform.py +++ b/tests/test_hp_platform.py @@ -263,14 +263,18 @@ def _run_c906_boot_tb(tmp_path: Path, *, sram_macros: str | None) -> None: macro_models = [sdlclkp_dir / "sky130_fd_sc_hd__sdlclkp_1.v"] macro_incdirs = [sdlclkp_dir] elif sram_macros == "gf180": - # ICG-only path: PDK_GF180 without PDK_BEHAV selects - # gf180mcu_fd_sc_mcu7t5v0__icgtp_1; the SRAM wrappers stay - # behavioral. The sim model is repo-owned (rtl/tech/ - # gf180_seq_sim_cells.v) because the vendor icgtp functional model - # references a UDP primitive that the locked GF180 checkout does not - # ship. + # GF180 macro path: PDK_GF180+HAVE_SRAM_MACRO without PDK_BEHAV + # selects the gf180mcu_fd_ip_sram__sram*x8m8wm1 tiles for the SRAM + # wrappers and gf180mcu_fd_sc_mcu7t5v0__icgtp_1 for the ICG cells. + # Both sim models are repo-owned (rtl/tech/gf180_*_sim_cells.*): the + # vendor icgtp functional model references a UDP primitive that the + # locked GF180 checkout does not ship, and the vendor SRAM verilog is + # timing-only. macro_defines = ["+define+PDK_GF180", "+define+HAVE_SRAM_MACRO"] - macro_models = [ROOT / "rtl/tech/gf180_seq_sim_cells.v"] + macro_models = [ + ROOT / "rtl/tech/gf180_seq_sim_cells.v", + ROOT / "rtl/tech/gf180_sram_sim_cells.sv", + ] macro_incdirs = [] else: macro_defines = [] @@ -339,8 +343,8 @@ def test_c906_boots_smoke_payload_with_sky130_icg(tmp_path: Path) -> None: _run_c906_boot_tb(tmp_path, sram_macros="sky130") -def test_c906_boots_smoke_payload_with_gf180_icg(tmp_path: Path) -> None: - """Boot the same payload with the C906 clock gates on GF180 ICG cells.""" +def test_c906_boots_smoke_payload_with_gf180_macros(tmp_path: Path) -> None: + """Boot the same payload with the C906 on GF180 SRAM macros + ICG cells.""" _run_c906_boot_tb(tmp_path, sram_macros="gf180") From 3d2f685a9a26888bb3205cdc4a3c431388b83725 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 15 Oct 2026 15:55:19 +0800 Subject: [PATCH 27/31] docs: record the GF180 SRAM macro path and its evidence Extend the chapter 3 memory-swap documentation to GF180: hp-platform.md adds the tiling table (8-bit macro stacking with registered read muxes), notes the repo-owned functional models versus the vendor collateral in the locked PDK, and documents the SKY130 byte-mask blocker as the reason that PDK stays behavioral; hp-rv64-validation.md records the directed-TB, MEM_INTF, boot-testbench, and SoC macro-sim evidence; the two READMEs generalize the override wording to IHP130/ICS55/GF180. Physical qualification (Liberty registration, STA, LEC) stays explicitly deferred. --- docs/hp-rv64-validation.md | 22 ++++++++++++++++++---- docs/ip/hp-platform.md | 26 ++++++++++++++++++++++++++ rtl/README.md | 5 +++-- scripts/README.md | 6 ++++-- 4 files changed, 51 insertions(+), 8 deletions(-) diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index 7208424a..30d11b90 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -134,6 +134,18 @@ qualification. Current evidence requires, at minimum: to Icarus) passes on the ICS55 path as well, and the `ics55.mk` CI profile smoke simulation (`APP=ci_smoke`, Verilator) passes with the macro path compiled into the SoC. +- The wrappers also have a GF180 macro path: under `PDK_GF180`+ + `HAVE_SRAM_MACRO` without `PDK_BEHAV` each wrapper is tiled from the GF180 + 8-bit bit-write macros `gf180mcu_fd_ip_sram__sram{64,128,256,512}x8m8wm1` + (identical active-low polarity; depth/width tiling with registered read + muxes where stacked). The vendor verilog views are timing-only, so the + simulation models are repo-owned in `rtl/tech/gf180_sram_sim_cells.sv`. + The directed eight-wrapper equivalence bench and the MEM_INTF suite both + pass on the GF180 path, and the focused boot testbench variant + `test_c906_boots_smoke_payload_with_gf180_macros` passes with the SRAM + tiles and the `icgtp_1` ICG active together. SKY130 stays behavioral: the + locked OpenRAM SRAM has only a byte-granular write mask while the wrappers + need per-bit write enable. - The chapter 3 ICG swap is validated in simulation on all four PDKs: the `gated_clk_cell.v`/`tdt_gated_clk_cell.v`/`BUFGCE.v` overrides select `sg13g2_slgcp_1` (IHP130), `ICGX1H7R` (ICS55, scan enable ORed into `E`), @@ -167,10 +179,12 @@ hp-smoke-sim` builds the whole SoC (C906 `aq_spsram_*` wrappers and `HP_GA2D_CACHE_CLEAN` markers; with the ICG overrides the same run also exercises the real `sg13g2_slgcp_1` clock gates. The same SoC smoke passes on the ICS55 macro+ICG path (`PDK=ICS55 PDK_BEHAV=NO`, 3.64M cycles, -`SIM_TEST_PASS code=0` with the full GA2D cache-lifecycle marker sequence), -and the `sky130.mk` and `gf180.mk` CI profile smokes (`APP=ci_smoke`, -Verilator) pass with the `sky130_fd_sc_hd__sdlclkp_1` / -`gf180mcu_fd_sc_mcu7t5v0__icgtp_1` ICG compiled in. The default 300 s +`SIM_TEST_PASS code=0` with the full GA2D cache-lifecycle marker sequence) +and on the GF180 macro+ICG path (`PDK=GF180 PDK_BEHAV=NO`, identical cycle +count), and the `sky130.mk` and `gf180.mk` CI profile smokes (`APP=ci_smoke`, +Verilator) pass with the SRAM tiles and the `sky130_fd_sc_hd__sdlclkp_1` / +`gf180mcu_fd_sc_mcu7t5v0__icgtp_1` ICG compiled in (the GF180 C906 SRAMs run +as macro tiles there too). The default 300 s `HP_SMOKE_SIM_TIME` is only enough when the run is uncontended, and the bare `ics55.mk` profile-default `sim` (no fast-flash) exceeds its 180 s default budget in this environment, so these were run with CI-sized time budgets. diff --git a/docs/ip/hp-platform.md b/docs/ip/hp-platform.md index f59f2755..4cd6e284 100644 --- a/docs/ip/hp-platform.md +++ b/docs/ip/hp-platform.md @@ -79,6 +79,32 @@ are active-low at identical widths), so the replacement is a direct connection with no inversion, padding, or stacking; `MARE`/`MAR` are tied off as in `tc_sram.sv`. +With `PDK_GF180` + `HAVE_SRAM_MACRO` and without `PDK_BEHAV`, each wrapper is +tiled from the GF180 8-bit bit-write macros +(`gf180mcu_fd_ip_sram__sram{64,128,256,512}x8m8wm1`; active-low +`CEN`/`GWEN`/per-bit `WEN` match the wrapper polarity). The vendor verilog +views are timing-only, so the simulation models are repo-owned in +`rtl/tech/gf180_sram_sim_cells.sv` (the 512x8 SoC model plus the +64/128/256x8 tiles): + +| Wrapper | Tile | Tiling | +| --- | --- | --- | +| `aq_spsram_1024x16` (BHT) | 512x8 | depth 2 (`A[9]`) x width 2 | +| `aq_spsram_2048x32` (ICache data) | 512x8 | depth 4 (`A[10:9]`) x width 4 | +| `aq_spsram_256x59` (ICache tag) | 256x8 | width 8; top tile's upper 5 bits tied inactive | +| `aq_spsram_1024x64` (DCache data) | 512x8 | depth 2 (`A[9]`) x width 8 | +| `aq_spsram_128x8` (DCache dirty) | 128x8 | exact, single tile | +| `aq_spsram_64x58` (DCache tag) | 64x8 | width 8; top tile's upper 6 bits tied inactive | +| `aq_spsram_64x88` (JTLB data) | 64x8 | width 11, exact | +| `aq_spsram_64x98` (JTLB tag) | 64x8 | width 13; top tile's upper 6 bits tied inactive | + +Depth stacks register the bank select on read transactions and mux the tile +outputs, like the IHP130 stacks. SKY130 stays on the behavioral path: the +locked OpenRAM SRAM (`sky130_sram_4kbyte_1rw_32x1024_8`) offers only a +byte-granular write mask (`wmask0[3:0]` per 32-bit word) while the C906 +wrappers require per-bit write enable, so no SKY130 SRAM macro can serve +them. + Every other configuration — including the committed `PDK_BEHAV=YES` CI profiles — compiles the upstream behavioral `aq_f_spsram_*` instance byte-identically. diff --git a/rtl/README.md b/rtl/README.md index 8ee06b5a..0ba89006 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -22,8 +22,9 @@ sources are an external lint boundary. The reviewed hart-ID, sysmap address-attribute, SRAM wrapper, and clock-gate (ICG) overrides live in `rtl/mini/ip_overrides/` (the `aq_spsram_*.v` overrides implement the integration manual chapter 3 -memory swap and select IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 -`ics55_ecos_sram_*` macros only under `PDK_IHP130`/`PDK_ICS55` + +memory swap and select IHP130 `RM_IHPSG13_1P_*`, exact-geometry ICS55 +`ics55_ecos_sram_*`, or tiled GF180 `gf180mcu_fd_ip_sram__sram*x8m8wm1` +macros only under `PDK_IHP130`/`PDK_ICS55`/`PDK_GF180` + `HAVE_SRAM_MACRO` without `PDK_BEHAV`; the `gated_clk_cell.v`, `tdt_gated_clk_cell.v`, and `BUFGCE.v` overrides implement the chapter 3 ICG swap and select the process clock-gating cell under a `PDK_*` define without diff --git a/scripts/README.md b/scripts/README.md index 08b23619..893b10bf 100644 --- a/scripts/README.md +++ b/scripts/README.md @@ -132,8 +132,10 @@ upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1 `aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, the eight `aq_spsram_*.v` SRAM wrappers whose PDK-selectable macro path — stacked -IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 `ics55_ecos_sram_*` — is -gated on `PDK_IHP130`/`PDK_ICS55`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, and +IHP130 `RM_IHPSG13_1P_*`, exact-geometry ICS55 `ics55_ecos_sram_*`, or tiled +GF180 `gf180mcu_fd_ip_sram__sram*x8m8wm1` — is +gated on `PDK_IHP130`/`PDK_ICS55`/`PDK_GF180`+`HAVE_SRAM_MACRO` without +`PDK_BEHAV`, and the `gated_clk_cell.v`/`tdt_gated_clk_cell.v`/`BUFGCE.v` clock-gate overrides that select the process ICG cell under a `PDK_*` define without `PDK_BEHAV`), each pinned to From 4497168950232ea9d7203a4670910c96109e263b Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 17 Oct 2026 03:46:32 +0800 Subject: [PATCH 28/31] docs: record the HP Linux write-channel wedge frontier and its evidence --- docs/hp-rv64-validation.md | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index 30d11b90..41b75c41 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -52,9 +52,35 @@ qualification. Current evidence requires, at minimum: SBI console: the earlier boot blocker is fixed (see the MAEE entry below). A longer bounded run (8 h wall) with the STIMECMP fix additionally boots the kernel through console init, BogoMIPS calibration, devtmpfs, and the - switch to the riscv_clocksource with a healthy periodic tick; userspace - acceptance (`HP_LINUX_READY`) evidence is collected on that run. The - target stays unqualified until that acceptance completes. + switch to the riscv_clocksource with a healthy periodic tick. The 12 h run + then probes the internal PLIC successfully at runtime (`riscv-plic: + interrupt-controller@8000000: mapped 31 interrupts`, validating the + OpenSBI `fdt_irqchip_init` hook) and completes the initramfs unpack + (`Unpacking initramfs...` / `Freeing initrd memory: 292K`). Userspace + acceptance (`HP_LINUX_READY`) is not yet reached: see the write-wedge + frontier entry below. The target stays unqualified until that acceptance + completes. +- The remaining boot frontier is a write-channel wedge, reproduced + deterministically by a bare-metal payload (dcache-dirty eviction traffic + interleaved with fenced MMIO polls wedges it at ~22 rounds in ~1.5 M HP + cycles) and by the kernel late in boot: the C906 issues a write AW whose W + data never leaves the core (zero W beats presented at the 128-bit port, the + LSU victim-buffer/store-buffer write-valids low, the BIU write buffers + empty), so the demux write FSM is parked in Active, the SDRAM core sits in + its write-data state waiting for the missing W stream, the concurrent read + fill's R never returns behind it, and the core freezes at the next fenced + MMIO poll (`retrosoc_hp_console_putc`). This is independent of the fence + instructions (the no-fence control payload wedges identically), of the + dcache write mode (write-back, write-through, and dcache-off all wedge), + and of the MAEE/cacheability work above. The hazard lives inside the + vendored C906's LSU write-data production under read/write concurrency + against a slow SDRAM partner; a guard write timeout does not cover the + source-stalled W stream, so the wedge is permanent. Root-causing it needs + C906 LSU debugging (store-buffer/victim-buffer data release) or an + interconnect that buffers a full write burst before engaging the SDRAM + command engine; both are out of this round's scope. An sdram_axi4-side + gate-the-command-on-full-burst prototype recovered the blocked read but + not the C906's withheld W, so it is not a fix and was not kept. - The Linux boot blocker was a doc/RTL mismatch in OpenC906, root-caused with bare-metal MMU payloads and locked by simulation evidence: the user manual states `mxstatus.MAEE` resets to 0, but the RTL (`aq_cp0_ext_csr.v`) resets From 59b6eca0950f3ae29239cb275fd689d00e26d543 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 17 Oct 2026 09:05:51 +0800 Subject: [PATCH 29/31] docs: pin the write wedge to the C906 LSU data-release with probe evidence --- docs/hp-rv64-validation.md | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index 41b75c41..a4a5542b 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -64,17 +64,20 @@ qualification. Current evidence requires, at minimum: deterministically by a bare-metal payload (dcache-dirty eviction traffic interleaved with fenced MMIO polls wedges it at ~22 rounds in ~1.5 M HP cycles) and by the kernel late in boot: the C906 issues a write AW whose W - data never leaves the core (zero W beats presented at the 128-bit port, the - LSU victim-buffer/store-buffer write-valids low, the BIU write buffers - empty), so the demux write FSM is parked in Active, the SDRAM core sits in - its write-data state waiting for the missing W stream, the concurrent read - fill's R never returns behind it, and the core freezes at the next fenced - MMIO poll (`retrosoc_hp_console_putc`). This is independent of the fence - instructions (the no-fence control payload wedges identically), of the - dcache write mode (write-back, write-through, and dcache-off all wedge), - and of the MAEE/cacheability work above. The hazard lives inside the - vendored C906's LSU write-data production under read/write concurrency - against a slow SDRAM partner; a guard write timeout does not cover the + data never leaves the core (zero W beats presented at the 128-bit port, and + at the stuck point the LSU store-buffer and victim-buffer write-valids and + the BIU write buffers are all empty, so the data vanished inside the core + after its AW was accepted), so the demux write FSM is parked in Active, the + SDRAM core sits in its write-data state waiting for the missing W stream, + the concurrent read fill's R never returns behind it, and the core freezes + at the next fenced MMIO poll (`retrosoc_hp_console_putc`). This is + independent of the fence instructions (the no-fence control payload wedges + identically), of the dcache write mode (write-back, write-through, and + dcache-off all wedge), and of the MAEE/cacheability work above. The + integration manual's write-channel contract (INCR only, len 1/4, 16 + outstanding with one per ID, no write interleave, bufferable responses) is + honored by our fabric; the violation is inside the core's LSU data release, + exposed by the slow-SDRAM window. A guard write timeout does not cover the source-stalled W stream, so the wedge is permanent. Root-causing it needs C906 LSU debugging (store-buffer/victim-buffer data release) or an interconnect that buffers a full write burst before engaging the SDRAM From 991ae606f9aefc8c1185e045739d74febb138248 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Wed, 21 Oct 2026 11:30:42 +0800 Subject: [PATCH 30/31] fix(hp): order OpenC906 write bursts behind their pad AW issue The vendored BIU streams a writeback's W data as soon as the victim buffer offers it (AXI-legal W-before-AW), while the AW still waits in awbuf for the serializing 128->64 downsizer to finish the previous write (the ~200-cycle SDRAM write response latency). The Mini HP fabric behind the pad is single-outstanding (downsizer + MMIO demux + target guard, no WID), so the early W beats are absorbed into the previous write's burst; each write's AW then arrives to find its W already consumed by the previous write's stream. The cascade persists until the LSU freezes (its fills block behind the SDRAM write channel, which is parked waiting for the orphaned write's W data), leaving a final orphaned AW whose W beats never come: the target guard parks in WriteStream, the SDRAM core parks in its write-data state and blocks the pending read fill, and the C906 stalls at the next LSU-serializing instruction. Event-level tracing pinned the mechanism: with the guard parked, the C906 write side is fully idle (victim buffer idle, store buffer idle, BIU write-selection FIFO empty, zero W beats presented at the 128-bit port for the wedged write) while the guard and the SDRAM controller both hold the orphaned write's AW. The rtl/mini/ip_overrides/aq_biu_write_channel.v override gates the W stream on the burst's AW having been issued on the pad (pad-issued-AW vs completed-W-burst order counters), restoring the AW-before-W order the fabric requires without touching the vendored checkout. The generator registers the override under the pinned sha256 guard, and the Makefile stamps it as a dependency. Evidence: the deterministic wedge payload and the no-fence control run unbounded (previously wedged at ~22 rounds); hp-smoke-sim and hp-rtthread-sim pass (SIM_TEST_PASS code=0); hp-linux-sim completes userspace acceptance (Run /init as init process, HP_LINUX_INIT_PASS, retroSoC HP Linux ready, HP_LINUX_READY, SIM_TEST_PASS code=0, 1.63 G emulator cycles, status: passed with no missing markers); pytest tests/test_hp_platform.py passes 20/20. docs/hp-rv64-validation.md records the mechanism and the acceptance. --- Makefile | 1 + docs/hp-rv64-validation.md | 68 +- rtl/mini/ip_overrides/aq_biu_write_channel.v | 842 +++++++++++++++++++ scripts/generate_openc906.py | 13 + 4 files changed, 896 insertions(+), 28 deletions(-) create mode 100644 rtl/mini/ip_overrides/aq_biu_write_channel.v diff --git a/Makefile b/Makefile index 15466355..21462830 100644 --- a/Makefile +++ b/Makefile @@ -1124,6 +1124,7 @@ npu-p5-lp-sim: firmware sim ifeq ($(HAVE_HP),YES) $(HP_GENERATED_STAMP): $(ROOT_PATH)/scripts/generate_openc906.py \ $(ROOT_PATH)/rtl/mini/ip_overrides/aq_sysio_kid.v \ + $(ROOT_PATH)/rtl/mini/ip_overrides/aq_biu_write_channel.v \ $(ROOT_PATH)/rtl/mini/ip_overrides/sysmap.h \ $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_1024x16.v \ $(ROOT_PATH)/rtl/mini/ip_overrides/aq_spsram_2048x32.v \ diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index a4a5542b..4eb1e5db 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -56,34 +56,46 @@ qualification. Current evidence requires, at minimum: then probes the internal PLIC successfully at runtime (`riscv-plic: interrupt-controller@8000000: mapped 31 interrupts`, validating the OpenSBI `fdt_irqchip_init` hook) and completes the initramfs unpack - (`Unpacking initramfs...` / `Freeing initrd memory: 292K`). Userspace - acceptance (`HP_LINUX_READY`) is not yet reached: see the write-wedge - frontier entry below. The target stays unqualified until that acceptance - completes. -- The remaining boot frontier is a write-channel wedge, reproduced - deterministically by a bare-metal payload (dcache-dirty eviction traffic - interleaved with fenced MMIO polls wedges it at ~22 rounds in ~1.5 M HP - cycles) and by the kernel late in boot: the C906 issues a write AW whose W - data never leaves the core (zero W beats presented at the 128-bit port, and - at the stuck point the LSU store-buffer and victim-buffer write-valids and - the BIU write buffers are all empty, so the data vanished inside the core - after its AW was accepted), so the demux write FSM is parked in Active, the - SDRAM core sits in its write-data state waiting for the missing W stream, - the concurrent read fill's R never returns behind it, and the core freezes - at the next fenced MMIO poll (`retrosoc_hp_console_putc`). This is - independent of the fence instructions (the no-fence control payload wedges - identically), of the dcache write mode (write-back, write-through, and - dcache-off all wedge), and of the MAEE/cacheability work above. The - integration manual's write-channel contract (INCR only, len 1/4, 16 - outstanding with one per ID, no write interleave, bufferable responses) is - honored by our fabric; the violation is inside the core's LSU data release, - exposed by the slow-SDRAM window. A guard write timeout does not cover the - source-stalled W stream, so the wedge is permanent. Root-causing it needs - C906 LSU debugging (store-buffer/victim-buffer data release) or an - interconnect that buffers a full write burst before engaging the SDRAM - command engine; both are out of this round's scope. An sdram_axi4-side - gate-the-command-on-full-burst prototype recovered the blocked read but - not the C906's withheld W, so it is not a fix and was not kept. + (`Unpacking initramfs...` / `Freeing initrd memory: 292K`). With the + write-channel fix below applied, the full `hp-linux-sim` run now reaches + userspace acceptance: `Run /init as init process`, busybox init, + `HP_LINUX_INIT_PASS`, `retroSoC HP Linux ready`, `HP_LINUX_READY`, and + `SIM_TEST_PASS code=0` (1.63 G emulator cycles in ~40.5 h wall; the result + checker reports `status: passed` with no missing markers). The wedge + payload and heartbeat probes below document the mechanism and the fix. +- The write-channel wedge is root-caused and fixed. Event-level tracing of + the C906 write channel showed the failure is a systematic AW/W misordering, + not data lost inside the LSU: the BIU streams a writeback's W beats to the + pad as soon as the victim buffer offers them, while the AW still waits in + `awbuf` for the serializing 128->64 downsizer to finish the previous write + (the ~200-cycle SDRAM write response latency). The early W beats are + AXI-legal (W-before-AW), but the Mini HP fabric behind the pad is + single-outstanding (downsizer + MMIO demux + target guard, no WID), so they + are absorbed into the previous write's burst; each write's AW then arrives + to find its W already consumed by the previous write's stream. The cascade + persists until the LSU freezes (its fills block behind the SDRAM write + channel, which is parked waiting for the orphaned write's W data), leaving + a final orphaned AW whose W beats never come: the target guard parks in + WriteStream, the SDRAM core parks in its write-data state and blocks the + pending read fill, and the C906 stalls at the next LSU-serializing + instruction (`retrosoc_hp_console_putc`). Evidence: with the guard parked, + the C906 write side is fully idle (victim buffer idle, store buffer idle, + BIU write-selection FIFO empty, and zero W beats ever presented at the + 128-bit port for the wedged write) while the guard and the SDRAM controller + both hold the orphaned write's AW. The fix is the + `rtl/mini/ip_overrides/aq_biu_write_channel.v` override, which gates the W + stream on the burst's AW having been issued on the pad (pad-issued-AW vs + completed-W-burst order counters), restoring the AW-before-W order the + fabric requires without touching the vendored checkout. Validated: the + deterministic wedge payload runs unbounded (previously wedged at ~22 + rounds/~1.83 M HP cycles, now clean past 10.5 M emulator cycles), the + no-fence control payload is clean, `hp-smoke-sim`/`hp-rtthread-sim` pass on + the committed IHP130 profile, and the full `hp-linux-sim` reaches + `HP_LINUX_READY` with `SIM_TEST_PASS code=0` (see the status entry above). + The earlier note that a guard write timeout cannot recover a source-stalled + W stream remains true and is a separate hardening gap (the guard's + read/write timeouts are gated by source readiness), not the wedge's cause; + it is out of this round's scope. - The Linux boot blocker was a doc/RTL mismatch in OpenC906, root-caused with bare-metal MMU payloads and locked by simulation evidence: the user manual states `mxstatus.MAEE` resets to 0, but the RTL (`aq_cp0_ext_csr.v`) resets diff --git a/rtl/mini/ip_overrides/aq_biu_write_channel.v b/rtl/mini/ip_overrides/aq_biu_write_channel.v new file mode 100644 index 00000000..2fb63232 --- /dev/null +++ b/rtl/mini/ip_overrides/aq_biu_write_channel.v @@ -0,0 +1,842 @@ +// retroSoC controlled override of the vendored OpenC906 aq_biu_write_channel.v. +// +// Source: openc906 dependency (dependencies.lock.json "openc906"), +// C906_RTL_FACTORY/gen_rtl/biu/rtl/aq_biu_write_channel.v +// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f +// License: Apache-2.0 (T-Head Semiconductor) +// +// retroSoC change (Mini HP fabric contract): upstream streams a write's W +// data as soon as the LSU offers it, even while the AW still waits in awbuf +// for a busy downstream slave (AXI-legal W-before-AW). The Mini HP fabric +// behind the pad is single-outstanding (serializing 128->64 downsizer + MMIO +// demux + target guard) and cannot attribute early W beats without a WID, so +// the early beats land in the prior write's burst, the queued AW is orphaned, +// and the write channel wedges. The override gates the W stream on the +// burst's AW having been issued on the pad (retro_aw_issued_q / +// retro_wburst_done_q below). Everything else is byte-identical to upstream. +// Keep in sync when the lock revision changes. + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &Depend("cpu_cfig.h"); @17 + +// &ModuleBeg; @19 +module aq_biu_write_channel( + ar_hit_wtable, + araddr, + arcache, + aw_hit_wtable, + awaddr, + awburst, + awcache, + awlen, + awlock, + awprot, + awready, + awsize, + awvalid, + axim_clk_en, + biu_clk, + biu_pad_awaddr, + biu_pad_awburst, + biu_pad_awcache, + biu_pad_awid, + biu_pad_awlen, + biu_pad_awlock, + biu_pad_awprot, + biu_pad_awsize, + biu_pad_awvalid, + biu_pad_bready, + biu_pad_wdata, + biu_pad_wlast, + biu_pad_wstrb, + biu_pad_wvalid, + cp0_biu_icg_en, + cpurst_b, + forever_cpuclk, + pad_biu_awready, + pad_biu_bid, + pad_biu_bresp, + pad_biu_bvalid, + pad_biu_wready, + pad_yy_icg_scan_en, + wdata, + wlast, + wready, + write_channel_clk_en, + wstrb, + wtable_no_op, + wvalid +); + +// &Ports; @20 +input [39 :0] araddr; +input [3 :0] arcache; +input [39 :0] awaddr; +input [1 :0] awburst; +input [3 :0] awcache; +input [1 :0] awlen; +input awlock; +input [2 :0] awprot; +input [2 :0] awsize; +input awvalid; +input axim_clk_en; +input biu_clk; +input cp0_biu_icg_en; +input cpurst_b; +input forever_cpuclk; +input pad_biu_awready; +input [7 :0] pad_biu_bid; +input [1 :0] pad_biu_bresp; +input pad_biu_bvalid; +input pad_biu_wready; +input pad_yy_icg_scan_en; +input [127:0] wdata; +input wlast; +input [15 :0] wstrb; +input wvalid; +output ar_hit_wtable; +output aw_hit_wtable; +output awready; +output [39 :0] biu_pad_awaddr; +output [1 :0] biu_pad_awburst; +output [3 :0] biu_pad_awcache; +output [7 :0] biu_pad_awid; +output [7 :0] biu_pad_awlen; +output biu_pad_awlock; +output [2 :0] biu_pad_awprot; +output [2 :0] biu_pad_awsize; +output biu_pad_awvalid; +output biu_pad_bready; +output [127:0] biu_pad_wdata; +output biu_pad_wlast; +output [15 :0] biu_pad_wstrb; +output biu_pad_wvalid; +output wready; +output write_channel_clk_en; +output wtable_no_op; + +// &Regs; @21 +reg awbuf_vld; +reg bbuf_vld; +reg [3 :0] bid; +reg [39 :0] biu_pad_awaddr; +reg [1 :0] biu_pad_awburst; +reg [3 :0] biu_pad_awcache; +reg [7 :0] biu_pad_awid; +reg [7 :0] biu_pad_awlen; +reg biu_pad_awlock; +reg [2 :0] biu_pad_awprot; +reg [2 :0] biu_pad_awsize; +reg [127:0] biu_pad_wdata; +reg biu_pad_wlast; +reg [15 :0] biu_pad_wstrb; +reg wbuf_vld; +reg [3 :0] wtable_create_ptr; +// retroSoC override: pad-order counters for the write W-after-AW gate. +reg [3 :0] retro_aw_issued_q; +reg [3 :0] retro_wburst_done_q; + +// &Wires; @22 +wire ar_hit_wtable; +wire [15 :0] ar_hit_wtable_addr; +wire [15 :0] ar_hit_wtable_so; +wire [39 :0] araddr; +wire [3 :0] arcache; +wire aw_hit_wtable; +wire [15 :0] aw_hit_wtable_addr; +wire [15 :0] aw_hit_wtable_so; +wire [39 :0] awaddr; +wire awbuf_create_en; +wire awbuf_pop_en; +wire [1 :0] awburst; +wire [3 :0] awcache; +wire awclk; +wire [1 :0] awlen; +wire awlock; +wire [2 :0] awprot; +wire awready; +wire [2 :0] awsize; +wire awvalid; +wire axim_clk_en; +wire bbuf_create_en; +wire bbuf_pop_en; +wire biu_clk; +wire biu_pad_awvalid; +wire biu_pad_bready; +wire biu_pad_wvalid; +wire cp0_biu_icg_en; +wire cpurst_b; +wire forever_cpuclk; +wire pad_biu_awready; +wire [7 :0] pad_biu_bid; +wire pad_biu_bvalid; +wire pad_biu_wready; +wire pad_yy_icg_scan_en; +wire wbuf_create_en; +wire wbuf_pop_en; +wire wclk; +wire [127:0] wdata; +wire wlast; +wire wready; +wire retro_w_ordered; +wire retro_w_burst_end; +wire write_channel_clk_en; +wire [15 :0] wstrb; +wire [9 :0] wtable_create_addr; +wire wtable_create_burst; +wire [15 :0] wtable_create_en; +wire [15 :0] wtable_create_sel; +wire wtable_create_so; +wire [15 :0] wtable_entry_vld; +wire wtable_full; +wire wtable_no_op; +wire [15 :0] wtable_pop_en; +wire wvalid; + + +parameter PADDR = 40; +parameter DEPTH = 16; + +//========================================================== +// address and so check +//========================================================== + +assign ar_hit_wtable = (|ar_hit_wtable_addr[DEPTH-1:0]) | + (|ar_hit_wtable_so[DEPTH-1:0]); + +assign aw_hit_wtable = (|aw_hit_wtable_addr[DEPTH-1:0]) | + (|aw_hit_wtable_so[DEPTH-1:0]); + +//============================================================================== +// AW channel +//============================================================================== +// &Force("bus","awid",3,0); @40 +// &Force("output","awready"); @41 + +assign awready = (!awbuf_vld | pad_biu_awready) & !wtable_full & axim_clk_en; + +assign awbuf_create_en = awvalid & awready; +assign awbuf_pop_en = awbuf_vld & pad_biu_awready & axim_clk_en; + +always @(posedge biu_clk or negedge cpurst_b) +begin + if (!cpurst_b) + awbuf_vld <= 1'b0; + else if (axim_clk_en) begin + if (awbuf_create_en) + awbuf_vld <= 1'b1; + else if (awbuf_pop_en) + awbuf_vld <= 1'b0; + else + awbuf_vld <= awbuf_vld; + end +end + +assign biu_pad_awvalid = awbuf_vld; + +always @(posedge awclk or negedge cpurst_b) +begin + if (!cpurst_b)begin + biu_pad_awaddr[PADDR-1:0] <= {PADDR{1'b0}}; + biu_pad_awsize[2:0] <= 3'b0; + biu_pad_awlen[7:0] <= 8'b0; + biu_pad_awburst[1:0] <= 2'b0; + biu_pad_awcache[3:0] <= 4'b0; + biu_pad_awprot[2:0] <= 3'b0; + biu_pad_awlock <= 1'b0; + biu_pad_awid[7:0] <= 8'b0; + + end + else if (awbuf_create_en & axim_clk_en) begin + biu_pad_awaddr[PADDR-1:0] <= awaddr[PADDR-1:0]; + biu_pad_awsize[2:0] <= awsize[2:0]; + biu_pad_awlen[7:0] <= {6'b0, awlen[1:0]}; + biu_pad_awburst[1:0] <= awburst[1:0]; + biu_pad_awcache[3:0] <= awcache[3:0]; + biu_pad_awprot[2:0] <= awprot[2:0]; + biu_pad_awlock <= awlock; + biu_pad_awid[7:0] <= {4'b0,wtable_create_ptr[3:0]}; + end +end + + +//============================================================================== +// W channel +//============================================================================== +// retroSoC override: hold a write burst's W data until its AW has been issued +// on the pad. The vendored BIU streams W as soon as the LSU offers it while +// the AW can still wait in awbuf for a busy downstream slave; on a +// single-outstanding fabric the early W beats are absorbed into the prior +// write's burst, orphaning this write's AW downstream and wedging the write +// channel. Count pad-issued AWs against completed W bursts: a W burst may +// stream only once its AW is out. In-order AW/W keeps the wrapped comparison +// exact (the counters never drift apart by more than the wsel depth). +assign retro_w_ordered = (retro_aw_issued_q != retro_wburst_done_q); +assign retro_w_burst_end = wvalid & wready & wlast; + +always @(posedge biu_clk or negedge cpurst_b) +begin + if (!cpurst_b) begin + retro_aw_issued_q <= 4'b0; + retro_wburst_done_q <= 4'b0; + end + else if (axim_clk_en) begin + if (awbuf_pop_en) + retro_aw_issued_q <= retro_aw_issued_q + 4'b1; + if (retro_w_burst_end) + retro_wburst_done_q <= retro_wburst_done_q + 4'b1; + end +end + +assign wready = (!wbuf_vld | pad_biu_wready) & axim_clk_en & retro_w_ordered; + +assign wbuf_create_en = wvalid & (!wbuf_vld | pad_biu_wready) & retro_w_ordered; +assign wbuf_pop_en = wbuf_vld & pad_biu_wready & axim_clk_en; + +always @(posedge biu_clk or negedge cpurst_b) +begin + if (!cpurst_b) + wbuf_vld <= 1'b0; + else if (axim_clk_en) begin + if (wbuf_create_en) + wbuf_vld <= 1'b1; + else if (wbuf_pop_en) + wbuf_vld <= 1'b0; + else + wbuf_vld <= wbuf_vld; + end +end + +assign biu_pad_wvalid = wbuf_vld; + +always @(posedge wclk or negedge cpurst_b) +begin + if (!cpurst_b) begin + biu_pad_wstrb[15:0] <= 16'b0; + biu_pad_wdata[127:0] <= 128'b0; + biu_pad_wlast <= 1'b0; + end + else if (wbuf_create_en & axim_clk_en) begin + biu_pad_wstrb[15:0] <= wstrb[15:0]; + biu_pad_wdata[127:0] <= wdata[127:0]; + biu_pad_wlast <= wlast; + end +end + +//============================================================================== +// B channel +//============================================================================== +// &Force("bus", "pad_biu_bid",7,0); @131 +// &Force("input","pad_biu_bresp"); @132 +// &Force("bus","pad_biu_bresp",1,0); @133 + +assign biu_pad_bready = 1'b1; + +assign bbuf_create_en = axim_clk_en & pad_biu_bvalid; +assign bbuf_pop_en = bbuf_vld; + +always @(posedge biu_clk or negedge cpurst_b) +begin + if (!cpurst_b) + bbuf_vld <= 1'b0; + else if (bbuf_create_en) + bbuf_vld <= 1'b1; + else if (bbuf_pop_en) + bbuf_vld <= 1'b0; +end + +always @(posedge biu_clk or negedge cpurst_b) +begin + if (!cpurst_b) + bid[3:0] <= 4'b0; + else if (bbuf_create_en) + bid[3:0] <= pad_biu_bid[3:0]; +end + +assign wtable_pop_en[DEPTH-1:0] = (16'b1 << bid[3:0]) & {DEPTH{bbuf_vld}}; + +//============================================================================== +// write table +//============================================================================== + +always @(posedge awclk or negedge cpurst_b) +begin + if (!cpurst_b) + wtable_create_ptr[3:0] <= 4'b0; + else if (awbuf_create_en) + wtable_create_ptr[3:0] <= wtable_create_ptr[3:0] + 4'b1; +end + +assign wtable_full = wtable_entry_vld[wtable_create_ptr[3:0]]; + +assign wtable_create_sel[DEPTH-1:0] = 16'b1 << wtable_create_ptr[3:0] ; +assign wtable_create_en[DEPTH-1:0] = wtable_create_sel[DEPTH-1:0] & {16{awbuf_create_en}}; +assign wtable_create_addr[9:0] = awaddr[13:4]; +assign wtable_create_so = !awcache[1]; +assign wtable_create_burst = awlen[1:0] == 2'b11; +//no_op +assign wtable_no_op = ~(|wtable_entry_vld[DEPTH-1:0]); + +//============================================================================== +// ICG +//============================================================================== +assign write_channel_clk_en = bbuf_create_en | bbuf_pop_en | + wbuf_create_en | wbuf_pop_en | + awbuf_create_en | awbuf_pop_en; + +// &Instance("gated_clk_cell", "x_aq_biu_aw_gated_clk"); @189 +gated_clk_cell x_aq_biu_aw_gated_clk ( + .clk_in (forever_cpuclk ), + .clk_out (awclk ), + .external_en (1'b0 ), + .global_en (1'b1 ), + .local_en (awbuf_create_en ), + .module_en (cp0_biu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect(.clk_in (forever_cpuclk), @190 +// .external_en (1'b0), @191 +// .global_en (1'b1), @192 +// .module_en (cp0_biu_icg_en), @193 +// .local_en (awbuf_create_en), @194 +// .clk_out (awclk)); @195 + +// &Instance("gated_clk_cell", "x_aq_biu_w_gated_clk"); @197 +gated_clk_cell x_aq_biu_w_gated_clk ( + .clk_in (forever_cpuclk ), + .clk_out (wclk ), + .external_en (1'b0 ), + .global_en (1'b1 ), + .local_en (wbuf_create_en ), + .module_en (cp0_biu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect(.clk_in (forever_cpuclk), @198 +// .external_en (1'b0), @199 +// .global_en (1'b1), @200 +// .module_en (cp0_biu_icg_en), @201 +// .local_en (wbuf_create_en), @202 +// .clk_out (wclk)); @203 +//============================================================================== +// write table Instance +//============================================================================== +// &ConnRule(s/_x$/[0]/); @207 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_0"); @208 +aq_biu_wt_entry x_aq_biu_wt_entry_0 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[0]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[0] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[0]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[0] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[0] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[0] ), + .wtable_pop_en_x (wtable_pop_en[0] ) +); + + +// &ConnRule(s/_x$/[1]/); @210 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_1"); @211 +aq_biu_wt_entry x_aq_biu_wt_entry_1 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[1]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[1] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[1]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[1] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[1] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[1] ), + .wtable_pop_en_x (wtable_pop_en[1] ) +); + + +// &ConnRule(s/_x$/[2]/); @213 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_2"); @214 +aq_biu_wt_entry x_aq_biu_wt_entry_2 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[2]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[2] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[2]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[2] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[2] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[2] ), + .wtable_pop_en_x (wtable_pop_en[2] ) +); + + +// &ConnRule(s/_x$/[3]/); @216 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_3"); @217 +aq_biu_wt_entry x_aq_biu_wt_entry_3 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[3]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[3] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[3]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[3] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[3] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[3] ), + .wtable_pop_en_x (wtable_pop_en[3] ) +); + + +// &ConnRule(s/_x$/[4]/); @219 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_4"); @220 +aq_biu_wt_entry x_aq_biu_wt_entry_4 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[4]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[4] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[4]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[4] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[4] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[4] ), + .wtable_pop_en_x (wtable_pop_en[4] ) +); + + +// &ConnRule(s/_x$/[5]/); @222 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_5"); @223 +aq_biu_wt_entry x_aq_biu_wt_entry_5 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[5]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[5] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[5]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[5] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[5] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[5] ), + .wtable_pop_en_x (wtable_pop_en[5] ) +); + + +// &ConnRule(s/_x$/[6]/); @225 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_6"); @226 +aq_biu_wt_entry x_aq_biu_wt_entry_6 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[6]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[6] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[6]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[6] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[6] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[6] ), + .wtable_pop_en_x (wtable_pop_en[6] ) +); + + +// &ConnRule(s/_x$/[7]/); @228 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_7"); @229 +aq_biu_wt_entry x_aq_biu_wt_entry_7 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[7]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[7] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[7]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[7] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[7] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[7] ), + .wtable_pop_en_x (wtable_pop_en[7] ) +); + + +// &ConnRule(s/_x$/[8]/); @231 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_8"); @232 +aq_biu_wt_entry x_aq_biu_wt_entry_8 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[8]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[8] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[8]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[8] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[8] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[8] ), + .wtable_pop_en_x (wtable_pop_en[8] ) +); + + +// &ConnRule(s/_x$/[9]/); @234 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_9"); @235 +aq_biu_wt_entry x_aq_biu_wt_entry_9 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[9]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[9] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[9]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[9] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[9] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[9] ), + .wtable_pop_en_x (wtable_pop_en[9] ) +); + + +// &ConnRule(s/_x$/[10]/); @237 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_10"); @238 +aq_biu_wt_entry x_aq_biu_wt_entry_10 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[10]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[10] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[10]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[10] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[10] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[10] ), + .wtable_pop_en_x (wtable_pop_en[10] ) +); + + +// &ConnRule(s/_x$/[11]/); @240 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_11"); @241 +aq_biu_wt_entry x_aq_biu_wt_entry_11 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[11]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[11] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[11]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[11] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[11] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[11] ), + .wtable_pop_en_x (wtable_pop_en[11] ) +); + + +// &ConnRule(s/_x$/[12]/); @243 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_12"); @244 +aq_biu_wt_entry x_aq_biu_wt_entry_12 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[12]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[12] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[12]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[12] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[12] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[12] ), + .wtable_pop_en_x (wtable_pop_en[12] ) +); + + +// &ConnRule(s/_x$/[13]/); @246 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_13"); @247 +aq_biu_wt_entry x_aq_biu_wt_entry_13 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[13]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[13] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[13]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[13] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[13] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[13] ), + .wtable_pop_en_x (wtable_pop_en[13] ) +); + + +// &ConnRule(s/_x$/[14]/); @249 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_14"); @250 +aq_biu_wt_entry x_aq_biu_wt_entry_14 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[14]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[14] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[14]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[14] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[14] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[14] ), + .wtable_pop_en_x (wtable_pop_en[14] ) +); + + +// &ConnRule(s/_x$/[15]/); @252 +// &Instance("aq_biu_wt_entry","x_aq_biu_wt_entry_15"); @253 +aq_biu_wt_entry x_aq_biu_wt_entry_15 ( + .ar_hit_wtable_addr_x (ar_hit_wtable_addr[15]), + .ar_hit_wtable_so_x (ar_hit_wtable_so[15] ), + .araddr (araddr ), + .arcache (arcache ), + .aw_hit_wtable_addr_x (aw_hit_wtable_addr[15]), + .aw_hit_wtable_so_x (aw_hit_wtable_so[15] ), + .awaddr (awaddr ), + .awcache (awcache ), + .awlen (awlen ), + .cp0_biu_icg_en (cp0_biu_icg_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .wtable_create_addr (wtable_create_addr ), + .wtable_create_burst (wtable_create_burst ), + .wtable_create_en_x (wtable_create_en[15] ), + .wtable_create_so (wtable_create_so ), + .wtable_entry_vld_x (wtable_entry_vld[15] ), + .wtable_pop_en_x (wtable_pop_en[15] ) +); + + +// &ModuleEnd; @255 +endmodule + + diff --git a/scripts/generate_openc906.py b/scripts/generate_openc906.py index 87736308..aa8b4306 100644 --- a/scripts/generate_openc906.py +++ b/scripts/generate_openc906.py @@ -10,6 +10,15 @@ for their vendored counterparts: - ``aq_sysio_kid.v``: upstream hardwires mhartid to 0; the Mini LP/HP contract requires the HP core to report hart 1. +- ``aq_biu_write_channel.v``: the vendored BIU streams a write's W data as + soon as the LSU offers it, even while the AW still waits in ``awbuf`` for a + busy downstream slave (AXI-legal W-before-AW). The Mini HP fabric behind the + pad is single-outstanding (serializing 128->64 downsizer + MMIO demux + + target guard) and cannot attribute early W beats without a WID, so the + beats land in the prior write's burst, the queued AW is orphaned, and the + channel wedges (observed as a permanent guard WriteStream stall with the + SDRAM controller parked waiting for write data). The override gates the W + stream on the burst's AW having been issued on the pad. - ``sysmap.h``: the upstream default region table marks the Mini peripheral window cacheable/bufferable; the override maps the Mini address map with the MMIO window (including the core-internal CLINT/PLIC window) as @@ -64,6 +73,10 @@ OVERRIDES = { "sysmap.h", "0389089a42ef762768e57bbb4fdcbe6b95f33ab650b5bacc0de8122e0d8711d5", ), + "C906_RTL_FACTORY/gen_rtl/biu/rtl/aq_biu_write_channel.v": ( + "aq_biu_write_channel.v", + "7d98d231287f4a8807593990411d96879deb68cfda764c2fb92bc93c2b10e204", + ), "C906_RTL_FACTORY/gen_rtl/ifu/rtl/aq_spsram_1024x16.v": ( "aq_spsram_1024x16.v", "8969cdfd73933ff4ca105d562e31283e16433f90e4ceaa4339759e6df7ba34d9", From 4ef4b1d4e41689dfb070389b60f265606c05f793 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Fri, 23 Oct 2026 07:27:19 +0800 Subject: [PATCH 31/31] fix(dv): hold Verilator UART1 RX idle instead of looping TX back The Verilator testbench tied the HP console UART1 RX pin directly to its TX pin, so every byte the C906 transmitted looped back into the UART1 RX FIFO. The Linux kernel's hvc console (hvc0) is a TTY with ECHO enabled; its __hvc_poll thread reads the looped-back bytes and the N_TTY line discipline re-emits them. The result is a feedback loop that re-prints the console output repeatedly with progressive character loss (the OpenSBI banner appearing four times, degrading into truncated fragments and thousands of blank lines in the boot log). Hold the RX pin idle (no external input) so console_getc always reports no input and the echo loop never starts. uart0 (the LP console) is unconnected on both pins and was already unaffected. Evidence: hp-linux-sim on configs/ci/ihp130-hp.mk (Verilator) now shows the OpenSBI banner exactly once with no blank-line artifacts, and still completes userspace acceptance (HP_LINUX_INIT_PASS, retroSoC HP Linux ready, HP_LINUX_READY, SIM_TEST_PASS code=0; 1.56 G emulator cycles, status: passed with no missing markers). --- rtl/mini/dv/verilator/rtl/retrosoc_top.sv | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/rtl/mini/dv/verilator/rtl/retrosoc_top.sv b/rtl/mini/dv/verilator/rtl/retrosoc_top.sv index 40bb28ac..5fac9646 100644 --- a/rtl/mini/dv/verilator/rtl/retrosoc_top.sv +++ b/rtl/mini/dv/verilator/rtl/retrosoc_top.sv @@ -103,7 +103,12 @@ module retrosoc_top ( assign s_jtag_tms = jtag_tms_i; assign s_jtag_tdi = jtag_tdi_i; assign s_jtag_trst_n = jtag_trst_n_i; - assign s_uart1_rx = s_uart1_tx; + // The UART1 RX pin is held idle (no external input). Looping TX back to RX + // here fed the HP console output into the kernel's hvc TTY, whose ECHO + // re-emitted it repeatedly with progressive character loss (degraded banner + // fragments and blank lines in the boot log), so it is intentionally left + // unconnected. + assign s_uart1_rx = 1'b1; assign jtag_tdo_o = s_jtag_tdo; assign test_done_o = u_retrosoc_asic.s_test_done; assign test_pass_o = u_retrosoc_asic.s_test_pass;