diff --git a/docs/hp-rv64-validation.md b/docs/hp-rv64-validation.md index b32384ee..7208424a 100644 --- a/docs/hp-rv64-validation.md +++ b/docs/hp-rv64-validation.md @@ -134,6 +134,23 @@ qualification. Current evidence requires, at minimum: to Icarus) passes on the ICS55 path as well, and the `ics55.mk` CI profile smoke simulation (`APP=ci_smoke`, Verilator) passes with the macro path compiled into the SoC. +- The chapter 3 ICG swap is validated in simulation on all four PDKs: the + `gated_clk_cell.v`/`tdt_gated_clk_cell.v`/`BUFGCE.v` overrides select + `sg13g2_slgcp_1` (IHP130), `ICGX1H7R` (ICS55, scan enable ORed into `E`), + `sky130_fd_sc_hd__sdlclkp_1` (SKY130), or + `gf180mcu_fd_sc_mcu7t5v0__icgtp_1` (GF180; repo-owned sim model in + `rtl/tech/gf180_seq_sim_cells.v` because the locked checkout never ships + the vendor latch UDP the cell model references) under a `PDK_*` define + without `PDK_BEHAV`. The vendored MEM_INTF `c906_icg_test_tb` gate sequence + passes on all four cell paths (Icarus adaptation; the pass-through default + fails it by design since it never gates). The focused boot testbench passes + with real clock gating for all four PDKs — the IHP130/ICS55 modes run SRAM + macros and ICG together, the SKY130/GF180 modes run ICG with behavioral + SRAMs. One integration fix was required for two-state simulators: + `hp_core_wrapper` asserts the C906/DTM ICG scan-enable while the core is + held in reset, so flops behind closed gates initialize on running-clock + edges (the DTM sleeps at boot and otherwise holds `hartreset_n` low); + pass-through modes ignore the scan-enable input and stay bit-identical. `hp-linux-sim` was run with a bounded wall-clock budget this round and its current frontier is recorded above; the synthesis-dependent gates remain @@ -147,17 +164,20 @@ evidence: `make CONFIG=configs/ci/ihp130-hp.mk PDK_BEHAV=NO SIMU=VERILATOR hp-smoke-sim` builds the whole SoC (C906 `aq_spsram_*` wrappers and `tc_sram`) on the IHP130 macro models and passes with `SIM_TEST_PASS code=0` plus the `HP_LINUX_READY`/`HP_GA2D_PASS`/ -`HP_GA2D_CACHE_CLEAN` markers. The same SoC smoke passes on the ICS55 macro -path (`PDK=ICS55 PDK_BEHAV=NO`, 3.64M cycles, `SIM_TEST_PASS code=0` with the -full GA2D cache-lifecycle marker sequence); the default 300 s +`HP_GA2D_CACHE_CLEAN` markers; with the ICG overrides the same run also +exercises the real `sg13g2_slgcp_1` clock gates. The same SoC smoke passes on +the ICS55 macro+ICG path (`PDK=ICS55 PDK_BEHAV=NO`, 3.64M cycles, +`SIM_TEST_PASS code=0` with the full GA2D cache-lifecycle marker sequence), +and the `sky130.mk` and `gf180.mk` CI profile smokes (`APP=ci_smoke`, +Verilator) pass with the `sky130_fd_sc_hd__sdlclkp_1` / +`gf180mcu_fd_sc_mcu7t5v0__icgtp_1` ICG compiled in. The default 300 s `HP_SMOKE_SIM_TIME` is only enough when the run is uncontended, and the bare `ics55.mk` profile-default `sim` (no fast-flash) exceeds its 180 s default -budget in this environment, so both were run with the CI-sized time budgets. +budget in this environment, so these were run with CI-sized time budgets. All stay required evidence for qualification. Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT -(scan/mbist tied off), the debug SBA AXI master (unconnected), the chapter 3 -ICG (`gated_clk_cell`) replacement, and HP Linux +(scan/mbist tied off), the debug SBA AXI master (unconnected), and HP Linux re-qualification timing/performance evidence. The repo-owned OpenSBI platform registers `fdt_irqchip_init` (v1.9 supports the `thead,c900-plic` match with T-Head delegation fixups), so the C906-internal PLIC is initialized by diff --git a/docs/ip/hp-platform.md b/docs/ip/hp-platform.md index 9439fa27..f59f2755 100644 --- a/docs/ip/hp-platform.md +++ b/docs/ip/hp-platform.md @@ -82,10 +82,38 @@ off as in `tc_sram.sv`. Every other configuration — including the committed `PDK_BEHAV=YES` CI profiles — compiles the upstream behavioral `aq_f_spsram_*` instance byte-identically. + +The chapter 3 ICG swap is implemented alongside: `gated_clk_cell.v` (the 216 +CPU clock gates), `tdt_gated_clk_cell.v` (the debug module gate), and +`BUFGCE.v` (the PLIC/CLINT divide-by-2 gate in `aq_mp_clk_top.v`) have +reviewed overrides in `rtl/mini/ip_overrides/`. With a PDK define and without +`PDK_BEHAV` — no `HAVE_SRAM_MACRO` knob, the ICG is a base cell — each +override instantiates the process clock-gating cell: + +| PDK | ICG cell | Enable/scan mapping | +| --- | --- | --- | +| IHP130 | `sg13g2_slgcp_1` | `GATE`=enable, `SCE`=scan enable | +| ICS55 | `ICGX1H7R` | no test-enable pin: scan enable ORed into `E` | +| SKY130 | `sky130_fd_sc_hd__sdlclkp_1` | `GATE`=enable, `SCE`=scan enable | +| GF180 | `gf180mcu_fd_sc_mcu7t5v0__icgtp_1` | `E`=enable, `TE`=scan enable | + +`BUFGCE` has no scan enable upstream, so SCE/TE tie off there. The GF180 +vendor model cannot elaborate (its UDP latch primitive is not shipped in the +locked checkout), so its simulation model is repo-owned in +`rtl/tech/gf180_seq_sim_cells.v`, following the existing `dffq` precedent. +Because two-state simulators only apply an async-reset flop's reset value on +a real reset edge, `hp_core_wrapper` asserts `pad_yy_icg_scan_en`/ +`pad_tdt_icg_scan_en` while the core/DTM is held in reset, keeping the gated +clocks transparent so flops behind closed gates initialize (the DTM sleeps at +boot and would otherwise hold `hartreset_n` low forever). `PDK_BEHAV` and +PDK-less builds keep the upstream defaults byte-identical (pass-through for +the two `*_gated_clk_cell`, the behavioral latch gate for `BUFGCE`), and +pass-through ignores the scan-enable input entirely. Deferred this phase: low-power support (`core0_pad_lpmd_b` unconnected), DFT (scan/mbist tied off), the debug SBA AXI -master (unconnected), the chapter 3 ICG (`gated_clk_cell`) replacement, -physical/LEC qualification of the macro path (synthesis mapping, STA), and +master (unconnected), +physical/LEC qualification of the macro and ICG paths (synthesis mapping, +STA), and HP Linux re-qualification timing/performance evidence. ### Boot bundle V2 diff --git a/rtl/README.md b/rtl/README.md index e8921ca7..8ee06b5a 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -19,11 +19,15 @@ SYSCTRL lifecycle signals. `make setup-openc906` (part of `make setup`) restores the locked checkout and `make openc906-prepare` emits the generated filelist and manifest below `build//generated/openc906/`; the OpenC906 sources are an external lint boundary. The reviewed hart-ID, sysmap -address-attribute, and SRAM wrapper overrides live in `rtl/mini/ip_overrides/` +address-attribute, SRAM wrapper, and clock-gate (ICG) overrides live in +`rtl/mini/ip_overrides/` (the `aq_spsram_*.v` overrides implement the integration manual chapter 3 memory swap and select IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 `ics55_ecos_sram_*` macros only under `PDK_IHP130`/`PDK_ICS55` + -`HAVE_SRAM_MACRO` without `PDK_BEHAV`) and are applied +`HAVE_SRAM_MACRO` without `PDK_BEHAV`; the `gated_clk_cell.v`, +`tdt_gated_clk_cell.v`, and `BUFGCE.v` overrides implement the chapter 3 ICG +swap and select the process clock-gating cell under a `PDK_*` define without +`PDK_BEHAV`) and are applied by filelist generation, never by editing the vendored checkout. The former VexiiRiscv HP generator is preserved only as the frozen Std-series asset (`make std-vexii-generate`). See diff --git a/scripts/README.md b/scripts/README.md index 6fb63e30..08b23619 100644 --- a/scripts/README.md +++ b/scripts/README.md @@ -130,10 +130,12 @@ source used by Mini product profiles and verifies the checked-out revision; the vendored checkout is never modified. `generate_openc906.py` resolves the upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1 -`aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, and the eight +`aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, the eight `aq_spsram_*.v` SRAM wrappers whose PDK-selectable macro path — stacked IHP130 `RM_IHPSG13_1P_*` or exact-geometry ICS55 `ics55_ecos_sram_*` — is -gated on `PDK_IHP130`/`PDK_ICS55`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, +gated on `PDK_IHP130`/`PDK_ICS55`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, and +the `gated_clk_cell.v`/`tdt_gated_clk_cell.v`/`BUFGCE.v` clock-gate overrides +that select the process ICG cell under a `PDK_*` define without `PDK_BEHAV`), each pinned to the upstream file's SHA-256 so a locked-revision move forces review), and emits the single compilation unit `openc906_combined.v` below `build/`;