From 7418acfe4219bb2760fd05aac8813cf08a33df34 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Tue, 21 Jul 2026 11:21:39 +0800 Subject: [PATCH] refactor: refactor Makefiles and related scripts for improved readability and consistency - Adjusted variable alignment in Makefiles for better readability. - Ensured consistent formatting across various Makefiles and scripts. - Added a new .bake.toml file to define project formatting policies for mbake. - Updated paths and variable definitions in multiple configuration files to enhance clarity. - Removed unnecessary comments and whitespace for cleaner code. --- .bake.toml | 5 ++ Makefile | 80 +++++++++++------------ app/apps/shell/app.mk | 2 +- app/asm/Makefile | 16 ++--- app/benchmark/coremark/coremark.mk | 2 +- app/middleware/fatfs/fatfs.mk | 2 +- app/network/userip/userip.mk | 4 +- app/ports/lvgl/lvgl.mk | 2 +- configs/ci/hazard3-rv32im-ihp130-shell.mk | 22 +++---- configs/ci/hazard3-rv32im-ihp130.mk | 22 +++---- configs/ci/mdd-rv32im-ihp130.mk | 22 +++---- configs/cluster/hazard3-ics55.mk | 22 +++---- configs/nightly/picorv32-rv32im-ihp130.mk | 22 +++---- rtl/mini/Makefile | 58 ++++++++-------- rtl/mini/mk/iverilog.mk | 40 ++++++------ rtl/mini/mk/software.mk | 26 ++++---- rtl/mini/mk/vcs.mk | 41 ++++++------ rtl/mini/mk/verilator.mk | 18 +++-- sta/opensta/opensta.mk | 24 +++---- syn/yosys/synth_config.mk | 6 +- syn/yosys/yosys.mk | 16 ++--- 21 files changed, 227 insertions(+), 225 deletions(-) create mode 100644 .bake.toml diff --git a/.bake.toml b/.bake.toml new file mode 100644 index 00000000..dc012e66 --- /dev/null +++ b/.bake.toml @@ -0,0 +1,5 @@ +# Project formatting policy for mbake. +[formatter] +# Align adjacent assignments, but start a new alignment group at comments. +align_variable_assignments = true +align_across_comments = false diff --git a/Makefile b/Makefile index 8d3d6027..ee85cd47 100644 --- a/Makefile +++ b/Makefile @@ -2,9 +2,9 @@ SHELL := /bin/bash .DEFAULT_GOAL := help .DELETE_ON_ERROR: -ROOT_PATH ?= $(abspath $(dir $(firstword $(MAKEFILE_LIST)))) -CONFIG ?= -LOCK_FILE ?= $(ROOT_PATH)/config/dependencies.lock.json +ROOT_PATH ?= $(abspath $(dir $(firstword $(MAKEFILE_LIST)))) +CONFIG ?= +LOCK_FILE ?= $(ROOT_PATH)/config/dependencies.lock.json ifneq ($(strip $(CONFIG)),) CONFIG_PATH := $(if $(filter /%,$(CONFIG)),$(CONFIG),$(ROOT_PATH)/$(CONFIG)) @@ -14,14 +14,14 @@ endif include $(CONFIG_PATH) PROFILE_NAME := $(basename $(notdir $(CONFIG_PATH))) else -CONFIG_PATH := +CONFIG_PATH := PROFILE_NAME := manual endif -SOC ?= MINI -SIMU ?= VCS -SYNTH ?= NONE -STA ?= NONE +SOC ?= MINI +SIMU ?= VCS +SYNTH ?= NONE +STA ?= NONE # HW PDK ?= IHP130 @@ -31,36 +31,36 @@ HAVE_SRAM_MACRO ?= NO HAVE_SVA ?= NO WAVE ?= NO -RTL_SIM_CORESEL ?= 0 -RTL_SIM_TIMEOUT ?= -1 -SIM_FIRMWARE_NAME ?= $(FIRMWARE_NAME) +RTL_SIM_CORESEL ?= 0 +RTL_SIM_TIMEOUT ?= -1 +SIM_FIRMWARE_NAME ?= $(FIRMWARE_NAME) SIM_SUCCESS_MARKER ?= retroSoC: A Customized ASIC for Retro Stuff -RTL_PATH := $(ROOT_PATH)/rtl/mini +RTL_PATH := $(ROOT_PATH)/rtl/mini -CORE ?= HAZARD3 -IP ?= NONE -RTL_TOP ?= retrosoc_tb +CORE ?= HAZARD3 +IP ?= NONE +RTL_TOP ?= retrosoc_tb # SW -ISA ?= RV32IM -HAVE_CSR ?= NO -FIRMWARE_NAME ?= retrosoc_fw -APP ?= shell -LINK_TYPE ?= ld2_sram +ISA ?= RV32IM +HAVE_CSR ?= NO +FIRMWARE_NAME ?= retrosoc_fw +APP ?= shell +LINK_TYPE ?= ld2_sram -BUILD_ROOT ?= $(ROOT_PATH)/build -CACHE_ROOT ?= $(ROOT_PATH)/.cache/retrosoc +BUILD_ROOT ?= $(ROOT_PATH)/build +CACHE_ROOT ?= $(ROOT_PATH)/.cache/retrosoc BUILD_TIMESTAMP ?= $(shell date '+%Y-%m-%d-%H-%M') -MAX_JOBS ?= 16 -HOST_CC ?= cc -CLANG_FORMAT ?= clang-format-14 -JOBS ?= $(shell count=$$(nproc 2>/dev/null || printf '1'); \ +MAX_JOBS ?= 16 +HOST_CC ?= cc +CLANG_FORMAT ?= clang-format-14 +JOBS ?= $(shell count=$$(nproc 2>/dev/null || printf '1'); \ if [ "$$count" -gt "$(MAX_JOBS)" ]; then printf '%s' '$(MAX_JOBS)'; \ - else printf '%s' "$$count"; fi) +else printf '%s' "$$count"; fi) CONFIG_KEY_VARS := SOC CORE IP PDK HAVE_PLL HAVE_SRAM_IF HAVE_SRAM_MACRO HAVE_SVA \ ISA HAVE_CSR APP LINK_TYPE RTL_TOP FIRMWARE_NAME -VARIANT_ID := $(strip $(shell python3 $(ROOT_PATH)/scripts/config_key.py \ +VARIANT_ID := $(strip $(shell python3 $(ROOT_PATH)/scripts/config_key.py \ --lock $(LOCK_FILE) --profile $(PROFILE_NAME) --timestamp $(BUILD_TIMESTAMP) \ $(foreach var,$(CONFIG_KEY_VARS),--value $(var)=$($(var))))) ifeq ($(VARIANT_ID),) @@ -68,13 +68,13 @@ $(error Failed to calculate build variant ID) endif LOCK_DIGEST := $(strip $(shell python3 $(ROOT_PATH)/scripts/dependency_lock.py --lock $(LOCK_FILE) --digest)) export BUILD_TIMESTAMP -VARIANT_ROOT := $(abspath $(BUILD_ROOT))/$(VARIANT_ID) -SW_BUILD_DIR := $(VARIANT_ROOT)/sw -SIM_TOOL_NAME := $(shell printf '%s' '$(SIMU)' | tr '[:upper:]' '[:lower:]') +VARIANT_ROOT := $(abspath $(BUILD_ROOT))/$(VARIANT_ID) +SW_BUILD_DIR := $(VARIANT_ROOT)/sw +SIM_TOOL_NAME := $(shell printf '%s' '$(SIMU)' | tr '[:upper:]' '[:lower:]') SIM_BUILD_ROOT := $(VARIANT_ROOT)/sim/$(SIM_TOOL_NAME) SYN_BUILD_ROOT := $(VARIANT_ROOT)/syn/yosys STA_BUILD_ROOT := $(VARIANT_ROOT)/sta/opensta -META_DIR := $(VARIANT_ROOT)/meta +META_DIR := $(VARIANT_ROOT)/meta ifeq ($(SYNTH),YOSYS) FLOW_FILELIST_DIR := $(SYN_BUILD_ROOT)/filelists else @@ -126,10 +126,10 @@ $(error OpenSTA currently supports PDK=IHP130 only) endif endif -DEF_LIST ?= +define+PDK_$(PDK) -DEF_LIST += +define+CORE_$(CORE) -DEF_LIST += +define+IP_$(IP) -DEF_LIST += +define+SIMU_$(SIMU) +DEF_LIST ?= +define+PDK_$(PDK) +DEF_LIST += +define+CORE_$(CORE) +DEF_LIST += +define+IP_$(IP) +DEF_LIST += +define+SIMU_$(SIMU) ifeq ($(HAVE_PLL), YES) DEF_LIST += +define+HAVE_PLL @@ -162,9 +162,9 @@ ifeq ($(STA), OPENSTA) endif .PHONY: help config doctor setup setup-mpw setup-core setup-clusterip setup-ip setup-pdk setup-app \ - clean-all purge-cache manifest check-warnings metrics check-metrics package \ - regress-pr regress-nightly sim-asm sw-format sw-format-check sw-policy-check sw-host-test \ - pin-map check-pin-map + clean-all purge-cache manifest check-warnings metrics check-metrics package \ + regress-pr regress-nightly sim-asm sw-format sw-format-check sw-policy-check sw-host-test \ + pin-map check-pin-map .NOTPARALLEL: setup help: @@ -288,4 +288,4 @@ regress-nightly: sim-asm: asm $(MAKE) SIM_FIRMWARE_NAME=$(ASM_FIRMWARE_NAME) \ - SIM_SUCCESS_MARKER='Mem wr/rd test success' sim + SIM_SUCCESS_MARKER='Mem wr/rd test success' sim \ No newline at end of file diff --git a/app/apps/shell/app.mk b/app/apps/shell/app.mk index 1b3c7ec4..9bf925ad 100644 --- a/app/apps/shell/app.mk +++ b/app/apps/shell/app.mk @@ -14,4 +14,4 @@ APP_INC_DIRS += $(ROOT_PATH)/app/media/include include $(ROOT_PATH)/app/middleware/fatfs/fatfs.mk include $(ROOT_PATH)/app/benchmark/coremark/coremark.mk -include $(ROOT_PATH)/app/network/userip/userip.mk +include $(ROOT_PATH)/app/network/userip/userip.mk \ No newline at end of file diff --git a/app/asm/Makefile b/app/asm/Makefile index b24c45bd..6551ab0d 100644 --- a/app/asm/Makefile +++ b/app/asm/Makefile @@ -2,15 +2,15 @@ GCC = riscv32-unknown-elf- -AS = $(GCC)as -LD = $(GCC)ld -OBJDUMP = $(GCC)objdump -OBJCOPY = $(GCC)objcopy +AS = $(GCC)as +LD = $(GCC)ld +OBJDUMP = $(GCC)objdump +OBJCOPY = $(GCC)objcopy AS_FLAGS = -fno-pic -march=rv32im -mabi=ilp32 LDFLAGS = -T flash.ld -melf32lriscv -APP ?= hello -OUT_DIR ?= . -APP_ALL = $(OUT_DIR)/$(APP)-asm +APP ?= hello +OUT_DIR ?= . +APP_ALL = $(OUT_DIR)/$(APP)-asm all: $(APP).s @mkdir -p $(OUT_DIR) @@ -21,4 +21,4 @@ all: $(APP).s $(OBJCOPY) -S -I binary -O verilog $(APP_ALL).bin $(APP_ALL).flash clean: - rm -rf $(APP_ALL).o $(APP_ALL).elf $(APP_ALL).txt $(APP_ALL).bin $(APP_ALL).flash + rm -rf $(APP_ALL).o $(APP_ALL).elf $(APP_ALL).txt $(APP_ALL).bin $(APP_ALL).flash \ No newline at end of file diff --git a/app/benchmark/coremark/coremark.mk b/app/benchmark/coremark/coremark.mk index daa91b9a..e5cb0897 100644 --- a/app/benchmark/coremark/coremark.mk +++ b/app/benchmark/coremark/coremark.mk @@ -6,4 +6,4 @@ APP_SRCS += $(ROOT_PATH)/app/coremark/coremark-main/core_util.c APP_SRCS += $(ROOT_PATH)/app/benchmark/coremark/core_portme.c APP_INC_DIRS += $(ROOT_PATH)/app/coremark/coremark-main -APP_INC_DIRS += $(ROOT_PATH)/app/benchmark/coremark +APP_INC_DIRS += $(ROOT_PATH)/app/benchmark/coremark \ No newline at end of file diff --git a/app/middleware/fatfs/fatfs.mk b/app/middleware/fatfs/fatfs.mk index 60d70818..cf51a4d2 100644 --- a/app/middleware/fatfs/fatfs.mk +++ b/app/middleware/fatfs/fatfs.mk @@ -3,4 +3,4 @@ APP_SRCS += $(ROOT_PATH)/app/fatfs/ff16/source/ff.c APP_SRCS += $(ROOT_PATH)/app/fatfs/ff16/source/ffsystem.c APP_SRCS += $(ROOT_PATH)/app/fatfs/ff16/source/ffunicode.c -APP_INC_DIRS += $(ROOT_PATH)/app/fatfs/ff16/source +APP_INC_DIRS += $(ROOT_PATH)/app/fatfs/ff16/source \ No newline at end of file diff --git a/app/network/userip/userip.mk b/app/network/userip/userip.mk index 08f74f07..5d668e4b 100644 --- a/app/network/userip/userip.mk +++ b/app/network/userip/userip.mk @@ -1,5 +1,5 @@ # User IP is optional and is linked only for MDD configurations. ifeq ($(IP), MDD) -APP_SRCS += $(ROOT_PATH)/app/network/userip/userip.c +APP_SRCS += $(ROOT_PATH)/app/network/userip/userip.c APP_INC_DIRS += $(ROOT_PATH)/app/network/userip -endif +endif \ No newline at end of file diff --git a/app/ports/lvgl/lvgl.mk b/app/ports/lvgl/lvgl.mk index 2380f872..b8626863 100644 --- a/app/ports/lvgl/lvgl.mk +++ b/app/ports/lvgl/lvgl.mk @@ -5,4 +5,4 @@ APP_SRCS += $(ROOT_PATH)/app/ports/lvgl/lv_port_disp.c APP_SRCS += $(ROOT_PATH)/app/ports/lvgl/lv_port_indev.c APP_INC_DIRS += $(LVGL_SDK_DIR) -APP_INC_DIRS += $(ROOT_PATH)/app/ports/lvgl +APP_INC_DIRS += $(ROOT_PATH)/app/ports/lvgl \ No newline at end of file diff --git a/configs/ci/hazard3-rv32im-ihp130-shell.mk b/configs/ci/hazard3-rv32im-ihp130-shell.mk index 45673f10..016b0e33 100644 --- a/configs/ci/hazard3-rv32im-ihp130-shell.mk +++ b/configs/ci/hazard3-rv32im-ihp130-shell.mk @@ -1,12 +1,12 @@ -SOC := MINI -CORE := HAZARD3 -IP := NONE -PDK := IHP130 -HAVE_PLL := NO -HAVE_SRAM_IF := NO +SOC := MINI +CORE := HAZARD3 +IP := NONE +PDK := IHP130 +HAVE_PLL := NO +HAVE_SRAM_IF := NO HAVE_SRAM_MACRO := NO -HAVE_SVA := NO -ISA := RV32IM -HAVE_CSR := YES -APP := shell -LINK_TYPE := ld2_psram +HAVE_SVA := NO +ISA := RV32IM +HAVE_CSR := YES +APP := shell +LINK_TYPE := ld2_psram \ No newline at end of file diff --git a/configs/ci/hazard3-rv32im-ihp130.mk b/configs/ci/hazard3-rv32im-ihp130.mk index 84a4aaa1..772b5fac 100644 --- a/configs/ci/hazard3-rv32im-ihp130.mk +++ b/configs/ci/hazard3-rv32im-ihp130.mk @@ -1,12 +1,12 @@ -SOC := MINI -CORE := HAZARD3 -IP := NONE -PDK := IHP130 -HAVE_PLL := NO -HAVE_SRAM_IF := NO +SOC := MINI +CORE := HAZARD3 +IP := NONE +PDK := IHP130 +HAVE_PLL := NO +HAVE_SRAM_IF := NO HAVE_SRAM_MACRO := NO -HAVE_SVA := NO -ISA := RV32IM -HAVE_CSR := NO -APP := bringup -LINK_TYPE := ld2_psram +HAVE_SVA := NO +ISA := RV32IM +HAVE_CSR := NO +APP := bringup +LINK_TYPE := ld2_psram \ No newline at end of file diff --git a/configs/ci/mdd-rv32im-ihp130.mk b/configs/ci/mdd-rv32im-ihp130.mk index 20e12b54..c3ed132a 100644 --- a/configs/ci/mdd-rv32im-ihp130.mk +++ b/configs/ci/mdd-rv32im-ihp130.mk @@ -1,12 +1,12 @@ -SOC := MINI -CORE := MDD -IP := NONE -PDK := IHP130 -HAVE_PLL := NO -HAVE_SRAM_IF := NO +SOC := MINI +CORE := MDD +IP := NONE +PDK := IHP130 +HAVE_PLL := NO +HAVE_SRAM_IF := NO HAVE_SRAM_MACRO := NO -HAVE_SVA := NO -ISA := RV32IM -HAVE_CSR := NO -APP := bringup -LINK_TYPE := ld2_psram +HAVE_SVA := NO +ISA := RV32IM +HAVE_CSR := NO +APP := bringup +LINK_TYPE := ld2_psram \ No newline at end of file diff --git a/configs/cluster/hazard3-ics55.mk b/configs/cluster/hazard3-ics55.mk index 0c4e754d..9e83de0f 100644 --- a/configs/cluster/hazard3-ics55.mk +++ b/configs/cluster/hazard3-ics55.mk @@ -1,12 +1,12 @@ -SOC := MINI -CORE := HAZARD3 -IP := NONE -PDK := ICS55 -HAVE_PLL := NO -HAVE_SRAM_IF := NO +SOC := MINI +CORE := HAZARD3 +IP := NONE +PDK := ICS55 +HAVE_PLL := NO +HAVE_SRAM_IF := NO HAVE_SRAM_MACRO := NO -HAVE_SVA := NO -ISA := RV32IM -HAVE_CSR := NO -APP := bringup -LINK_TYPE := ld2_psram +HAVE_SVA := NO +ISA := RV32IM +HAVE_CSR := NO +APP := bringup +LINK_TYPE := ld2_psram \ No newline at end of file diff --git a/configs/nightly/picorv32-rv32im-ihp130.mk b/configs/nightly/picorv32-rv32im-ihp130.mk index 88e08dde..1b96819b 100644 --- a/configs/nightly/picorv32-rv32im-ihp130.mk +++ b/configs/nightly/picorv32-rv32im-ihp130.mk @@ -1,12 +1,12 @@ -SOC := MINI -CORE := PICORV32 -IP := NONE -PDK := IHP130 -HAVE_PLL := NO -HAVE_SRAM_IF := NO +SOC := MINI +CORE := PICORV32 +IP := NONE +PDK := IHP130 +HAVE_PLL := NO +HAVE_SRAM_IF := NO HAVE_SRAM_MACRO := NO -HAVE_SVA := NO -ISA := RV32IM -HAVE_CSR := NO -APP := bringup -LINK_TYPE := ld2_psram +HAVE_SVA := NO +ISA := RV32IM +HAVE_CSR := NO +APP := bringup +LINK_TYPE := ld2_psram \ No newline at end of file diff --git a/rtl/mini/Makefile b/rtl/mini/Makefile index 8052b82a..8e1e5272 100644 --- a/rtl/mini/Makefile +++ b/rtl/mini/Makefile @@ -1,29 +1,29 @@ -GENERATED_FL_DIR := $(FLOW_FILELIST_DIR) -MEMORY_MAP_SOURCE := $(RTL_PATH)/address_map/memory_map.json -MEMORY_MAP_SCRIPT := $(RTL_PATH)/address_map/generate_memory_map.py -MEMORY_MAP_DIR := $(VARIANT_ROOT)/generated/memory_map -MEMORY_MAP_STAMP := $(MEMORY_MAP_DIR)/.stamp -MEMORY_MAP_RTL_DIR := $(MEMORY_MAP_DIR)/rtl -MEMORY_MAP_C_DIR := $(MEMORY_MAP_DIR)/include +GENERATED_FL_DIR := $(FLOW_FILELIST_DIR) +MEMORY_MAP_SOURCE := $(RTL_PATH)/address_map/memory_map.json +MEMORY_MAP_SCRIPT := $(RTL_PATH)/address_map/generate_memory_map.py +MEMORY_MAP_DIR := $(VARIANT_ROOT)/generated/memory_map +MEMORY_MAP_STAMP := $(MEMORY_MAP_DIR)/.stamp +MEMORY_MAP_RTL_DIR := $(MEMORY_MAP_DIR)/rtl +MEMORY_MAP_C_DIR := $(MEMORY_MAP_DIR)/include MEMORY_MAP_LINKER_DIR := $(MEMORY_MAP_DIR)/linker -MEMORY_MAP_FILELIST := $(MEMORY_MAP_DIR)/memory_map.fl -PIN_MAP_SOURCE := $(RTL_PATH)/pin_map/pin_map.json -PIN_MAP_SCRIPT := $(RTL_PATH)/pin_map/generate_pin_map.py -PIN_MAP_DIR := $(VARIANT_ROOT)/generated/pin_map -PIN_MAP_STAMP := $(PIN_MAP_DIR)/.stamp -PIN_MAP_FILELIST := $(PIN_MAP_DIR)/pin_map.fl -MPW_STAMP := $(CACHE_ROOT)/stamps/mpw-$(LOCK_DIGEST).prepared -MPW_OUTPUT_DIR := $(VARIANT_ROOT)/generated/mpw/$(SIM_TOOL_NAME) -MPW_VARIANT_STAMP := $(MPW_OUTPUT_DIR)/.stamp -FILELIST_STAMP := $(GENERATED_FL_DIR)/.stamp -FILELIST_TEMPLATES := $(sort $(wildcard $(ROOT_PATH)/rtl/filelist/pdk_*.fl) \ +MEMORY_MAP_FILELIST := $(MEMORY_MAP_DIR)/memory_map.fl +PIN_MAP_SOURCE := $(RTL_PATH)/pin_map/pin_map.json +PIN_MAP_SCRIPT := $(RTL_PATH)/pin_map/generate_pin_map.py +PIN_MAP_DIR := $(VARIANT_ROOT)/generated/pin_map +PIN_MAP_STAMP := $(PIN_MAP_DIR)/.stamp +PIN_MAP_FILELIST := $(PIN_MAP_DIR)/pin_map.fl +MPW_STAMP := $(CACHE_ROOT)/stamps/mpw-$(LOCK_DIGEST).prepared +MPW_OUTPUT_DIR := $(VARIANT_ROOT)/generated/mpw/$(SIM_TOOL_NAME) +MPW_VARIANT_STAMP := $(MPW_OUTPUT_DIR)/.stamp +FILELIST_STAMP := $(GENERATED_FL_DIR)/.stamp +FILELIST_TEMPLATES := $(sort $(wildcard $(ROOT_PATH)/rtl/filelist/pdk_*.fl) \ $(wildcard $(RTL_PATH)/filelist/*.fl) $(RTL_PATH)/lint.msg) $(MPW_STAMP): @test -d $(ROOT_PATH)/rtl/managed/mpw/.git || { \ echo "missing $(ROOT_PATH)/rtl/managed/mpw; run 'make setup-mpw' first" >&2; \ exit 1; \ - } + } python3 $(ROOT_PATH)/scripts/prepare_mpw.py \ --lock-file $(CACHE_ROOT)/locks/mpw-prepare.lock @mkdir -p $(@D) @@ -58,7 +58,7 @@ check-pin-map: python3 $(PIN_MAP_SCRIPT) --map $(PIN_MAP_SOURCE) --check $(FILELIST_STAMP): $(FILELIST_TEMPLATES) $(RTL_PATH)/script/generate_filelist.py \ - $(RTL_PATH)/script/filelist.py $(MEMORY_MAP_STAMP) $(PIN_MAP_STAMP) + $(RTL_PATH)/script/filelist.py $(MEMORY_MAP_STAMP) $(PIN_MAP_STAMP) python3 $(RTL_PATH)/script/generate_filelist.py \ --output-dir $(GENERATED_FL_DIR) \ $(foreach define,$(DEF_LIST),--define $(define)) @@ -80,15 +80,15 @@ else ifeq ($(PDK), GF180) NET_FLIST := -f $(GENERATED_FL_DIR)/pdk_gf180.fl endif -NET_FLIST += -f $(GENERATED_FL_DIR)/def.fl -NET_FLIST += -f $(GENERATED_FL_DIR)/sys_def.fl -NET_FLIST += -f $(GENERATED_FL_DIR)/commonip.fl -NET_FLIST += -f $(GENERATED_FL_DIR)/inc.fl +NET_FLIST += -f $(GENERATED_FL_DIR)/def.fl +NET_FLIST += -f $(GENERATED_FL_DIR)/sys_def.fl +NET_FLIST += -f $(GENERATED_FL_DIR)/commonip.fl +NET_FLIST += -f $(GENERATED_FL_DIR)/inc.fl -RTL_FLIST := -f $(MEMORY_MAP_FILELIST) -f $(PIN_MAP_FILELIST) $(NET_FLIST) -RTL_FLIST += -f $(GENERATED_FL_DIR)/clusterip.fl -RTL_FLIST += -f $(GENERATED_FL_DIR)/ip.fl -RTL_FLIST += -f $(GENERATED_FL_DIR)/tech.fl +RTL_FLIST := -f $(MEMORY_MAP_FILELIST) -f $(PIN_MAP_FILELIST) $(NET_FLIST) +RTL_FLIST += -f $(GENERATED_FL_DIR)/clusterip.fl +RTL_FLIST += -f $(GENERATED_FL_DIR)/ip.fl +RTL_FLIST += -f $(GENERATED_FL_DIR)/tech.fl ifeq ($(CORE), PICORV32) RTL_FLIST += -f $(GENERATED_FL_DIR)/core_picorv32.fl @@ -113,4 +113,4 @@ else ifeq ($(SIMU), IVERILOG) include $(RTL_PATH)/mk/iverilog.mk endif -.PHONY: gen_mpw_code generate_filelist memory-map check-memory-map pin-map check-pin-map firmware +.PHONY: gen_mpw_code generate_filelist memory-map check-memory-map pin-map check-pin-map firmware \ No newline at end of file diff --git a/rtl/mini/mk/iverilog.mk b/rtl/mini/mk/iverilog.mk index ba7ce6c4..95de8257 100644 --- a/rtl/mini/mk/iverilog.mk +++ b/rtl/mini/mk/iverilog.mk @@ -1,24 +1,24 @@ -IVERILOG ?= iverilog -VVP ?= vvp -GTKWAVE ?= gtkwave +IVERILOG ?= iverilog +VVP ?= vvp +GTKWAVE ?= gtkwave -NETLIST_PATH ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v -POST_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic.v -SDF_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz -SDF_SCOPE ?= $(RTL_TOP).u_retrosoc_asic +NETLIST_PATH ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v +POST_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic.v +SDF_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz +SDF_SCOPE ?= $(RTL_TOP).u_retrosoc_asic -IVERILOG_ROOT := $(SIM_BUILD_ROOT) -IVERILOG_BEHV_DIR := $(IVERILOG_ROOT)/behv -IVERILOG_NETL_DIR := $(IVERILOG_ROOT)/netl -IVERILOG_POST_DIR := $(IVERILOG_ROOT)/post -IVERILOG_BEHV_FLIST := $(IVERILOG_BEHV_DIR)/iverilog.fl -IVERILOG_NETL_FLIST := $(IVERILOG_NETL_DIR)/iverilog.fl -IVERILOG_POST_FLIST := $(IVERILOG_POST_DIR)/iverilog.fl -CONVERTED_SOC := $(IVERILOG_BEHV_DIR)/converted_soc.v -CONVERTED_DEPFILE := $(IVERILOG_BEHV_DIR)/converted_soc.d -IVERILOG_BEHV_SIMV := $(IVERILOG_BEHV_DIR)/simv -IVERILOG_NETL_SIMV := $(IVERILOG_NETL_DIR)/simv -IVERILOG_POST_SIMV := $(IVERILOG_POST_DIR)/simv +IVERILOG_ROOT := $(SIM_BUILD_ROOT) +IVERILOG_BEHV_DIR := $(IVERILOG_ROOT)/behv +IVERILOG_NETL_DIR := $(IVERILOG_ROOT)/netl +IVERILOG_POST_DIR := $(IVERILOG_ROOT)/post +IVERILOG_BEHV_FLIST := $(IVERILOG_BEHV_DIR)/iverilog.fl +IVERILOG_NETL_FLIST := $(IVERILOG_NETL_DIR)/iverilog.fl +IVERILOG_POST_FLIST := $(IVERILOG_POST_DIR)/iverilog.fl +CONVERTED_SOC := $(IVERILOG_BEHV_DIR)/converted_soc.v +CONVERTED_DEPFILE := $(IVERILOG_BEHV_DIR)/converted_soc.d +IVERILOG_BEHV_SIMV := $(IVERILOG_BEHV_DIR)/simv +IVERILOG_NETL_SIMV := $(IVERILOG_NETL_DIR)/simv +IVERILOG_POST_SIMV := $(IVERILOG_POST_DIR)/simv IVERILOG_BEHV_DEPFILE := $(IVERILOG_BEHV_DIR)/simv.d IVERILOG_NETL_DEPFILE := $(IVERILOG_NETL_DIR)/simv.d IVERILOG_POST_DEPFILE := $(IVERILOG_POST_DIR)/simv.d @@ -128,4 +128,4 @@ postwave: clean: python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(IVERILOG_ROOT) -.PHONY: convt_sv2v gen_iverilog_filelist comp netcomp postcomp sim netsim postsim wave netwave postwave clean +.PHONY: convt_sv2v gen_iverilog_filelist comp netcomp postcomp sim netsim postsim wave netwave postwave clean \ No newline at end of file diff --git a/rtl/mini/mk/software.mk b/rtl/mini/mk/software.mk index 401b2bbb..1b0d583d 100644 --- a/rtl/mini/mk/software.mk +++ b/rtl/mini/mk/software.mk @@ -1,12 +1,12 @@ # Software SDK and application build CROSS ?= riscv32-unknown-elf- -CP = $(CROSS)cpp -CC = $(CROSS)gcc +CP = $(CROSS)cpp +CC = $(CROSS)gcc OBJC = $(CROSS)objcopy DUMP = $(CROSS)objdump -GCC_FLAGS := -std=gnu11 -Wall -Wextra \ +GCC_FLAGS := -std=gnu11 -Wall -Wextra \ -Wl,-Bstatic,-T,$(LINK_TYPE).lds,--strip-debug -O3 \ -ffreestanding -nostdlib SW_WARN_FLAGS := -Wformat=2 -Wshadow -Wstrict-prototypes -Wmissing-prototypes \ @@ -91,9 +91,9 @@ CRT_SRCS += $(ROOT_PATH)/crt/src/core/system_irq_handler.c CRT_SRCS += $(ROOT_PATH)/crt/src/core/irq.c endif -APP_SRCS := +APP_SRCS := APP_INC_DIRS := -APP_MK := $(ROOT_PATH)/app/apps/$(APP)/app.mk +APP_MK := $(ROOT_PATH)/app/apps/$(APP)/app.mk ifeq ($(wildcard $(APP_MK)),) $(error Application profile not found: $(APP_MK)) @@ -110,17 +110,17 @@ CRT_SRCS += $(ROOT_PATH)/crt/arch/riscv/libgcc/muldi3.S CRT_SRCS += $(ROOT_PATH)/crt/arch/riscv/libgcc/mulsi3.c endif -INC_PATH := -I$(SW_BUILD_DIR)/include \ +INC_PATH := -I$(SW_BUILD_DIR)/include \ -I$(MEMORY_MAP_C_DIR) \ -I$(ROOT_PATH)/crt/include \ $(addprefix -I,$(APP_INC_DIRS)) -SRC_PATH := $(CRT_SRCS) $(APP_SRCS) -LDS_PATH := $(ROOT_PATH)/crt/linker/$(LINK_TYPE).lds +SRC_PATH := $(CRT_SRCS) $(APP_SRCS) +LDS_PATH := $(ROOT_PATH)/crt/linker/$(LINK_TYPE).lds MEMORY_REGIONS_LD := $(MEMORY_MAP_LINKER_DIR)/memory_regions.ld -VERSION_HEADER := $(SW_BUILD_DIR)/include/socver.h -FIRMWARE_ELF := $(SW_BUILD_DIR)/firmware +VERSION_HEADER := $(SW_BUILD_DIR)/include/socver.h +FIRMWARE_ELF := $(SW_BUILD_DIR)/firmware ASM_FIRMWARE_NAME ?= retrosoc_asm -SW_HEADERS := $(shell find $(ROOT_PATH)/crt/include $(ROOT_PATH)/app -type f \ +SW_HEADERS := $(shell find $(ROOT_PATH)/crt/include $(ROOT_PATH)/app -type f \ \( -name '*.h' -o -name '*.hpp' \) 2>/dev/null) $(VERSION_HEADER): FORCE_VERSION $(ROOT_PATH)/crt/ver.py $(ROOT_PATH)/crt/ver.tmpl @@ -139,7 +139,7 @@ asm: $(MPW_VARIANT_STAMP) cp $(SW_BUILD_DIR)/asm/hello-asm.txt $(SW_BUILD_DIR)/$(ASM_FIRMWARE_NAME)_all.txt $(FIRMWARE_ELF): $(MPW_VARIANT_STAMP) $(MEMORY_MAP_STAMP) $(VERSION_HEADER) $(SRC_PATH) $(SW_HEADERS) $(LDS_PATH) \ - $(ROOT_PATH)/rtl/mini/mk/software.mk + $(ROOT_PATH)/rtl/mini/mk/software.mk @mkdir -p $(SW_BUILD_DIR) cd $(SW_BUILD_DIR) && $(CP) -P -o $(LINK_TYPE).lds $(LDS_PATH) cp $(MEMORY_REGIONS_LD) $(SW_BUILD_DIR)/memory_regions.ld @@ -153,4 +153,4 @@ firmware: $(FIRMWARE_ELF) firmware asm: | manifest -.PHONY: FORCE_VERSION +.PHONY: FORCE_VERSION \ No newline at end of file diff --git a/rtl/mini/mk/vcs.mk b/rtl/mini/mk/vcs.mk index e72b8fc4..24ed8c04 100644 --- a/rtl/mini/mk/vcs.mk +++ b/rtl/mini/mk/vcs.mk @@ -1,20 +1,20 @@ # tools & paths -NOVAS ?= /nfs/tools/synopsys/verdi/V-2023.12-SP1-1/share/PLI/VCS/LINUX64 -VCS_RUNNER ?= bsub -Is -VCS ?= vcs -VERDI ?= verdi -EXTRA ?= -P $(NOVAS)/novas.tab $(NOVAS)/pli.a -SIM_TOOL := $(VCS_RUNNER) $(VCS) -SIM_BINY := $(VCS_RUNNER) ./simv -VERDI_TOOL := $(VCS_RUNNER) $(VERDI) -COMP_LOG := -l compile.log -SIM_LOG := -l sim.log +NOVAS ?= /nfs/tools/synopsys/verdi/V-2023.12-SP1-1/share/PLI/VCS/LINUX64 +VCS_RUNNER ?= bsub -Is +VCS ?= vcs +VERDI ?= verdi +EXTRA ?= -P $(NOVAS)/novas.tab $(NOVAS)/pli.a +SIM_TOOL := $(VCS_RUNNER) $(VCS) +SIM_BINY := $(VCS_RUNNER) ./simv +VERDI_TOOL := $(VCS_RUNNER) $(VERDI) +COMP_LOG := -l compile.log +SIM_LOG := -l sim.log # netlist file path NETLIST_PATH := -v $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v POST_PATH := -v $(ROOT_PATH)/pd/sdf/retrosoc_asic.v SDF_PATH := "$(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz" # testbench filelist -TB_FLIST := -f $(GENERATED_FL_DIR)/tb.fl +TB_FLIST := -f $(GENERATED_FL_DIR)/tb.fl ## vcs option # -debug_region=cell+lib @@ -23,7 +23,7 @@ TB_FLIST := -f $(GENERATED_FL_DIR)/tb.fl # -error=all(turn all warning into error) # +vcs+loopreport+100000 \ # --- Compilation Flags --- -COMMON_OPTS := -full64 +v2k -sverilog -timescale=1ns/10ps \ +COMMON_OPTS := -full64 +v2k -sverilog -timescale=1ns/10ps \ $(EXTRA) \ -kdb \ -debug_access+all \ @@ -35,7 +35,7 @@ COMMON_OPTS := -full64 +v2k -sverilog -timescale=1ns/10ps \ -reportstats \ -work DEFAULT -POST_OPTS := -sdf min:retrosoc_tb.u_retrosoc_asic:$(SDF_PATH) \ +POST_OPTS := -sdf min:retrosoc_tb.u_retrosoc_asic:$(SDF_PATH) \ +delay_mode_path \ +sdfverbose \ +neg_tchk \ @@ -48,12 +48,12 @@ TIME_OPTION := +notimingcheck +nospecify SIM_OPTS := +vcs+loopreport+1000 -suppress=ASLR_DETECTED_INFO \ +core_sel=$(RTL_SIM_CORESEL) +sim_timeout=$(RTL_SIM_TIMEOUT) +wave_$(WAVE) -VCS_BEHV_DIR := $(SIM_BUILD_ROOT)/behv -VCS_NETL_DIR := $(SIM_BUILD_ROOT)/netl -VCS_POST_DIR := $(SIM_BUILD_ROOT)/post -VCS_BEHV_SIMV := $(VCS_BEHV_DIR)/simv -VCS_NETL_SIMV := $(VCS_NETL_DIR)/simv -VCS_POST_SIMV := $(VCS_POST_DIR)/simv +VCS_BEHV_DIR := $(SIM_BUILD_ROOT)/behv +VCS_NETL_DIR := $(SIM_BUILD_ROOT)/netl +VCS_POST_DIR := $(SIM_BUILD_ROOT)/post +VCS_BEHV_SIMV := $(VCS_BEHV_DIR)/simv +VCS_NETL_SIMV := $(VCS_NETL_DIR)/simv +VCS_POST_SIMV := $(VCS_POST_DIR)/simv VCS_BEHV_DEPFILE := $(VCS_BEHV_DIR)/simv.d VCS_NETL_DEPFILE := $(VCS_NETL_DIR)/simv.d VCS_POST_DEPFILE := $(VCS_POST_DIR)/simv.d @@ -86,7 +86,6 @@ wave: DIR := $(SIM_BUILD_ROOT)/behv netwave: DIR := $(SIM_BUILD_ROOT)/netl postwave: DIR := $(SIM_BUILD_ROOT)/post - comp: $(VCS_BEHV_SIMV) netcomp: $(VCS_NETL_SIMV) postcomp: $(VCS_POST_SIMV) @@ -121,4 +120,4 @@ wave netwave postwave: clean: python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(SIM_BUILD_ROOT) -.PHONY: comp netcomp postcomp sim netsim postsim wave clean +.PHONY: comp netcomp postcomp sim netsim postsim wave clean \ No newline at end of file diff --git a/rtl/mini/mk/verilator.mk b/rtl/mini/mk/verilator.mk index ec4c1fe4..02b407ce 100644 --- a/rtl/mini/mk/verilator.mk +++ b/rtl/mini/mk/verilator.mk @@ -5,11 +5,9 @@ SOC_CXXFILES += $(sort $(wildcard $(SOC_CSRC_HOME)/*.cpp)) SOC_CSRC_INCLPATH += -I$(SOC_CSRC_HOME) SOC_CSRC_INCLPATH += $(foreach val, $(SOC_CSRC_LIB_HOME), -I$(val)) -SOC_VSRC_TOP := retrosoc_top -SOC_VSRC_HOME += $(RTL_PATH)/dv/verilator/rtl -SOC_COMPILE_HOME := $(BUILD_DIR)/emu_compile - - +SOC_VSRC_TOP := retrosoc_top +SOC_VSRC_HOME += $(RTL_PATH)/dv/verilator/rtl +SOC_COMPILE_HOME := $(BUILD_DIR)/emu_compile SOC_VXXFILES := $(RTL_FLIST) SOC_VXXFILES += $(RTL_PATH)/dv/model/ESP_PSRAM64H.sv @@ -29,10 +27,10 @@ VERILATOR_FLAGS += -o $(BUILD_DIR)/emu VERILATOR_FLAGS += -Mdir $(SOC_COMPILE_HOME) VERILATOR_FLAGS += $(SOC_VSRC_INCLPATH) $(SOC_CXXFILES) $(SOC_VXXFILES) -SOC_SIM_TIME ?= 40 -VERILATOR_STAMP := $(BUILD_DIR)/verilate.stamp -VERILATOR_DEPFILE := $(BUILD_DIR)/verilate.d -VERILATOR_EMU := $(BUILD_DIR)/emu +SOC_SIM_TIME ?= 40 +VERILATOR_STAMP := $(BUILD_DIR)/verilate.stamp +VERILATOR_DEPFILE := $(BUILD_DIR)/verilate.d +VERILATOR_EMU := $(BUILD_DIR)/emu VERILATOR_EXTRA_SOURCES := $(RTL_PATH)/dv/model/ESP_PSRAM64H.sv \ $(RTL_PATH)/dv/verilator/rtl/flash_read_binder.sv \ $(RTL_PATH)/dv/verilator/rtl/QSPIFlash.sv \ @@ -86,4 +84,4 @@ wave: clean: python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(BUILD_DIR) -.PHONY: comp sim clean +.PHONY: comp sim clean \ No newline at end of file diff --git a/sta/opensta/opensta.mk b/sta/opensta/opensta.mk index 030d2546..b2d3836c 100644 --- a/sta/opensta/opensta.mk +++ b/sta/opensta/opensta.mk @@ -1,15 +1,15 @@ -OPENSTA ?= sta -OPENSTA_THREADS ?= $(JOBS) -OPENSTA_NETLIST ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v -OPENSTA_LIBERTY ?= $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib -OPENSTA_IO_LIB ?= $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib +OPENSTA ?= sta +OPENSTA_THREADS ?= $(JOBS) +OPENSTA_NETLIST ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v +OPENSTA_LIBERTY ?= $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib +OPENSTA_IO_LIB ?= $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib OPENSTA_SRAM_LIBS ?= $(wildcard $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/lib/*_typ_1p20V_25C.lib) -OPENSTA_SDC ?= $(ROOT_PATH)/sta/opensta/gen2.sdc -OPENSTA_REPORT ?= $(STA_BUILD_ROOT)/retrosoc_sta.log -OPENSTA_LOG ?= $(STA_BUILD_ROOT)/opensta.log -OPENSTA_METRICS ?= $(STA_BUILD_ROOT)/timing_metrics.rpt -OPENSTA_CONFIG ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.config +OPENSTA_SDC ?= $(ROOT_PATH)/sta/opensta/gen2.sdc +OPENSTA_REPORT ?= $(STA_BUILD_ROOT)/retrosoc_sta.log +OPENSTA_LOG ?= $(STA_BUILD_ROOT)/opensta.log +OPENSTA_METRICS ?= $(STA_BUILD_ROOT)/timing_metrics.rpt +OPENSTA_CONFIG ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.config sta: @mkdir -p $(STA_BUILD_ROOT) @@ -19,7 +19,7 @@ sta: @grep -qx 'PDK=$(PDK)' $(OPENSTA_CONFIG) || { \ echo "OpenSTA netlist configuration does not match PDK=$(PDK); rerun synthesis" >&2; \ exit 1; \ - } + } python3 $(ROOT_PATH)/scripts/run_flow.py --tool opensta --log $(OPENSTA_LOG) \ --result $(STA_BUILD_ROOT)/result-sta.json \ --env OPENSTA_NETLIST=$(OPENSTA_NETLIST) --env OPENSTA_LIBERTY=$(OPENSTA_LIBERTY) \ @@ -30,4 +30,4 @@ sta: sta: | manifest -.PHONY: sta +.PHONY: sta \ No newline at end of file diff --git a/syn/yosys/synth_config.mk b/syn/yosys/synth_config.mk index 336322ec..080c59ad 100644 --- a/syn/yosys/synth_config.mk +++ b/syn/yosys/synth_config.mk @@ -14,7 +14,7 @@ export YOSYS_BLACKBOX_MODULES := "*tc_sram_blackbox*" # flatten hierarchy (except for below selections) export YOSYS_FLATTEN_HIER := 1 -# a list of yosys selection strings, all selected instances will be +# a list of yosys selection strings, all selected instances will be # kept as a seperate hierarchical element, all others will be flattened # https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/select.html export YOSYS_KEEP_HIER_INST := "t:tc_clk*$$*" \ @@ -24,7 +24,7 @@ export YOSYS_KEEP_HIER_INST := "t:tc_clk*$$*" \ "t:ip_natv_wrapper*$$*" \ "t:ip_apb_wrapper*$$*" \ "t:apb_spi_master*$$*" \ - "t:spi_flash*$$*" \ + "t:spi_flash*$$*" \ "t:mem2apb*$$*" \ "t:apb4_archinfo*$$*" \ "t:apb4_rng*$$*" \ @@ -36,4 +36,4 @@ export YOSYS_KEEP_HIER_INST := "t:tc_clk*$$*" \ # the paths (full names) of all instances matching these strings is reported # for floorplaning or writing constraints -export YOSYS_REPORT_INSTS := "t:*core_wrapper*" +export YOSYS_REPORT_INSTS := "t:*core_wrapper*" \ No newline at end of file diff --git a/syn/yosys/yosys.mk b/syn/yosys/yosys.mk index 2c6d0ded..abf9f387 100644 --- a/syn/yosys/yosys.mk +++ b/syn/yosys/yosys.mk @@ -27,15 +27,15 @@ YOSYS_RPT := $(YOSYS_BUILD)/rpt include $(YOSYS_DIR)/synth_config.mk -TOP_DESIGN ?= retrosoc_asic -RTL_NAME ?= retrosoc_asic -SV_FLIST := $(GENERATED_FL_DIR)/yosys.fl +TOP_DESIGN ?= retrosoc_asic +RTL_NAME ?= retrosoc_asic +SV_FLIST := $(GENERATED_FL_DIR)/yosys.fl -NETLIST := $(YOSYS_OUT)/$(RTL_NAME)_yosys.v -NETLIST_DEBUG := $(YOSYS_OUT)/$(RTL_NAME)_yosys_debug.v +NETLIST := $(YOSYS_OUT)/$(RTL_NAME)_yosys.v +NETLIST_DEBUG := $(YOSYS_OUT)/$(RTL_NAME)_yosys_debug.v NETLIST_CONFIG := $(YOSYS_OUT)/$(RTL_NAME)_yosys.config -YOSYS_DEPFILE := $(YOSYS_BUILD)/yosys.d -YOSYS_SCRIPTS := $(wildcard $(YOSYS_DIR)/script/*) $(YOSYS_DIR)/synth_config.mk $(YOSYS_DIR)/yosys.mk +YOSYS_DEPFILE := $(YOSYS_BUILD)/yosys.d +YOSYS_SCRIPTS := $(wildcard $(YOSYS_DIR)/script/*) $(YOSYS_DIR)/synth_config.mk $(YOSYS_DIR)/yosys.mk -include $(YOSYS_DEPFILE) @@ -69,4 +69,4 @@ synth_clean: .PHONY: gen_synth_filelist synth_clean synth -synth: | manifest +synth: | manifest \ No newline at end of file