From 758b6ed800ab520dc7caac4d110e34d07c546d9f Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 1 Feb 2025 21:36:23 +0800 Subject: [PATCH] feat: add archinfo module and axil2apb bridge --- rtl/ip/axil_ip_wrapper.v | 129 +++++++++++++++++++ rtl/ip/cust/archinfo.v | 128 +++++++++++++++++++ rtl/ip/cust/register.v | 265 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 522 insertions(+) create mode 100644 rtl/ip/axil_ip_wrapper.v create mode 100644 rtl/ip/cust/archinfo.v create mode 100644 rtl/ip/cust/register.v diff --git a/rtl/ip/axil_ip_wrapper.v b/rtl/ip/axil_ip_wrapper.v new file mode 100644 index 00000000..e8620dd1 --- /dev/null +++ b/rtl/ip/axil_ip_wrapper.v @@ -0,0 +1,129 @@ +module axil_ip_wrapper ( + input clk_i, + input rst_n_i, + input mem_axi_awvalid, + output mem_axi_awready, + input [31:0] mem_axi_awaddr, + input [ 2:0] mem_axi_awprot, + input mem_axi_wvalid, + output mem_axi_wready, + input [31:0] mem_axi_wdata, + input [ 3:0] mem_axi_wstrb, + output mem_axi_bvalid, + input mem_axi_bready, + input mem_axi_arvalid, + output mem_axi_arready, + input [31:0] mem_axi_araddr, + input [ 2:0] mem_axi_arprot, + output mem_axi_rvalid, + input mem_axi_rready, + output [31:0] mem_axi_rdata +); + + localparam APB_SLAVES_NUM = 2; + localparam [32*APB_SLAVES_NUM-1 : 0] MEM_REGIONS1 = 32'h0300_0100 + 64'h0300_0110_0000_0000; + localparam [32*APB_SLAVES_NUM-1 : 0] MEM_REGIONS2 = 32'h0300_0108 + 64'h0300_0118_0000_0000; + + wire [ 31:0] s_m_apb_paddr; + wire [ 2:0] s_m_apb_pprot; + wire [APB_SLAVES_NUM-1:0] s_m_apb_psel; + wire s_m_apb_penable; + wire s_m_apb_pwrite; + wire [ 31:0] s_m_apb_pwdata; + wire [ 3:0] s_m_apb_pstrb; + wire [APB_SLAVES_NUM-1:0] s_m_apb_pready; + + wire [ 31:0] s_m_apb_prdata; + wire [ 31:0] s_m_apb_prdata2; + wire [APB_SLAVES_NUM-1:0] s_m_apb_pslverr; + // ARCHINFO + // RNG + + apb4_archinfo u_apb4_archinfo ( + .pclk (clk_i), + .presetn(rst_n_i), + .paddr (s_m_apb_paddr), + .pprot (s_m_apb_pprot), + .psel (s_m_apb_psel[0]), + .penable(s_m_apb_penable), + .pwrite (s_m_apb_pwrite), + .pwdata (s_m_apb_pwdata), + .pstrb (s_m_apb_pstrb), + .pready (s_m_apb_pready[0]), + .prdata (s_m_apb_prdata), + .pslverr(s_m_apb_pslverr[0]) + ); + + apb4_archinfo u_apb4_archinfo2 ( + .pclk (clk_i), + .presetn(rst_n_i), + .paddr (s_m_apb_paddr), + .pprot (s_m_apb_pprot), + .psel (s_m_apb_psel[1]), + .penable(s_m_apb_penable), + .pwrite (s_m_apb_pwrite), + .pwdata (s_m_apb_pwdata), + .pstrb (s_m_apb_pstrb), + .pready (s_m_apb_pready[1]), + .prdata (s_m_apb_prdata2), + .pslverr(s_m_apb_pslverr[1]) + ); + + axi_apb_bridge #( + .c_apb_num_slaves(APB_SLAVES_NUM), + .memory_regions1 (MEM_REGIONS1), + .memory_regions2 (MEM_REGIONS2), + .timeout_val (1), + .APB_Protocol (4) + ) u_axi_apb_bridge ( + .s_axi_clk (clk_i), + .s_axi_aresetn(rst_n_i), + .s_axi_awaddr (mem_axi_awaddr), + .s_axi_awvalid(mem_axi_awvalid), + .s_axi_awready(mem_axi_awready), + .s_axi_wdata (mem_axi_wdata), + .s_axi_wvalid (mem_axi_wvalid), + .s_axi_wstrb (mem_axi_wstrb), + .s_axi_wready (mem_axi_wready), + .s_axi_bresp (), + .s_axi_bvalid (mem_axi_bvalid), + .s_axi_bready (mem_axi_bready), + .s_axi_araddr (mem_axi_araddr), + .s_axi_arvalid(mem_axi_arvalid), + .s_axi_arready(mem_axi_arready), + .s_axi_rresp (), + .s_axi_rvalid (mem_axi_rvalid), + .s_axi_rdata (mem_axi_rdata), + .s_axi_rready (mem_axi_rready), + .s_axi_arprot (mem_axi_arprot), + .s_axi_awprot (mem_axi_awprot), + + .m_apb_paddr (s_m_apb_paddr), + .m_apb_pprot (s_m_apb_pprot), + .m_apb_psel (s_m_apb_psel), + .m_apb_penable (s_m_apb_penable), + .m_apb_pwrite (s_m_apb_pwrite), + .m_apb_pwdata (s_m_apb_pwdata), + .m_apb_pstrb (s_m_apb_pstrb), + .m_apb_pready (s_m_apb_pready), + // diff apb slave rdata + .m_apb_prdata (s_m_apb_prdata), + .m_apb_prdata2 (s_m_apb_prdata2), + .m_apb_prdata3 (32'h0), + .m_apb_prdata4 (32'h0), + .m_apb_prdata5 (32'h0), + .m_apb_prdata6 (32'h0), + .m_apb_prdata7 (32'h0), + .m_apb_prdata8 (32'h0), + .m_apb_prdata9 (32'h0), + .m_apb_prdata10(32'h0), + .m_apb_prdata11(32'h0), + .m_apb_prdata12(32'h0), + .m_apb_prdata13(32'h0), + .m_apb_prdata14(32'h0), + .m_apb_prdata15(32'h0), + .m_apb_prdata16(32'h0), + .m_apb_pslverr (s_m_apb_pslverr) + ); + +endmodule diff --git a/rtl/ip/cust/archinfo.v b/rtl/ip/cust/archinfo.v new file mode 100644 index 00000000..c6382883 --- /dev/null +++ b/rtl/ip/cust/archinfo.v @@ -0,0 +1,128 @@ +// Copyright (c) 2023-2024 Miao Yuchi +// archinfo is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. + +`ifndef INC_ARCHINFO_DEF_SV +`define INC_ARCHINFO_DEF_SV + +/* register mapping + * ARCHINFO_SYS: + * BITS: | 31:20 | 19:8 | 7:0 | + * FIELDS: | RES | CLOCK | SRAM | + * PERMS: | NONE | RW | RW | + * ------------------------------------------- + * ARCHINFO_IDL: + * BITS: | 31:30 | 29:22 | 21:6 | 5:0 | + * FIELDS: | TYPE | VENDOR | PROCESS | CUST | + * PERMS: | RW | RW | RW | RW | + * ------------------------------------------- + * ARCHINFO_IDH: + * BITS: | 31:24 | 23:0 | + * FIELDS: | RES | DATE | + * PERMS: | NONE | RW | + * ------------------------------------------- +*/ + +// verilog_format: off +`define ARCHINFO_SYS 4'b0000 // BASEADDR + 0x00 +`define ARCHINFO_IDL 4'b0001 // BASEADDR + 0x04 +`define ARCHINFO_IDH 4'b0010 // BASEADDR + 0x08 + +`define ARCHINFO_SYS_ADDR {26'b0, `ARCHINFO_SYS, 2'b00} +`define ARCHINFO_IDL_ADDR {26'b0, `ARCHINFO_IDL, 2'b00} +`define ARCHINFO_IDH_ADDR {26'b0, `ARCHINFO_IDH, 2'b00} + +`define ARCHINFO_SYS_WIDTH 20 +`define ARCHINFO_IDL_WIDTH 32 +`define ARCHINFO_IDH_WIDTH 24 + +`define SYS_VAL 20'hF_1010 +`define IDL_VAL 32'hFFFF_2022 +`define IDH_VAL 24'hFF_FFFF +// verilog_format: on + +`endif + + +// Copyright (c) 2023-2024 Miao Yuchi +// archinfo is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. + +module apb4_archinfo ( + input pclk, + input presetn, + input [31:0] paddr, + input [ 2:0] pprot, + input psel, + input penable, + input pwrite, + input [31:0] pwdata, + input [ 3:0] pstrb, + output pready, + output [31:0] prdata, + output pslverr +); + + wire [3:0] s_apb4_addr; + wire s_apb4_wr_hdshk, s_apb4_rd_hdshk; + wire [`ARCHINFO_SYS_WIDTH-1:0] s_arch_sys_d, s_arch_sys_q; + wire s_arch_sys_en; + wire [`ARCHINFO_IDL_WIDTH-1:0] s_arch_idl_d, s_arch_idl_q; + wire s_arch_idl_en; + wire [`ARCHINFO_IDH_WIDTH-1:0] s_arch_idh_d, s_arch_idh_q; + wire s_arch_idh_en; + + assign s_apb4_addr = paddr[5:2]; + assign s_apb4_wr_hdshk = psel && penable && pwrite; + assign s_apb4_rd_hdshk = psel && penable && (~pwrite); + assign pready = 1'b1; + assign pslverr = 1'b0; + + assign s_arch_sys_en = s_apb4_wr_hdshk && s_apb4_addr == `ARCHINFO_SYS; + assign s_arch_sys_d = pwdata[`ARCHINFO_SYS_WIDTH-1:0]; + dfferc #(`ARCHINFO_SYS_WIDTH, `SYS_VAL) u_arch_sys_dfferc ( + pclk, + presetn, + s_arch_sys_en, + s_arch_sys_d, + s_arch_sys_q + ); + + assign s_arch_idl_en = s_apb4_wr_hdshk && s_apb4_addr == `ARCHINFO_IDL; + assign s_arch_idl_d = pwdata[`ARCHINFO_IDL_WIDTH-1:0]; + dfferc #(`ARCHINFO_IDL_WIDTH, `IDL_VAL) u_arch_idl_dfferc ( + pclk, + presetn, + s_arch_idl_en, + s_arch_idl_d, + s_arch_idl_q + ); + + assign s_arch_idh_en = s_apb4_wr_hdshk && s_apb4_addr == `ARCHINFO_IDH; + assign s_arch_idh_d = pwdata[`ARCHINFO_IDH_WIDTH-1:0]; + dfferc #(`ARCHINFO_IDH_WIDTH, `IDH_VAL) u_arch_idh_dfferc ( + pclk, + presetn, + s_arch_idh_en, + s_arch_idh_d, + s_arch_idh_q + ); + + assign prdata = ~s_apb4_rd_hdshk ? 32'h0 : + s_apb4_addr == `ARCHINFO_SYS ? {12'h0, s_arch_sys_q} : + s_apb4_addr == `ARCHINFO_IDL ? s_arch_idl_q : + s_apb4_addr == `ARCHINFO_IDH ? {8'h0, s_arch_idh_q} : 32'h0; + +endmodule diff --git a/rtl/ip/cust/register.v b/rtl/ip/cust/register.v new file mode 100644 index 00000000..c41c8542 --- /dev/null +++ b/rtl/ip/cust/register.v @@ -0,0 +1,265 @@ +// Copyright (c) 2023-2024 Miao Yuchi +// common is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. + +`ifndef INC_REGISTER_SV +`define INC_REGISTER_SV + +`define SV_ASSRT_DISABLE + +// `include "config.svh" + +module dff #( + parameter DATA_WIDTH = 1 +) ( + input clk_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i) begin + dat_o <= dat_i; + end +endmodule + +module dffr #( + parameter DATA_WIDTH = 1 +) ( + input clk_i, + input rst_n_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i, negedge rst_n_i) begin + if (~rst_n_i) begin + dat_o <= {DATA_WIDTH{1'b0}}; + end else begin + dat_o <= dat_i; + end + end +endmodule + +module ndffr #( + parameter DATA_WIDTH = 1 +) ( + input clk_i, + input rst_n_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(negedge clk_i, negedge rst_n_i) begin + if (~rst_n_i) begin + dat_o <= {DATA_WIDTH{1'b0}}; + end else begin + dat_o <= dat_i; + end + end +endmodule + +module dffrh #( + parameter DATA_WIDTH = 1 +) ( + input clk_i, + input rst_n_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i, negedge rst_n_i) begin + if (~rst_n_i) begin + dat_o <= {DATA_WIDTH{1'b1}}; + end else begin + dat_o <= dat_i; + end + end +endmodule + +module dffrc #( + parameter DATA_WIDTH = 1, + parameter [DATA_WIDTH-1:0] RESET_VAL = {DATA_WIDTH{1'b0}} +) ( + input clk_i, + input rst_n_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i, negedge rst_n_i) begin + if (~rst_n_i) begin + dat_o <= RESET_VAL; + end else begin + dat_o <= dat_i; + end + end +endmodule + +module dffsr #( + parameter DATA_WIDTH = 1 +) ( + input clk_i, + input rst_n_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i) begin + if (~rst_n_i) begin + dat_o <= {DATA_WIDTH{1'b0}}; + end else begin + dat_o <= dat_i; + end + end +endmodule + +module dffl #( + parameter DATA_WIDTH = 1 +) ( + input clk_i, + input en_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i) begin + if (en_i) begin + dat_o <= dat_i; + end + end + +`ifndef SV_ASSRT_DISABLE + xchecker #( + .DATA_WIDTH(1) + ) u_xchecker ( + clk_i, + en_i + ); +`endif + +endmodule + +module dffer #( + parameter DATA_WIDTH = 1 +) ( + input clk_i, + input rst_n_i, + input en_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i, negedge rst_n_i) begin + if (~rst_n_i) begin + dat_o <= {DATA_WIDTH{1'b0}}; + end else if (en_i) begin + dat_o <= dat_i; + end + end + +`ifndef SV_ASSRT_DISABLE + xchecker #( + .DATA_WIDTH(1) + ) u_xchecker ( + clk_i, + en_i + ); +`endif + +endmodule + +module dfferh #( + parameter DATA_WIDTH = 1 +) ( + input clk_i, + input rst_n_i, + input en_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i, negedge rst_n_i) begin + if (~rst_n_i) begin + dat_o <= {DATA_WIDTH{1'b1}}; + end else if (en_i) begin + dat_o <= dat_i; + end + end + +`ifndef SV_ASSRT_DISABLE + xchecker #( + .DATA_WIDTH(1) + ) u_xchecker ( + clk_i, + en_i + ); +`endif + +endmodule + +module dfferc #( + parameter DATA_WIDTH = 1, + parameter [DATA_WIDTH-1:0] RESET_VAL = {DATA_WIDTH{1'b0}} +) ( + input clk_i, + input rst_n_i, + input en_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i, negedge rst_n_i) begin + if (~rst_n_i) begin + dat_o <= RESET_VAL; + end else if (en_i) begin + dat_o <= dat_i; + end + end + +`ifndef SV_ASSRT_DISABLE + xchecker #( + .DATA_WIDTH(1) + ) u_xchecker ( + clk_i, + en_i + ); +`endif + +endmodule + +module dffesr #( + parameter DATA_WIDTH = 1 +) ( + input clk_i, + input rst_n_i, + input en_i, + input [DATA_WIDTH-1:0] dat_i, + output reg [DATA_WIDTH-1:0] dat_o +); + + always @(posedge clk_i) begin + if (~rst_n_i) begin + dat_o <= {DATA_WIDTH{1'b0}}; + end else if (en_i) begin + dat_o <= dat_i; + end + end + +`ifndef SV_ASSRT_DISABLE + xchecker #( + .DATA_WIDTH(1) + ) u_xchecker ( + clk_i, + en_i + ); +`endif + +endmodule + +`endif