From 7a7c0b2973d3bbe92bb3c2bbb9808edc5181b641 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Fri, 14 Aug 2026 18:51:02 +0800 Subject: [PATCH] feat: add Yosys synthesis scripts and update PDK paths - Introduced common setup script for Yosys () to manage global variables and configurations. - Added output filtering script () to enhance log readability. - Created technology initialization script () for handling different PDKs. - Developed main synthesis script () to orchestrate the synthesis flow using Yosys. - Added a configuration makefile () for synthesis settings. - Updated Yosys makefile () to integrate new scripts and configurations. - Adjusted paths in and RTL filelists to reflect new directory structure under . - Modified various scripts and test files to accommodate the new PDK paths and ensure compatibility. - Enhanced warning normalization in the analysis script to preserve PDK signatures. --- .dockerignore | 8 ++++---- .github/workflows/_regression.yml | 8 ++++---- .github/workflows/release.yml | 2 +- AGENTS.md | 5 +---- Makefile | 6 +++--- README.md | 3 +-- dependencies/dependencies.lock.json | 8 ++++---- pd/README.md | 10 ---------- {pd => physical}/Makefile | 0 physical/README.md | 18 +++++++++++++++++ {pdk => physical/pdk}/README.md | 3 ++- .../pdk}/generate_gf180_liberty.py | 2 +- .../pdk}/generate_sky130_liberty.py | 2 +- .../pdk}/prepare_ics55_liberty.py | 2 +- .../pdk}/prepare_ics55_sim_model.py | 2 +- {pdk => physical/pdk}/setup.py | 17 ++++++++-------- physical/smoke/README.md | 9 +++++++++ {sta => physical/smoke/sta}/README.md | 0 .../smoke/sta}/opensta/generate_sdc.py | 4 ++-- .../smoke/sta}/opensta/opensta.mk | 6 +++--- .../smoke/sta}/opensta/opensta.tcl | 0 .../smoke/sta}/opensta/pdk_timing.mk | 10 +++++----- .../smoke/sta}/opensta/retrosoc_pll.sdc | 0 .../sta}/opensta/sky130_io_blackbox.liberty | 0 {syn => physical/smoke/syn}/Makefile | 0 {syn => physical/smoke/syn}/README.md | 0 .../smoke/syn}/tools/export_soc_sources.py | 4 ++-- {syn => physical/smoke/syn}/yosys/.gitignore | 0 .../smoke/syn}/yosys/script/abc-opt.script | 0 .../smoke/syn}/yosys/script/abc.constr | 0 .../smoke/syn}/yosys/script/cell_dont_use.py | 0 .../smoke/syn}/yosys/script/common.tcl | 0 .../smoke/syn}/yosys/script/filter_output.awk | 0 .../smoke/syn}/yosys/script/init_tech.tcl | 6 +++--- .../smoke/syn}/yosys/script/synth.tcl | 0 .../smoke/syn}/yosys/synth_config.mk | 0 {syn => physical/smoke/syn}/yosys/yosys.mk | 0 pyproject.toml | 4 ++-- rtl/filelist/pdk_gf180.fl | 8 ++++---- rtl/filelist/pdk_ics55.fl | 2 +- rtl/filelist/pdk_ihp130.fl | 8 ++++---- rtl/filelist/pdk_sky130.fl | 16 +++++++-------- rtl/mini/lint.msg | 2 +- rtl/mini/mk/iverilog.mk | 4 ++-- rtl/mini/mk/vcs.mk | 8 ++++---- rtl/mini/script/gen_iverilog_filelist.py | 6 ++++-- rtl/mini/script/generate_filelist.py | 2 +- scripts/analyze_warnings.py | 1 + scripts/package.py | 2 +- tests/test_script_tools.py | 20 ++++++++++++++++++- tests/test_sta_constraints.py | 10 +++++----- 51 files changed, 132 insertions(+), 96 deletions(-) delete mode 100644 pd/README.md rename {pd => physical}/Makefile (100%) create mode 100644 physical/README.md rename {pdk => physical/pdk}/README.md (96%) rename {pdk => physical/pdk}/generate_gf180_liberty.py (98%) rename {pdk => physical/pdk}/generate_sky130_liberty.py (98%) rename {pdk => physical/pdk}/prepare_ics55_liberty.py (98%) rename {pdk => physical/pdk}/prepare_ics55_sim_model.py (98%) rename {pdk => physical/pdk}/setup.py (90%) create mode 100644 physical/smoke/README.md rename {sta => physical/smoke/sta}/README.md (100%) rename {sta => physical/smoke/sta}/opensta/generate_sdc.py (98%) rename {sta => physical/smoke/sta}/opensta/opensta.mk (90%) rename {sta => physical/smoke/sta}/opensta/opensta.tcl (100%) rename {sta => physical/smoke/sta}/opensta/pdk_timing.mk (51%) rename {sta => physical/smoke/sta}/opensta/retrosoc_pll.sdc (100%) rename {sta => physical/smoke/sta}/opensta/sky130_io_blackbox.liberty (100%) rename {syn => physical/smoke/syn}/Makefile (100%) rename {syn => physical/smoke/syn}/README.md (100%) rename {syn => physical/smoke/syn}/tools/export_soc_sources.py (98%) rename {syn => physical/smoke/syn}/yosys/.gitignore (100%) rename {syn => physical/smoke/syn}/yosys/script/abc-opt.script (100%) rename {syn => physical/smoke/syn}/yosys/script/abc.constr (100%) rename {syn => physical/smoke/syn}/yosys/script/cell_dont_use.py (100%) rename {syn => physical/smoke/syn}/yosys/script/common.tcl (100%) rename {syn => physical/smoke/syn}/yosys/script/filter_output.awk (100%) rename {syn => physical/smoke/syn}/yosys/script/init_tech.tcl (94%) rename {syn => physical/smoke/syn}/yosys/script/synth.tcl (100%) rename {syn => physical/smoke/syn}/yosys/synth_config.mk (100%) rename {syn => physical/smoke/syn}/yosys/yosys.mk (100%) diff --git a/.dockerignore b/.dockerignore index 915647a7..bce2a18e 100644 --- a/.dockerignore +++ b/.dockerignore @@ -4,10 +4,10 @@ .ruff_cache/ build/ dist/ -pdk/IHP-Open-PDK/ -pdk/gf180mcu-pdk/ -pdk/icsprout55-pdk/ -pdk/skywater-pdk/ +physical/pdk/IHP-Open-PDK/ +physical/pdk/gf180mcu-pdk/ +physical/pdk/icsprout55-pdk/ +physical/pdk/skywater-pdk/ rtl/managed/clusterip/ rtl/managed/hazard3/ rtl/managed/mpw/ diff --git a/.github/workflows/_regression.yml b/.github/workflows/_regression.yml index e735dba6..bb006e49 100644 --- a/.github/workflows/_regression.yml +++ b/.github/workflows/_regression.yml @@ -60,10 +60,10 @@ jobs: path: | app/coremark/coremark-main app/fatfs/ff16 - pdk/IHP-Open-PDK - pdk/gf180mcu-pdk - pdk/icsprout55-pdk - pdk/skywater-pdk + physical/pdk/IHP-Open-PDK + physical/pdk/gf180mcu-pdk + physical/pdk/icsprout55-pdk + physical/pdk/skywater-pdk rtl/managed/clusterip/archinfo rtl/managed/clusterip/clint rtl/managed/clusterip/common diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 521137b8..db5f0fab 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -22,7 +22,7 @@ jobs: path: | app/coremark/coremark-main app/fatfs/ff16 - pdk/IHP-Open-PDK + physical/pdk/IHP-Open-PDK rtl/managed/clusterip/archinfo rtl/managed/clusterip/clint rtl/managed/clusterip/common diff --git a/AGENTS.md b/AGENTS.md index e804998f..65c14dbf 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -41,14 +41,11 @@ and validation boundary. | `docs/` | [docs/README.md](docs/README.md) | Engineering and MISRA policy. | | `fpga/` | [fpga/README.md](fpga/README.md) | FPGA wrapper and board constraints. | | `licenses/` | [licenses/README.md](licenses/README.md) | Third-party notices and license texts. | -| `pd/` | [pd/README.md](pd/README.md) | Physical-design entry points. | -| `pdk/` | [pdk/README.md](pdk/README.md) | Managed PDK and technology inputs. | +| `physical/` | [physical/README.md](physical/README.md) | Physical design, managed PDK inputs, and smoke synthesis/STA flows. | | `quality/` | [quality/README.md](quality/README.md) | Executable quality policy and baselines. | | `requirements/` | [requirements/README.md](requirements/README.md) | Pinned Python tool requirements. | | `rtl/` | [rtl/README.md](rtl/README.md) | RTL, testbench, and SoC integration. | | `scripts/` | [scripts/README.md](scripts/README.md) | Build, setup, regression, and quality helpers. | -| `sta/` | [sta/README.md](sta/README.md) | Static timing analysis. | -| `syn/` | [syn/README.md](syn/README.md) | Synthesis and source export. | | `tests/` | [tests/README.md](tests/README.md) | Host C and Python test suites. | Do not create project documentation inside generated/local roots such as diff --git a/Makefile b/Makefile index 7c2fc844..c4f49add 100644 --- a/Makefile +++ b/Makefile @@ -248,11 +248,11 @@ PERF_LOG ?= $(SIM_BUILD_ROOT)/sim.log endif ifeq ($(SYNTH), YOSYS) -include syn/yosys/yosys.mk +include physical/smoke/syn/yosys/yosys.mk endif ifeq ($(STA), OPENSTA) - include sta/opensta/opensta.mk + include physical/smoke/sta/opensta/opensta.mk endif .PHONY: help config doctor setup setup-regression setup-mpw setup-clusterip setup-ip setup-pdk setup-app \ @@ -375,7 +375,7 @@ setup-ip: python3 $(ROOT_PATH)/rtl/ip/setup.py setup-pdk: - python3 $(ROOT_PATH)/pdk/setup.py --pdk $(PDK) + python3 $(ROOT_PATH)/physical/pdk/setup.py --pdk $(PDK) setup-app: python3 $(ROOT_PATH)/app/setup.py diff --git a/README.md b/README.md index dab90c6f..ec8259e5 100644 --- a/README.md +++ b/README.md @@ -57,8 +57,7 @@ under the [Mulan Permissive Software License, Version 2](LICENSE). | [`crt/`](crt) | Freestanding RISC-V startup code, linker scripts, runtime library, core services, and HAL headers. | | [`app/`](app) | Applications, board support, media, middleware, networking, ports, and benchmarks. | | [`configs/`](configs) | Versioned build profiles for CI, nightly, and cluster flows. | -| [`pdk/`](pdk) | PDK setup entry points and technology-specific integration. | -| [`syn/`](syn) and [`sta/`](sta) | Synthesis and static timing analysis flows. | +| [`physical/`](physical) | Physical-design entry points, managed PDK integration, and smoke synthesis/STA flows. | | [`scripts/`](scripts) and [`quality/`](quality) | Build helpers, regression orchestration, checks, warning baselines, and metric policy. | | [`.github/`](.github) | GitHub automation, Dependabot configuration, and CI/release workflows; see [`GUIDE.md`](.github/GUIDE.md). | | [`docs/`](docs) | Engineering workflow and release-process documentation. | diff --git a/dependencies/dependencies.lock.json b/dependencies/dependencies.lock.json index 9a20f45d..5a98f60b 100644 --- a/dependencies/dependencies.lock.json +++ b/dependencies/dependencies.lock.json @@ -34,28 +34,28 @@ "pdk_ihp130": { "url": "https://github.com/IHP-GmbH/IHP-Open-PDK.git", "revision": "68eebafcd9b2f5e92c69d37a8d3d90eb266550f5", - "destination": "pdk/IHP-Open-PDK", + "destination": "physical/pdk/IHP-Open-PDK", "recursive": true, "license": "Apache-2.0" }, "pdk_ics55": { "url": "https://github.com/openecos-projects/icsprout55-pdk.git", "revision": "e696e093129ca2212487aa169af74d06ebd86eb6", - "destination": "pdk/icsprout55-pdk", + "destination": "physical/pdk/icsprout55-pdk", "recursive": true, "license": "Apache-2.0" }, "pdk_gf180": { "url": "https://github.com/google/gf180mcu-pdk.git", "revision": "de3240d7529a6970437ac3344820aaae7839f215", - "destination": "pdk/gf180mcu-pdk", + "destination": "physical/pdk/gf180mcu-pdk", "recursive": true, "license": "Apache-2.0" }, "pdk_sky130": { "url": "https://github.com/google/skywater-pdk.git", "revision": "7198cf647113f56041e02abf3eb623692820c5e1", - "destination": "pdk/skywater-pdk", + "destination": "physical/pdk/skywater-pdk", "recursive": true, "submodules": ["libraries/sky130_fd_sc_hd/latest"], "license": "Apache-2.0" diff --git a/pd/README.md b/pd/README.md deleted file mode 100644 index 836ac260..00000000 --- a/pd/README.md +++ /dev/null @@ -1,10 +0,0 @@ -# Physical Design Entry Points - -This directory contains physical-design integration entry points. The local -Makefile is reserved for implementation flows that require the selected PDK, -technology collateral, and often site-specific tools. - -Generated layout, report, and database outputs must remain outside tracked -source paths. Treat PDK-dependent physical-design results as toolchain-specific -evidence and record the selected profile, PDK, and validation command when -handing off a change. See [Engineering Workflow](../docs/engineering.md). diff --git a/pd/Makefile b/physical/Makefile similarity index 100% rename from pd/Makefile rename to physical/Makefile diff --git a/physical/README.md b/physical/README.md new file mode 100644 index 00000000..4025a8e0 --- /dev/null +++ b/physical/README.md @@ -0,0 +1,18 @@ +# Physical Design + +This directory owns physical-design integration, managed technology inputs, +and smoke implementation-flow sources. + +- `pdk/` contains the locked PDK setup helpers and managed PDK checkouts. +- `smoke/syn/` contains Yosys synthesis and source-export integration. +- `smoke/sta/` contains OpenSTA constraints and timing integration. +- `sdf/`, when supplied by an implementation flow, contains post-layout + netlist and SDF collateral consumed by post-layout simulation. + +The local Makefile is reserved for implementation flows that require the +selected PDK, technology collateral, and often site-specific tools. + +Generated layout, report, and database outputs must remain outside tracked +source paths. Treat PDK-dependent physical-design results as toolchain-specific +evidence and record the selected profile, PDK, and validation command when +handing off a change. See [Engineering Workflow](../docs/engineering.md). diff --git a/pdk/README.md b/physical/pdk/README.md similarity index 96% rename from pdk/README.md rename to physical/pdk/README.md index a198bc33..cd6032a8 100644 --- a/pdk/README.md +++ b/physical/pdk/README.md @@ -8,7 +8,8 @@ source. Use the dependency lock and PDK setup targets to acquire or update managed inputs. Do not reformat, patch, or delete vendor content as part of unrelated work. PDK changes require the affected synthesis, timing, physical-design, or -FPGA validation flow and the ownership review defined by `.github/CODEOWNERS`. +FPGA validation flow and the ownership review defined by +[`../../.github/CODEOWNERS`](../../.github/CODEOWNERS). The supported CI PDKs are IHP130, GF180, ICS55, and SKY130. ICS55 obtains its locked H7CR standard-cell Liberty archive through diff --git a/pdk/generate_gf180_liberty.py b/physical/pdk/generate_gf180_liberty.py similarity index 98% rename from pdk/generate_gf180_liberty.py rename to physical/pdk/generate_gf180_liberty.py index 1b810b78..e1cce186 100644 --- a/pdk/generate_gf180_liberty.py +++ b/physical/pdk/generate_gf180_liberty.py @@ -7,7 +7,7 @@ import sys from pathlib import Path -ROOT = Path(__file__).resolve().parents[1] +ROOT = Path(__file__).resolve().parents[2] sys.path.insert(0, str(ROOT)) from scripts.setup_helpers import atomic_write # noqa: E402 diff --git a/pdk/generate_sky130_liberty.py b/physical/pdk/generate_sky130_liberty.py similarity index 98% rename from pdk/generate_sky130_liberty.py rename to physical/pdk/generate_sky130_liberty.py index 23e99cf8..8e9d0fd3 100644 --- a/pdk/generate_sky130_liberty.py +++ b/physical/pdk/generate_sky130_liberty.py @@ -10,7 +10,7 @@ import tempfile from pathlib import Path -ROOT = Path(__file__).resolve().parents[1] +ROOT = Path(__file__).resolve().parents[2] sys.path.insert(0, str(ROOT)) from scripts.setup_helpers import atomic_write # noqa: E402 diff --git a/pdk/prepare_ics55_liberty.py b/physical/pdk/prepare_ics55_liberty.py similarity index 98% rename from pdk/prepare_ics55_liberty.py rename to physical/pdk/prepare_ics55_liberty.py index 39ab9f28..f3693fd7 100644 --- a/pdk/prepare_ics55_liberty.py +++ b/physical/pdk/prepare_ics55_liberty.py @@ -12,7 +12,7 @@ from pathlib import Path from typing import Iterable -ROOT = Path(__file__).resolve().parents[1] +ROOT = Path(__file__).resolve().parents[2] sys.path.insert(0, str(ROOT)) from scripts.install_toolchain import safe_extract # noqa: E402 from scripts.setup_helpers import atomic_write, sha256 # noqa: E402 diff --git a/pdk/prepare_ics55_sim_model.py b/physical/pdk/prepare_ics55_sim_model.py similarity index 98% rename from pdk/prepare_ics55_sim_model.py rename to physical/pdk/prepare_ics55_sim_model.py index 8a1ce2c4..9a14b7f0 100644 --- a/pdk/prepare_ics55_sim_model.py +++ b/physical/pdk/prepare_ics55_sim_model.py @@ -9,7 +9,7 @@ import sys from pathlib import Path -ROOT = Path(__file__).resolve().parents[1] +ROOT = Path(__file__).resolve().parents[2] sys.path.insert(0, str(ROOT)) from scripts.setup_helpers import atomic_write, sha256 # noqa: E402 diff --git a/pdk/setup.py b/physical/pdk/setup.py similarity index 90% rename from pdk/setup.py rename to physical/pdk/setup.py index 3e0afa60..087257fe 100644 --- a/pdk/setup.py +++ b/physical/pdk/setup.py @@ -6,7 +6,8 @@ import sys from pathlib import Path -ROOT = Path(__file__).resolve().parents[1] +ROOT = Path(__file__).resolve().parents[2] +PDK_DIR = Path(__file__).resolve().parent sys.path.insert(0, str(ROOT)) from scripts.dependency_lock import archive, source # noqa: E402 from scripts.setup_helpers import download_file, ensure_git_repo # noqa: E402 @@ -39,7 +40,7 @@ def main() -> int: subprocess.run( ( sys.executable, - str(ROOT / "pdk/generate_gf180_liberty.py"), + str(PDK_DIR / "generate_gf180_liberty.py"), "--source", str(destination), "--output-dir", @@ -52,7 +53,7 @@ def main() -> int: subprocess.run( ( sys.executable, - str(ROOT / "pdk/generate_gf180_liberty.py"), + str(PDK_DIR / "generate_gf180_liberty.py"), "--source", str(destination), "--output-dir", @@ -67,7 +68,7 @@ def main() -> int: subprocess.run( ( sys.executable, - str(ROOT / "pdk/generate_gf180_liberty.py"), + str(PDK_DIR / "generate_gf180_liberty.py"), "--source", str(destination), "--output-dir", @@ -91,7 +92,7 @@ def main() -> int: subprocess.run( ( sys.executable, - str(ROOT / "pdk/generate_sky130_liberty.py"), + str(PDK_DIR / "generate_sky130_liberty.py"), "--source", str(destination), "--output-dir", @@ -104,7 +105,7 @@ def main() -> int: subprocess.run( ( sys.executable, - str(ROOT / "pdk/generate_sky130_liberty.py"), + str(PDK_DIR / "generate_sky130_liberty.py"), "--source", str(destination), "--output-dir", @@ -129,7 +130,7 @@ def main() -> int: subprocess.run( ( sys.executable, - str(ROOT / "pdk/prepare_ics55_liberty.py"), + str(PDK_DIR / "prepare_ics55_liberty.py"), "--archive", str(archive_path), "--output-dir", @@ -142,7 +143,7 @@ def main() -> int: subprocess.run( ( sys.executable, - str(ROOT / "pdk/prepare_ics55_sim_model.py"), + str(PDK_DIR / "prepare_ics55_sim_model.py"), "--source", str( destination diff --git a/physical/smoke/README.md b/physical/smoke/README.md new file mode 100644 index 00000000..bec38e5c --- /dev/null +++ b/physical/smoke/README.md @@ -0,0 +1,9 @@ +# Smoke Implementation Flows + +This directory contains the reproducible synthesis and static-timing source +flows used by smoke and regression coverage. `syn/` owns Yosys synthesis and +source export; `sta/` owns OpenSTA constraints and timing integration. + +Generated netlists, reports, and timing artifacts remain below the selected +`build//` directory. Run the flows through the root Makefile with a +committed profile; do not write generated output into this source tree. diff --git a/sta/README.md b/physical/smoke/sta/README.md similarity index 100% rename from sta/README.md rename to physical/smoke/sta/README.md diff --git a/sta/opensta/generate_sdc.py b/physical/smoke/sta/opensta/generate_sdc.py similarity index 98% rename from sta/opensta/generate_sdc.py rename to physical/smoke/sta/opensta/generate_sdc.py index bc53b687..35e3952f 100644 --- a/sta/opensta/generate_sdc.py +++ b/physical/smoke/sta/opensta/generate_sdc.py @@ -10,7 +10,7 @@ from pathlib import Path from typing import Any -ROOT = Path(__file__).resolve().parents[2] +ROOT = Path(__file__).resolve().parents[4] sys.path.insert(0, str(ROOT)) from rtl.mini.pin_map.generate_pin_map import read_map # noqa: E402 from scripts.check_clock_reset_domains import validate # noqa: E402 @@ -59,7 +59,7 @@ def parse_document(path: Path, pin_map: Path) -> tuple[list[dict[str, Any]], lis def render(domains: list[dict[str, Any]], reset_ports: list[str]) -> str: lines = [ - "# Generated by sta/opensta/generate_sdc.py; do not edit.", + "# Generated by physical/smoke/sta/opensta/generate_sdc.py; do not edit.", "# Core-STA baseline: pad/package timing is intentionally excluded.", "", "proc require_pins {label name} {", diff --git a/sta/opensta/opensta.mk b/physical/smoke/sta/opensta/opensta.mk similarity index 90% rename from sta/opensta/opensta.mk rename to physical/smoke/sta/opensta/opensta.mk index 70be7b5b..df8cfd81 100644 --- a/sta/opensta/opensta.mk +++ b/physical/smoke/sta/opensta/opensta.mk @@ -7,11 +7,11 @@ OPENSTA_LOG ?= $(STA_BUILD_ROOT)/opensta.log OPENSTA_METRICS ?= $(STA_BUILD_ROOT)/timing_metrics.rpt OPENSTA_CONFIG ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.config OPENSTA_SDC ?= $(STA_BUILD_ROOT)/retrosoc_core.sdc -OPENSTA_SDC_GEN := $(ROOT_PATH)/sta/opensta/generate_sdc.py +OPENSTA_SDC_GEN := $(ROOT_PATH)/physical/smoke/sta/opensta/generate_sdc.py OPENSTA_DOMAIN_MAP := $(ROOT_PATH)/rtl/mini/integration/clock_reset_domains.json OPENSTA_PIN_MAP := $(ROOT_PATH)/rtl/mini/pin_map/pin_map.json -include $(ROOT_PATH)/sta/opensta/pdk_timing.mk +include $(ROOT_PATH)/physical/smoke/sta/opensta/pdk_timing.mk $(OPENSTA_SDC): $(OPENSTA_SDC_GEN) $(OPENSTA_DOMAIN_MAP) $(OPENSTA_PIN_MAP) | manifest @mkdir -p $(dir $@) @@ -32,6 +32,6 @@ sta: $(OPENSTA_SDC) | manifest --env 'OPENSTA_LINK_LIBS=$(OPENSTA_LINK_LIBS)' --env 'OPENSTA_SRAM_LIBS=$(OPENSTA_SRAM_LIBS)' \ --env OPENSTA_SDC=$(OPENSTA_SDC) --env OPENSTA_REPORT=$(OPENSTA_REPORT) \ --env OPENSTA_METRICS=$(OPENSTA_METRICS) -- \ - $(OPENSTA) -no_init -exit -threads $(OPENSTA_THREADS) $(ROOT_PATH)/sta/opensta/opensta.tcl + $(OPENSTA) -no_init -exit -threads $(OPENSTA_THREADS) $(ROOT_PATH)/physical/smoke/sta/opensta/opensta.tcl .PHONY: sta \ No newline at end of file diff --git a/sta/opensta/opensta.tcl b/physical/smoke/sta/opensta/opensta.tcl similarity index 100% rename from sta/opensta/opensta.tcl rename to physical/smoke/sta/opensta/opensta.tcl diff --git a/sta/opensta/pdk_timing.mk b/physical/smoke/sta/opensta/pdk_timing.mk similarity index 51% rename from sta/opensta/pdk_timing.mk rename to physical/smoke/sta/opensta/pdk_timing.mk index bb58865a..e4cecaea 100644 --- a/sta/opensta/pdk_timing.mk +++ b/physical/smoke/sta/opensta/pdk_timing.mk @@ -1,20 +1,20 @@ # PDK-specific Liberty inputs for the reproducible core-STA baseline. ifeq ($(PDK),IHP130) -OPENSTA_LIBERTY := $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib -OPENSTA_LINK_LIBS := $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib +OPENSTA_LIBERTY := $(ROOT_PATH)/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib +OPENSTA_LINK_LIBS := $(ROOT_PATH)/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib ifeq ($(HAVE_SRAM_MACRO),YES) -OPENSTA_SRAM_LIBS := $(wildcard $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/lib/*_slow_1p08V_125C.lib) +OPENSTA_SRAM_LIBS := $(wildcard $(ROOT_PATH)/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/lib/*_slow_1p08V_125C.lib) endif else ifeq ($(PDK),GF180) OPENSTA_LIBERTY := $(ROOT_PATH)/.cache/retrosoc/pdk/gf180/gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50.lib OPENSTA_LINK_LIBS := $(ROOT_PATH)/.cache/retrosoc/pdk/gf180/gf180mcu_fd_io_retrosoc__ss_125C_4v50.lib else ifeq ($(PDK),SKY130) OPENSTA_LIBERTY := $(ROOT_PATH)/.cache/retrosoc/pdk/sky130/sky130_fd_sc_hd__ss_100C_1v40.lib -OPENSTA_LINK_LIBS := $(ROOT_PATH)/sta/opensta/sky130_io_blackbox.liberty +OPENSTA_LINK_LIBS := $(ROOT_PATH)/physical/smoke/sta/opensta/sky130_io_blackbox.liberty else ifeq ($(PDK),ICS55) OPENSTA_LIBERTY := $(ROOT_PATH)/.cache/retrosoc/pdk/ics55/ics55_h7cr_ss.lib -OPENSTA_LINK_LIBS := $(ROOT_PATH)/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/liberty/ICSIOA_N55_3P3_ss_1p08_2p97_125c.lib +OPENSTA_LINK_LIBS := $(ROOT_PATH)/physical/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/liberty/ICSIOA_N55_3P3_ss_1p08_2p97_125c.lib else $(error OpenSTA core-STA does not support PDK=$(PDK)) endif diff --git a/sta/opensta/retrosoc_pll.sdc b/physical/smoke/sta/opensta/retrosoc_pll.sdc similarity index 100% rename from sta/opensta/retrosoc_pll.sdc rename to physical/smoke/sta/opensta/retrosoc_pll.sdc diff --git a/sta/opensta/sky130_io_blackbox.liberty b/physical/smoke/sta/opensta/sky130_io_blackbox.liberty similarity index 100% rename from sta/opensta/sky130_io_blackbox.liberty rename to physical/smoke/sta/opensta/sky130_io_blackbox.liberty diff --git a/syn/Makefile b/physical/smoke/syn/Makefile similarity index 100% rename from syn/Makefile rename to physical/smoke/syn/Makefile diff --git a/syn/README.md b/physical/smoke/syn/README.md similarity index 100% rename from syn/README.md rename to physical/smoke/syn/README.md diff --git a/syn/tools/export_soc_sources.py b/physical/smoke/syn/tools/export_soc_sources.py similarity index 98% rename from syn/tools/export_soc_sources.py rename to physical/smoke/syn/tools/export_soc_sources.py index 57d8a32e..b201ce88 100644 --- a/syn/tools/export_soc_sources.py +++ b/physical/smoke/syn/tools/export_soc_sources.py @@ -12,7 +12,7 @@ import tempfile from pathlib import Path -REPO_ROOT = Path(__file__).resolve().parents[2] +REPO_ROOT = Path(__file__).resolve().parents[4] SCRIPT_DIR = REPO_ROOT / "rtl/mini/script" INTEGRATION_DIR = REPO_ROOT / "rtl/mini/integration" sys.path.insert(0, str(SCRIPT_DIR)) @@ -138,7 +138,7 @@ def defines_to_sv(defines: list[str]) -> list[str]: def write_single_sv(filelist: FileList, output: Path) -> None: lines = [ - "// Generated by syn/tools/export_soc_sources.py", + "// Generated by physical/smoke/syn/tools/export_soc_sources.py", *defines_to_sv(filelist.defines), "", ] diff --git a/syn/yosys/.gitignore b/physical/smoke/syn/yosys/.gitignore similarity index 100% rename from syn/yosys/.gitignore rename to physical/smoke/syn/yosys/.gitignore diff --git a/syn/yosys/script/abc-opt.script b/physical/smoke/syn/yosys/script/abc-opt.script similarity index 100% rename from syn/yosys/script/abc-opt.script rename to physical/smoke/syn/yosys/script/abc-opt.script diff --git a/syn/yosys/script/abc.constr b/physical/smoke/syn/yosys/script/abc.constr similarity index 100% rename from syn/yosys/script/abc.constr rename to physical/smoke/syn/yosys/script/abc.constr diff --git a/syn/yosys/script/cell_dont_use.py b/physical/smoke/syn/yosys/script/cell_dont_use.py similarity index 100% rename from syn/yosys/script/cell_dont_use.py rename to physical/smoke/syn/yosys/script/cell_dont_use.py diff --git a/syn/yosys/script/common.tcl b/physical/smoke/syn/yosys/script/common.tcl similarity index 100% rename from syn/yosys/script/common.tcl rename to physical/smoke/syn/yosys/script/common.tcl diff --git a/syn/yosys/script/filter_output.awk b/physical/smoke/syn/yosys/script/filter_output.awk similarity index 100% rename from syn/yosys/script/filter_output.awk rename to physical/smoke/syn/yosys/script/filter_output.awk diff --git a/syn/yosys/script/init_tech.tcl b/physical/smoke/syn/yosys/script/init_tech.tcl similarity index 94% rename from syn/yosys/script/init_tech.tcl rename to physical/smoke/syn/yosys/script/init_tech.tcl index 880de01e..0ee114df 100644 --- a/syn/yosys/script/init_tech.tcl +++ b/physical/smoke/syn/yosys/script/init_tech.tcl @@ -18,12 +18,12 @@ # See the Mulan PSL v2 for more details. # get environment variables -set root_dir [file dirname [file dirname [file dirname [file dirname [info script]]]]] +set root_dir [file normalize [file join [file dirname [info script]] ../../../../..]] puts "0. Executing init_tech: load technology from Github PDK" if {$pdk == "IHP130"} { - set pdk_dir "$root_dir/pdk/IHP-Open-PDK" + set pdk_dir "$root_dir/physical/pdk/IHP-Open-PDK" set pdk_cells_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib set pdk_sram_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_sram/lib set pdk_io_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_io/lib @@ -34,7 +34,7 @@ if {$pdk == "IHP130"} { set tech_cell_tiehi {sg13g2_tiehi L_HI} set tech_cell_tielo {sg13g2_tielo L_LO} } elseif {$pdk == "ICS55"} { - set pdk_dir "$root_dir/pdk/icsprout55-pdk" + set pdk_dir "$root_dir/physical/pdk/icsprout55-pdk" set pdk_cells_lib "$root_dir/.cache/retrosoc/pdk/ics55" set pdk_io_lib "${pdk_dir}/IP/IO/ICsprout_55LLULP1233_IO_251013/liberty" set tech_cells [list "$pdk_cells_lib/ics55_h7cr_tt.lib"] diff --git a/syn/yosys/script/synth.tcl b/physical/smoke/syn/yosys/script/synth.tcl similarity index 100% rename from syn/yosys/script/synth.tcl rename to physical/smoke/syn/yosys/script/synth.tcl diff --git a/syn/yosys/synth_config.mk b/physical/smoke/syn/yosys/synth_config.mk similarity index 100% rename from syn/yosys/synth_config.mk rename to physical/smoke/syn/yosys/synth_config.mk diff --git a/syn/yosys/yosys.mk b/physical/smoke/syn/yosys/yosys.mk similarity index 100% rename from syn/yosys/yosys.mk rename to physical/smoke/syn/yosys/yosys.mk diff --git a/pyproject.toml b/pyproject.toml index e0db68e0..f10b09c3 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -11,8 +11,8 @@ extend-exclude = [ "dist", "app/coremark/coremark-main", "app/fatfs/ff16", - "pdk/IHP-Open-PDK", - "pdk/icsprout55-pdk", + "physical/pdk/IHP-Open-PDK", + "physical/pdk/icsprout55-pdk", "rtl/managed/clusterip", "rtl/managed/third_party", "rtl/managed/mpw", diff --git a/rtl/filelist/pdk_gf180.fl b/rtl/filelist/pdk_gf180.fl index 92e6646e..fb2392b4 100644 --- a/rtl/filelist/pdk_gf180.fl +++ b/rtl/filelist/pdk_gf180.fl @@ -2,7 +2,7 @@ # Technology wrappers instantiate these models directly in RTL simulation. /tech/gf180_io_sim_cells.v /tech/gf180_seq_sim_cells.v -/pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.functional.v -/pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.functional.v -/pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.functional.v -/pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.functional.v +/physical/pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.functional.v +/physical/pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.functional.v +/physical/pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.functional.v +/physical/pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.functional.v diff --git a/rtl/filelist/pdk_ics55.fl b/rtl/filelist/pdk_ics55.fl index bf3686cd..50b3aa64 100644 --- a/rtl/filelist/pdk_ics55.fl +++ b/rtl/filelist/pdk_ics55.fl @@ -1,3 +1,3 @@ +define+functional /cache/retrosoc/pdk/ics55/ics55_h7cr_functional.v -/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v +/physical/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v diff --git a/rtl/filelist/pdk_ihp130.fl b/rtl/filelist/pdk_ihp130.fl index 1468688c..e13aa61c 100644 --- a/rtl/filelist/pdk_ihp130.fl +++ b/rtl/filelist/pdk_ihp130.fl @@ -1,4 +1,4 @@ -/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v -/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v -/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v -/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v +/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v +/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v +/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v +/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v diff --git a/rtl/filelist/pdk_sky130.fl b/rtl/filelist/pdk_sky130.fl index fb2f267c..d2eb5d04 100644 --- a/rtl/filelist/pdk_sky130.fl +++ b/rtl/filelist/pdk_sky130.fl @@ -1,12 +1,12 @@ # SKY130 standard-cell models are selected by gen_iverilog_filelist.py. # Technology wrappers instantiate these functional models directly in RTL simulation. +define+FUNCTIONAL -+incdir+/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf -+incdir+/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv -+incdir+/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2 -+incdir+/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/xor2 ++incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf ++incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv ++incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2 ++incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/xor2 /tech/sky130_io_sim_cells.v -/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v -/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_1.v -/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v -/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/xor2/sky130_fd_sc_hd__xor2_1.v +/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v +/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_1.v +/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v +/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/xor2/sky130_fd_sc_hd__xor2_1.v diff --git a/rtl/mini/lint.msg b/rtl/mini/lint.msg index 08540928..6ac77bb4 100644 --- a/rtl/mini/lint.msg +++ b/rtl/mini/lint.msg @@ -1,5 +1,5 @@ { +lint=all; - -file=/hazard3/arith/hazard3_muldiv_seq.v,/hazard3/hazard3_frontend.v,/hazard3/arith/hazard3_onehot_encode.v,/hazard3/hazard3_instr_decompress.v,/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/verilog/ics55_LLSC_H7CL.v,/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CH/verilog/ics55_LLSC_H7CH.v,/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v,/clusterip/i2c/model/at24cxxx.sv,/clusterip/spi/model/w25q128jvxim.sv,/clusterip/common/rtl/cdc/cdc_2phase.sv,/clusterip/common/rtl/utils/register.sv,/model/uart_model.sv,/tb/retrosoc_tb.sv,/clusterip/i2s/model/mic.sv,/model/ESP_PSRAM64H.sv,/third_party/model/sdram/sdr.v; + -file=/hazard3/arith/hazard3_muldiv_seq.v,/hazard3/hazard3_frontend.v,/hazard3/arith/hazard3_onehot_encode.v,/hazard3/hazard3_instr_decompress.v,/physical/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v,/physical/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v,/physical/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/verilog/ics55_LLSC_H7CL.v,/physical/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CH/verilog/ics55_LLSC_H7CH.v,/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v,/clusterip/i2c/model/at24cxxx.sv,/clusterip/spi/model/w25q128jvxim.sv,/clusterip/common/rtl/cdc/cdc_2phase.sv,/clusterip/common/rtl/utils/register.sv,/model/uart_model.sv,/tb/retrosoc_tb.sv,/clusterip/i2s/model/mic.sv,/model/ESP_PSRAM64H.sv,/third_party/model/sdram/sdr.v; } { +warn=all; } diff --git a/rtl/mini/mk/iverilog.mk b/rtl/mini/mk/iverilog.mk index 26f41648..5d0dc6b0 100644 --- a/rtl/mini/mk/iverilog.mk +++ b/rtl/mini/mk/iverilog.mk @@ -3,8 +3,8 @@ VVP ?= vvp GTKWAVE ?= gtkwave NETLIST_PATH ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v -POST_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic.v -SDF_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz +POST_PATH ?= $(ROOT_PATH)/physical/sdf/retrosoc_asic.v +SDF_PATH ?= $(ROOT_PATH)/physical/sdf/retrosoc_asic_CTS_MIN.sdf.gz SDF_SCOPE ?= $(RTL_TOP).u_retrosoc_asic IVERILOG_ROOT := $(SIM_BUILD_ROOT) diff --git a/rtl/mini/mk/vcs.mk b/rtl/mini/mk/vcs.mk index ea1ba599..3fbfe08f 100644 --- a/rtl/mini/mk/vcs.mk +++ b/rtl/mini/mk/vcs.mk @@ -11,8 +11,8 @@ COMP_LOG := -l compile.log SIM_LOG := -l sim.log # netlist file path NETLIST_PATH := -v $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v -POST_PATH := -v $(ROOT_PATH)/pd/sdf/retrosoc_asic.v -SDF_PATH := "$(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz" +POST_PATH := -v $(ROOT_PATH)/physical/sdf/retrosoc_asic.v +SDF_PATH := "$(ROOT_PATH)/physical/sdf/retrosoc_asic_CTS_MIN.sdf.gz" # testbench filelist TB_FLIST := -f $(GENERATED_FL_DIR)/tb.fl @@ -75,7 +75,7 @@ $(VCS_POST_SIMV): DIR := $(VCS_POST_DIR) $(VCS_POST_SIMV): FLIST := $(POST_PATH) $(NET_FLIST) $(TB_FLIST) $(VCS_POST_SIMV): OPTS := $(POST_OPTS) $(VCS_POST_SIMV): DEPFILE := $(VCS_POST_DEPFILE) -$(VCS_POST_SIMV): DEPS_ARGS := $(NET_FLIST) -f $(GENERATED_FL_DIR)/tb.fl --extra $(ROOT_PATH)/pd/sdf/retrosoc_asic.v --extra $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz +$(VCS_POST_SIMV): DEPS_ARGS := $(NET_FLIST) -f $(GENERATED_FL_DIR)/tb.fl --extra $(ROOT_PATH)/physical/sdf/retrosoc_asic.v --extra $(ROOT_PATH)/physical/sdf/retrosoc_asic_CTS_MIN.sdf.gz sim: DIR := $(VCS_BEHV_DIR) netsim: DIR := $(VCS_NETL_DIR) @@ -102,7 +102,7 @@ $(VCS_BEHV_SIMV) $(VCS_NETL_SIMV) $(VCS_POST_SIMV): $(MPW_VARIANT_STAMP) $(FILEL $(FLOW_PYTHON) $(RTL_PATH)/script/filelist_deps.py $(DEPS_ARGS) --target $@ --output $(DEPFILE) $(VCS_NETL_SIMV): $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v -$(VCS_POST_SIMV): $(ROOT_PATH)/pd/sdf/retrosoc_asic.v $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz +$(VCS_POST_SIMV): $(ROOT_PATH)/physical/sdf/retrosoc_asic.v $(ROOT_PATH)/physical/sdf/retrosoc_asic_CTS_MIN.sdf.gz sim netsim postsim: $(FLOW_PYTHON) $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(DIR) \ diff --git a/rtl/mini/script/gen_iverilog_filelist.py b/rtl/mini/script/gen_iverilog_filelist.py index e4536601..2b25dae2 100644 --- a/rtl/mini/script/gen_iverilog_filelist.py +++ b/rtl/mini/script/gen_iverilog_filelist.py @@ -61,7 +61,7 @@ def _standard_cell_models(pdk: str, netlist: Path | None = None) -> list[Path]: if pdk == "GF180": cells_dir = ( ROOT_DIR - / "pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells" + / "physical/pdk/gf180mcu-pdk/libraries/gf180mcu_fd_sc_mcu7t5v0/latest/cells" ) sequential_models = { "gf180mcu_fd_sc_mcu7t5v0__dffq_1", @@ -77,7 +77,9 @@ def _standard_cell_models(pdk: str, netlist: Path | None = None) -> list[Path]: ), ] if pdk == "SKY130": - cells_dir = ROOT_DIR / "pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells" + cells_dir = ( + ROOT_DIR / "physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells" + ) if netlist is None: raise ValueError("SKY130 standard-cell models require a netlist") cell_models = { diff --git a/rtl/mini/script/generate_filelist.py b/rtl/mini/script/generate_filelist.py index 3d4d84e3..522079a6 100644 --- a/rtl/mini/script/generate_filelist.py +++ b/rtl/mini/script/generate_filelist.py @@ -17,7 +17,7 @@ DEFAULT_OUTPUT_DIR = MINI_DIR / ".generated_fl" PATH_PREFIXES = { "cache": ROOT_DIR / ".cache", - "pdk": ROOT_DIR / "pdk", + "physical": ROOT_DIR / "physical", "clusterip": RTL_DIR / "managed" / "clusterip", "ip": RTL_DIR / "ip", "third_party": RTL_DIR / "managed" / "third_party", diff --git a/scripts/analyze_warnings.py b/scripts/analyze_warnings.py index 6c5359f6..153540a4 100644 --- a/scripts/analyze_warnings.py +++ b/scripts/analyze_warnings.py @@ -63,6 +63,7 @@ def normalize(root: Path, identifier: str, message: str) -> str: value, ) value = value.replace(resolved_root, "$ROOT") + value = value.replace("$ROOT/physical/pdk/", "$ROOT/pdk/") value = GENERATED_MPW_PATH_RE.sub(_normalize_generated_mpw_path, value) value = LOCATION_RE.sub(lambda match: match.group("path") + ":", value) value = re.sub(r"\s+", " ", value) diff --git a/scripts/package.py b/scripts/package.py index a53cd4bf..3518c9af 100644 --- a/scripts/package.py +++ b/scripts/package.py @@ -102,7 +102,7 @@ def main() -> int: staging.mkdir() command = [ "python3", - str(root / "syn/tools/export_soc_sources.py"), + str(root / "physical/smoke/syn/tools/export_soc_sources.py"), "sv", "--output-dir", str(staging), diff --git a/tests/test_script_tools.py b/tests/test_script_tools.py index 9c97ef02..7a3ae716 100644 --- a/tests/test_script_tools.py +++ b/tests/test_script_tools.py @@ -118,8 +118,10 @@ def test_generate_all_is_stable_and_expands_paths(tmp_path: Path) -> None: ) cluster = (tmp_path / "clusterip.fl").read_text(encoding="utf-8") hazard3 = (tmp_path / "core_hazard3.fl").read_text(encoding="utf-8") + ihp130 = (tmp_path / "pdk_ihp130.fl").read_text(encoding="utf-8") assert str(ROOT / "rtl/managed/clusterip") in cluster assert str(ROOT / "rtl/managed/hazard3/hdl") in hazard3 + assert str(ROOT / "physical/pdk/IHP-Open-PDK") in ihp130 assert "rtl/managed/mpw/core/username3" not in hazard3 assert (tmp_path / "core_hazard3.fl").is_file() assert not (tmp_path / "core_picorv32.fl").exists() @@ -147,7 +149,7 @@ def test_filelist_round_trips_verilog_define_values(tmp_path: Path) -> None: def test_source_export_uses_the_fixed_hazard3_management_core(tmp_path: Path) -> None: - module_path = ROOT / "syn/tools/export_soc_sources.py" + module_path = ROOT / "physical/smoke/syn/tools/export_soc_sources.py" spec = importlib.util.spec_from_file_location("retrosoc_source_export", module_path) assert spec is not None and spec.loader is not None source_export = importlib.util.module_from_spec(spec) @@ -1305,6 +1307,22 @@ def test_warning_normalization_keeps_ranges_and_removes_variant_hash(tmp_path: P ) +def test_warning_normalization_preserves_pdk_signatures(tmp_path: Path) -> None: + message = ( + f"{tmp_path}/physical/pdk/IHP-Open-PDK/ihp-sg13g2/" + "libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v:42: " + "Ignoring unsupported specify block" + ) + + normalized = normalize(tmp_path, "SPECIFYIGN", message) + + assert normalized == ( + "SPECIFYIGN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/" + "libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v:: " + "Ignoring unsupported specify block" + ) + + def test_warning_normalization_maps_isolated_mpw_sources_to_managed_sources( tmp_path: Path, ) -> None: diff --git a/tests/test_sta_constraints.py b/tests/test_sta_constraints.py index 354556f2..b3d54bb3 100644 --- a/tests/test_sta_constraints.py +++ b/tests/test_sta_constraints.py @@ -14,11 +14,11 @@ from pathlib import Path ROOT = Path(__file__).resolve().parents[1] DOMAINS = ROOT / "rtl/mini/integration/clock_reset_domains.json" PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json" -GENERATOR = ROOT / "sta/opensta/generate_sdc.py" -OPENSTA_MAKEFILE = ROOT / "sta/opensta/opensta.mk" -GF180_GENERATOR = ROOT / "pdk/generate_gf180_liberty.py" -ICS55_PREPARER = ROOT / "pdk/prepare_ics55_liberty.py" -ICS55_SIM_MODEL_PREPARER = ROOT / "pdk/prepare_ics55_sim_model.py" +GENERATOR = ROOT / "physical/smoke/sta/opensta/generate_sdc.py" +OPENSTA_MAKEFILE = ROOT / "physical/smoke/sta/opensta/opensta.mk" +GF180_GENERATOR = ROOT / "physical/pdk/generate_gf180_liberty.py" +ICS55_PREPARER = ROOT / "physical/pdk/prepare_ics55_liberty.py" +ICS55_SIM_MODEL_PREPARER = ROOT / "physical/pdk/prepare_ics55_sim_model.py" def generate(domains: Path, output: Path) -> subprocess.CompletedProcess[str]: