From 7eda4e6c46f3d37ae8c44d80106279e663af1276 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 15 Aug 2026 08:33:27 +0800 Subject: [PATCH] refactor: refactor RTL style checker and update test cases - Enhanced the RTL style checker script to include new diagnostic rules for function declarations, primary design units, and synthesis exclusions. - Added functions to handle audit issues, ensuring that the audit records match the current inventory of RTL files. - Updated test cases to reflect changes in RTL file names and paths, ensuring consistency with the new naming conventions. - Introduced additional tests for style violations, including mismatched primary design units and synthesizable initial blocks. - Adjusted file paths in various test files to align with the new RTL structure and naming conventions. --- AGENTS.md | 4 + Makefile | 3 +- docs/README.md | 3 + docs/rtl-coding-style-compliance.md | 84 +++ quality/warnings/ihp130/rtl-lint.json | 692 ++++++------------ rtl/README.md | 5 + rtl/ip/experimental/axi4f2ribp.sv | 5 +- rtl/ip/experimental/{gpu.sv => ribp_gpu.sv} | 0 rtl/ip/experimental/sdio_cache.sv | 9 - rtl/ip/experimental/sdio_clkgen.sv | 9 - rtl/ip/experimental/sdio_cmd.sv | 9 - rtl/ip/experimental/sdio_core.sv | 9 - rtl/ip/experimental/sdio_dat.sv | 9 - rtl/ip/experimental/sdio_init.sv | 9 - rtl/ip/experimental/sdio_reg.sv | 9 - rtl/ip/interconnect/axi4l2ribp.sv | 101 +-- rtl/ip/interconnect/ribp2ribp.sv | 2 + rtl/ip/interconnect/ribp_regslice.sv | 30 +- rtl/ip/memory/{sdram.sv => axi4_sdram.sv} | 17 +- rtl/ip/memory/opipsram_core.sv | 10 - rtl/ip/memory/psram_core.sv | 364 ++++----- .../memory/{opipsram.sv => ribp_opipsram.sv} | 14 +- rtl/ip/memory/{psram.sv => ribp_psram.sv} | 181 ++--- rtl/ip/memory/sdram_core.sv | 304 ++++---- rtl/ip/memory/sdram_reg.sv | 6 +- rtl/ip/multimedia/{dvp.sv => axi4s_dvp.sv} | 61 +- rtl/ip/multimedia/dvp_core.sv | 2 +- rtl/ip/multimedia/dvp_define.svh | 10 +- rtl/ip/multimedia/dvp_reg.sv | 2 +- rtl/ip/peripheral/clint_core.sv | 18 +- rtl/ip/peripheral/clint_define.svh | 2 +- rtl/ip/peripheral/clint_reg.sv | 18 +- rtl/ip/peripheral/clint_timebase.sv | 4 +- rtl/ip/peripheral/dma_core.sv | 46 +- rtl/ip/peripheral/gpio_core.sv | 18 +- rtl/ip/peripheral/gpio_define.svh | 2 +- rtl/ip/peripheral/gpio_reg.sv | 16 +- rtl/ip/peripheral/ribp_clint.sv | 12 +- rtl/ip/peripheral/{dma.sv => ribp_dma.sv} | 22 +- rtl/ip/peripheral/ribp_gpio.sv | 12 +- .../{sysctrl.sv => ribp_sysctrl.sv} | 32 +- rtl/ip/peripheral/ribp_timer.sv | 2 +- rtl/ip/peripheral/timer_core.sv | 38 +- rtl/ip/peripheral/timer_define.svh | 2 +- rtl/ip/peripheral/timer_reg.sv | 2 +- rtl/ip/serial/i2c_core.sv | 2 +- rtl/ip/serial/i2c_filter.sv | 2 +- rtl/ip/serial/i2c_reg.sv | 4 +- rtl/ip/serial/i2s_core.sv | 2 +- rtl/ip/serial/i2s_define.svh | 2 +- rtl/ip/serial/i2s_reg.sv | 4 +- rtl/ip/serial/ribp_i2c.sv | 2 +- rtl/ip/serial/ribp_i2c_define.svh | 2 +- rtl/ip/serial/{i2s.sv => ribp_i2s.sv} | 22 +- rtl/ip/serial/ribp_uart.sv | 2 +- rtl/ip/serial/ribp_uart_define.svh | 2 +- rtl/ip/serial/ribp_uart_rx.sv | 2 +- rtl/ip/serial/ribp_uart_tx.sv | 2 +- rtl/ip/serial/ribp_ws2812.sv | 8 +- rtl/ip/serial/uart_baudgen.sv | 2 +- rtl/ip/serial/uart_core.sv | 2 +- rtl/ip/serial/uart_flow_ctrl.sv | 2 +- rtl/ip/serial/uart_reg.sv | 4 +- rtl/ip/serial/ws2812_core.sv | 2 +- rtl/ip/serial/ws2812_define.svh | 2 +- rtl/ip/serial/ws2812_reg.sv | 2 +- rtl/ip/storage/{sdio.sv => ribp_sdio.sv} | 18 +- rtl/ip/storage/{spisd.sv => ribp_spisd.sv} | 13 +- rtl/ip/storage/{xpi.sv => ribp_xpi.sv} | 101 +-- rtl/ip/storage/spisd_cache.sv | 56 +- rtl/ip/storage/spisd_data.sv | 42 +- rtl/ip/storage/spisd_init.sv | 250 ++++--- rtl/ip/storage/spisd_read.sv | 212 +++--- rtl/ip/storage/spisd_reg.sv | 8 +- rtl/ip/storage/spisd_write.sv | 208 +++--- rtl/ip/storage/xpi_core.sv | 110 +-- rtl/ip/storage/xpi_define.svh | 2 +- rtl/ip/storage/xpi_mm.sv | 134 ++-- rtl/ip/storage/xpi_reg.sv | 56 +- rtl/ip/util/async_fifo.sv | 75 +- ...otocol_sva.sv => axi4_interconnect_sva.sv} | 10 +- rtl/mini/filelist/ip.fl | 21 +- rtl/mini/filelist/top.fl | 8 +- rtl/mini/formal/generate_formal_filelist.py | 5 +- rtl/mini/integration/clock_reset_domains.json | 12 +- rtl/mini/mk/formal.mk | 7 +- rtl/mini/top/axi4_bus.sv | 192 +++++ rtl/mini/top/axi4_interconnect.sv | 263 +++---- rtl/mini/top/core_wrapper.sv | 22 +- rtl/mini/top/ip_apb_wrapper.sv | 4 +- rtl/mini/top/ip_ribp_wrapper.sv | 68 +- rtl/mini/top/mgmt_core_wrapper.sv | 4 +- rtl/mini/top/onchip_ram.sv | 68 +- rtl/mini/top/pll_rcu_controller.sv | 274 +++++++ rtl/mini/top/rcu.sv | 263 ------- rtl/mini/top/retrosoc.sv | 48 +- rtl/mini/top/rib2apb.sv | 2 +- rtl/mini/top/{bus.sv => rib_bus.sv} | 245 +------ rtl/mini/top/ribp2rib.sv | 4 +- ...design_template.sv => user_core_design.sv} | 4 +- rtl/mini/top/user_core_top.sv | 4 +- rtl/mini/top/user_extensions.svh | 4 +- rtl/mini/top/user_ip_design_template.sv | 8 +- rtl/mini/top/user_ip_top.sv | 2 +- rtl/mini/top/user_ip_wrapper.sv | 2 +- rtl/rtl_style_audit.json | 284 +++++++ scripts/check_rtl_style.py | 383 +++++++++- tests/test_dma.py | 2 +- tests/test_dvp.py | 2 +- tests/test_memory_map.py | 9 +- tests/test_rib.py | 2 +- tests/test_rtl_style.py | 123 +++- tests/test_script_tools.py | 9 +- tests/test_sdram.py | 4 +- tests/test_ws2812.py | 2 +- tests/test_xpi_io.py | 2 +- 116 files changed, 3310 insertions(+), 2624 deletions(-) create mode 100644 docs/rtl-coding-style-compliance.md rename rtl/ip/experimental/{gpu.sv => ribp_gpu.sv} (100%) delete mode 100644 rtl/ip/experimental/sdio_cache.sv delete mode 100644 rtl/ip/experimental/sdio_clkgen.sv delete mode 100644 rtl/ip/experimental/sdio_cmd.sv delete mode 100644 rtl/ip/experimental/sdio_core.sv delete mode 100644 rtl/ip/experimental/sdio_dat.sv delete mode 100644 rtl/ip/experimental/sdio_init.sv delete mode 100644 rtl/ip/experimental/sdio_reg.sv rename rtl/ip/memory/{sdram.sv => axi4_sdram.sv} (89%) delete mode 100644 rtl/ip/memory/opipsram_core.sv rename rtl/ip/memory/{opipsram.sv => ribp_opipsram.sv} (80%) rename rtl/ip/memory/{psram.sv => ribp_psram.sv} (64%) rename rtl/ip/multimedia/{dvp.sv => axi4s_dvp.sv} (86%) rename rtl/ip/peripheral/{dma.sv => ribp_dma.sv} (95%) rename rtl/ip/peripheral/{sysctrl.sv => ribp_sysctrl.sv} (96%) rename rtl/ip/serial/{i2s.sv => ribp_i2s.sv} (90%) rename rtl/ip/storage/{sdio.sv => ribp_sdio.sv} (77%) rename rtl/ip/storage/{spisd.sv => ribp_spisd.sv} (91%) rename rtl/ip/storage/{xpi.sv => ribp_xpi.sv} (81%) rename rtl/mini/dv/sva/{axi4_protocol_sva.sv => axi4_interconnect_sva.sv} (92%) create mode 100644 rtl/mini/top/axi4_bus.sv create mode 100644 rtl/mini/top/pll_rcu_controller.sv rename rtl/mini/top/{bus.sv => rib_bus.sv} (80%) rename rtl/mini/top/{user_core_design_template.sv => user_core_design.sv} (94%) create mode 100644 rtl/rtl_style_audit.json diff --git a/AGENTS.md b/AGENTS.md index 65c14dbf..cb74a939 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -22,6 +22,10 @@ truth wins. `quality/metrics/policy.json` define the active quality policy. - [rtl/README.md](rtl/README.md) defines the self-owned SystemVerilog naming, register-state, macro, and formatting conventions. +- [docs/rtl-coding-style.md](docs/rtl-coding-style.md) is the normative + self-owned RTL policy; [docs/rtl-coding-style-compliance.md](docs/rtl-coding-style-compliance.md) + defines the required audit, equivalence-preserving migration, and validation + process. Do not guess a profile, tool version, dependency revision, or generated-file location. Inspect the corresponding source of truth first. diff --git a/Makefile b/Makefile index c4f49add..05950616 100644 --- a/Makefile +++ b/Makefile @@ -445,7 +445,8 @@ rtl-style-check: rtl-style-check-all: python3 $(ROOT_PATH)/scripts/check_rtl_style.py --root $(ROOT_PATH) \ - --profile owned --verible-verilog-lint $(VERIBLE_LINT) + --profile owned --enforce-naming --audit $(ROOT_PATH)/rtl/rtl_style_audit.json \ + --verible-verilog-lint $(VERIBLE_LINT) rtl-readiness-check: python3 $(ROOT_PATH)/scripts/check_rtl_readiness.py --root $(ROOT_PATH) diff --git a/docs/README.md b/docs/README.md index 950ce5e7..f78670c3 100644 --- a/docs/README.md +++ b/docs/README.md @@ -9,6 +9,9 @@ the root README and subsystem guides. Docker, Nix, and manual open-source regression environments. - [misra-c-2012.md](misra-c-2012.md) defines the MISRA C:2012 Amendment 2 baseline, scope, partial automation, and deviation process. +- [rtl-coding-style.md](rtl-coding-style.md) is the normative self-owned RTL + policy; [rtl-coding-style-compliance.md](rtl-coding-style-compliance.md) + defines its executable audit and behavior-preserving migration process. - [pll-clock-control.md](pll-clock-control.md) describes the SYSCTRL PLL register protocol and software quiesce contract. - [hazard3-debug.md](hazard3-debug.md) defines the management Hazard3 JTAG diff --git a/docs/rtl-coding-style-compliance.md b/docs/rtl-coding-style-compliance.md new file mode 100644 index 00000000..824a6b44 --- /dev/null +++ b/docs/rtl-coding-style-compliance.md @@ -0,0 +1,84 @@ +# RTL Coding Style Compliance + +This document defines the executable compliance process for self-owned RTL. +The normative requirements remain in [RTL Coding Style](rtl-coding-style.md); +this document records how those requirements are reviewed, enforced, and +validated without changing functional behavior. + +## Scope and Evidence + +The owned profile in +[`rtl/rtl_style_manifest.json`](../rtl/rtl_style_manifest.json) is the source +of truth for the reviewed source set. It includes `rtl/ip/**` and +`rtl/mini/top/**`, but excludes managed, generated, PDK, formal, device-model, +and third-party sources. + +[`rtl/rtl_style_audit.json`](../rtl/rtl_style_audit.json) records the exact +owned files, policy revision, review method, and reviewed integration +boundaries. The audit record is evidence of review, not a waiver or a warning +baseline. It must be refreshed whenever a source enters or leaves the owned +profile. + +A reviewed boundary does not hide a remediable violation. It is limited to a +behavior-preservation block, such as dual-clock storage, inferred memory, a +technology pin boundary, or priority-sensitive sequential logic. The audit +record names its owner, related commit, expiry condition, and removal plan; +the block must be removed by an isolated, equivalence-validated change. + +## Rule Matrix + +| Rule group | Policy sections | Evidence | +| --- | --- | --- | +| File and primary-unit ownership | 2 | Full-profile checker verifies a primary design unit and its file name; filelist and elaboration checks validate moves. | +| Restricted SystemVerilog subset | 3 | `check_rtl_style.py`, Verible, and simulator compilation reject prohibited timing controls, tasks, positional connections, wildcard connections, implicit nets, `defparam`, `casex`, and legacy procedural blocks. | +| Naming, types, packages, and macros | 4 | Full-profile naming check enforces staged module, port, interface, enum, parameter, macro, and reset spelling rules. Review verifies public protocol and PDK names remain at their compatibility boundaries. | +| Structure and connections | 5 | Checker and Verible validate named connections, generated-block labels, net restrictions, and format hygiene. Review verifies one-driver ownership, explicit unused-output rationale, and declared-before-use ordering. | +| Combinational, sequential, and FSM logic | 6 | Review checks defaults, assignment style, reset/update priority, state naming, Common primitive selection, and illegal-state behavior. Structural register rewrites require cycle or sequential-equivalence evidence. | +| Width, signedness, and invalid values | 7 | Verilator lint and review cover explicit widths, casts, predicates, dynamic indices, and X/Z restrictions. | +| Clock, reset, CDC, and interfaces | 8 | Module-boundary comments, `clock_reset_domains.json`, CDC primitive review, protocol tests, and affected simulator runs supply evidence. | +| Assertions and readiness | 9 | Applicable SVA/formal tests and `rtl-readiness-check-all` supplement functional simulation; readiness metadata is not a substitute for verification. | +| Formatting and comments | 10 | `rtl-format-check` and the full-profile style check enforce ASCII, whitespace, final newline, line length, and paired formatter directives. A formatter-disabled span must be narrow and state why aligned declarations cannot be preserved otherwise. | + +## Behavior-Preserving Migration + +Style work must not alter storage behavior, reset precedence, CDC behavior, +protocol timing, register ABI, or software-observable behavior. Apply the +following sequence for every change: + +1. Rename an owned file, module, or internal identifier only after locating + every filelist, testbench, formal harness, generator, and documentation + consumer. +2. Keep protocol fields, PDK pins, and managed IP names at their boundary. + Adapt them only from owned RTL; never edit managed or PDK source to make a + local style check pass. +3. Prefer ClusterIP Common `dffr`, `dffer`, `dffrc`, `dfferc`, CDC, FIFO, and + register components when they exactly preserve the existing reset and + enable semantics. Do not replace inferred memories, dual-clock storage, or + priority-sensitive sequential logic without equivalence evidence. +4. Treat a simulation, formal, synthesis, timing, or software-visible + difference as a blocker. Record it as a separate functional issue rather + than resolving it as part of a style migration. + +## Formatter Exceptions + +The root `.verible-format` configuration normally aligns module ports, +parameters, macros, named ports, and assignments. Use +`// verilog_format: off/on` only for the smallest declaration or macro table +that Verible cannot preserve. The `off` line must state the alignment reason; +the paired `on` line must follow immediately after the exceptional region. + +## Required Validation + +Run these commands after a full owned-profile migration: + +```sh +make rtl-format-check rtl-style-check-all rtl-readiness-check-all +make CONFIG=configs/ci/ihp130.mk SIMU=VERILATOR HAVE_SVA=YES rtl-lint +python3 -m pytest -q +python3 scripts/regress.py --root . --suite pr --pdk IHP130 --netsim-boot-only +``` + +The boot-only netlist target terminates Icarus only after `Hello retroSoC!` is +observed. The regression runner continues with the remaining OpenSTA, warning, +and metrics observations. Review warning and metric deltas from the successful +variant; never hand-edit warning signatures. diff --git a/quality/warnings/ihp130/rtl-lint.json b/quality/warnings/ihp130/rtl-lint.json index 38036f61..a34ef186 100644 --- a/quality/warnings/ihp130/rtl-lint.json +++ b/quality/warnings/ihp130/rtl-lint.json @@ -1,10 +1,5 @@ { "entries": [ - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/memory/opipsram.sv:: Signal is not used: 'dummy1'", - "signature": "008d95747db7d189" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'U_MODE'", @@ -40,11 +35,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_BREV8'", "signature": "0466b2d33d754335" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/memory/opipsram.sv:: Signal is not used: 'dummy0'", - "signature": "04bac65dbc35e317" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT24'", @@ -60,11 +50,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER21'", "signature": "05b67f901c971eb6" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv:: Instance pin connected by name with empty reference: 'cnt_o'", - "signature": "06196c17d5f6490d" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_A'", @@ -85,6 +70,11 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/store_decoder.v:: Filename 'store_decoder' does not match MODULE name: 'mpw_core_kianv_rv32i_store_decoder'", "signature": "078a551602e8a9bd" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/sdram_core.sv:: Bits of signal are not used: 's_req_addr_rel'[31:26,10:0]", + "signature": "07b7fef4be3fc9e0" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER9H'", @@ -100,11 +90,6 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_core.v:: Signal is not used: 'x_pmp_cfg_addr'", "signature": "0905fde6635da519" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/crc/rtl/apb4_crc.sv:: Signal is not driven, nor used: 's_crc_stat_en'", - "signature": "092fb17faa08b69c" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_XNOR'", @@ -147,34 +132,29 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Parameter is not used: 'DCSR_CAUSE_HALTREQ'", - "signature": "0b7b8393d0f9480a" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/serial/ribp_i2s.sv:: Signal is not driven, nor used: 's_rx_pop_ready'", + "signature": "0b59c2d7a80a8594" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/crc/rtl/apb4_crc.sv:: Signal is not used: 's_bit_done'", - "signature": "0b902e996255b2e6" + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Parameter is not used: 'DCSR_CAUSE_HALTREQ'", + "signature": "0b7b8393d0f9480a" }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'W_ADDR'", "signature": "0bdf9e1cb55e00af" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_sdio.sv:: Signal is not used: 's_dummy_clk'", + "signature": "0be030e87d9747cb" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/femtorv32/user_core_design.sv:: Filename 'user_core_design' does not match MODULE name: 'mpw_c3'", "signature": "0c690b06f95f782f" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/timer/rtl/apb4_tmr.sv:: Instance pin connected by name with empty reference: 'ovf_o'", - "signature": "0cd6ad0666cb4214" - }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv:: Instance pin connected by name with empty reference: 'clk_o'", - "signature": "0d06be595a08493b" - }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_15_io_pad'", @@ -185,11 +165,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Parameter is not used: 'EXTENSION_ZCA'", "signature": "0d4b7a581134891f" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/peripheral/clint.sv:: Filename 'clint' does not match IFACE name: 'simp_clint_if'", - "signature": "0d58f8e3a70c0796" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_REGADDR'", @@ -210,6 +185,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT3'", "signature": "0fc1f528cb6bfcf4" }, + { + "count": 2, + "example": "CMPCONST:$ROOT/rtl/ip/storage/spisd_write.sv:: Comparison is constant due to limited range", + "signature": "0fd871f3bf943c63" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/picorv32/picorv32/picorv32.v:: Signal is not used: 'dbg_insn_addr'", @@ -255,11 +235,6 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/picorv32/picorv32/picorv32.v:: Bits of signal are not used: 'raddr2'[5]", "signature": "14fcd75ce06a0174" }, - { - "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/clusterip/archinfo/rtl/archinfo_reg_pkg.sv:: Parameter is not used: 'ARCHINFO_IDH_ADDR'", - "signature": "1510a46d72b53794" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER19H'", @@ -290,26 +265,21 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'CSR_M_TRAP'", "signature": "175b566afe0b1799" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'tid'", + "signature": "17869ed3816eaa41" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER23H'", "signature": "17cdabd58cde47df" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/uart/rtl/apb4_uart.sv:: Signal is not used: 's_tx_push_ready'", - "signature": "180e0d114ef963d3" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_CLMUL'", "signature": "1841f569b8cc3a63" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Bits of signal are not used: 's_xpi_mm_addr'[31:24]", - "signature": "18aed22c95543f04" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MIP'", @@ -320,11 +290,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER6'", "signature": "18c677611636b19e" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/timer/rtl/apb4_tmr.sv:: Instance pin connected by name with empty reference: 'clk_fir_trg_o'", - "signature": "18dc57d578bf4b27" - }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'xpi_nss3_o_pad'", @@ -352,13 +317,13 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/peripheral/gpio.sv:: Filename 'gpio' does not match IFACE name: 'gpio_if'", - "signature": "1a9428981de81b81" + "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_28_io_pad'", + "signature": "1a98ef9f57ed19a3" }, { "count": 1, - "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_28_io_pad'", - "signature": "1a98ef9f57ed19a3" + "example": "DECLFILENAME:$ROOT/rtl/ip/serial/ribp_i2s.sv:: Filename 'ribp_i2s' does not match IFACE name: 'i2s_if'", + "signature": "1b67439e60ee65a4" }, { "count": 1, @@ -382,13 +347,13 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/i2c/rtl/i2c_if.sv:: Signal is not used: 'scl_i'", - "signature": "1c34583186130058" + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_core.v:: Signal is not used: 'f_pmp_i_m_mode'", + "signature": "1cf0646dce9f2a7e" }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_core.v:: Signal is not used: 'f_pmp_i_m_mode'", - "signature": "1cf0646dce9f2a7e" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/psram_core.sv:: Bits of signal are not used: 'wr_data_i'[7:0]", + "signature": "1cf8db8be4af50fc" }, { "count": 1, @@ -410,11 +375,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_XH3BEXTM'", "signature": "1e6a8002b79b391c" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv:: Instance pin connected by name with empty reference: 'clk_cnt_o'", - "signature": "1e835069bdd38609" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZILSD'", @@ -440,11 +400,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MEPC'", "signature": "2075469dae6126d1" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Signal is not driven, nor used: 's_xpi_rxlowb'", - "signature": "208d42d47a5e277e" - }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_27_io_pad'", @@ -455,11 +410,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_ZBC'", "signature": "23236599e40a834a" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi_reg.sv:: Signal is not driven, nor used: 's_xpi_status_en'", - "signature": "233d164f9debed2f" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_STORE_FAULT'", @@ -495,21 +445,11 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_decode.v:: Filename 'serv_decode' does not match MODULE name: 'mpw_core_serv_serv_decode'", "signature": "263e9997bd006810" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/serial/i2s.sv:: Signal is not driven, nor used: 's_tx_pop_ready'", - "signature": "26abec594813c294" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPCFG2'", "signature": "270714b35fca9eb1" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/multimedia/dvp.sv:: Filename 'dvp' does not match IFACE name: 'dvp_if'", - "signature": "27c5f9b9abea31f5" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT7'", @@ -525,6 +465,16 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_ECALL_M'", "signature": "2835c1b086dc09a8" }, + { + "count": 1, + "example": "DECLFILENAME:$ROOT/rtl/ip/storage/xpi_mm.sv:: Filename 'xpi_mm' does not match MODULE name: 'xfer_dispatcher'", + "signature": "2885cde3f9c3e26b" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Signal is not used: 's_xpi_altlen'", + "signature": "28a0075957404cb7" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER28'", @@ -540,6 +490,11 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32ima/kianV/load_decoder.v:: Filename 'load_decoder' does not match MODULE name: 'mpw_core_kianv_rv32ima_load_decoder'", "signature": "29cab1ed4499d0fb" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/axi4_interconnect.sv:: Signal is not used: 's_target_grant'", + "signature": "29cd24d635039555" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ROL'", @@ -582,13 +537,18 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'SLEEP'", - "signature": "2e8ad717e150a3a3" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_sdio.sv:: Signal is not used: 'dat_di_i'", + "signature": "2df8c8de40fdf52c" + }, + { + "count": 3, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/storage/spisd_write.sv:: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.", + "signature": "2e50abf9f7bdb683" }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv:: Instance pin connected by name with empty reference: 'clk_fir_trg_o'", - "signature": "2e995f85d4f98f79" + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'SLEEP'", + "signature": "2e8ad717e150a3a3" }, { "count": 1, @@ -620,16 +580,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_LH'", "signature": "316eeb1293a744d1" }, - { - "count": 2, - "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/ribp/interconnect/ribp2ribp.sv:: Instance pin connected by name with empty reference: 'wr_full_o'", - "signature": "318efa86c71de71f" - }, - { - "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/clusterip/archinfo/rtl/archinfo_reg_pkg.sv:: Parameter is not used: 'ARCHINFO_IDL_ADDR'", - "signature": "322396a00ca3c09c" - }, { "count": 1, "example": "WIDTHEXPAND:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Operator COND expects 32 bits on the Conditional True, but Conditional True's LTS generates 1 bits.", @@ -640,11 +590,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_LW'", "signature": "3279cc6e12dab448" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi_core.sv:: Signal is not driven, nor used: 's_dma_xfer_start'", - "signature": "32c054fef632543e" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_REFETCH'", @@ -655,11 +600,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MVENDORID'", "signature": "335de7bf8e6c35ef" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/peripheral/dma.sv:: Filename 'dma' does not match IFACE name: 'dma_hw_trg_if'", - "signature": "33e39d0d0a1dff75" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'BREAKPOINT_TRIGGERS'", @@ -700,6 +640,11 @@ "example": "PROCASSINIT:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Procedural assignment to declaration with initial value: 'XRES'", "signature": "35c9018653a86b06" }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/memory/sdram_core.sv:: Operator ASSIGNW expects 26 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits.", + "signature": "35d9d9952f36aa91" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MCYCLE'", @@ -715,11 +660,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'H3MISA'", "signature": "36d239ac9763c9ff" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv:: Instance pin connected by name with empty reference: 'clk_fir_trg_o'", - "signature": "371c638e15ec836e" - }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/register_file.v:: Filename 'register_file' does not match MODULE name: 'mpw_core_kianv_rv32i_register_file'", @@ -750,11 +690,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR0'", "signature": "37becfab88bb012e" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Signal is not used: 's_xpi_altdat'", - "signature": "382777b4699511c0" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MSECCFGH'", @@ -770,6 +705,11 @@ "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_8_io_pad'", "signature": "39ad425791d14c56" }, + { + "count": 1, + "example": "DECLFILENAME:$ROOT/rtl/ip/memory/ribp_opipsram.sv:: Filename 'ribp_opipsram' does not match IFACE name: 'opipsram_if'", + "signature": "39e0f6e59ac7c2b7" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Filename 'user_core_design' does not match MODULE name: 'mpw_c4'", @@ -832,8 +772,13 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/crc/rtl/crc8_model.sv:: Filename 'crc8_model' does not match MODULE name: 'crc8_07'", - "signature": "3f29990b3c40eff6" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/xpi_core.sv:: Signal is not driven, nor used: 's_dma_xfer_start'", + "signature": "3f26289069d70d82" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'tlast'", + "signature": "4019e9ec76f9a627" }, { "count": 1, @@ -900,6 +845,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TSELECT'", "signature": "457641eeae2b7235" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/ribp_opipsram.sv:: Signal is not used: 'irq_o'", + "signature": "4576ad727bc2f8f4" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_BCOND'", @@ -920,11 +870,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER15'", "signature": "46c26a66462b624d" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Filename 'xpi' does not match IFACE name: 'xpi_if'", - "signature": "46cf25197f1a6ee0" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ADD'", @@ -960,26 +905,11 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/picorv32/user_core_design.sv:: Filename 'user_core_design' does not match MODULE name: 'mpw_c5'", "signature": "4801ccefb75b11ae" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Signal is not used: 's_xpi_alttyp'", - "signature": "480e9c277321b847" - }, - { - "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/clusterip/archinfo/rtl/archinfo_reg_pkg.sv:: Parameter is not used: 'ARCHINFO_SYS_ADDR'", - "signature": "4817fb88856e974b" - }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_29_io_pad'", "signature": "48c03f194a9399da" }, - { - "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/ip/ribp/memory/sdram_core.sv:: Parameter is not used: 'CMD_BST'", - "signature": "48f36633918e6491" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_irq_ctrl.v:: Bits of signal are not used: 'wdata_raw'[31:7]", @@ -1005,11 +935,6 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'OPCODE'", "signature": "4a34235c605f92a2" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv:: Instance pin connected by name with empty reference: 'clk_cnt_o'", - "signature": "4a4ff64dc2adf3cc" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUSRCA_PC'", @@ -1027,13 +952,13 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_INSTR_ILLEGAL'", - "signature": "4b71bbd60c64333c" + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Instance pin connected by name with empty reference: 'xpi_accmd_o'", + "signature": "4b16c237737d9d17" }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/ip/ribp/memory/sdram_core.sv:: Parameter is not used: 'AUTO_REFRESH'", - "signature": "4be9214ddeeaaae1" + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_INSTR_ILLEGAL'", + "signature": "4b71bbd60c64333c" }, { "count": 1, @@ -1070,11 +995,6 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32ima/kianV/multiplier_decoder.v:: Filename 'multiplier_decoder' does not match MODULE name: 'mpw_core_kianv_rv32ima_multiplier_decoder'", "signature": "4d6ba9328c1d4ccf" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv:: Signal is not used: 's_bit_rsynf'", - "signature": "4d70669b8a494847" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT30'", @@ -1095,11 +1015,6 @@ "example": "DECLFILENAME:$ROOT/rtl/tech/tc_clk.sv:: Filename 'tc_clk' does not match MODULE name: 'tc_clk_inv'", "signature": "4ec048718bb177a1" }, - { - "count": 1, - "example": "EOFNEWLINE:$ROOT/rtl/managed/clusterip/rng/rtl/rng_define.svh:: Missing newline at end of file (POSIX 3.206).", - "signature": "4eca5822dac20719" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'CSR_WTYPE_C'", @@ -1110,11 +1025,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'EXCEPT_LOAD_FAULT'", "signature": "4fb8fdc3c3390dbb" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv:: Instance pin connected by name with empty reference: 'dst_data_o'", - "signature": "4fbad4a28d5694d0" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_HARDWIRED_ADDR'", @@ -1125,16 +1035,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MEDELEG'", "signature": "4fcb995a51d1180a" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/serial/i2s.sv:: Signal is not driven, nor used: 's_rx_pop_ready'", - "signature": "501fb1ec09712dd9" - }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/sdio.sv:: Signal is not used: 'dummy1'", - "signature": "505d36ef15386786" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR13'", @@ -1147,13 +1047,8 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv:: Instance pin connected by name with empty reference: 'src_ready_o'", - "signature": "509303f3fb8f202d" - }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/sdio.sv:: Signal is not used: 'irq_o'", - "signature": "511ddb07a652ec8b" + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv:: Signal is not used: 'aclk'", + "signature": "50ffea6ec9f3319c" }, { "count": 1, @@ -1165,11 +1060,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_C'", "signature": "51fb79f7714621a3" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/timer/rtl/apb4_tmr.sv:: Instance pin connected by name with empty reference: 'clk_cnt_o'", - "signature": "5205bf154806930b" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER13H'", @@ -1185,11 +1075,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_SB'", "signature": "5298c4e58dca3b51" }, - { - "count": 3, - "example": "WIDTHTRUNC:$ROOT/rtl/ip/ribp/storage/spisd_write.sv:: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.", - "signature": "52a801eec8db2eda" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER27H'", @@ -1220,11 +1105,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Parameter is not used: 'DCSR_CAUSE_EBREAK'", "signature": "550e02682aa2da16" }, - { - "count": 2, - "example": "CMPCONST:$ROOT/rtl/ip/ribp/storage/spisd_write.sv:: Comparison is constant due to limited range", - "signature": "5656f3e197d9119c" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER10H'", @@ -1240,11 +1120,6 @@ "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/picorv32/user_core_design.sv:: Instance pin connected by name with empty reference: 'pcpi_rd'", "signature": "56f5e81e565a48e6" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/memory/opipsram.sv:: Signal is not used: 'irq_o'", - "signature": "57218855d88e0355" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MCAUSE'", @@ -1260,11 +1135,26 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/kianv_rv32ima/kianV/alu.v:: Bits of signal are not used: 'sra_srai_rslt'[63:32]", "signature": "57fe2ba51c012db9" }, + { + "count": 1, + "example": "WIDTHEXPAND:$ROOT/rtl/ip/storage/spisd_init.sv:: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 's_overflow_cnt' generates 16 bits.", + "signature": "57ffc0e0e452fae1" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_LB'", "signature": "581f2d8a061dbde7" }, + { + "count": 1, + "example": "DECLFILENAME:$ROOT/rtl/ip/memory/ribp_psram.sv:: Filename 'ribp_psram' does not match IFACE name: 'psram_if'", + "signature": "58cd3a21ff70e1cc" + }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Signal is not used: 's_xpi_alttyp'", + "signature": "58ceb74a8fadffdc" + }, { "count": 1, "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/kianv_rv32i/user_core_design.sv:: Instance pin connected by name with empty reference: 'PC'", @@ -1280,11 +1170,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_ROR'", "signature": "5b19472d61a385fd" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/memory/psram_core.sv:: Filename 'psram_core' does not match MODULE name: 'load_new_byte'", - "signature": "5b488e71ed72e215" - }, { "count": 1, "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Instance pin connected by name with empty reference: 'DEBUG'", @@ -1295,11 +1180,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MINSTRETH'", "signature": "5d19ef0c8ba1c56f" }, - { - "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/ip/ribp/memory/sdram_core.sv:: Parameter is not used: 'PRE_CHARGE_ALL'", - "signature": "5d3a48d50d593bc5" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT11'", @@ -1330,11 +1210,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_GRAIN'", "signature": "5f511bc2d35407ec" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/peripheral/pll_ctrl_if.sv:: Signal is not used: 'req_sel_o'", - "signature": "5fb57637c4ad423d" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'RESET_REGFILE'", @@ -1345,6 +1220,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/mpw/core/kianv_rv32ima/user_core_design.sv:: Parameter is not used: 'ID'", "signature": "6014cd8bb32150f6" }, + { + "count": 2, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/interconnect/ribp2ribp.sv:: Instance pin connected by name with empty reference: 'wr_full_o'", + "signature": "60221cb3ea17ea73" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_PACKH'", @@ -1365,11 +1245,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPCFGM0'", "signature": "623bf821e2a9c639" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Signal is not driven, nor used: 's_xpi_rxupb'", - "signature": "62d067d16e9e1df1" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT28'", @@ -1410,21 +1285,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER30'", "signature": "67011f5eacc2e78f" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/serial/i2s.sv:: Filename 'i2s' does not match IFACE name: 'i2s_if'", - "signature": "6719cee607366904" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT21'", "signature": "67e8e8f7c1532aac" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Signal is not driven, nor used: 's_xpi_txupb'", - "signature": "685951089304c347" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT20'", @@ -1452,13 +1317,8 @@ }, { "count": 1, - "example": "SYNCASYNCNET:$ROOT/rtl/managed/clusterip/common/rtl/utils/register.sv:: Signal flopped as both synchronous and async: 'retrosoc_top.u_retrosoc_asic.u_rcu.u_sys_rst_sync.__Vcellout__RST_SYNC_BLOCK[4].RST_SYNC_N0_BLOCK.u_sync_dffr____pinNumber4'", - "signature": "69ad9c2d06349b9b" - }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Signal is not driven, nor used: 's_xpi_txlowb'", - "signature": "6a7a79f1a4a4e2e2" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/sdram_core.sv:: Bits of signal are not used: 's_mem_addr'[23:11,1:0]", + "signature": "69f65b84df00b796" }, { "count": 1, @@ -1485,11 +1345,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MSECCFG'", "signature": "6cb6b8ad455cc035" }, - { - "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/ip/ribp/storage/spisd_init.sv:: Parameter is not used: 'DIV_FREQ'", - "signature": "6e3568070195ade2" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_UNZIP'", @@ -1500,11 +1355,6 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/picorv32/picorv32/picorv32.v:: Signal is not used: 'dbg_rs2val_valid'", "signature": "6f447f6386d6d2e0" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/mini/top/rcu.sv:: Filename 'rcu' does not match MODULE name: 'pll_rcu_controller'", - "signature": "6f97fc8d1bb13758" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/debug/dm/hazard3_dm.v:: Bits of signal are not used: 'dmi_paddr'[1:0]", @@ -1537,13 +1387,13 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/multimedia/dvp.sv:: Signal is not used: 's_rx_elem_num'", - "signature": "7267112d7087ea51" + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'DEBUG_SUPPORT'", + "signature": "73096c7d99d662dd" }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'DEBUG_SUPPORT'", - "signature": "73096c7d99d662dd" + "example": "UNUSEDPARAM:$ROOT/rtl/ip/storage/spisd_init.sv:: Parameter is not used: 'DivFreq'", + "signature": "736850bbf0e6fb7d" }, { "count": 1, @@ -1610,6 +1460,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MSLEEP'", "signature": "77cfd15c72609921" }, + { + "count": 1, + "example": "UNUSEDPARAM:$ROOT/rtl/ip/memory/sdram_core.sv:: Parameter is not used: 'CmdBst'", + "signature": "7946272fc744cea4" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'uart0_rx_i_pad'", @@ -1625,21 +1480,11 @@ "example": "SPECIFYIGN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v:: Ignoring unsupported: specify block construct", "signature": "7a759d6e07651fd8" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/multimedia/dvp.sv:: Signal is not used: 's_rx_full'", - "signature": "7ad3156be256bac0" - }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_0_io_pad'", "signature": "7b105b7a92957ce9" }, - { - "count": 1, - "example": "EOFNEWLINE:$ROOT/rtl/managed/clusterip/wdg/rtl/wdg_if.sv:: Missing newline at end of file (POSIX 3.206).", - "signature": "7b606887e11f2fa9" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Signal is not used: 'match_urw'", @@ -1661,15 +1506,20 @@ "signature": "7c2c3cb746584653" }, { - "count": 2, - "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/ribp/interconnect/ribp2ribp.sv:: Instance pin connected by name with empty reference: 'elem_num_o'", - "signature": "7d5aa06fd6dc15b1" + "count": 1, + "example": "DECLFILENAME:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Filename 'ribp_xpi' does not match IFACE name: 'xpi_if'", + "signature": "7c2e5dcb72ada3a6" }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/femtorv32/user_core_design.sv:: Bits of signal are not used: 's_mem_addr'[1:0]", "signature": "7d77240b3d7ea34d" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'aresetn'", + "signature": "7e24f33fb923deb5" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT16'", @@ -1685,6 +1535,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER27'", "signature": "7f30d21586d6102f" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_sdio.sv:: Signal is not used: 'irq_o'", + "signature": "8009dba48fe4bfd2" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR11'", @@ -1765,11 +1620,6 @@ "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Instance pin connected by name with empty reference: 'HLT'", "signature": "8558e9362c52e672" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/serial/uart.sv:: Filename 'uart' does not match MODULE name: 'ribp_uart'", - "signature": "855b022f0926bca0" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_AND'", @@ -1840,11 +1690,6 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32ima/kianV/register_file.v:: Filename 'register_file' does not match MODULE name: 'mpw_core_kianv_rv32ima_register_file'", "signature": "8aa42083214ecd37" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/sdio.sv:: Signal is not used: 'dummy0'", - "signature": "8ae4fbcbd523adbb" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_top.v:: Signal is not used: 'i_ext_rd'", @@ -1855,6 +1700,11 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/alu.v:: Filename 'alu' does not match MODULE name: 'mpw_core_kianv_rv32i_alu'", "signature": "8b12b31c58ed721e" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/ribp_opipsram.sv:: Signal is not used: 'io_di_i'", + "signature": "8b1c7981ded5516c" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_SRL'", @@ -1900,11 +1750,6 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/femtorv32/user_core_design.sv:: Signal is not used: 'irq_i'", "signature": "8d790409df1b9130" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/memory/opipsram.sv:: Signal is not used: 'io_di_i'", - "signature": "8f5ee23c310fcf71" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_core.v:: Signal is not used: 'x_pmp_cfg_wdata'", @@ -1920,11 +1765,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Parameter is not used: 'CPTR'", "signature": "90b5295c79348584" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/memory/psram.sv:: Filename 'psram' does not match IFACE name: 'psram_if'", - "signature": "90f952693335f81a" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_XH3POWER'", @@ -1970,11 +1810,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT25'", "signature": "92a5f90729168667" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/crc/rtl/crc32_model.sv:: Filename 'crc32_model' does not match MODULE name: 'crc32_04c11db7'", - "signature": "92b6ff76224f2d3e" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/arith/hazard3_alu.v:: Bits of signal are not used: 'funct7_32b'[6:4,0]", @@ -2005,6 +1840,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_CLZ'", "signature": "94c9130b5e38de1d" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'tdest'", + "signature": "94ce4081818687e6" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_XOR'", @@ -2070,11 +1910,6 @@ "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_3_io_pad'", "signature": "9893b007f511a231" }, - { - "count": 1, - "example": "EOFNEWLINE:$ROOT/rtl/managed/clusterip/pwm/rtl/pwm_if.sv:: Missing newline at end of file (POSIX 3.206).", - "signature": "98ba924f79eb6e14" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/mpw/core/darkriscv/user_core_design.sv:: Parameter is not used: 'ID'", @@ -2125,11 +1960,6 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_top.v:: Filename 'serv_top' does not match MODULE name: 'mpw_core_serv_serv_top'", "signature": "9bc9f670bb4d815b" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/peripheral/sysctrl.sv:: Filename 'sysctrl' does not match IFACE name: 'sysctrl_if'", - "signature": "9cfd8d907569961e" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'MTVEC_INIT'", @@ -2150,6 +1980,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'INSTRETH'", "signature": "9e0e1f130a9a1c41" }, + { + "count": 1, + "example": "DECLFILENAME:$ROOT/rtl/ip/memory/psram_core.sv:: Filename 'psram_core' does not match MODULE name: 'load_new_byte'", + "signature": "9e4e508b300970ea" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_BEXT'", @@ -2195,11 +2030,6 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32ima/kianV/divider.v:: Filename 'divider' does not match MODULE name: 'mpw_core_kianv_rv32ima_divider'", "signature": "a2037979e39c4dcb" }, - { - "count": 1, - "example": "EOFNEWLINE:$ROOT/rtl/managed/clusterip/timer/rtl/tmr_if.sv:: Missing newline at end of file (POSIX 3.206).", - "signature": "a279807dd0b5fc33" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/picorv32/picorv32/picorv32.v:: Signal is not used: 'dbg_mem_wdata'", @@ -2265,16 +2095,6 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv:: Filename 'cdc_sync' does not match MODULE name: 'cdc_sync_det'", "signature": "a6f0024b7dbf24d8" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/sdio.sv:: Signal is not used: 'cmd_di_i'", - "signature": "a71198dc158d0f05" - }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/storage/xpi_mm.sv:: Filename 'xpi_mm' does not match MODULE name: 'xfer_dispatcher'", - "signature": "a76bc229e3b89fcb" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER21H'", @@ -2285,11 +2105,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TDATA3'", "signature": "a7da8d2afcf0360a" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/memory/psram_core.sv:: Bits of signal are not used: 'wr_data_i'[7:0]", - "signature": "a8845119c49a953a" - }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/datapath_unit.v:: Filename 'datapath_unit' does not match MODULE name: 'mpw_core_kianv_rv32i_datapath_unit'", @@ -2297,13 +2112,13 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'M_OP_MULH'", - "signature": "a993d1b40bab8558" + "example": "DECLFILENAME:$ROOT/rtl/ip/memory/axi4_sdram.sv:: Filename 'axi4_sdram' does not match IFACE name: 'sdram_if'", + "signature": "a90916740809d34f" }, { "count": 1, - "example": "WIDTHTRUNC:$ROOT/rtl/ip/ribp/storage/spisd_read.sv:: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's REPLICATE generates 9 bits.", - "signature": "aa37292a001a430c" + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'M_OP_MULH'", + "signature": "a993d1b40bab8558" }, { "count": 1, @@ -2337,8 +2152,8 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/storage/spisd.sv:: Filename 'spisd' does not match MODULE name: 'ribp_spisd'", - "signature": "ac8b69917114a248" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Signal is not driven, nor used: 's_xpi_txupb'", + "signature": "ac8cc14c26efde91" }, { "count": 1, @@ -2390,21 +2205,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_HARDWIRED'", "signature": "af5b16328f2ef48b" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Signal is not used: 's_xpi_altlen'", - "signature": "affc23b5e22a53c2" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_bufreg.v:: Signal is not used: 'i_cnt_done'", "signature": "b091d4717edc7d92" }, - { - "count": 1, - "example": "IMPORTSTAR:$ROOT/rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv:: 'import::*' in $unit scope may pollute global namespace", - "signature": "b13fd37a1362d500" - }, { "count": 1, "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/picorv32/user_core_design.sv:: Instance pin connected by name with empty reference: 'mem_la_wstrb'", @@ -2437,8 +2242,8 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/managed/clusterip/crc/rtl/crc16_model.sv:: Filename 'crc16_model' does not match MODULE name: 'crc16_1021'", - "signature": "b47f45226a43e65c" + "example": "DECLFILENAME:$ROOT/rtl/ip/storage/ribp_sdio.sv:: Filename 'ribp_sdio' does not match IFACE name: 'sdio_if'", + "signature": "b44117ff5dcdba59" }, { "count": 1, @@ -2452,13 +2257,8 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/ps2/rtl/apb4_ps2.sv:: Instance pin connected by name with empty reference: 'full_o'", - "signature": "b5e3e9fef2e40ff1" - }, - { - "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/ip/ribp/memory/sdram_core.sv:: Parameter is not used: 'LAST_STATE'", - "signature": "b720e859b3d96689" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/ribp_opipsram.sv:: Signal is not used: 's_dummy_clk'", + "signature": "b727422b89c51475" }, { "count": 1, @@ -2500,11 +2300,6 @@ "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'uart0_tx_o_pad'", "signature": "b8e6c3c794a223bf" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/ribp/serial/onewire.sv:: Instance pin connected by name with empty reference: 'cnt_o'", - "signature": "b912a08a58a3d7fe" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Signal is not used: 'DAER'", @@ -2512,13 +2307,8 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/memory/opipsram.sv:: Filename 'opipsram' does not match IFACE name: 'opipsram_if'", - "signature": "b9eb41b5b6eb5ccc" - }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/storage/sdio.sv:: Filename 'sdio' does not match IFACE name: 'sdio_if'", - "signature": "bb2fd6dc28d116b0" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_sdio.sv:: Signal is not used: 's_dummy_rst_n'", + "signature": "ba89ad329f97b187" }, { "count": 1, @@ -2540,6 +2330,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER10'", "signature": "bc5974b822f99576" }, + { + "count": 1, + "example": "DECLFILENAME:$ROOT/rtl/ip/peripheral/ribp_sysctrl.sv:: Filename 'ribp_sysctrl' does not match IFACE name: 'sysctrl_if'", + "signature": "bc93fe8e2c72a887" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32ima/kianV/cells.v:: Filename 'cells' does not match MODULE name: 'mpw_core_kianv_rv32ima_buffer_cell'", @@ -2585,11 +2380,6 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/design_elements.v:: Filename 'design_elements' does not match MODULE name: 'mpw_core_kianv_rv32i_mux2'", "signature": "be2743ec0029efad" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/multimedia/dvp.sv:: Signal is not driven, nor used: 's_rx_pop_ready'", - "signature": "be2c06de368977ce" - }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/hazard3/hdl/hazard3_frontend.v:: Bits of signal are not used: 'btb_src_addr'[0]", @@ -2602,13 +2392,13 @@ }, { "count": 1, - "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_MATCH_NAPOT'", - "signature": "bf91d18fa461423f" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/ribp_opipsram.sv:: Signal is not used: 's_dummy_rst_n'", + "signature": "becffd61e525ff7c" }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv:: Instance pin connected by name with empty reference: 'clk_fir_trg_o'", - "signature": "bfd3207837c35f83" + "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'PMP_MATCH_NAPOT'", + "signature": "bf91d18fa461423f" }, { "count": 1, @@ -2670,11 +2460,21 @@ "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/picorv32/user_core_design.sv:: Instance pin connected by name with empty reference: 'pcpi_ready'", "signature": "c6e26f231e951afb" }, + { + "count": 1, + "example": "WIDTHTRUNC:$ROOT/rtl/ip/storage/spisd_read.sv:: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's REPLICATE generates 9 bits.", + "signature": "c7560adc7bbae3a3" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'MEMOP_SW'", "signature": "c7c55c60199f03dc" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Signal is not driven, nor used: 's_xpi_rxlowb'", + "signature": "c7ea01ae58ba8d67" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MENVCFGH'", @@ -2700,11 +2500,6 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Signal is not used: 'IHLT'", "signature": "ca81f9845d564cad" }, - { - "count": 2, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/uart/rtl/apb4_uart.sv:: Instance pin connected by name with empty reference: 'busy_o'", - "signature": "ca99a5392993487e" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr.v:: Parameter is not used: 'DCSR_CAUSE_TRIGGER'", @@ -2720,26 +2515,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMEVENT19'", "signature": "cb50e4344c949ae7" }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/storage/sdio.sv:: Signal is not used: 'dat_di_i'", - "signature": "cb8001b4af1077a9" - }, { "count": 1, "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/picorv32/user_core_design.sv:: Instance pin connected by name with empty reference: 'pcpi_wr'", "signature": "cb8eca0c4a81d222" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/timer/rtl/apb4_tmr.sv:: Instance pin connected by name with empty reference: 'dat_o'", - "signature": "cbc24339ec49c826" - }, - { - "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/timer/rtl/apb4_tmr.sv:: Signal is not used: 's_cap_in'", - "signature": "cc39d539774eec98" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER18'", @@ -2767,13 +2547,8 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/serial/i2c.sv:: Filename 'i2c' does not match MODULE name: 'ribp_i2c'", - "signature": "ce0fe3787cfc243e" - }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/mini/top/user_core_design_template.sv:: Filename 'user_core_design_template' does not match MODULE name: 'user_core_design'", - "signature": "d00b4d58006976c6" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/peripheral/pll_ctrl_if.sv:: Signal is not used: 'req_sel_o'", + "signature": "cd98cd5f8ba452a7" }, { "count": 1, @@ -2790,6 +2565,11 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_aligner.v:: Filename 'serv_aligner' does not match MODULE name: 'mpw_core_serv_serv_aligner'", "signature": "d080db27a7911a99" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'tstrb'", + "signature": "d107b15c3ab26a79" + }, { "count": 1, "example": "PROCASSINIT:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkriscv.v:: Procedural assignment to declaration with initial value: 'FLUSH'", @@ -2800,11 +2580,21 @@ "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/mpw/core/picorv32/user_core_design.sv:: Instance pin connected by name with empty reference: 'pcpi_rs2'", "signature": "d180668432728ed4" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/xpi_reg.sv:: Signal is not driven, nor used: 's_xpi_stat_en'", + "signature": "d22968862efab0b2" + }, { "count": 1, "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'fence_d_vld'", "signature": "d253cb3cc4d59917" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Signal is not driven, nor used: 's_xpi_rxupb'", + "signature": "d2a471cbca33151f" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_MIN'", @@ -2817,8 +2607,8 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/memory/opipsram.sv:: Signal is not used: 'dqs_di_i'", - "signature": "d454eb037ab7517a" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/memory/ribp_opipsram.sv:: Signal is not used: 'dqs_di_i'", + "signature": "d4863f5b7d5c417c" }, { "count": 1, @@ -2832,8 +2622,8 @@ }, { "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/timer/rtl/apb4_tmr.sv:: Instance pin connected by name with empty reference: 'clk_o'", - "signature": "d530c365aa32fb3d" + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_if.sv:: Signal is not used: 'aresetn'", + "signature": "d4f29a2333f1740c" }, { "count": 1, @@ -2872,13 +2662,8 @@ }, { "count": 1, - "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/ribp/peripheral/gpio.sv:: Signal is not used: 'irq_o'", - "signature": "d8674d3f3a79d5d0" - }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/memory/sdram.sv:: Filename 'sdram' does not match IFACE name: 'sdram_if'", - "signature": "d8996d75a35d3386" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Signal is not used: 's_xpi_altdat'", + "signature": "d84937eb7ed0fc5f" }, { "count": 1, @@ -2890,6 +2675,11 @@ "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'hexcl'", "signature": "d92b91d2e2895f82" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_sdio.sv:: Signal is not used: 'cmd_di_i'", + "signature": "d9508e2a6c9e66f9" + }, { "count": 1, "example": "PINCONNECTEMPTY:$BUILD/generated/pin_map/rtl/retrosoc_asic_verilator_bindings.svh:: Instance pin connected by name with empty reference: 'gpio_6_io_pad'", @@ -2917,8 +2707,13 @@ }, { "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/peripheral/timer.sv:: Filename 'timer' does not match MODULE name: 'ribp_timer'", - "signature": "ddca3d25d44af331" + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Signal is not driven, nor used: 's_xpi_txlowb'", + "signature": "db2ba97526587d30" + }, + { + "count": 2, + "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/interconnect/ribp2ribp.sv:: Instance pin connected by name with empty reference: 'elem_num_o'", + "signature": "dce1c6c8f8f2db8c" }, { "count": 1, @@ -2932,8 +2727,8 @@ }, { "count": 1, - "example": "EOFNEWLINE:$ROOT/rtl/managed/clusterip/ps2/rtl/ps2_if.sv:: Missing newline at end of file (POSIX 3.206).", - "signature": "dede41f7cadcb4e8" + "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/axi42ribp_burst.sv:: Bits of signal are not used: 's_read_last_addr'[11:0]", + "signature": "e060929df8f148e9" }, { "count": 1, @@ -2970,11 +2765,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MCYCLEH'", "signature": "e1142fcbcdebe68e" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv:: Instance pin connected by name with empty reference: 'clk_o'", - "signature": "e12f263c34f144e9" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'PMPADDR14'", @@ -3025,6 +2815,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER17H'", "signature": "e3b694052fa14e04" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/serial/ribp_i2s.sv:: Signal is not driven, nor used: 's_tx_pop_ready'", + "signature": "e3ee0bf56d2689e5" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/darkriscv/darkriscv/darkbridge.v:: Filename 'darkbridge' does not match MODULE name: 'mpw_core_darkriscv_darkbridge'", @@ -3070,11 +2865,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MEIEA'", "signature": "e76bc25ed2f5fd1d" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/ip/ribp/storage/xpi.sv:: Instance pin connected by name with empty reference: 'xpi_accmd_o'", - "signature": "e787228a473eb0bb" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'MCONFIGPTR_VAL'", @@ -3110,6 +2900,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_ops.vh:: Parameter is not used: 'ALUOP_REV8'", "signature": "e95d893d80f702a6" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'tuser'", + "signature": "e95d96d8ad151b2c" + }, { "count": 1, "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/picorv32/picorv32/picorv32.v:: Bits of signal are not used: 'waddr'[5]", @@ -3120,6 +2915,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MISA'", "signature": "e98223c9514b66f3" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv:: Signal is not used: 'aclk'", + "signature": "ea1bfdc6665f301a" + }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER11'", @@ -3190,11 +2990,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'TCONTROL'", "signature": "eee1f40880b0c327" }, - { - "count": 1, - "example": "SYNCASYNCNET:$ROOT/rtl/managed/mpw/core/femtorv32/user_core_design.sv:: Signal flopped as both synchronous and async: 'retrosoc_top.u_retrosoc_asic.u_retrosoc.u_user_core_top.__Vcellinp__u_mpw_core_femtorv32__rst_n_i'", - "signature": "ef7bcb09123f998f" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER3H'", @@ -3230,6 +3025,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'CYCLE'", "signature": "f2d3d9e31d7a7e1b" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/mini/top/axi42ribp_burst.sv:: Bits of signal are not used: 's_write_last_addr'[11:0]", + "signature": "f2dc357b957fd0ec" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32i/kianV/load_alignment.v:: Filename 'load_alignment' does not match MODULE name: 'mpw_core_kianv_rv32i_load_alignment'", @@ -3240,6 +3040,11 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MCOUNTINHIBIT'", "signature": "f423f1b5d0e86d3f" }, + { + "count": 1, + "example": "UNUSEDSIGNAL:$ROOT/rtl/ip/storage/ribp_xpi.sv:: Bits of signal are not used: 's_xpi_mm_addr'[31:24]", + "signature": "f46469a9b66cc51c" + }, { "count": 1, "example": "PINCONNECTEMPTY:$ROOT/rtl/mini/top/mgmt_core_wrapper.sv:: Instance pin connected by name with empty reference: 'clk_en'", @@ -3260,11 +3065,6 @@ "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_bufreg2.v:: Filename 'serv_bufreg2' does not match MODULE name: 'mpw_core_serv_serv_bufreg2'", "signature": "f54afe8681d27688" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv:: Instance pin connected by name with empty reference: 'clk_o'", - "signature": "f5c86d2641312606" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_csr_addr.vh:: Parameter is not used: 'MHPMCOUNTER31'", @@ -3285,11 +3085,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'EXTENSION_M'", "signature": "f75253922b3ef29c" }, - { - "count": 1, - "example": "DECLFILENAME:$ROOT/rtl/ip/ribp/serial/onewire.sv:: Filename 'onewire' does not match IFACE name: 'onewire_if'", - "signature": "f7f7426e19a5dd7e" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/mpw/core/femtorv32/user_core_design.sv:: Parameter is not used: 'ID'", @@ -3300,6 +3095,11 @@ "example": "UNUSEDSIGNAL:$ROOT/rtl/managed/mpw/core/serv/serv/serv_top.v:: Bits of signal are not used: 'i_wb_rdt'[1:0]", "signature": "f8e1f216abc4cf66" }, + { + "count": 1, + "example": "DECLFILENAME:$ROOT/rtl/ip/peripheral/ribp_dma.sv:: Filename 'ribp_dma' does not match IFACE name: 'dma_hw_trg_if'", + "signature": "f9e3d8cdd15d4db1" + }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/serv/serv/serv_immdec.v:: Filename 'serv_immdec' does not match MODULE name: 'mpw_core_serv_serv_immdec'", @@ -3320,11 +3120,6 @@ "example": "SPECIFYIGN:$ROOT/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v:: Ignoring unsupported: specify block construct", "signature": "faa191e2dbf4a242" }, - { - "count": 1, - "example": "EOFNEWLINE:$ROOT/rtl/managed/clusterip/uart/rtl/uart_if.sv:: Missing newline at end of file (POSIX 3.206).", - "signature": "fad478d50a43d7ce" - }, { "count": 1, "example": "DECLFILENAME:$ROOT/rtl/managed/mpw/core/kianv_rv32ima/kianV/alu_decoder.v:: Filename 'alu_decoder' does not match MODULE name: 'mpw_core_kianv_rv32ima_alu_decoder'", @@ -3345,11 +3140,6 @@ "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_width_const.vh:: Parameter is not used: 'W_ALUOP'", "signature": "fc6f395584c3a436" }, - { - "count": 1, - "example": "PINCONNECTEMPTY:$ROOT/rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv:: Instance pin connected by name with empty reference: 'clk_cnt_o'", - "signature": "fd5e8e149f4a4f56" - }, { "count": 1, "example": "UNUSEDPARAM:$ROOT/rtl/managed/hazard3/hdl/hazard3_config.vh:: Parameter is not used: 'MUL_FAST'", diff --git a/rtl/README.md b/rtl/README.md index 9dff0a5b..04a35ba0 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -53,6 +53,11 @@ The complete ownership-aware rules, including semantic signal grammar, handshake/error vocabulary, module/interface/instance suffixes, parameter and macro namespaces, FSM examples, compatibility boundaries, and migration policy are documented in [RTL Coding Style](../docs/rtl-coding-style.md). +The behavior-preserving audit process, rule matrix, formatter-exception +requirements, and required validation are documented in +[RTL Coding Style Compliance](../docs/rtl-coding-style-compliance.md); +[`rtl_style_audit.json`](rtl_style_audit.json) records the reviewed owned +source inventory. `make rtl-style-check` rejects new positional connections and legacy constructs in changed self-owned RTL while the existing migration backlog is handled separately. diff --git a/rtl/ip/experimental/axi4f2ribp.sv b/rtl/ip/experimental/axi4f2ribp.sv index 000d8119..a8b110e7 100644 --- a/rtl/ip/experimental/axi4f2ribp.sv +++ b/rtl/ip/experimental/axi4f2ribp.sv @@ -8,8 +8,11 @@ // MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. // See the Mulan PSL v2 for more details. +// Inactive AXI-to-RIBP prototype. Its protocol behavior is intentionally +// unimplemented and must not be enabled without a separate interface contract +// and AXI/RIBP verification project. module axi4f2ribp ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic aclk_i, input logic aresetn_i, input logic [31:0] awaddr_i, diff --git a/rtl/ip/experimental/gpu.sv b/rtl/ip/experimental/ribp_gpu.sv similarity index 100% rename from rtl/ip/experimental/gpu.sv rename to rtl/ip/experimental/ribp_gpu.sv diff --git a/rtl/ip/experimental/sdio_cache.sv b/rtl/ip/experimental/sdio_cache.sv deleted file mode 100644 index db7e6f6e..00000000 --- a/rtl/ip/experimental/sdio_cache.sv +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (c) 2023-2026 Yuchi Miao -// retroSoC is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -// See the Mulan PSL v2 for more details. diff --git a/rtl/ip/experimental/sdio_clkgen.sv b/rtl/ip/experimental/sdio_clkgen.sv deleted file mode 100644 index db7e6f6e..00000000 --- a/rtl/ip/experimental/sdio_clkgen.sv +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (c) 2023-2026 Yuchi Miao -// retroSoC is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -// See the Mulan PSL v2 for more details. diff --git a/rtl/ip/experimental/sdio_cmd.sv b/rtl/ip/experimental/sdio_cmd.sv deleted file mode 100644 index db7e6f6e..00000000 --- a/rtl/ip/experimental/sdio_cmd.sv +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (c) 2023-2026 Yuchi Miao -// retroSoC is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -// See the Mulan PSL v2 for more details. diff --git a/rtl/ip/experimental/sdio_core.sv b/rtl/ip/experimental/sdio_core.sv deleted file mode 100644 index db7e6f6e..00000000 --- a/rtl/ip/experimental/sdio_core.sv +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (c) 2023-2026 Yuchi Miao -// retroSoC is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -// See the Mulan PSL v2 for more details. diff --git a/rtl/ip/experimental/sdio_dat.sv b/rtl/ip/experimental/sdio_dat.sv deleted file mode 100644 index db7e6f6e..00000000 --- a/rtl/ip/experimental/sdio_dat.sv +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (c) 2023-2026 Yuchi Miao -// retroSoC is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -// See the Mulan PSL v2 for more details. diff --git a/rtl/ip/experimental/sdio_init.sv b/rtl/ip/experimental/sdio_init.sv deleted file mode 100644 index db7e6f6e..00000000 --- a/rtl/ip/experimental/sdio_init.sv +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (c) 2023-2026 Yuchi Miao -// retroSoC is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -// See the Mulan PSL v2 for more details. diff --git a/rtl/ip/experimental/sdio_reg.sv b/rtl/ip/experimental/sdio_reg.sv deleted file mode 100644 index db7e6f6e..00000000 --- a/rtl/ip/experimental/sdio_reg.sv +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (c) 2023-2026 Yuchi Miao -// retroSoC is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -// See the Mulan PSL v2 for more details. diff --git a/rtl/ip/interconnect/axi4l2ribp.sv b/rtl/ip/interconnect/axi4l2ribp.sv index e1b5ac5b..3a630928 100644 --- a/rtl/ip/interconnect/axi4l2ribp.sv +++ b/rtl/ip/interconnect/axi4l2ribp.sv @@ -9,7 +9,7 @@ // See the Mulan PSL v2 for more details. module axi4l2ribp ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic aclk_i, input logic aresetn_i, input logic [31:0] awaddr_i, @@ -29,23 +29,28 @@ module axi4l2ribp ( output logic [ 1:0] rresp_o, output logic rvalid_o, input logic rready_i, - ribp_if.master ribp + ribp_if.master ribp // verilog_format: on ); - localparam [1:0] RD_IDLE = 2'd0; - localparam [1:0] RD_DATA = 2'd1; - localparam [1:0] RD_WAIT = 2'd2; + // AXI-Lite requests are accepted only in each channel's idle state; one read + // and one write may be outstanding. RIBP errors map to SLVERR responses. + typedef enum logic [1:0] { + RdIdle = 2'd0, + RdData = 2'd1, + RdWait = 2'd2 + } rd_state_e; + typedef enum logic [1:0] { + WrIdle = 2'd0, + WrData = 2'd1, + WrWait = 2'd2, + WrResp = 2'd3 + } wr_state_e; + localparam logic [1:0] AxiRespOkay = 2'b00; + localparam logic [1:0] AxiRespSlvErr = 2'b10; - localparam [1:0] WR_IDLE = 2'd0; - localparam [1:0] WR_DATA = 2'd1; - localparam [1:0] WR_WAIT = 2'd2; - localparam [1:0] WR_RESP = 2'd3; - localparam [1:0] AXI_RESP_OKAY = 2'b00; - localparam [1:0] AXI_RESP_SLVERR = 2'b10; - - logic [1:0] s_rd_fsm_d, s_rd_fsm_q; - logic [1:0] s_wr_fsm_d, s_wr_fsm_q; + rd_state_e s_rd_fsm_d, s_rd_fsm_q; + wr_state_e s_wr_fsm_d, s_wr_fsm_q; logic [31:0] s_addr_d, s_addr_q; logic [31:0] s_rdata_d, s_rdata_q; @@ -58,16 +63,16 @@ module axi4l2ribp ( always_comb begin s_rd_fsm_d = s_rd_fsm_q; case (s_rd_fsm_q) - RD_IDLE: begin - if (arvalid_i) s_rd_fsm_d = RD_DATA; + RdIdle: begin + if (arvalid_i) s_rd_fsm_d = RdData; end - RD_DATA: begin - if (ribp.ready) s_rd_fsm_d = RD_WAIT; + RdData: begin + if (ribp.ready) s_rd_fsm_d = RdWait; end - RD_WAIT: begin - if (rready_i) s_rd_fsm_d = RD_IDLE; + RdWait: begin + if (rready_i) s_rd_fsm_d = RdIdle; end - default: s_rd_fsm_d = RD_IDLE; + default: s_rd_fsm_d = RdIdle; endcase end dffr #( @@ -82,19 +87,19 @@ module axi4l2ribp ( always_comb begin s_wr_fsm_d = s_wr_fsm_q; case (s_wr_fsm_q) - WR_IDLE: begin - if (awvalid_i) s_wr_fsm_d = WR_DATA; + WrIdle: begin + if (awvalid_i) s_wr_fsm_d = WrData; end - WR_DATA: begin - if (wvalid_i) s_wr_fsm_d = WR_WAIT; + WrData: begin + if (wvalid_i) s_wr_fsm_d = WrWait; end - WR_WAIT: begin - if (ribp.ready) s_wr_fsm_d = WR_RESP; + WrWait: begin + if (ribp.ready) s_wr_fsm_d = WrResp; end - WR_RESP: begin - if (bready_i) s_wr_fsm_d = WR_IDLE; + WrResp: begin + if (bready_i) s_wr_fsm_d = WrIdle; end - default: s_wr_fsm_d = WR_IDLE; + default: s_wr_fsm_d = WrIdle; endcase end dffr #( @@ -108,10 +113,10 @@ module axi4l2ribp ( always_comb begin ribp.addr = s_addr_q; - if (s_rd_fsm_q == RD_IDLE && arvalid_i) begin + if (s_rd_fsm_q == RdIdle && arvalid_i) begin ribp.addr = araddr_i; s_addr_d = araddr_i; - end else if (s_wr_fsm_q == WR_IDLE && awvalid_i) begin + end else if (s_wr_fsm_q == WrIdle && awvalid_i) begin ribp.addr = awaddr_i; s_addr_d = awaddr_i; end @@ -121,7 +126,7 @@ module axi4l2ribp ( ) u_addr_dffer ( .clk_i (aclk_i), .rst_n_i(aresetn_i), - .en_i ((s_rd_fsm_q == RD_IDLE && arvalid_i) || (s_wr_fsm_q == WR_IDLE && awvalid_i)), + .en_i ((s_rd_fsm_q == RdIdle && arvalid_i) || (s_wr_fsm_q == WrIdle && awvalid_i)), .dat_i (s_addr_d), .dat_o (s_addr_q) ); @@ -132,18 +137,18 @@ module axi4l2ribp ( ) u_rdata_dffer ( .clk_i (aclk_i), .rst_n_i(aresetn_i), - .en_i (s_rd_fsm_q == RD_DATA && ribp.ready), + .en_i (s_rd_fsm_q == RdData && ribp.ready), .dat_i (s_rdata_d), .dat_o (s_rdata_q) ); - assign s_rresp_d = ribp.resp_err ? AXI_RESP_SLVERR : AXI_RESP_OKAY; + assign s_rresp_d = ribp.resp_err ? AxiRespSlvErr : AxiRespOkay; dffer #( .DATA_WIDTH(2) ) u_rresp_dffer ( .clk_i (aclk_i), .rst_n_i(aresetn_i), - .en_i (s_rd_fsm_q == RD_DATA && ribp.ready), + .en_i (s_rd_fsm_q == RdData && ribp.ready), .dat_i (s_rresp_d), .dat_o (s_rresp_q) ); @@ -154,7 +159,7 @@ module axi4l2ribp ( ) u_wdata_dffer ( .clk_i (aclk_i), .rst_n_i(aresetn_i), - .en_i (s_wr_fsm_q == WR_DATA && wvalid_i), + .en_i (s_wr_fsm_q == WrData && wvalid_i), .dat_i (s_wdata_d), .dat_o (s_wdata_q) ); @@ -165,36 +170,36 @@ module axi4l2ribp ( ) u_wstrb_dffer ( .clk_i (aclk_i), .rst_n_i(aresetn_i), - .en_i (s_wr_fsm_q == WR_DATA && wvalid_i), + .en_i (s_wr_fsm_q == WrData && wvalid_i), .dat_i (s_wstrb_d), .dat_o (s_wstrb_q) ); - assign s_bresp_d = ribp.resp_err ? AXI_RESP_SLVERR : AXI_RESP_OKAY; + assign s_bresp_d = ribp.resp_err ? AxiRespSlvErr : AxiRespOkay; dffer #( .DATA_WIDTH(2) ) u_bresp_dffer ( .clk_i (aclk_i), .rst_n_i(aresetn_i), - .en_i (s_wr_fsm_q == WR_WAIT && ribp.ready), + .en_i (s_wr_fsm_q == WrWait && ribp.ready), .dat_i (s_bresp_d), .dat_o (s_bresp_q) ); // axil - assign arready_o = s_rd_fsm_q == RD_IDLE && arvalid_i; - assign rvalid_o = s_rd_fsm_q == RD_WAIT; + assign arready_o = s_rd_fsm_q == RdIdle && arvalid_i; + assign rvalid_o = s_rd_fsm_q == RdWait; assign rresp_o = s_rresp_q; assign rdata_o = s_rdata_q; - assign awready_o = s_wr_fsm_q == WR_IDLE && awvalid_i; - assign wready_o = s_wr_fsm_q == WR_DATA && wvalid_i; - assign bvalid_o = s_wr_fsm_q == WR_RESP; + assign awready_o = s_wr_fsm_q == WrIdle && awvalid_i; + assign wready_o = s_wr_fsm_q == WrData && wvalid_i; + assign bvalid_o = s_wr_fsm_q == WrResp; assign bresp_o = s_bresp_q; - assign s_rd_req = (s_rd_fsm_q == RD_DATA || s_rd_fsm_q == RD_WAIT); - assign s_wr_req = s_wr_fsm_q == WR_WAIT; + assign s_rd_req = (s_rd_fsm_q == RdData || s_rd_fsm_q == RdWait); + assign s_wr_req = s_wr_fsm_q == WrWait; assign ribp.valid = s_rd_req || s_wr_req; assign ribp.wdata = s_wdata_q; - assign ribp.wstrb = (s_wr_fsm_q == WR_WAIT) ? s_wstrb_q : '0; + assign ribp.wstrb = (s_wr_fsm_q == WrWait) ? s_wstrb_q : '0; endmodule diff --git a/rtl/ip/interconnect/ribp2ribp.sv b/rtl/ip/interconnect/ribp2ribp.sv index 6096df54..356e350e 100644 --- a/rtl/ip/interconnect/ribp2ribp.sv +++ b/rtl/ip/interconnect/ribp2ribp.sv @@ -29,6 +29,8 @@ module ribp2ribp ( input logic slvr_ready_i ); + // Requests and responses cross independently through depth-16 asynchronous + // FIFOs; each side observes only its local clock/reset domain. logic s_mstr_valid_re; logic s_req_empty; logic s_req_empty_d, s_req_empty_q; diff --git a/rtl/ip/interconnect/ribp_regslice.sv b/rtl/ip/interconnect/ribp_regslice.sv index 0fcd7825..bf1dc7e4 100644 --- a/rtl/ip/interconnect/ribp_regslice.sv +++ b/rtl/ip/interconnect/ribp_regslice.sv @@ -9,19 +9,23 @@ // See the Mulan PSL v2 for more details. module ribp_regslice ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, ribp_if.slave ribp_slv, ribp_if.master ribp_mst // verilog_format: on ); - localparam FSM_IDLE = 2'd0; - localparam FSM_REQ = 2'd1; - localparam FSM_RESP = 2'd2; + // One RIBP request is buffered until its response returns; backpressure is + // applied while it is outstanding, and response error/data are replayed. + typedef enum logic [1:0] { + Idle = 2'd0, + Request = 2'd1, + Response = 2'd2 + } regslice_state_e; - logic [1:0] s_fsm_d, s_fsm_q; + regslice_state_e s_fsm_d, s_fsm_q; logic s_ribp_mst_valid_d, s_ribp_mst_valid_q; logic [31:0] s_ribp_mst_addr_d, s_ribp_mst_addr_q; logic [31:0] s_ribp_mst_wdata_d, s_ribp_mst_wdata_q; @@ -49,26 +53,26 @@ module ribp_regslice ( ribp_slv.rdata = '0; ribp_slv.resp_err = 1'b0; unique case (s_fsm_q) - FSM_IDLE: begin + Idle: begin if (ribp_slv.valid) begin - s_fsm_d = FSM_REQ; + s_fsm_d = Request; s_ribp_mst_valid_d = ribp_slv.valid; s_ribp_mst_addr_d = ribp_slv.addr; s_ribp_mst_wdata_d = ribp_slv.wdata; s_ribp_mst_wstrb_d = ribp_slv.wstrb; end end - FSM_REQ: begin + Request: begin if (ribp_mst.ready) begin - s_fsm_d = FSM_RESP; + s_fsm_d = Response; s_ribp_mst_valid_d = 1'b0; s_ribp_mst_ready_d = ribp_mst.ready; s_ribp_mst_rdata_d = ribp_mst.rdata; s_ribp_mst_resp_err_d = ribp_mst.resp_err; end end - FSM_RESP: begin - s_fsm_d = FSM_IDLE; + Response: begin + s_fsm_d = Idle; ribp_slv.ready = s_ribp_mst_ready_q; ribp_slv.rdata = s_ribp_mst_rdata_q; ribp_slv.resp_err = s_ribp_mst_resp_err_q; diff --git a/rtl/ip/memory/sdram.sv b/rtl/ip/memory/axi4_sdram.sv similarity index 89% rename from rtl/ip/memory/sdram.sv rename to rtl/ip/memory/axi4_sdram.sv index 89858881..3e3c878c 100644 --- a/rtl/ip/memory/sdram.sv +++ b/rtl/ip/memory/axi4_sdram.sv @@ -38,20 +38,21 @@ interface sdram_if (); input dq_i, output dq_o ); - // verilog_format: on endinterface module axi4_sdram ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - axi4_if.slave axi4, - ribp_if.slave cfg_ribp, - sdram_if.dut sdram + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + axi4_if.slave axi4, + ribp_if.slave cfg_ribp, + sdram_if.dut sdram // verilog_format: on ); + // clk_i/rst_n_i drive all logic. Configuration and AXI traffic arbitrate onto + // one RIBP path; ready/resp_err return only from the selected target. logic s_sdram_reg_sel; logic [1:0] s_sdram_clkdiv; logic s_sdram_clk; @@ -91,7 +92,7 @@ module axi4_sdram ( assign u_mem_ribp_if.wdata = u_merged_ribp_if.wdata; assign u_mem_ribp_if.wstrb = u_merged_ribp_if.wstrb; - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment assign u_merged_ribp_if.ready = (u_reg_ribp_if.valid & u_reg_ribp_if.ready) | (u_mem_ribp_if.valid & u_mem_ribp_if.ready); assign u_merged_ribp_if.resp_err = diff --git a/rtl/ip/memory/opipsram_core.sv b/rtl/ip/memory/opipsram_core.sv deleted file mode 100644 index c20b2dfc..00000000 --- a/rtl/ip/memory/opipsram_core.sv +++ /dev/null @@ -1,10 +0,0 @@ -// Copyright (c) 2023-2026 Yuchi Miao -// retroSoC is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -// See the Mulan PSL v2 for more details. - diff --git a/rtl/ip/memory/psram_core.sv b/rtl/ip/memory/psram_core.sv index 669318fb..e9eb14b5 100644 --- a/rtl/ip/memory/psram_core.sv +++ b/rtl/ip/memory/psram_core.sv @@ -37,281 +37,283 @@ module psram_core ( ); // sclk(max: 144MHz ~ 6.94ns) // 6.94 * 50000 = 347us / 2 = 174us > 150us - `define RETROSOC_PSRAM__BOOT_COUNTER 18'd50_000 + localparam logic [17:0] BootCounter = 18'd50_000; - // verilog_format: off - localparam FSM_INIT = 5'd0; - localparam FSM_RSTEN = 5'd1; - localparam FSM_RSTEN2RST = 5'd2; - localparam FSM_RST = 5'd3; - localparam FSM_RST2QE = 5'd4; - localparam FSM_QE = 5'd5; - localparam FSM_QE2IDLE = 5'd6; - localparam FSM_IDLE = 5'd7; - localparam FSM_SEND = 5'd8; - localparam FSM_SEND_QPI = 5'd9; - localparam FSM_RD_PRE_QPI = 5'd10; - localparam FSM_RD_QPI = 5'd11; - localparam FSM_WR_QPI = 5'd12; - localparam FSM_RD2IDLE = 5'd13; - localparam FSM_WR2IDLE = 5'd14; - // verilog_format: on + typedef enum logic [4:0] { + Init = 5'd0, + ResetEnable = 5'd1, + ResetEnableToReset = 5'd2, + Reset = 5'd3, + ResetToQuadEnable = 5'd4, + QuadEnable = 5'd5, + QuadEnableToIdle = 5'd6, + Idle = 5'd7, + Send = 5'd8, + SendQpi = 5'd9, + ReadPreQpi = 5'd10, + ReadQpi = 5'd11, + WriteQpi = 5'd12, + ReadToIdle = 5'd13, + WriteToIdle = 5'd14 + } psram_state_e; - logic [ 4:0] r_fsm_state; - logic [ 4:0] r_fsm_state_tgt; - logic [17:0] r_boot_cnt; + psram_state_e s_fsm_state; + psram_state_e s_fsm_state_tgt; + logic [17:0] s_boot_cnt; // ca mean: cmd + addr - logic [31:0] r_xfer_ca; - logic [31:0] r_xfer_data; - logic [ 7:0] r_xfer_ca_bit_cnt; - logic [ 7:0] r_xfer_data_bit_cnt; - logic [ 7:0] r_xfer_byte_data; - logic [ 4:0] r_ce_cnt; - logic [ 3:0] r_rd_wait_cnt; - logic [ 2:0] r_cfg_chd; - logic r_dev_rst; - logic r_wr_st; - logic r_rd_st; - logic r_init_done; + logic [31:0] s_xfer_ca; + logic [31:0] s_xfer_data; + logic [ 7:0] s_xfer_ca_bit_cnt; + logic [ 7:0] s_xfer_data_bit_cnt; + logic [ 7:0] s_xfer_byte_data; + logic [ 4:0] s_ce_cnt; + logic [ 3:0] s_rd_wait_cnt; + logic [ 2:0] s_cfg_chd; + logic s_dev_rst; + logic s_wr_st; + logic s_rd_st; + logic s_init_done; - logic s_xfer_new_byte_upd; - logic [ 7:0] s_xfer_new_byte; + logic s_xfer_new_byte_upd; + logic [ 7:0] s_xfer_new_byte; - assign init_done_o = r_init_done; - assign idle_o = r_fsm_state == FSM_IDLE; - assign psram_sio_oen_o = (r_fsm_state == FSM_RD_PRE_QPI) | (r_fsm_state == FSM_RD_QPI); - assign mem_rdata_o = r_xfer_data; + assign init_done_o = s_init_done; + assign idle_o = s_fsm_state == Idle; + assign psram_sio_oen_o = (s_fsm_state == ReadPreQpi) | (s_fsm_state == ReadQpi); + assign mem_rdata_o = s_xfer_data; always_comb begin - if (r_fsm_state == FSM_INIT) begin + if (s_fsm_state == Init) begin {psram_sio3_o, psram_sio2_o, psram_miso_o, psram_mosi_o} = 4'd0; - end else if (r_fsm_state != FSM_IDLE) begin - if (r_fsm_state < FSM_SEND_QPI) begin // spi mode - psram_mosi_o = r_xfer_ca[31]; + end else if (s_fsm_state != Idle) begin + if (s_fsm_state < SendQpi) begin // spi mode + psram_mosi_o = s_xfer_ca[31]; {psram_sio3_o, psram_sio2_o, psram_miso_o} = 3'd0; end else begin // qpi mode {psram_sio3_o, psram_sio2_o, psram_miso_o, psram_mosi_o} = - r_fsm_state == FSM_WR_QPI - ? {r_xfer_byte_data[7:4]} - : {r_xfer_ca[31], r_xfer_ca[30], r_xfer_ca[29], r_xfer_ca[28]}; + s_fsm_state == WriteQpi + ? {s_xfer_byte_data[7:4]} + : {s_xfer_ca[31], s_xfer_ca[30], s_xfer_ca[29], s_xfer_ca[28]}; end end else begin {psram_sio3_o, psram_sio2_o, psram_miso_o, psram_mosi_o} = 4'd0; end end - always_ff @(posedge clk_i, negedge rst_n_i) begin - if (~rst_n_i) r_rd_st <= 1'b0; - else if (rd_st_i) r_rd_st <= 1'b1; - else if (r_fsm_state == FSM_RD2IDLE) r_rd_st <= 1'b0; + // These protocol-state processes retain ordered update and reset priority; + // decomposing them into Common DFFs would risk changing same-cycle behavior. + always_ff @(posedge clk_i or negedge rst_n_i) begin + if (~rst_n_i) s_rd_st <= 1'b0; + else if (rd_st_i) s_rd_st <= 1'b1; + else if (s_fsm_state == ReadToIdle) s_rd_st <= 1'b0; end - always_ff @(posedge clk_i, negedge rst_n_i) begin - if (~rst_n_i) r_wr_st <= 1'b0; - else if (wr_st_i) r_wr_st <= 1'b1; - else if (r_fsm_state == FSM_WR2IDLE) r_wr_st <= 1'b0; + always_ff @(posedge clk_i or negedge rst_n_i) begin + if (~rst_n_i) s_wr_st <= 1'b0; + else if (wr_st_i) s_wr_st <= 1'b1; + else if (s_fsm_state == WriteToIdle) s_wr_st <= 1'b0; end // >150us, ce high, sclk low, si/so/sio[3:0] low - always_ff @(posedge clk_i, negedge rst_n_i) begin + always_ff @(posedge clk_i or negedge rst_n_i) begin if (~rst_n_i) begin - r_fsm_state <= FSM_INIT; - r_fsm_state_tgt <= FSM_INIT; - r_boot_cnt <= `RETROSOC_PSRAM__BOOT_COUNTER; - r_xfer_ca <= 32'd0; - r_xfer_data <= 32'd0; - r_xfer_ca_bit_cnt <= 8'd0; - r_xfer_data_bit_cnt <= 8'd0; - r_xfer_byte_data <= 8'd0; - r_ce_cnt <= 5'd0; - r_rd_wait_cnt <= 4'd0; - r_cfg_chd <= 3'd0; - r_dev_rst <= 1'b1; - r_init_done <= 1'b0; + s_fsm_state <= Init; + s_fsm_state_tgt <= Init; + s_boot_cnt <= BootCounter; + s_xfer_ca <= 32'd0; + s_xfer_data <= 32'd0; + s_xfer_ca_bit_cnt <= 8'd0; + s_xfer_data_bit_cnt <= 8'd0; + s_xfer_byte_data <= 8'd0; + s_ce_cnt <= 5'd0; + s_rd_wait_cnt <= 4'd0; + s_cfg_chd <= 3'd0; + s_dev_rst <= 1'b1; + s_init_done <= 1'b0; mem_ready_o <= 1'b0; psram_sclk_o <= 1'b0; psram_ce_o <= 1'b1; end else begin mem_ready_o <= 1'b0; /* verilator lint_off CASEINCOMPLETE */ - case (r_fsm_state) - FSM_INIT: begin - if (r_boot_cnt != '0) r_boot_cnt <= r_boot_cnt - 1'b1; - else if (cfg_init_i) r_fsm_state <= FSM_RSTEN; + case (s_fsm_state) + Init: begin + if (s_boot_cnt != '0) s_boot_cnt <= s_boot_cnt - 1'b1; + else if (cfg_init_i) s_fsm_state <= ResetEnable; end - FSM_RSTEN: begin - r_xfer_ca <= {8'h66, 24'd0}; - r_xfer_ca_bit_cnt <= 8'd8; - r_cfg_chd <= 3'd0; + ResetEnable: begin + s_xfer_ca <= {8'h66, 24'd0}; + s_xfer_ca_bit_cnt <= 8'd8; + s_cfg_chd <= 3'd0; psram_ce_o <= 1'b0; - r_ce_cnt <= cfg_wait_i; - r_fsm_state <= FSM_SEND; - r_fsm_state_tgt <= FSM_RSTEN2RST; + s_ce_cnt <= cfg_wait_i; + s_fsm_state <= Send; + s_fsm_state_tgt <= ResetEnableToReset; end - FSM_RSTEN2RST: begin // tCPH >= 50ns, when 192MHz, ce need keep high(>=10 cycles) - if (r_cfg_chd == cfg_chd_i) begin - if (r_ce_cnt != cfg_wait_i) psram_ce_o <= 1'b1; - if (r_ce_cnt == 5'd0) r_fsm_state <= FSM_RST; - r_ce_cnt <= r_ce_cnt - 1'b1; + ResetEnableToReset: begin // tCPH >= 50ns, when 192MHz, ce need keep high(>=10 cycles) + if (s_cfg_chd == cfg_chd_i) begin + if (s_ce_cnt != cfg_wait_i) psram_ce_o <= 1'b1; + if (s_ce_cnt == 5'd0) s_fsm_state <= Reset; + s_ce_cnt <= s_ce_cnt - 1'b1; end else begin - r_cfg_chd <= r_cfg_chd + 1'b1; + s_cfg_chd <= s_cfg_chd + 1'b1; end end - FSM_RST: begin - r_xfer_ca <= {8'h99, 24'd0}; - r_xfer_ca_bit_cnt <= 8'd8; - r_cfg_chd <= 3'd0; + Reset: begin + s_xfer_ca <= {8'h99, 24'd0}; + s_xfer_ca_bit_cnt <= 8'd8; + s_cfg_chd <= 3'd0; psram_ce_o <= 1'b0; - r_ce_cnt <= cfg_wait_i; - r_fsm_state <= FSM_SEND; - r_fsm_state_tgt <= FSM_RST2QE; + s_ce_cnt <= cfg_wait_i; + s_fsm_state <= Send; + s_fsm_state_tgt <= ResetToQuadEnable; end - FSM_RST2QE: begin - if (r_cfg_chd == cfg_chd_i) begin - if (r_ce_cnt != cfg_wait_i) psram_ce_o <= 1'b1; - if (r_ce_cnt == 5'd0) r_fsm_state <= FSM_QE; - r_ce_cnt <= r_ce_cnt - 1'b1; + ResetToQuadEnable: begin + if (s_cfg_chd == cfg_chd_i) begin + if (s_ce_cnt != cfg_wait_i) psram_ce_o <= 1'b1; + if (s_ce_cnt == 5'd0) s_fsm_state <= QuadEnable; + s_ce_cnt <= s_ce_cnt - 1'b1; end else begin - r_cfg_chd <= r_cfg_chd + 1'b1; + s_cfg_chd <= s_cfg_chd + 1'b1; end end - FSM_QE: begin - r_xfer_ca <= {8'h35, 24'd0}; - r_xfer_ca_bit_cnt <= 8'd8; - r_cfg_chd <= 3'd0; + QuadEnable: begin + s_xfer_ca <= {8'h35, 24'd0}; + s_xfer_ca_bit_cnt <= 8'd8; + s_cfg_chd <= 3'd0; psram_ce_o <= 1'b0; - r_ce_cnt <= cfg_wait_i; - r_fsm_state <= FSM_SEND; - r_fsm_state_tgt <= FSM_QE2IDLE; + s_ce_cnt <= cfg_wait_i; + s_fsm_state <= Send; + s_fsm_state_tgt <= QuadEnableToIdle; end - FSM_QE2IDLE: begin - if (r_cfg_chd == cfg_chd_i) begin - if (r_ce_cnt != cfg_wait_i) psram_ce_o <= 1'b1; - if (r_ce_cnt == 5'd0) begin - r_fsm_state <= FSM_IDLE; - r_init_done <= 1'b1; + QuadEnableToIdle: begin + if (s_cfg_chd == cfg_chd_i) begin + if (s_ce_cnt != cfg_wait_i) psram_ce_o <= 1'b1; + if (s_ce_cnt == 5'd0) begin + s_fsm_state <= Idle; + s_init_done <= 1'b1; end - r_ce_cnt <= r_ce_cnt - 1'b1; + s_ce_cnt <= s_ce_cnt - 1'b1; end else begin - r_cfg_chd <= r_cfg_chd + 1'b1; + s_cfg_chd <= s_cfg_chd + 1'b1; end end - FSM_IDLE: begin + Idle: begin psram_sclk_o <= 1'b0; // release dev rst ctrl signal - if (r_dev_rst) begin - r_dev_rst <= 1'b0; + if (s_dev_rst) begin + s_dev_rst <= 1'b0; psram_ce_o <= 1'b1; - end else if (r_wr_st) begin - r_xfer_ca <= {8'h38, mem_addr_i[23:0]}; - r_xfer_ca_bit_cnt <= 8'd32; - r_fsm_state <= FSM_SEND_QPI; - r_fsm_state_tgt <= FSM_WR_QPI; - r_xfer_data_bit_cnt <= 8'd0; - r_cfg_chd <= 3'd0; + end else if (s_wr_st) begin + s_xfer_ca <= {8'h38, mem_addr_i[23:0]}; + s_xfer_ca_bit_cnt <= 8'd32; + s_fsm_state <= SendQpi; + s_fsm_state_tgt <= WriteQpi; + s_xfer_data_bit_cnt <= 8'd0; + s_cfg_chd <= 3'd0; psram_ce_o <= 1'b0; - end else if (r_rd_st) begin - r_xfer_ca <= {8'hEB, mem_addr_i[23:0]}; - r_xfer_ca_bit_cnt <= 8'd32; - r_fsm_state <= FSM_SEND_QPI; - r_fsm_state_tgt <= FSM_RD_PRE_QPI; - r_rd_wait_cnt <= 4'd12; // wait 6 cycle afer cmd+addr accrondig to TRM - r_xfer_data_bit_cnt <= 8'd0; - r_cfg_chd <= 3'd0; + end else if (s_rd_st) begin + s_xfer_ca <= {8'hEB, mem_addr_i[23:0]}; + s_xfer_ca_bit_cnt <= 8'd32; + s_fsm_state <= SendQpi; + s_fsm_state_tgt <= ReadPreQpi; + s_rd_wait_cnt <= 4'd12; // wait 6 cycle afer cmd+addr accrondig to TRM + s_xfer_data_bit_cnt <= 8'd0; + s_cfg_chd <= 3'd0; psram_ce_o <= 1'b0; end else begin psram_ce_o <= 1'b1; end end - FSM_SEND: begin + Send: begin psram_sclk_o <= ~psram_sclk_o; if (psram_sclk_o) begin - r_xfer_ca_bit_cnt <= r_xfer_ca_bit_cnt - 1'b1; - r_xfer_ca <= {r_xfer_ca[30:0], 1'b1}; - if (r_xfer_ca_bit_cnt == 8'd1) begin - r_fsm_state <= r_fsm_state_tgt; + s_xfer_ca_bit_cnt <= s_xfer_ca_bit_cnt - 1'b1; + s_xfer_ca <= {s_xfer_ca[30:0], 1'b1}; + if (s_xfer_ca_bit_cnt == 8'd1) begin + s_fsm_state <= s_fsm_state_tgt; end end end - FSM_SEND_QPI: begin + SendQpi: begin psram_sclk_o <= ~psram_sclk_o; if (psram_sclk_o) begin - r_xfer_ca_bit_cnt <= r_xfer_ca_bit_cnt - 8'd4; - r_xfer_ca <= {r_xfer_ca[27:0], 4'd1}; - if (r_xfer_ca_bit_cnt == 8'd4) begin - r_fsm_state <= r_fsm_state_tgt; - r_xfer_data <= mem_wdata_i; - r_xfer_byte_data <= mem_wdata_i[7:0]; + s_xfer_ca_bit_cnt <= s_xfer_ca_bit_cnt - 8'd4; + s_xfer_ca <= {s_xfer_ca[27:0], 4'd1}; + if (s_xfer_ca_bit_cnt == 8'd4) begin + s_fsm_state <= s_fsm_state_tgt; + s_xfer_data <= mem_wdata_i; + s_xfer_byte_data <= mem_wdata_i[7:0]; end end end - FSM_RD_PRE_QPI: begin + ReadPreQpi: begin // 6 cycles psram_sclk_o <= ~psram_sclk_o; - r_rd_wait_cnt <= r_rd_wait_cnt - 1'b1; - if (r_rd_wait_cnt == 4'd0) r_fsm_state <= FSM_RD_QPI; + s_rd_wait_cnt <= s_rd_wait_cnt - 1'b1; + if (s_rd_wait_cnt == 4'd0) s_fsm_state <= ReadQpi; end - FSM_RD_QPI: begin + ReadQpi: begin // the first 'psram_sclk_o' is 0 in this state psram_sclk_o <= ~psram_sclk_o; if (psram_sclk_o) begin - if (r_xfer_data_bit_cnt == 8'd8) r_xfer_data[7:0] <= r_xfer_byte_data; - else if (r_xfer_data_bit_cnt == 8'd16) r_xfer_data[15:8] <= r_xfer_byte_data; - else if (r_xfer_data_bit_cnt == 8'd24) r_xfer_data[23:16] <= r_xfer_byte_data; - r_xfer_byte_data <= { - r_xfer_byte_data[3:0], psram_sio3_i, psram_sio2_i, psram_miso_i, psram_mosi_i + if (s_xfer_data_bit_cnt == 8'd8) s_xfer_data[7:0] <= s_xfer_byte_data; + else if (s_xfer_data_bit_cnt == 8'd16) s_xfer_data[15:8] <= s_xfer_byte_data; + else if (s_xfer_data_bit_cnt == 8'd24) s_xfer_data[23:16] <= s_xfer_byte_data; + s_xfer_byte_data <= { + s_xfer_byte_data[3:0], psram_sio3_i, psram_sio2_i, psram_miso_i, psram_mosi_i }; - r_xfer_data_bit_cnt <= r_xfer_data_bit_cnt + 8'd4; - if (r_xfer_data_bit_cnt == xfer_data_bit_cnt_i - 8'd4) begin - r_fsm_state <= FSM_RD2IDLE; - r_ce_cnt <= cfg_wait_i; + s_xfer_data_bit_cnt <= s_xfer_data_bit_cnt + 8'd4; + if (s_xfer_data_bit_cnt == xfer_data_bit_cnt_i - 8'd4) begin + s_fsm_state <= ReadToIdle; + s_ce_cnt <= cfg_wait_i; end end end - FSM_WR_QPI: begin + WriteQpi: begin // the first 'psram_sclk_o' is 0 in this state psram_sclk_o <= ~psram_sclk_o; if (psram_sclk_o) begin - if (s_xfer_new_byte_upd) r_xfer_byte_data <= s_xfer_new_byte; - else r_xfer_byte_data <= {r_xfer_byte_data[3:0], 4'hF}; + if (s_xfer_new_byte_upd) s_xfer_byte_data <= s_xfer_new_byte; + else s_xfer_byte_data <= {s_xfer_byte_data[3:0], 4'hF}; - r_xfer_data_bit_cnt <= r_xfer_data_bit_cnt + 8'd4; - if (r_xfer_data_bit_cnt == xfer_data_bit_cnt_i - 8'd4) begin - r_fsm_state <= FSM_WR2IDLE; - r_ce_cnt <= cfg_wait_i; + s_xfer_data_bit_cnt <= s_xfer_data_bit_cnt + 8'd4; + if (s_xfer_data_bit_cnt == xfer_data_bit_cnt_i - 8'd4) begin + s_fsm_state <= WriteToIdle; + s_ce_cnt <= cfg_wait_i; end end end - FSM_RD2IDLE: begin - if (r_cfg_chd == cfg_chd_i) begin - if (r_ce_cnt != cfg_wait_i) begin + ReadToIdle: begin + if (s_cfg_chd == cfg_chd_i) begin + if (s_ce_cnt != cfg_wait_i) begin psram_ce_o <= 1'b1; - r_xfer_data[31:24] <= r_xfer_byte_data; // HACK: + s_xfer_data[31:24] <= s_xfer_byte_data; // HACK: end - if (r_ce_cnt == 5'd0) begin - r_fsm_state <= FSM_IDLE; + if (s_ce_cnt == 5'd0) begin + s_fsm_state <= Idle; mem_ready_o <= 1'b1; end - r_ce_cnt <= r_ce_cnt - 1'b1; + s_ce_cnt <= s_ce_cnt - 1'b1; end else begin - r_cfg_chd <= r_cfg_chd + 1'b1; + s_cfg_chd <= s_cfg_chd + 1'b1; end end - FSM_WR2IDLE: begin - if (r_cfg_chd == cfg_chd_i) begin - if (r_ce_cnt != cfg_wait_i) psram_ce_o <= 1'b1; - if (r_ce_cnt == 5'd0) begin - r_fsm_state <= FSM_IDLE; + WriteToIdle: begin + if (s_cfg_chd == cfg_chd_i) begin + if (s_ce_cnt != cfg_wait_i) psram_ce_o <= 1'b1; + if (s_ce_cnt == 5'd0) begin + s_fsm_state <= Idle; mem_ready_o <= 1'b1; end - r_ce_cnt <= r_ce_cnt - 1'b1; + s_ce_cnt <= s_ce_cnt - 1'b1; end else begin - r_cfg_chd <= r_cfg_chd + 1'b1; + s_cfg_chd <= s_cfg_chd + 1'b1; end end default: begin - r_fsm_state <= FSM_INIT; + s_fsm_state <= Init; psram_sclk_o <= 1'b0; psram_ce_o <= 1'b1; end @@ -320,8 +322,8 @@ module psram_core ( end load_new_byte u_load_new_byte ( - .xfer_data_bit_cnt_i(r_xfer_data_bit_cnt), - .wr_data_i (r_xfer_data), + .xfer_data_bit_cnt_i(s_xfer_data_bit_cnt), + .wr_data_i (s_xfer_data), .xfer_new_byte_upd_o(s_xfer_new_byte_upd), .xfer_new_byte_o (s_xfer_new_byte) ); diff --git a/rtl/ip/memory/opipsram.sv b/rtl/ip/memory/ribp_opipsram.sv similarity index 80% rename from rtl/ip/memory/opipsram.sv rename to rtl/ip/memory/ribp_opipsram.sv index b93ffba1..da1cbb31 100644 --- a/rtl/ip/memory/opipsram.sv +++ b/rtl/ip/memory/ribp_opipsram.sv @@ -33,19 +33,21 @@ interface opipsram_if (); endinterface module ribp_opipsram ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, - ribp_if.slave ribp, + ribp_if.slave ribp, opipsram_if.dut psram // verilog_format: on ); - logic dummy0; - logic dummy1; + // This placeholder accepts no RIBP requests (ready remains low) and reports + // no errors; all external memory outputs are deliberately held inactive. + logic s_dummy_clk; + logic s_dummy_rst_n; - assign dummy0 = clk_i; - assign dummy1 = rst_n_i; + assign s_dummy_clk = clk_i; + assign s_dummy_rst_n = rst_n_i; // ribp assign ribp.rdata = '0; diff --git a/rtl/ip/memory/psram.sv b/rtl/ip/memory/ribp_psram.sv similarity index 64% rename from rtl/ip/memory/psram.sv rename to rtl/ip/memory/ribp_psram.sv index ba6087f8..070f4094 100644 --- a/rtl/ip/memory/psram.sv +++ b/rtl/ip/memory/ribp_psram.sv @@ -18,7 +18,7 @@ // tKHKL(max: 1.5ns) is meet // // tCPH(min: 50ns) -> 50 / 6.94 = ~7.2 so wait cycles need to >= ceil(7.2) = 8, -// so 'r_cfg_wait' = 8 * 2 >= 16 in default, reset value is '18' +// so 's_cfg_wait' = 8 * 2 >= 16 in default, reset value is '18' // for lower freq, can modify this value for performance tuning // // tCEM(max: 8us) is enough long for just 32bits xfer: @@ -30,7 +30,7 @@ // // tCHD(min: 20ns) > tACLK + tCLK // sclk keep 6.94 * 1.5 = 10.41 at least(no meet!) -// need to set 'r_cfg_chd' = ceil(ceil(20 / 6.94) - 1.5) * 2 = 3, reset value is '4' +// need to set 's_cfg_chd' = ceil(ceil(20 / 6.94) - 1.5) * 2 = 3, reset value is '4' // for lower freq, can modify this value for performance tuning // // tSP(min: 2ns) is meet @@ -39,7 +39,7 @@ `ifndef RIBP_PSRAM_DEF_SV `define RIBP_PSRAM_DEF_SV -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_PSRAM_WAIT 8'h00 `define RIBP_PSRAM_CHD 8'h04 `define RIBP_PSRAM_INIT 8'h08 @@ -70,49 +70,52 @@ endinterface module ribp_psram ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, ribp_if.slave ribp, - psram_if.dut psram + psram_if.dut psram // verilog_format: on ); - // verilog_format: off - localparam FSM_IDLE = 6'd0; - localparam FSM_WE_ST = 6'd1; - localparam FSM_WE = 6'd2; - localparam FSM_RD_ST = 6'd3; - localparam FSM_RD = 6'd4; - // verilog_format: on + // clk_i/rst_n_i drive configuration and memory transfers. Configuration + // accesses respond immediately; one memory transaction remains outstanding + // until the PSRAM core asserts ready, and no response errors are generated. + typedef enum logic [5:0] { + Idle = 6'd0, + WriteStart = 6'd1, + Write = 6'd2, + ReadStart = 6'd3, + Read = 6'd4 + } psram_state_e; // reg - logic [ 4:0] r_cfg_wait; - logic [ 2:0] r_cfg_chd; - logic r_cfg_init; - logic s_cfg_reg_sel; - logic s_mem_sel; - logic s_mem_ready; - logic [31:0] s_mem_rdata; + logic [ 4:0] s_cfg_wait; + logic [ 2:0] s_cfg_chd; + logic s_cfg_init; + logic s_cfg_reg_sel; + logic s_mem_sel; + logic s_mem_ready; + logic [31:0] s_mem_rdata; - logic r_rd_st; - logic r_wr_st; - logic [ 7:0] r_xfer_data_bit_cnt; - logic [ 5:0] r_fsm_state; - logic [23:0] r_mem_addr; - logic [31:0] r_mem_wdata; + logic s_rd_st; + logic s_wr_st; + logic [ 7:0] s_xfer_data_bit_cnt; + psram_state_e s_fsm_state; + logic [23:0] s_mem_addr; + logic [31:0] s_mem_wdata; - logic s_psram_ce; - logic s_psram_sio_oen; - logic [ 1:0] s_disp_addr_ofst; - logic [ 7:0] s_disp_xfer_bit_cnt; - logic [31:0] s_disp_wdata; - logic s_init_done; - logic s_core_idle; - logic s_mem_valid_re; + logic s_psram_ce; + logic s_psram_sio_oen; + logic [ 1:0] s_disp_addr_ofst; + logic [ 7:0] s_disp_xfer_bit_cnt; + logic [31:0] s_disp_wdata; + logic s_init_done; + logic s_core_idle; + logic s_mem_valid_re; - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment assign psram.nss_o[0] = (~s_init_done) || (s_init_done && ribp.addr[24:23] == 2'd0) ? s_psram_ce : 1'b1; assign psram.nss_o[1] = (~s_init_done) || (s_init_done && ribp.addr[24:23] == 2'd1) ? s_psram_ce : 1'b1; assign psram.nss_o[2] = (~s_init_done) || (s_init_done && ribp.addr[24:23] == 2'd2) ? s_psram_ce : 1'b1; @@ -134,36 +137,38 @@ module ribp_psram ( if (s_mem_sel) begin ribp.rdata = s_mem_rdata; end else if (ribp.addr[7:0] == `RIBP_PSRAM_WAIT) begin - ribp.rdata = {27'd0, r_cfg_wait}; + ribp.rdata = {27'd0, s_cfg_wait}; end else if (ribp.addr[7:0] == `RIBP_PSRAM_CHD) begin - ribp.rdata = {29'd0, r_cfg_chd}; + ribp.rdata = {29'd0, s_cfg_chd}; end else if (ribp.addr[7:0] == `RIBP_PSRAM_INIT) begin - ribp.rdata = {31'd0, r_cfg_init}; + ribp.rdata = {31'd0, s_cfg_init}; end end // wait cycles(mmio) - always_ff @(posedge clk_i, negedge rst_n_i) begin - if (~rst_n_i) r_cfg_wait <= 5'd18; + // Configuration and transfer state share ordered request/reset priority, so + // these processes remain intact rather than splitting behavior across DFFs. + always_ff @(posedge clk_i or negedge rst_n_i) begin + if (~rst_n_i) s_cfg_wait <= 5'd18; else if (ribp.valid && ribp.wstrb[0] && s_cfg_reg_sel && (ribp.addr[7:0] == `RIBP_PSRAM_WAIT)) begin - r_cfg_wait <= ribp.wdata[4:0]; + s_cfg_wait <= ribp.wdata[4:0]; end end // extra cycle for tCHD(mmio) - always_ff @(posedge clk_i, negedge rst_n_i) begin - if (~rst_n_i) r_cfg_chd <= 3'd4; + always_ff @(posedge clk_i or negedge rst_n_i) begin + if (~rst_n_i) s_cfg_chd <= 3'd4; else if (ribp.valid && ribp.wstrb[0] && s_cfg_reg_sel && (ribp.addr[7:0] == `RIBP_PSRAM_CHD)) begin - r_cfg_chd <= ribp.wdata[2:0]; + s_cfg_chd <= ribp.wdata[2:0]; end end // init device/switch qpi mode - always_ff @(posedge clk_i, negedge rst_n_i) begin - if (~rst_n_i) r_cfg_init <= '0; + always_ff @(posedge clk_i or negedge rst_n_i) begin + if (~rst_n_i) s_cfg_init <= '0; else if (ribp.valid && ribp.wstrb[0] && s_cfg_reg_sel && (ribp.addr[7:0] == `RIBP_PSRAM_INIT)) begin - r_cfg_init <= ribp.wdata[0]; + s_cfg_init <= ribp.wdata[0]; end end @@ -176,55 +181,55 @@ module ribp_psram ( .re_o (s_mem_valid_re) ); - always_ff @(posedge clk_i, negedge rst_n_i) begin + always_ff @(posedge clk_i or negedge rst_n_i) begin if (~rst_n_i) begin - r_rd_st <= '0; - r_wr_st <= '0; - r_xfer_data_bit_cnt <= '0; - r_fsm_state <= FSM_IDLE; - r_mem_addr <= '0; - r_mem_wdata <= '0; + s_rd_st <= '0; + s_wr_st <= '0; + s_xfer_data_bit_cnt <= '0; + s_fsm_state <= Idle; + s_mem_addr <= '0; + s_mem_wdata <= '0; end else begin if (s_mem_sel) begin /* verilator lint_off CASEINCOMPLETE */ - case (r_fsm_state) - FSM_IDLE: begin + case (s_fsm_state) + Idle: begin if (s_mem_valid_re && (|ribp.wstrb)) begin - r_fsm_state <= FSM_WE_ST; - r_xfer_data_bit_cnt <= s_disp_xfer_bit_cnt; - r_mem_addr <= {1'b0, ribp.addr[22:0]} + {22'd0, s_disp_addr_ofst}; - r_mem_wdata <= s_disp_wdata; + s_fsm_state <= WriteStart; + s_xfer_data_bit_cnt <= s_disp_xfer_bit_cnt; + s_mem_addr <= {1'b0, ribp.addr[22:0]} + {22'd0, s_disp_addr_ofst}; + s_mem_wdata <= s_disp_wdata; end else if (s_mem_valid_re && (~(|ribp.wstrb))) begin - r_fsm_state <= FSM_RD_ST; - r_xfer_data_bit_cnt <= 8'd32; - r_mem_addr <= {1'b0, ribp.addr[22:0]}; - r_mem_wdata <= ribp.wdata; // NOTE: no used + s_fsm_state <= ReadStart; + s_xfer_data_bit_cnt <= 8'd32; + s_mem_addr <= {1'b0, ribp.addr[22:0]}; + s_mem_wdata <= ribp.wdata; // NOTE: no used end end - FSM_WE_ST: begin + WriteStart: begin if (s_core_idle) begin - r_wr_st <= 1'b1; - r_fsm_state <= FSM_WE; + s_wr_st <= 1'b1; + s_fsm_state <= Write; end end - FSM_WE: begin - r_wr_st <= 1'b0; - if (s_mem_ready) r_fsm_state <= FSM_IDLE; + Write: begin + s_wr_st <= 1'b0; + if (s_mem_ready) s_fsm_state <= Idle; end - FSM_RD_ST: begin + ReadStart: begin if (s_core_idle) begin - r_rd_st <= 1'b1; - r_fsm_state <= FSM_RD; + s_rd_st <= 1'b1; + s_fsm_state <= Read; end end - FSM_RD: begin - r_rd_st <= 1'b0; - if (s_mem_ready) r_fsm_state <= FSM_IDLE; + Read: begin + s_rd_st <= 1'b0; + if (s_mem_ready) s_fsm_state <= Idle; end default: begin - r_fsm_state <= FSM_IDLE; - r_rd_st <= 1'b0; - r_wr_st <= 1'b0; + s_fsm_state <= Idle; + s_rd_st <= 1'b0; + s_wr_st <= 1'b0; end endcase end @@ -233,16 +238,16 @@ module ribp_psram ( psram_core u_psram_core ( .clk_i (clk_i), .rst_n_i (rst_n_i), - .cfg_wait_i (r_cfg_wait), - .cfg_chd_i (r_cfg_chd), - .cfg_init_i (r_cfg_init), + .cfg_wait_i (s_cfg_wait), + .cfg_chd_i (s_cfg_chd), + .cfg_init_i (s_cfg_init), .mem_ready_o (s_mem_ready), - .mem_addr_i (r_mem_addr), - .mem_wdata_i (r_mem_wdata), + .mem_addr_i (s_mem_addr), + .mem_wdata_i (s_mem_wdata), .mem_rdata_o (s_mem_rdata), - .xfer_data_bit_cnt_i(r_xfer_data_bit_cnt), - .rd_st_i (r_rd_st), - .wr_st_i (r_wr_st), + .xfer_data_bit_cnt_i(s_xfer_data_bit_cnt), + .rd_st_i (s_rd_st), + .wr_st_i (s_wr_st), .init_done_o (s_init_done), .idle_o (s_core_idle), .psram_sclk_o (psram.sck_o), diff --git a/rtl/ip/memory/sdram_core.sv b/rtl/ip/memory/sdram_core.sv index 16e95a89..86f907b2 100644 --- a/rtl/ip/memory/sdram_core.sv +++ b/rtl/ip/memory/sdram_core.sv @@ -32,99 +32,104 @@ `include "mmap_define.svh" module sdram_core ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic sdram_clk_i, - input logic fir_edge_i, - input logic sec_edge_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic sdram_clk_i, + input logic fir_edge_i, + input logic sec_edge_i, ribp_if.slave ribp, - sdram_if.dut sdram + sdram_if.dut sdram // verilog_format: on ); - localparam CLK_FREQ = 36; - localparam TRP_NS = 20; - localparam TRC_NS = 66; - localparam TRCD_NS = 20; - localparam TCH_NS = 2; - localparam CAS = 3'd2; + // clk_i/rst_n_i control the scheduler; SDRAM commands advance only on the + // supplied phase edges. RIBP accepts one captured request and never reports + // resp_err; ready is asserted when that request's response is available. + localparam int signed ClkFreq = 32'sd36; + localparam int signed TrpNs = 32'sd20; + localparam int signed TrcNs = 32'sd66; + localparam int signed TrcdNs = 32'sd20; + localparam int signed TchNs = 32'sd2; + localparam logic [2:0] Cas = 3'd2; - // CLK_FREQ * 1/CLK_FREQe6s = 1us - localparam ONE_OVER_MICROSECOND = CLK_FREQ; - localparam WAIT_100US = 100 * ONE_OVER_MICROSECOND; - // command period; PRE to ACT in ns, e.g. 20ns - localparam TRP = (TRP_NS * ONE_OVER_MICROSECOND / 1000) + 1; - // tRC command period (REF to REF/ACT TO ACT) in ns - localparam TRC = (TRC_NS * ONE_OVER_MICROSECOND / 1000) + 1; - // tRCD active command to read/write command delay; row-col-delay in ns - localparam TRCD = (TRCD_NS * ONE_OVER_MICROSECOND / 1000) + 1; - // tCH command hold time - localparam TCH = (TCH_NS * ONE_OVER_MICROSECOND / 1000) + 1; + // ClkFreq * 1/CLK_FREQe6s = 1us + localparam int signed OneOverMicrosecond = ClkFreq; + localparam int signed Wait100Us = 32'sd100 * OneOverMicrosecond; + // Command period: PRE to ACT in ns, e.g. 20 ns. + localparam int signed Trp = (TrpNs * OneOverMicrosecond / 32'sd1000) + 32'sd1; + // tRC command period (REF to REF/ACT to ACT) in ns. + localparam int signed Trc = (TrcNs * OneOverMicrosecond / 32'sd1000) + 32'sd1; + // tRCD active-command to read/write-command delay in ns. + localparam int signed Trcd = (TrcdNs * OneOverMicrosecond / 32'sd1000) + 32'sd1; + // tCH command hold time. + localparam int signed Tch = (TchNs * OneOverMicrosecond / 32'sd1000) + 32'sd1; // 000: 1-burst, 001: 2-burst // 010: 4-burst, 011: 8-burst - localparam BURST_LENGTH = 3'b001; + localparam logic [2:0] BurstLength = 3'b001; // 0: sequential, 1: interleaved - localparam ACCESS_TYPE = 1'b0; - // 2/3 allowed, tRCD=20ns -> 3 cycles@128MHz - localparam CAS_LATENCY = CAS; - // only 00 (standard operation) allowed - localparam OP_MODE = 2'b00; - // 0: write burst enabled, 1: only single access write - localparam NO_WRITE_BURST = 1'b0; - // (CS, RAS, CAS, WE) + localparam logic AccessType = 1'b0; + // 2/3 allowed, tRCD=20 ns -> 3 cycles@128 MHz + localparam logic [2:0] CasLatency = Cas; + // Only 00 (standard operation) is allowed. + localparam logic [1:0] OpMode = 2'b00; + // 0: write burst enabled, 1: only single-access write. + localparam logic NoWriteBurst = 1'b0; + // (CS, RAS, Cas, WE) // mode register set - localparam CMD_MRS = 4'b0000; - // bank active - localparam CMD_ACT = 4'b0011; - // have read variant with autoprecharge set A10=H - localparam CMD_READ = 4'b0101; - // A10=H to have autoprecharge - localparam CMD_WRITE = 4'b0100; - // burst stop - localparam CMD_BST = 4'b0110; - // precharge selected bank, A10=H both banks - localparam CMD_PRER = 4'b0010; - // auto refresh (cke=H), selfrefresh assign cke=L - localparam CMD_RFSH = 4'b0001; - localparam CMD_NOP = 4'b0111; - // sdram mode NOTE: can config - localparam SDRAM_MODE = {3'b0, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + localparam logic [3:0] CmdMrs = 4'b0000; + // Bank active. + localparam logic [3:0] CmdAct = 4'b0011; + // Read variant with auto-precharge set A10=H. + localparam logic [3:0] CmdRead = 4'b0101; + // A10=H selects auto-precharge. + localparam logic [3:0] CmdWrite = 4'b0100; + // Burst stop. + localparam logic [3:0] CmdBst = 4'b0110; + // Precharge selected bank; A10=H selects both banks. + localparam logic [3:0] CmdPrer = 4'b0010; + // Auto refresh (cke=H); self refresh assigns cke=L. + localparam logic [3:0] CmdRfsh = 4'b0001; + localparam logic [3:0] CmdNop = 4'b0111; + // SDRAM mode; this implementation does not configure it dynamically. + localparam logic [12:0] SdramMode = { + 3'b0, NoWriteBurst, OpMode, CasLatency, AccessType, BurstLength + }; - // verilog_format: off - localparam RESET = 4'd0; - localparam ASSERT_CKE = 4'd1; - localparam INIT_SEQ_PRE_CHARGE_ALL = 4'd2; - localparam INIT_SEQ_AUTO_REFRESH0 = 4'd3; - localparam INIT_SEQ_AUTO_REFRESH1 = 4'd4; - localparam INIT_SEQ_LOAD_MODE = 4'd5; - localparam IDLE = 4'd6; - localparam COL_READ = 4'd7; - localparam COL_READL = 4'd8; - localparam COL_READH = 4'd9; - localparam COL_WRITEL = 4'd10; - localparam COL_WRITEH = 4'd11; - localparam AUTO_REFRESH = 4'd12; - localparam PRE_CHARGE_ALL = 4'd13; - localparam WAIT_STATE = 4'd14; - localparam LAST_STATE = 4'd15; - // verilog_format: on + typedef enum logic [3:0] { + Reset = 4'd0, + AssertCke = 4'd1, + InitSeqPreChargeAll = 4'd2, + InitSeqAutoRefresh0 = 4'd3, + InitSeqAutoRefresh1 = 4'd4, + InitSeqLoadMode = 4'd5, + Idle = 4'd6, + ColRead = 4'd7, + ColReadLow = 4'd8, + ColReadHigh = 4'd9, + ColWriteLow = 4'd10, + ColWriteHigh = 4'd11, + AutoRefresh = 4'd12, + PreChargeAll = 4'd13, + WaitState = 4'd14, + LastState = 4'd15 + } sdram_state_e; `ifndef SYNTHESIS initial begin - $display("Clk frequence: %6d MHz", CLK_FREQ); - $display("WAIT_100US: %6d cycles", WAIT_100US); - $display("TRP: %6d cycles", TRP); - $display("TRC: %6d cycles", TRC); - $display("TRCD: %6d cycles", TRCD); - $display("TCH: %6d cycles", TCH); - $display("CAS_LATENCY: %6d cycles", CAS_LATENCY); + $display("Clk frequence: %6d MHz", ClkFreq); + $display("Wait100Us: %6d cycles", Wait100Us); + $display("Trp: %6d cycles", Trp); + $display("Trc: %6d cycles", Trc); + $display("Trcd: %6d cycles", Trcd); + $display("Tch: %6d cycles", Tch); + $display("CasLatency: %6d cycles", CasLatency); end `endif - logic [3:0] s_state_d, s_state_q; - logic [3:0] s_ret_state_d, s_ret_state_q; + sdram_state_e s_state_d, s_state_q; + sdram_state_e s_ret_state_d, s_ret_state_q; logic [15:0] s_wait_cnt_d, s_wait_cnt_q; logic [3:0] s_cmd_d, s_cmd_q; logic s_ready_d, s_ready_q; @@ -137,7 +142,7 @@ module sdram_core ( logic s_cke_q, s_cke_d; logic [12:0] s_addr_d, s_addr_q; logic s_upd_ready_d, s_upd_ready_q; - // Registered RIB inputs (captured at IDLE-to-ACT) + // Registered RIB inputs (captured at Idle-to-ACT) logic [31:0] s_ribp_addr_d, s_ribp_addr_q; logic [25:0] s_mem_addr; logic [31:0] s_req_addr_rel; @@ -182,46 +187,46 @@ module sdram_core ( s_ribp_wdata_d = s_ribp_wdata_q; s_ribp_wstrb_d = s_ribp_wstrb_q; case (s_state_q) - RESET: begin + Reset: begin s_cke_d = 1'b0; - s_state_d = WAIT_STATE; - s_ret_state_d = ASSERT_CKE; - s_wait_cnt_d = 16'(WAIT_100US); + s_state_d = WaitState; + s_ret_state_d = AssertCke; + s_wait_cnt_d = 16'(Wait100Us); end - ASSERT_CKE: begin + AssertCke: begin s_cke_d = 1'b1; - s_state_d = WAIT_STATE; - s_ret_state_d = INIT_SEQ_PRE_CHARGE_ALL; + s_state_d = WaitState; + s_ret_state_d = InitSeqPreChargeAll; s_wait_cnt_d = 16'd2; end - INIT_SEQ_PRE_CHARGE_ALL: begin + InitSeqPreChargeAll: begin s_cke_d = 1'b1; - s_cmd_d = CMD_PRER; + s_cmd_d = CmdPrer; s_addr_d[10] = 1'b1; - s_state_d = WAIT_STATE; - s_ret_state_d = INIT_SEQ_AUTO_REFRESH0; - s_wait_cnt_d = 16'(TRP); + s_state_d = WaitState; + s_ret_state_d = InitSeqAutoRefresh0; + s_wait_cnt_d = 16'(Trp); end - INIT_SEQ_AUTO_REFRESH0: begin - s_cmd_d = CMD_RFSH; - s_state_d = WAIT_STATE; - s_ret_state_d = INIT_SEQ_AUTO_REFRESH1; - s_wait_cnt_d = 16'(TRC); + InitSeqAutoRefresh0: begin + s_cmd_d = CmdRfsh; + s_state_d = WaitState; + s_ret_state_d = InitSeqAutoRefresh1; + s_wait_cnt_d = 16'(Trc); end - INIT_SEQ_AUTO_REFRESH1: begin - s_cmd_d = CMD_RFSH; - s_state_d = WAIT_STATE; - s_ret_state_d = INIT_SEQ_LOAD_MODE; - s_wait_cnt_d = 16'(TRC); + InitSeqAutoRefresh1: begin + s_cmd_d = CmdRfsh; + s_state_d = WaitState; + s_ret_state_d = InitSeqLoadMode; + s_wait_cnt_d = 16'(Trc); end - INIT_SEQ_LOAD_MODE: begin - s_cmd_d = CMD_MRS; - s_addr_d = SDRAM_MODE; - s_state_d = WAIT_STATE; - s_ret_state_d = IDLE; - s_wait_cnt_d = 16'(TCH); + InitSeqLoadMode: begin + s_cmd_d = CmdMrs; + s_addr_d = SdramMode; + s_state_d = WaitState; + s_ret_state_d = Idle; + s_wait_cnt_d = 16'(Tch); end - IDLE: begin + Idle: begin s_oe_d = 1'b0; s_dqm_d = 2'b11; s_ready_d = 1'b0; @@ -230,103 +235,106 @@ module sdram_core ( s_ribp_addr_d = ribp.addr; s_ribp_wdata_d = ribp.wdata; s_ribp_wstrb_d = ribp.wstrb; - s_cmd_d = CMD_ACT; + s_cmd_d = CmdAct; s_ba_d = s_req_addr_rel[25:24]; s_addr_d = s_req_addr_rel[23:11]; - s_state_d = WAIT_STATE; - s_ret_state_d = |ribp.wstrb ? COL_WRITEL : COL_READ; - s_wait_cnt_d = 16'(TRCD); + s_state_d = WaitState; + s_ret_state_d = |ribp.wstrb ? ColWriteLow : ColRead; + s_wait_cnt_d = 16'(Trcd); s_upd_ready_d = 1'b1; end else begin // autorefresh - s_cmd_d = CMD_RFSH; + s_cmd_d = CmdRfsh; s_addr_d = '0; s_ba_d = '0; - // TRC - s_state_d = WAIT_STATE; - s_ret_state_d = IDLE; - s_wait_cnt_d = 16'(TRC); + // Trc + s_state_d = WaitState; + s_ret_state_d = Idle; + s_wait_cnt_d = 16'(Trc); s_upd_ready_d = 1'b0; end end - COL_READ: begin - s_cmd_d = CMD_READ; + ColRead: begin + s_cmd_d = CmdRead; s_dqm_d = 2'b00; // autoprecharge and column (use registered addr) s_ba_d = s_mem_addr[25:24]; s_addr_d = {3'b001, s_mem_addr[10:2], 1'b0}; // $display("rd col addr: %0x", s_addr_d); - s_state_d = WAIT_STATE; - s_ret_state_d = COL_READL; - s_wait_cnt_d = 16'(CAS_LATENCY); + s_state_d = WaitState; + s_ret_state_d = ColReadLow; + s_wait_cnt_d = 16'(CasLatency); end - COL_READL: begin - s_cmd_d = CMD_NOP; + ColReadLow: begin + s_cmd_d = CmdNop; s_dqm_d = 2'b00; s_rdata_d[15:0] = sdram.dq_i; - s_state_d = COL_READH; + s_state_d = ColReadHigh; end - COL_READH: begin - s_cmd_d = CMD_NOP; + ColReadHigh: begin + s_cmd_d = CmdNop; s_dqm_d = 2'b00; s_rdata_d[31:16] = sdram.dq_i; - s_state_d = WAIT_STATE; - s_ret_state_d = IDLE; - s_wait_cnt_d = 16'(TRP); + s_state_d = WaitState; + s_ret_state_d = Idle; + s_wait_cnt_d = 16'(Trp); end - COL_WRITEL: begin - s_cmd_d = CMD_WRITE; + ColWriteLow: begin + s_cmd_d = CmdWrite; s_dqm_d = ~s_ribp_wstrb_q[1:0]; // autoprecharge and column (use registered addr) s_ba_d = s_mem_addr[25:24]; s_addr_d = {3'b001, s_mem_addr[10:2], 1'b0}; s_dq_d = s_ribp_wdata_q[15:0]; s_oe_d = 1'b1; - s_state_d = COL_WRITEH; + s_state_d = ColWriteHigh; end - COL_WRITEH: begin - s_cmd_d = CMD_NOP; + ColWriteHigh: begin + s_cmd_d = CmdNop; s_dqm_d = ~s_ribp_wstrb_q[3:2]; // autoprecharge and column (use registered wdata) s_dq_d = s_ribp_wdata_q[31:16]; s_oe_d = 1'b1; - s_state_d = WAIT_STATE; - s_ret_state_d = IDLE; - s_wait_cnt_d = 16'(TRP); + s_state_d = WaitState; + s_ret_state_d = Idle; + s_wait_cnt_d = 16'(Trp); end // NOTE: notused - // PRE_CHARGE_ALL: begin - // s_cmd_d = CMD_PRER; + // PreChargeAll: begin + // s_cmd_d = CmdPrer; // // select all banks // s_addr_d[10] = 1'b1; // s_ba_d = 0; - // s_state_d = WAIT_STATE; - // s_ret_state_d = IDLE; - // s_wait_cnt_d = TRP; + // s_state_d = WaitState; + // s_ret_state_d = Idle; + // s_wait_cnt_d = Trp; // end - WAIT_STATE: begin - s_cmd_d = CMD_NOP; + WaitState: begin + s_cmd_d = CmdNop; s_wait_cnt_d = s_wait_cnt_q - 1'b1; if (s_wait_cnt_q == 16'd1) begin s_state_d = s_ret_state_q; - if (s_ret_state_q == IDLE && s_upd_ready_q) begin + if (s_ret_state_q == Idle && s_upd_ready_q) begin s_upd_ready_d = 1'b0; s_ready_d = 1'b1; end end end default: begin + // Preserve the legacy illegal-state hold rather than adding recovery. s_state_d = s_state_q; end endcase end - always_ff @(posedge clk_i, negedge rst_n_i) begin + // The fir/sec edge-qualified state updates share reset and update priority. + // Retain this process to preserve the SDRAM cycle schedule exactly. + always_ff @(posedge clk_i or negedge rst_n_i) begin if (~rst_n_i) begin - s_state_q <= RESET; - s_ret_state_q <= RESET; + s_state_q <= Reset; + s_ret_state_q <= Reset; s_wait_cnt_q <= '0; - s_cmd_q <= CMD_NOP; + s_cmd_q <= CmdNop; s_ready_q <= '0; s_rdata_q <= '0; // sdram diff --git a/rtl/ip/memory/sdram_reg.sv b/rtl/ip/memory/sdram_reg.sv index 2d0e321b..3ab1c97a 100644 --- a/rtl/ip/memory/sdram_reg.sv +++ b/rtl/ip/memory/sdram_reg.sv @@ -11,7 +11,7 @@ `ifndef RIBP_SDRAM_DEF_SV `define RIBP_SDRAM_DEF_SV -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_SDRAM_CLKDIV 8'h00 `define RIBP_SDRAM_CFG 8'h04 // verilog_format: on @@ -19,10 +19,10 @@ `endif module sdram_reg ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, - ribp_if.slave ribp, + ribp_if.slave ribp, output logic [1:0] clkdiv_o // verilog_format: on ); diff --git a/rtl/ip/multimedia/dvp.sv b/rtl/ip/multimedia/axi4s_dvp.sv similarity index 86% rename from rtl/ip/multimedia/dvp.sv rename to rtl/ip/multimedia/axi4s_dvp.sv index 334c2153..3698c8eb 100644 --- a/rtl/ip/multimedia/dvp.sv +++ b/rtl/ip/multimedia/axi4s_dvp.sv @@ -14,14 +14,17 @@ interface dvp_if (); endinterface /* verilator lint_on DECLFILENAME */ +// Configuration and commands cross from clk_i into the selected pixel clock; +// captured payloads return through the warm-flush FIFO. The FIFO backpressures +// the pixel core, and reset clears both transfer domains before streaming resumes. module axi4s_dvp ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - ribp_if.slave ribp, - axi4_stream_if.source rx_axis, - dvp_if.dut dvp, - output logic irq_o + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + ribp_if.slave ribp, + axi4_stream_if.source rx_axis, + dvp_if.dut dvp, + output logic irq_o // verilog_format: on ); localparam int DvpPayloadWidth = 42; @@ -56,6 +59,8 @@ module axi4s_dvp ( logic s_fifo_src_clear; logic s_fifo_src_clear_busy; logic s_fifo_dst_clear_busy; + logic [DvpPayloadWidth-1:0] s_core_push_data; + logic s_core_push_valid; logic [ 31:0] s_fifo_rx_data; logic s_rx_pop; logic s_fifo_full_sys; @@ -184,8 +189,6 @@ module axi4s_dvp ( .dst_valid_o (s_fifo_dst_valid), .dst_ready_i (s_fifo_dst_ready) ); - logic [DvpPayloadWidth-1:0] s_core_push_data; - logic s_core_push_valid; assign s_cmd_core = s_cmd_v_pclk ? s_cmd_pclk : 2'b00; cdc_sync #( @@ -211,42 +214,42 @@ module axi4s_dvp ( edge_det #( .STAGE(2) ) u_frame_start_event ( - .clk_i (clk_i), + .clk_i(clk_i), .rst_n_i(rst_n_i), - .dat_i (s_frm_start_tgl), - .dat_o (), - .re_o (s_frame_start_event), - .fe_o () + .dat_i(s_frm_start_tgl), + .dat_o(), // Synchronized level is intentionally unused; only the rising edge is consumed. + .re_o(s_frame_start_event), + .fe_o() // Falling edge is intentionally unused. ); edge_det #( .STAGE(2) ) u_line_done_event ( - .clk_i (clk_i), + .clk_i(clk_i), .rst_n_i(rst_n_i), - .dat_i (s_line_done_tgl), - .dat_o (), - .re_o (s_line_done_event), - .fe_o () + .dat_i(s_line_done_tgl), + .dat_o(), // Synchronized level is intentionally unused; only the rising edge is consumed. + .re_o(s_line_done_event), + .fe_o() // Falling edge is intentionally unused. ); edge_det #( .STAGE(2) ) u_frame_done_event ( - .clk_i (clk_i), + .clk_i(clk_i), .rst_n_i(rst_n_i), - .dat_i (s_frm_done_tgl), - .dat_o (), - .re_o (s_frame_done_event), - .fe_o () + .dat_i(s_frm_done_tgl), + .dat_o(), // Synchronized level is intentionally unused; only the rising edge is consumed. + .re_o(s_frame_done_event), + .fe_o() // Falling edge is intentionally unused. ); edge_det #( .STAGE(2) ) u_error_event ( - .clk_i (clk_i), + .clk_i(clk_i), .rst_n_i(rst_n_i), - .dat_i (s_err_tgl), - .dat_o (), - .re_o (s_err_evt), - .fe_o () + .dat_i(s_err_tgl), + .dat_o(), // Synchronized level is intentionally unused; only the rising edge is consumed. + .re_o(s_err_evt), + .fe_o() // Falling edge is intentionally unused. ); /* verilator lint_on PINCONNECTEMPTY */ diff --git a/rtl/ip/multimedia/dvp_core.sv b/rtl/ip/multimedia/dvp_core.sv index 97a27f8b..9c8d0363 100644 --- a/rtl/ip/multimedia/dvp_core.sv +++ b/rtl/ip/multimedia/dvp_core.sv @@ -4,7 +4,7 @@ `include "dvp_define.svh" module dvp_core ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, /* verilator lint_off UNUSEDSIGNAL */ diff --git a/rtl/ip/multimedia/dvp_define.svh b/rtl/ip/multimedia/dvp_define.svh index 32794baa..5b5ec985 100644 --- a/rtl/ip/multimedia/dvp_define.svh +++ b/rtl/ip/multimedia/dvp_define.svh @@ -4,7 +4,7 @@ `ifndef RIBP_DVP_DEFINE_SVH `define RIBP_DVP_DEFINE_SVH -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_DVP_CTRL 12'h000 `define RIBP_DVP_RXDATA 12'h004 `define RIBP_DVP_STATUS 12'h008 @@ -32,12 +32,12 @@ `define RIBP_DVP__CTRL_SNAPSHOT 1 `define RIBP_DVP__CTRL_CROP_ENABLE 2 `define RIBP_DVP__STREAM_ENABLE 0 -`define RIBP_DVP__FORMAT_SELECT 1:0 +`define RIBP_DVP__FORMAT_SELECT 1:0 `define RIBP_DVP__FORMAT_BYTE_SWAP 2 `define RIBP_DVP__FORMAT_PIXEL_SWAP 3 -`define RIBP_DVP__SYNC_VSYNC_LOW 0 -`define RIBP_DVP__SYNC_HREF_LOW 1 -`define RIBP_DVP__SYNC_PCLK_FALLING 2 +`define RIBP_DVP__SYNC_VSYNC_LOW 0 +`define RIBP_DVP__SYNC_HREF_LOW 1 +`define RIBP_DVP__SYNC_PCLK_FALLING 2 `define RIBP_DVP__INTR_FRAME_START 0 `define RIBP_DVP__INTR_LINE_DONE 1 diff --git a/rtl/ip/multimedia/dvp_reg.sv b/rtl/ip/multimedia/dvp_reg.sv index 37af8ebc..8a888e5c 100644 --- a/rtl/ip/multimedia/dvp_reg.sv +++ b/rtl/ip/multimedia/dvp_reg.sv @@ -4,7 +4,7 @@ `include "dvp_define.svh" module dvp_reg ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, ribp_if.slave ribp, diff --git a/rtl/ip/peripheral/clint_core.sv b/rtl/ip/peripheral/clint_core.sv index 50967780..d753beeb 100644 --- a/rtl/ip/peripheral/clint_core.sv +++ b/rtl/ip/peripheral/clint_core.sv @@ -4,25 +4,27 @@ module clint_core #( parameter int HartNum = 1 ) ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic tick_i, - input logic mtime_load_i, - input logic [63:0] mtime_load_value_i, - input logic [63:0] mtimecmp_i [0:HartNum-1], - output logic [63:0] mtime_o, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic tick_i, + input logic mtime_load_i, + input logic [63:0] mtime_load_value_i, + input logic [63:0] mtimecmp_i [0:HartNum-1], + output logic [63:0] mtime_o, output logic [HartNum-1:0] timer_irq_o // verilog_format: on ); logic [HartNum-1:0] s_timer_irq_d, s_timer_irq_q; +`ifndef SYNTHESIS initial begin if ((HartNum < 1) || (HartNum > 4095)) begin $fatal(1, "clint_core: HartNum must be between 1 and 4095"); end end +`endif // MTIME wraps modulo 2^64, so the Common carry output is intentionally unused. /* verilator lint_off PINCONNECTEMPTY */ diff --git a/rtl/ip/peripheral/clint_define.svh b/rtl/ip/peripheral/clint_define.svh index f70ed0d9..e8ac45ba 100644 --- a/rtl/ip/peripheral/clint_define.svh +++ b/rtl/ip/peripheral/clint_define.svh @@ -4,7 +4,7 @@ `ifndef CLINT_DEFINE_SVH `define CLINT_DEFINE_SVH -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_CLINT_MSIP 16'h0000 `define RIBP_CLINT_MTIMECMP 16'h4000 `define RIBP_CLINT_MTIME 16'hBFF8 diff --git a/rtl/ip/peripheral/clint_reg.sv b/rtl/ip/peripheral/clint_reg.sv index 8bc2894d..135bf65b 100644 --- a/rtl/ip/peripheral/clint_reg.sv +++ b/rtl/ip/peripheral/clint_reg.sv @@ -6,15 +6,15 @@ module clint_reg #( parameter int HartNum = 1 ) ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - ribp_if.slave ribp, - input logic [63:0] mtime_i, - output logic mtime_load_o, - output logic [63:0] mtime_load_value_o, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + ribp_if.slave ribp, + input logic [63:0] mtime_i, + output logic mtime_load_o, + output logic [63:0] mtime_load_value_o, output logic [HartNum-1:0] msip_o, - output logic [63:0] mtimecmp_o [0:HartNum-1] + output logic [63:0] mtimecmp_o [0:HartNum-1] // verilog_format: on ); @@ -60,11 +60,13 @@ module clint_reg #( end endfunction +`ifndef SYNTHESIS initial begin if ((HartNum < 1) || (HartNum > 4095)) begin $fatal(1, "clint_reg: HartNum must be between 1 and 4095"); end end +`endif assign s_req = ribp.valid && !s_ribp_ready_q; assign s_write = |ribp.wstrb; diff --git a/rtl/ip/peripheral/clint_timebase.sv b/rtl/ip/peripheral/clint_timebase.sv index 4883378e..75983417 100644 --- a/rtl/ip/peripheral/clint_timebase.sv +++ b/rtl/ip/peripheral/clint_timebase.sv @@ -6,7 +6,7 @@ module clint_timebase #( parameter int TimebaseHz = 1_000_000, parameter int CdcStage = 2 ) ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic ref_clk_i, input logic ref_rst_n_i, input logic sys_clk_i, @@ -24,12 +24,14 @@ module clint_timebase #( logic s_tick_toggle_sync; logic s_tick_re, s_tick_fe; +`ifndef SYNTHESIS initial begin if ((RefClkHz <= 0) || (TimebaseHz <= 0) || (RefClkHz < TimebaseHz) || ((RefClkHz % TimebaseHz) != 0)) begin $fatal(1, "clint_timebase: RefClkHz must be a positive multiple of TimebaseHz"); end end +`endif assign s_div_terminal = s_div_count == DIV_WIDTH'(DIVISOR - 1); diff --git a/rtl/ip/peripheral/dma_core.sv b/rtl/ip/peripheral/dma_core.sv index a24c3f5c..9da3afd6 100644 --- a/rtl/ip/peripheral/dma_core.sv +++ b/rtl/ip/peripheral/dma_core.sv @@ -12,28 +12,28 @@ `include "rib_defs.svh" module dma_core ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic [3:0] mode_i, - input logic [31:0] srcaddr_i, - input logic srcincr_i, - input logic [31:0] dstaddr_i, - input logic dstincr_i, - input logic [31:0] xferlen_i, - input logic start_i, - input logic stop_i, - input logic reset_i, - output logic done_o, - output logic error_o, - output logic [2:0] error_code_o, - output logic [31:0] error_addr_o, - output logic [1:0] fsm_o, - dma_hw_trg_if.dut hw_trg, - rib_if.master rib, - axi4_stream_if.source i2s_tx_axis, - axi4_stream_if.sink i2s_rx_axis, - axi4_stream_if.sink dvp_rx_axis + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic [3:0] mode_i, + input logic [31:0] srcaddr_i, + input logic srcincr_i, + input logic [31:0] dstaddr_i, + input logic dstincr_i, + input logic [31:0] xferlen_i, + input logic start_i, + input logic stop_i, + input logic reset_i, + output logic done_o, + output logic error_o, + output logic [2:0] error_code_o, + output logic [31:0] error_addr_o, + output logic [1:0] fsm_o, + dma_hw_trg_if.dut hw_trg, + rib_if.master rib, + axi4_stream_if.source i2s_tx_axis, + axi4_stream_if.sink i2s_rx_axis, + axi4_stream_if.sink dvp_rx_axis // verilog_format: on ); @@ -83,7 +83,7 @@ module dma_core ( logic s_stream_tx_hdshk; assign s_remaining_words = xferlen_i - s_xfer_cnt_q; - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment assign s_use_burst = (mode_i == SFT_TRG) && srcincr_i && dstincr_i && (s_remaining_words >= 32'd4) && diff --git a/rtl/ip/peripheral/gpio_core.sv b/rtl/ip/peripheral/gpio_core.sv index ccfc8bc5..46c73c5f 100644 --- a/rtl/ip/peripheral/gpio_core.sv +++ b/rtl/ip/peripheral/gpio_core.sv @@ -4,9 +4,9 @@ module gpio_core #( parameter int PinNum = 32 ) ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, input logic [PinNum-1:0] data_out_i, input logic [PinNum-1:0] output_enable_i, input logic [PinNum-1:0] open_drain_i, @@ -18,17 +18,17 @@ module gpio_core #( input logic [PinNum-1:0] user_select_i, input logic [PinNum-1:0] user_handoff_i, input logic [PinNum-1:0] filter_enable_i, - input logic [15:0] filter_div_i, - input logic [3:0] filter_count_i, + input logic [15:0] filter_div_i, + input logic [3:0] filter_count_i, input logic [PinNum-1:0] intr_rise_enable_i, input logic [PinNum-1:0] intr_fall_enable_i, input logic [PinNum-1:0] intr_high_enable_i, input logic [PinNum-1:0] intr_low_enable_i, - input logic irq_i, + input logic irq_i, output logic [PinNum-1:0] data_in_o, output logic [PinNum-1:0] intr_event_o, - gpio_if.dut gpio, - user_gpio_if.padctrl user_gpio + gpio_if.dut gpio, + user_gpio_if.padctrl user_gpio // verilog_format: on ); @@ -44,11 +44,13 @@ module gpio_core #( logic [PinNum-1:0] s_native_data, s_native_oe; logic [PinNum-1:0] s_selected_data, s_selected_oe; +`ifndef SYNTHESIS initial begin if ((PinNum < 1) || (PinNum > 32)) begin $fatal(1, "gpio_core: PinNum must be between 1 and 32"); end end +`endif cdc_sync #( .STAGE (2), diff --git a/rtl/ip/peripheral/gpio_define.svh b/rtl/ip/peripheral/gpio_define.svh index f2b374b9..f0da2537 100644 --- a/rtl/ip/peripheral/gpio_define.svh +++ b/rtl/ip/peripheral/gpio_define.svh @@ -4,7 +4,7 @@ `ifndef RIBP_GPIO_DEFINE_SVH `define RIBP_GPIO_DEFINE_SVH -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_GPIO_NUM 32 `define RIBP_GPIO_USER_DATA_IN 12'h000 diff --git a/rtl/ip/peripheral/gpio_reg.sv b/rtl/ip/peripheral/gpio_reg.sv index 4e49f811..9fe9abec 100644 --- a/rtl/ip/peripheral/gpio_reg.sv +++ b/rtl/ip/peripheral/gpio_reg.sv @@ -11,10 +11,10 @@ module gpio_reg #( parameter bit HasPullUp = 1'b0, parameter bit HasPullDown = 1'b0 ) ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - ribp_if.slave ribp, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + ribp_if.slave ribp, input logic [PinNum-1:0] data_in_i, input logic [PinNum-1:0] intr_event_i, output logic [PinNum-1:0] data_out_o, @@ -28,13 +28,13 @@ module gpio_reg #( output logic [PinNum-1:0] user_select_o, output logic [PinNum-1:0] user_handoff_o, output logic [PinNum-1:0] filter_enable_o, - output logic [15:0] filter_div_o, - output logic [3:0] filter_count_o, + output logic [15:0] filter_div_o, + output logic [3:0] filter_count_o, output logic [PinNum-1:0] intr_rise_enable_o, output logic [PinNum-1:0] intr_fall_enable_o, output logic [PinNum-1:0] intr_high_enable_o, output logic [PinNum-1:0] intr_low_enable_o, - output logic irq_o + output logic irq_o // verilog_format: on ); @@ -126,6 +126,7 @@ module gpio_reg #( end endfunction +`ifndef SYNTHESIS initial begin if ((PinNum < 1) || (PinNum > 32)) begin $fatal(1, "gpio_reg: PinNum must be between 1 and 32"); @@ -135,6 +136,7 @@ module gpio_reg #( $fatal(1, "gpio_reg: register window bases must be distinct and 4 KiB aligned"); end end +`endif assign s_req = ribp.valid && !s_ribp_ready_q; assign s_write = |ribp.wstrb; diff --git a/rtl/ip/peripheral/ribp_clint.sv b/rtl/ip/peripheral/ribp_clint.sv index abebe7b7..cc6ddf86 100644 --- a/rtl/ip/peripheral/ribp_clint.sv +++ b/rtl/ip/peripheral/ribp_clint.sv @@ -4,12 +4,12 @@ module ribp_clint #( parameter int HartNum = 1 ) ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic timebase_tick_i, - ribp_if.slave ribp, - clint_if.dut clint + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic timebase_tick_i, + ribp_if.slave ribp, + clint_if.dut clint // verilog_format: on ); diff --git a/rtl/ip/peripheral/dma.sv b/rtl/ip/peripheral/ribp_dma.sv similarity index 95% rename from rtl/ip/peripheral/dma.sv rename to rtl/ip/peripheral/ribp_dma.sv index 435d68e8..02ad4cd6 100644 --- a/rtl/ip/peripheral/dma.sv +++ b/rtl/ip/peripheral/ribp_dma.sv @@ -11,7 +11,7 @@ `ifndef RIBP_DMA_DEF_SV `define RIBP_DMA_DEF_SV -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_DMA_MODE 8'h00 `define RIBP_DMA_SRCADDR 8'h04 `define RIBP_DMA_SRCINCR 8'h08 @@ -56,16 +56,16 @@ endinterface `endif module ribp_dma ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - output logic dma_xfer_done_o, - dma_hw_trg_if.dut hw_trg, - ribp_if.slave ribp, - rib_if.master rib, - axi4_stream_if.source i2s_tx_axis, - axi4_stream_if.sink i2s_rx_axis, - axi4_stream_if.sink dvp_rx_axis + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + output logic dma_xfer_done_o, + dma_hw_trg_if.dut hw_trg, + ribp_if.slave ribp, + rib_if.master rib, + axi4_stream_if.source i2s_tx_axis, + axi4_stream_if.sink i2s_rx_axis, + axi4_stream_if.sink dvp_rx_axis // verilog_format: on ); diff --git a/rtl/ip/peripheral/ribp_gpio.sv b/rtl/ip/peripheral/ribp_gpio.sv index b2c85dd7..45d2681d 100644 --- a/rtl/ip/peripheral/ribp_gpio.sv +++ b/rtl/ip/peripheral/ribp_gpio.sv @@ -9,12 +9,12 @@ module ribp_gpio #( parameter bit HasPullUp = 1'b0, parameter bit HasPullDown = 1'b0 ) ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - ribp_if.slave ribp, - gpio_if.dut gpio, - user_gpio_if.padctrl user_gpio + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + ribp_if.slave ribp, + gpio_if.dut gpio, + user_gpio_if.padctrl user_gpio // verilog_format: on ); diff --git a/rtl/ip/peripheral/sysctrl.sv b/rtl/ip/peripheral/ribp_sysctrl.sv similarity index 96% rename from rtl/ip/peripheral/sysctrl.sv rename to rtl/ip/peripheral/ribp_sysctrl.sv index 2d86628b..f375019e 100644 --- a/rtl/ip/peripheral/sysctrl.sv +++ b/rtl/ip/peripheral/ribp_sysctrl.sv @@ -63,15 +63,15 @@ interface sysctrl_if (); endinterface module ribp_sysctrl ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic fault_valid_i, - input logic [31:0] fault_addr_i, - input logic [3:0] fault_wstrb_i, - input logic fault_reserved_i, - ribp_if.slave ribp, - sysctrl_if.dut sysctrl, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic fault_valid_i, + input logic [31:0] fault_addr_i, + input logic [3:0] fault_wstrb_i, + input logic fault_reserved_i, + ribp_if.slave ribp, + sysctrl_if.dut sysctrl, pll_ctrl_if.sysctrl pll_ctrl // verilog_format: on ); @@ -707,11 +707,14 @@ module ribp_sysctrl ( always_comb begin s_ribp_rdata_d = s_ribp_rdata_q; unique case (ribp.addr[7:0]) - // verilog_format: off - SYSCTRL_CORESEL_OFFSET: s_ribp_rdata_d = {{(32 - `USER_CORESEL_WIDTH) {1'b0}}, s_sysctrl_coresel_q}; - SYSCTRL_IPSEL_OFFSET: s_ribp_rdata_d = {{(32 - `USER_IPSEL_WIDTH) {1'b0}}, s_sysctrl_ipsel_q}; + // verilog_format: off -- preserve reviewed column alignment + SYSCTRL_CORESEL_OFFSET: + s_ribp_rdata_d = {{(32 - `USER_CORESEL_WIDTH) {1'b0}}, s_sysctrl_coresel_q}; + SYSCTRL_IPSEL_OFFSET: + s_ribp_rdata_d = {{(32 - `USER_IPSEL_WIDTH) {1'b0}}, s_sysctrl_ipsel_q}; SYSCTRL_PLL_CFG_OFFSET: s_ribp_rdata_d = {29'd0, s_pll_cfg_q}; - SYSCTRL_FAULT_STATUS_OFFSET: s_ribp_rdata_d = {27'd0, s_fault_reason_q, s_fault_write_q, s_fault_pending_q}; + SYSCTRL_FAULT_STATUS_OFFSET: + s_ribp_rdata_d = {27'd0, s_fault_reason_q, s_fault_write_q, s_fault_pending_q}; SYSCTRL_FAULT_ADDR_OFFSET: s_ribp_rdata_d = s_fault_addr_q; SYSCTRL_FAULT_COUNT_OFFSET: s_ribp_rdata_d = s_fault_count_q; SYSCTRL_PLL_STATUS_OFFSET: s_ribp_rdata_d = { @@ -725,7 +728,8 @@ module ribp_sysctrl ( s_pll_active_valid_q, s_pll_active_sel_q }; - SYSCTRL_USER_CORE_RESET_OFFSET: s_ribp_rdata_d = {{(32 - `USER_CORE_COUNT) {1'b0}}, s_user_reset_q}; + SYSCTRL_USER_CORE_RESET_OFFSET: + s_ribp_rdata_d = {{(32 - `USER_CORE_COUNT) {1'b0}}, s_user_reset_q}; SYSCTRL_USER_CORE_STATUS_OFFSET: s_ribp_rdata_d = { 20'd0, s_user_config_err_q, diff --git a/rtl/ip/peripheral/ribp_timer.sv b/rtl/ip/peripheral/ribp_timer.sv index f29c8f25..2d92ca56 100644 --- a/rtl/ip/peripheral/ribp_timer.sv +++ b/rtl/ip/peripheral/ribp_timer.sv @@ -2,7 +2,7 @@ // retroSoC is licensed under Mulan PSL v2. module ribp_timer ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic debug_halted_i, diff --git a/rtl/ip/peripheral/timer_core.sv b/rtl/ip/peripheral/timer_core.sv index dc2c4477..9d752756 100644 --- a/rtl/ip/peripheral/timer_core.sv +++ b/rtl/ip/peripheral/timer_core.sv @@ -5,29 +5,29 @@ module timer_core #( parameter int CounterWidth = 32, parameter int PrescaleWidth = 16 ) ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic enable_i, - input logic [1:0] mode_i, - input logic direction_i, - input logic debug_freeze_enable_i, - input logic debug_halted_i, - input logic compare0_enable_i, - input logic compare1_enable_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic enable_i, + input logic [1:0] mode_i, + input logic direction_i, + input logic debug_freeze_enable_i, + input logic debug_halted_i, + input logic compare0_enable_i, + input logic compare1_enable_i, input logic [PrescaleWidth-1:0] prescale_i, input logic [CounterWidth-1:0] load_i, input logic [CounterWidth-1:0] compare0_i, input logic [CounterWidth-1:0] compare1_i, - input logic start_i, - input logic stop_i, - input logic load_now_i, + input logic start_i, + input logic stop_i, + input logic load_now_i, output logic [CounterWidth-1:0] value_o, - output logic debug_frozen_o, - output logic timeout_event_o, - output logic compare0_event_o, - output logic compare1_event_o, - output logic one_shot_done_o + output logic debug_frozen_o, + output logic timeout_event_o, + output logic compare0_event_o, + output logic compare1_event_o, + output logic one_shot_done_o // verilog_format: on ); @@ -43,11 +43,13 @@ module timer_core #( logic s_prescale_overflow; logic [CounterWidth-1:0] s_value_d, s_value_q; +`ifndef SYNTHESIS initial begin if (CounterWidth < 1 || PrescaleWidth < 1) begin $fatal(1, "timer_core: parameter widths must be positive"); end end +`endif assign debug_frozen_o = enable_i && debug_freeze_enable_i && debug_halted_i; assign value_o = s_value_q; diff --git a/rtl/ip/peripheral/timer_define.svh b/rtl/ip/peripheral/timer_define.svh index eefab13b..4a863cc8 100644 --- a/rtl/ip/peripheral/timer_define.svh +++ b/rtl/ip/peripheral/timer_define.svh @@ -4,7 +4,7 @@ `ifndef RIBP_TIMER_DEFINE_SVH `define RIBP_TIMER_DEFINE_SVH -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_TIMER_CTRL 12'h000 `define RIBP_TIMER_LOAD 12'h004 `define RIBP_TIMER_VALUE 12'h008 diff --git a/rtl/ip/peripheral/timer_reg.sv b/rtl/ip/peripheral/timer_reg.sv index 00c47492..0868bb96 100644 --- a/rtl/ip/peripheral/timer_reg.sv +++ b/rtl/ip/peripheral/timer_reg.sv @@ -4,7 +4,7 @@ `include "timer_define.svh" module timer_reg ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, ribp_if.slave ribp, diff --git a/rtl/ip/serial/i2c_core.sv b/rtl/ip/serial/i2c_core.sv index 7bda2342..72895a2a 100644 --- a/rtl/ip/serial/i2c_core.sv +++ b/rtl/ip/serial/i2c_core.sv @@ -2,7 +2,7 @@ // retroSoC is licensed under Mulan PSL v2. module i2c_core ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic enable_i, diff --git a/rtl/ip/serial/i2c_filter.sv b/rtl/ip/serial/i2c_filter.sv index 02913837..01482cad 100644 --- a/rtl/ip/serial/i2c_filter.sv +++ b/rtl/ip/serial/i2c_filter.sv @@ -2,7 +2,7 @@ // retroSoC is licensed under Mulan PSL v2. module i2c_filter ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic [3:0] scl_filter_cycles_i, diff --git a/rtl/ip/serial/i2c_reg.sv b/rtl/ip/serial/i2c_reg.sv index 9d9d88fc..a1eca5f7 100644 --- a/rtl/ip/serial/i2c_reg.sv +++ b/rtl/ip/serial/i2c_reg.sv @@ -9,7 +9,7 @@ module i2c_reg #( parameter int CmdFifoLogDepth = $clog2(CmdFifoDepth), parameter int RxFifoLogDepth = $clog2(RxFifoDepth) ) ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, ribp_if.slave ribp, @@ -149,11 +149,13 @@ module i2c_reg #( end endfunction +`ifndef SYNTHESIS initial begin if ((CmdFifoDepth > 255) || (RxFifoDepth > 255)) begin $fatal(1, "i2c_reg: FIFO depths must fit CAPABILITY fields"); end end +`endif assign s_req = ribp.valid && !s_ribp_ready_q; assign s_write = |ribp.wstrb; diff --git a/rtl/ip/serial/i2s_core.sv b/rtl/ip/serial/i2s_core.sv index 64ca21c4..a54d6b81 100644 --- a/rtl/ip/serial/i2s_core.sv +++ b/rtl/ip/serial/i2s_core.sv @@ -9,7 +9,7 @@ // See the Mulan PSL v2 for more details. module i2s_core ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic mode_i, diff --git a/rtl/ip/serial/i2s_define.svh b/rtl/ip/serial/i2s_define.svh index 124f030b..9a4f4603 100644 --- a/rtl/ip/serial/i2s_define.svh +++ b/rtl/ip/serial/i2s_define.svh @@ -11,7 +11,7 @@ `ifndef RIBP_I2S_DEF_SV `define RIBP_I2S_DEF_SV -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_I2S_MODE 8'h00 `define RIBP_I2S_FORMAT 8'h04 `define RIBP_I2S_UPBOUND 8'h08 diff --git a/rtl/ip/serial/i2s_reg.sv b/rtl/ip/serial/i2s_reg.sv index 7fcc2625..b1829f92 100644 --- a/rtl/ip/serial/i2s_reg.sv +++ b/rtl/ip/serial/i2s_reg.sv @@ -11,10 +11,10 @@ `include "i2s_define.svh" module i2s_reg ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, - ribp_if.slave ribp, + ribp_if.slave ribp, output logic mode_o, output logic [ 1:0] format_o, output logic recven_o, diff --git a/rtl/ip/serial/ribp_i2c.sv b/rtl/ip/serial/ribp_i2c.sv index 13e4e0d5..7dd8a1a7 100644 --- a/rtl/ip/serial/ribp_i2c.sv +++ b/rtl/ip/serial/ribp_i2c.sv @@ -5,7 +5,7 @@ module ribp_i2c #( parameter int CmdFifoDepth = 16, parameter int RxFifoDepth = 16 ) ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, output logic dma_tx_stall_o, diff --git a/rtl/ip/serial/ribp_i2c_define.svh b/rtl/ip/serial/ribp_i2c_define.svh index dcbb2a61..67bdfc24 100644 --- a/rtl/ip/serial/ribp_i2c_define.svh +++ b/rtl/ip/serial/ribp_i2c_define.svh @@ -4,7 +4,7 @@ `ifndef RETROSOC_RIBP_I2C_DEFINE_SVH `define RETROSOC_RIBP_I2C_DEFINE_SVH -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_I2C_CTRL 8'h00 `define RIBP_I2C_SCL_TIMING 8'h04 `define RIBP_I2C_START_TIMING 8'h08 diff --git a/rtl/ip/serial/i2s.sv b/rtl/ip/serial/ribp_i2s.sv similarity index 90% rename from rtl/ip/serial/i2s.sv rename to rtl/ip/serial/ribp_i2s.sv index 5a7238be..c1765bdb 100644 --- a/rtl/ip/serial/i2s.sv +++ b/rtl/ip/serial/ribp_i2s.sv @@ -30,17 +30,17 @@ endinterface module ribp_i2s ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic clk_aud_i, - input logic rst_aud_n_i, - output logic dma_tx_stall_o, - output logic dma_rx_stall_o, - ribp_if.slave ribp, - axi4_stream_if.sink tx_axis, - axi4_stream_if.source rx_axis, - i2s_if.dut i2s + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic clk_aud_i, + input logic rst_aud_n_i, + output logic dma_tx_stall_o, + output logic dma_rx_stall_o, + ribp_if.slave ribp, + axi4_stream_if.sink tx_axis, + axi4_stream_if.source rx_axis, + i2s_if.dut i2s // verilog_format: on ); diff --git a/rtl/ip/serial/ribp_uart.sv b/rtl/ip/serial/ribp_uart.sv index 09805b52..0e0163aa 100644 --- a/rtl/ip/serial/ribp_uart.sv +++ b/rtl/ip/serial/ribp_uart.sv @@ -5,7 +5,7 @@ module ribp_uart #( parameter int TxFifoDepth = 64, parameter int RxFifoDepth = 64 ) ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, output logic dma_tx_stall_o, diff --git a/rtl/ip/serial/ribp_uart_define.svh b/rtl/ip/serial/ribp_uart_define.svh index a1bd672b..c88a5393 100644 --- a/rtl/ip/serial/ribp_uart_define.svh +++ b/rtl/ip/serial/ribp_uart_define.svh @@ -4,7 +4,7 @@ `ifndef RIBP_UART_DEFINE_SVH `define RIBP_UART_DEFINE_SVH -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_UART_BAUD_INT 8'h00 `define RIBP_UART_BAUD_FRAC 8'h04 `define RIBP_UART_LINE_CTRL 8'h08 diff --git a/rtl/ip/serial/ribp_uart_rx.sv b/rtl/ip/serial/ribp_uart_rx.sv index 3e292131..0025f96d 100644 --- a/rtl/ip/serial/ribp_uart_rx.sv +++ b/rtl/ip/serial/ribp_uart_rx.sv @@ -2,7 +2,7 @@ // retroSoC is licensed under Mulan PSL v2. module ribp_uart_rx ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic sample_tick_i, diff --git a/rtl/ip/serial/ribp_uart_tx.sv b/rtl/ip/serial/ribp_uart_tx.sv index 09c9de28..7933f2e9 100644 --- a/rtl/ip/serial/ribp_uart_tx.sv +++ b/rtl/ip/serial/ribp_uart_tx.sv @@ -2,7 +2,7 @@ // retroSoC is licensed under Mulan PSL v2. module ribp_uart_tx ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic sample_tick_i, diff --git a/rtl/ip/serial/ribp_ws2812.sv b/rtl/ip/serial/ribp_ws2812.sv index 217ed884..38060cc2 100644 --- a/rtl/ip/serial/ribp_ws2812.sv +++ b/rtl/ip/serial/ribp_ws2812.sv @@ -11,10 +11,10 @@ module ribp_ws2812 #( parameter int TxFifoDepth = 16 ) ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - ribp_if.slave ribp, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + ribp_if.slave ribp, ws2812_if.dut ws2812 // verilog_format: on ); diff --git a/rtl/ip/serial/uart_baudgen.sv b/rtl/ip/serial/uart_baudgen.sv index 0ca5e7a1..a25b7316 100644 --- a/rtl/ip/serial/uart_baudgen.sv +++ b/rtl/ip/serial/uart_baudgen.sv @@ -2,7 +2,7 @@ // retroSoC is licensed under Mulan PSL v2. module uart_baudgen ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic enable_i, diff --git a/rtl/ip/serial/uart_core.sv b/rtl/ip/serial/uart_core.sv index f926f7de..74111d2f 100644 --- a/rtl/ip/serial/uart_core.sv +++ b/rtl/ip/serial/uart_core.sv @@ -2,7 +2,7 @@ // retroSoC is licensed under Mulan PSL v2. module uart_core ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic [23:0] baud_int_i, diff --git a/rtl/ip/serial/uart_flow_ctrl.sv b/rtl/ip/serial/uart_flow_ctrl.sv index 1d6eeefc..103ddbca 100644 --- a/rtl/ip/serial/uart_flow_ctrl.sv +++ b/rtl/ip/serial/uart_flow_ctrl.sv @@ -2,7 +2,7 @@ // retroSoC is licensed under Mulan PSL v2. module uart_flow_ctrl ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic cts_n_async_i, diff --git a/rtl/ip/serial/uart_reg.sv b/rtl/ip/serial/uart_reg.sv index bc3bfcab..c03c29cc 100644 --- a/rtl/ip/serial/uart_reg.sv +++ b/rtl/ip/serial/uart_reg.sv @@ -9,7 +9,7 @@ module uart_reg #( parameter int TxFifoLogDepth = $clog2(TxFifoDepth), parameter int RxFifoLogDepth = $clog2(RxFifoDepth) ) ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, ribp_if.slave ribp, @@ -137,11 +137,13 @@ module uart_reg #( end endfunction +`ifndef SYNTHESIS initial begin if ((TxFifoDepth != 64) || (RxFifoDepth != 64)) begin $fatal(1, "uart_reg: 64-entry FIFOs are required"); end end +`endif assign s_req = ribp.valid && !s_ribp_ready_q; assign s_write = |ribp.wstrb; diff --git a/rtl/ip/serial/ws2812_core.sv b/rtl/ip/serial/ws2812_core.sv index f21e919b..f8829307 100644 --- a/rtl/ip/serial/ws2812_core.sv +++ b/rtl/ip/serial/ws2812_core.sv @@ -9,7 +9,7 @@ // See the Mulan PSL v2 for more details. module ws2812_core ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic [15:0] bit_cycles_i, diff --git a/rtl/ip/serial/ws2812_define.svh b/rtl/ip/serial/ws2812_define.svh index 569ad332..c669d9ea 100644 --- a/rtl/ip/serial/ws2812_define.svh +++ b/rtl/ip/serial/ws2812_define.svh @@ -5,7 +5,7 @@ `ifndef WS2812_DEFINE_SVH `define WS2812_DEFINE_SVH -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_WS2812_BIT_CYCLES 8'h00 `define RIBP_WS2812_T0H_CYCLES 8'h04 `define RIBP_WS2812_T1H_CYCLES 8'h08 diff --git a/rtl/ip/serial/ws2812_reg.sv b/rtl/ip/serial/ws2812_reg.sv index bc8b1d03..2336bb2d 100644 --- a/rtl/ip/serial/ws2812_reg.sv +++ b/rtl/ip/serial/ws2812_reg.sv @@ -14,7 +14,7 @@ module ws2812_reg #( parameter int TxFifoDepth = 16, parameter int TxFifoLogDepth = $clog2(TxFifoDepth) ) ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, ribp_if.slave ribp, diff --git a/rtl/ip/storage/sdio.sv b/rtl/ip/storage/ribp_sdio.sv similarity index 77% rename from rtl/ip/storage/sdio.sv rename to rtl/ip/storage/ribp_sdio.sv index 28074ea5..c6b5fb34 100644 --- a/rtl/ip/storage/sdio.sv +++ b/rtl/ip/storage/ribp_sdio.sv @@ -32,19 +32,21 @@ endinterface module ribp_sdio ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, ribp_if.slave ribp, - sdio_if.dut sdio + sdio_if.dut sdio // verilog_format: on ); - logic dummy0; - logic dummy1; + // This placeholder accepts no RIBP requests (ready remains low) and reports + // no errors; all SDIO outputs are deliberately held inactive. + logic s_dummy_clk; + logic s_dummy_rst_n; - assign dummy0 = clk_i; - assign dummy1 = rst_n_i; + assign s_dummy_clk = clk_i; + assign s_dummy_rst_n = rst_n_i; // ribp assign ribp.rdata = '0; assign ribp.ready = '0; diff --git a/rtl/ip/storage/spisd.sv b/rtl/ip/storage/ribp_spisd.sv similarity index 91% rename from rtl/ip/storage/spisd.sv rename to rtl/ip/storage/ribp_spisd.sv index 1a582dde..1b472019 100644 --- a/rtl/ip/storage/spisd.sv +++ b/rtl/ip/storage/ribp_spisd.sv @@ -15,14 +15,17 @@ `include "mmap_define.svh" module ribp_spisd ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, ribp_if.slave ribp, - spi_if.dut spi + spi_if.dut spi // verilog_format: on ); + // clk_i/rst_n_i control configuration and media traffic. Requests route to + // either configuration or cache mode; each selected child supplies ready, + // data, and resp_err, with one cache operation outstanding at a time. logic s_cfg_reg_sel; logic s_init_done; logic s_wr_sync; @@ -45,7 +48,7 @@ module ribp_spisd ( ribp_if u_cache_mem_ribp_if (); ribp_if u_cache_byp_ribp_if (); - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment assign s_cfg_reg_sel = `SOC_ADDR_IS_RIBP_SPISD(ribp.addr); assign u_cfg_ribp_if.valid = ribp.valid && s_cfg_reg_sel; assign u_cfg_ribp_if.addr = ribp.addr; diff --git a/rtl/ip/storage/xpi.sv b/rtl/ip/storage/ribp_xpi.sv similarity index 81% rename from rtl/ip/storage/xpi.sv rename to rtl/ip/storage/ribp_xpi.sv index a93e4c17..710bf533 100644 --- a/rtl/ip/storage/xpi.sv +++ b/rtl/ip/storage/ribp_xpi.sv @@ -30,17 +30,20 @@ interface xpi_if (); endinterface module ribp_xpi ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic dma_xfer_done_i, - output logic dma_tx_stall_o, - output logic dma_rx_stall_o, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic dma_xfer_done_i, + output logic dma_tx_stall_o, + output logic dma_rx_stall_o, ribp_if.slave ribp, - xpi_if.dut xpi + xpi_if.dut xpi // verilog_format: on ); + // clk_i/rst_n_i drive register and memory-mapped transfers. The selected + // path supplies response data/errors; FIFO limits apply backpressure through + // its ready signals while an XPI transfer is in progress. // nss logic [`XPI_LNS_NUM-1:0] s_xpi_nss; // reg mode @@ -118,7 +121,7 @@ module ribp_xpi ( assign u_mm_ribp_if.wdata = ribp.wdata; assign u_mm_ribp_if.wstrb = ribp.wstrb; - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment assign ribp.ready = (u_reg_ribp_if.valid & u_reg_ribp_if.ready) | (u_mm_ribp_if.valid & u_mm_ribp_if.ready); assign ribp.resp_err = (u_reg_ribp_if.valid & u_reg_ribp_if.ready & u_reg_ribp_if.resp_err) | @@ -137,53 +140,53 @@ module ribp_xpi ( xpi_reg u_xpi_reg ( - .clk_i (clk_i), - .rst_n_i (rst_n_i), + .clk_i(clk_i), + .rst_n_i(rst_n_i), // reg - .xpi_accmd_o (), - .xpi_mmstad_o (s_xpi_mmstad), - .xpi_mmoffst_o (s_xpi_mmoffst), - .xpi_mode_o (s_xpi_mode), - .xpi_regnss_o (s_xpi_regnss), - .xpi_clkdiv_o (s_xpi_clkdiv), - .xpi_rdwr_o (s_xpi_rdwr), - .xpi_revdat_o (s_xpi_revdat), - .xpi_tx_flush_o (s_tx_flush), - .xpi_rx_flush_o (s_rx_flush), - .xpi_cmdtyp_o (s_xpi_cmdtyp), - .xpi_cmdlen_o (s_xpi_cmdlen), - .xpi_cmddat_o (s_xpi_cmddat), - .xpi_adrtyp_o (s_xpi_adrtyp), - .xpi_adrlen_o (s_xpi_adrlen), - .xpi_adrdat_o (s_xpi_adrdat), - .xpi_alttyp_o (s_xpi_alttyp), - .xpi_altlen_o (s_xpi_altlen), - .xpi_altdat_o (s_xpi_altdat), - .xpi_tdulen_o (s_xpi_tdulen), - .xpi_rdulen_o (s_xpi_rdulen), - .xpi_dattyp_o (s_xpi_dattyp), - .xpi_datlen_o (s_xpi_datlen), - .xpi_datbit_o (s_xpi_datbit), - .xpi_hlvlen_o (s_xpi_hlvlen), + .xpi_accmd_o(), // The software-visible accumulated command is not used here. + .xpi_mmstad_o(s_xpi_mmstad), + .xpi_mmoffst_o(s_xpi_mmoffst), + .xpi_mode_o(s_xpi_mode), + .xpi_regnss_o(s_xpi_regnss), + .xpi_clkdiv_o(s_xpi_clkdiv), + .xpi_rdwr_o(s_xpi_rdwr), + .xpi_revdat_o(s_xpi_revdat), + .xpi_tx_flush_o(s_tx_flush), + .xpi_rx_flush_o(s_rx_flush), + .xpi_cmdtyp_o(s_xpi_cmdtyp), + .xpi_cmdlen_o(s_xpi_cmdlen), + .xpi_cmddat_o(s_xpi_cmddat), + .xpi_adrtyp_o(s_xpi_adrtyp), + .xpi_adrlen_o(s_xpi_adrlen), + .xpi_adrdat_o(s_xpi_adrdat), + .xpi_alttyp_o(s_xpi_alttyp), + .xpi_altlen_o(s_xpi_altlen), + .xpi_altdat_o(s_xpi_altdat), + .xpi_tdulen_o(s_xpi_tdulen), + .xpi_rdulen_o(s_xpi_rdulen), + .xpi_dattyp_o(s_xpi_dattyp), + .xpi_datlen_o(s_xpi_datlen), + .xpi_datbit_o(s_xpi_datbit), + .xpi_hlvlen_o(s_xpi_hlvlen), // tx fifo .tx_push_valid_o(s_reg_tx_push_valid), - .tx_push_data_o (s_reg_tx_push_data), - .tx_full_i (s_tx_full), - .tx_empty_i (s_tx_empty), - .tx_elem_num_i (s_tx_elem_num), + .tx_push_data_o(s_reg_tx_push_data), + .tx_full_i(s_tx_full), + .tx_empty_i(s_tx_empty), + .tx_elem_num_i(s_tx_elem_num), // rx fifo - .rx_pop_valid_o (s_reg_rx_pop_valid), - .rx_pop_data_i (s_rx_pop_data), - .rx_full_i (s_rx_full), - .rx_empty_i (s_rx_empty), - .rx_elem_num_i (s_rx_elem_num), + .rx_pop_valid_o(s_reg_rx_pop_valid), + .rx_pop_data_i(s_rx_pop_data), + .rx_full_i(s_rx_full), + .rx_empty_i(s_rx_empty), + .rx_elem_num_i(s_rx_elem_num), // ctrl - .xfer_start_o (s_reg_xfer_start), - .xfer_done_i (s_xfer_done), + .xfer_start_o(s_reg_xfer_start), + .xfer_done_i(s_xfer_done), // dma - .dma_tx_stall_o (dma_tx_stall_o), - .dma_rx_stall_o (dma_rx_stall_o), - .ribp (u_reg_ribp_if) + .dma_tx_stall_o(dma_tx_stall_o), + .dma_rx_stall_o(dma_rx_stall_o), + .ribp(u_reg_ribp_if) ); diff --git a/rtl/ip/storage/spisd_cache.sv b/rtl/ip/storage/spisd_cache.sv index 9e86b3f0..eee06a7e 100644 --- a/rtl/ip/storage/spisd_cache.sv +++ b/rtl/ip/storage/spisd_cache.sv @@ -9,7 +9,7 @@ // See the Mulan PSL v2 for more details. module spisd_cache ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic mode_i, @@ -26,25 +26,29 @@ module spisd_cache ( input logic sd_wr_data_req_i, output logic [7:0] sd_wr_data_o, input logic sd_wr_busy_i, - ribp_if.slave ribp + ribp_if.slave ribp // verilog_format: on ); - // verilog_format: off - localparam FSM_IDLE = 2'd0; - localparam FSM_COMP_TAG = 2'd1; - localparam FSM_ALLOC = 2'd2; - localparam FSM_WR_BACK = 2'd3; - // verilog_format: on + // This single-clock cache accepts one RIBP request through its state machine; + // cache misses backpressure until media fill/writeback completes. It reports + // no response errors. + typedef enum logic [1:0] { + Idle = 2'd0, + CompareTag = 2'd1, + Allocate = 2'd2, + WriteBack = 2'd3 + } cache_state_e; logic s_cache_mem_hit, s_cache_byp_hit; logic [6:0] s_cache_index; logic s_cache_valid_d, s_cache_valid_q; logic s_cache_dirty_d, s_cache_dirty_q; logic [31:0] s_cache_tag_d, s_cache_tag_q; - logic [1:0] s_cache_fsm_d, s_cache_fsm_q; - logic [31:0] s_cache_data_d[0:127]; - logic [31:0] s_cache_data_q[0:127]; + cache_state_e s_cache_fsm_d, s_cache_fsm_q; + logic [ 1:0] s_cache_fsm_bits_q; + logic [31:0] s_cache_data_d [0:127]; + logic [31:0] s_cache_data_q [0:127]; // sd if logic [7:0] s_sd_wr_data_d, s_sd_wr_data_q; // common @@ -61,6 +65,7 @@ module spisd_cache ( assign s_cache_index = ribp.addr[8:2]; assign s_cache_mem_hit = ~mode_i && (ribp.addr[27:9] == s_cache_tag_q[18:0]); assign s_cache_byp_hit = mode_i && (ribp.addr == s_cache_tag_q); + assign s_cache_fsm_q = cache_state_e'(s_cache_fsm_bits_q); always_comb begin // cache @@ -84,17 +89,17 @@ module spisd_cache ( // wr sync wr_sync_done_o = '0; unique case (s_cache_fsm_q) - FSM_IDLE: begin + Idle: begin if (init_done_i) begin - if (ribp.valid) s_cache_fsm_d = FSM_COMP_TAG; + if (ribp.valid) s_cache_fsm_d = CompareTag; // sw wr sync else if (wr_sync_i && s_cache_dirty_q) begin - s_cache_fsm_d = FSM_WR_BACK; + s_cache_fsm_d = WriteBack; s_cache_dirty_d = 1'b0; end end end - FSM_COMP_TAG: begin + CompareTag: begin // cache hit if ((s_cache_mem_hit || s_cache_byp_hit) && s_cache_valid_q) begin if (s_wr_sync_q) wr_sync_done_o = 1'b1; // wr sync oper @@ -109,23 +114,23 @@ module spisd_cache ( if (ribp.wstrb[3]) s_cache_data_d[s_cache_index][31:24] = ribp.wdata[31:24]; end end - s_cache_fsm_d = FSM_IDLE; + s_cache_fsm_d = Idle; end else begin // need to update tag line info s_cache_valid_d = 1'b1; s_cache_dirty_d = |ribp.wstrb; // tag line is clean if (s_cache_valid_q == 1'b0 || s_cache_dirty_q == 1'b0) begin - s_cache_fsm_d = FSM_ALLOC; + s_cache_fsm_d = Allocate; if (~mode_i) s_cache_tag_d = {13'd0, ribp.addr[27:9]}; else s_cache_tag_d = ribp.addr; end else begin // need to flush data into sd card sectors - s_cache_fsm_d = FSM_WR_BACK; + s_cache_fsm_d = WriteBack; end end end - FSM_ALLOC: begin + Allocate: begin if (~sd_rd_busy_i) begin sd_rd_req_o = 1'b1; sd_addr_o = s_cache_tag_q; @@ -136,14 +141,14 @@ module spisd_cache ( s_word_cnt_d = '0; s_line_cnt_d = s_line_cnt_q + 1'b1; s_cache_data_d[s_line_cnt_q] = {sd_rd_data_i, s_word_data_q[31:8]}; - if (s_line_cnt_q == 7'd127) s_cache_fsm_d = FSM_COMP_TAG; + if (s_line_cnt_q == 7'd127) s_cache_fsm_d = CompareTag; end else begin s_word_cnt_d = s_word_cnt_q + 1'b1; s_word_data_d = {sd_rd_data_i, s_word_data_q[31:8]}; end end end - FSM_WR_BACK: begin + WriteBack: begin if (~sd_wr_busy_i) begin sd_wr_req_o = 1'b1; sd_addr_o = s_cache_tag_q; @@ -159,7 +164,7 @@ module spisd_cache ( s_line_cnt_d = s_line_cnt_q + 1'b1; s_word_data_d = s_cache_data_q[s_line_cnt_d]; if (s_line_cnt_q == 7'd127) begin - s_cache_fsm_d = FSM_ALLOC; + s_cache_fsm_d = Allocate; if (~mode_i) s_cache_tag_d = {13'd0, ribp.addr[27:9]}; else s_cache_tag_d = ribp.addr; end @@ -170,6 +175,9 @@ module spisd_cache ( end end end + default: begin + // Preserve the legacy illegal-state hold through the default assignments. + end endcase end @@ -179,7 +187,7 @@ module spisd_cache ( .clk_i (clk_i), .rst_n_i(rst_n_i), .dat_i (s_cache_fsm_d), - .dat_o (s_cache_fsm_q) + .dat_o (s_cache_fsm_bits_q) ); dffr #( @@ -245,6 +253,8 @@ module spisd_cache ( .dat_o (s_word_data_q) ); + // This is inferred cache-array storage; a Common DFF bank would not preserve + // array write semantics or the intended memory inference. always_ff @(posedge clk_i or negedge rst_n_i) begin if (~rst_n_i) begin for (int i = 0; i < 128; ++i) s_cache_data_q[i] <= '0; diff --git a/rtl/ip/storage/spisd_data.sv b/rtl/ip/storage/spisd_data.sv index 137255ff..c62efb11 100644 --- a/rtl/ip/storage/spisd_data.sv +++ b/rtl/ip/storage/spisd_data.sv @@ -43,21 +43,23 @@ module spisd_data ( logic s_pos_init_done; logic s_neg_wr_busy; - logic r_wr_req; - logic r_rd_req; - logic [31:0] r_sec_addr; + logic s_wr_req; + logic s_rd_req; + logic [31:0] s_sec_addr; - assign wr_req_o = r_wr_req; - assign rd_req_o = r_rd_req; - assign sec_addr_o = r_sec_addr; + assign wr_req_o = s_wr_req; + assign rd_req_o = s_rd_req; + assign sec_addr_o = s_sec_addr; assign s_pos_init_done = (~sd_init_done_d1) & sd_init_done_d0; assign s_neg_wr_busy = wr_busy_d1 & (~wr_busy_d0); assign wr_data_o = wr_data_t; - always_ff @(posedge clk_i, negedge rst_n_i) begin + // These edge-qualified protocol monitors retain their ordered reset/update + // behavior; splitting them into DFF primitives would not improve storage intent. + always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin sd_init_done_d0 <= 1'b0; sd_init_done_d1 <= 1'b0; @@ -69,34 +71,34 @@ module spisd_data ( end end - always_ff @(posedge clk_i, negedge rst_n_i) begin + always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_wr_req <= 1'b0; - r_rd_req <= 1'b0; - r_sec_addr <= '0; + s_wr_req <= 1'b0; + s_rd_req <= 1'b0; + s_sec_addr <= '0; end else begin if (fir_clk_edge_i) begin if (s_pos_init_done) begin - r_wr_req <= 1'b1; - r_sec_addr <= 32'd20000; + s_wr_req <= 1'b1; + s_sec_addr <= 32'd20000; end else if (s_neg_wr_busy) begin - r_rd_req <= 1'b1; - r_sec_addr <= 32'd20000; + s_rd_req <= 1'b1; + s_sec_addr <= 32'd20000; end else begin - r_wr_req <= 1'b0; - r_rd_req <= 1'b0; + s_wr_req <= 1'b0; + s_rd_req <= 1'b0; end end end end - always_ff @(posedge clk_i, negedge rst_n_i) begin + always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) wr_data_t <= '1; else if (fir_clk_edge_i && wr_data_req_i) wr_data_t <= wr_data_t + 1'b1; end - always_ff @(posedge clk_i, negedge rst_n_i) begin + always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin wr_busy_d0 <= 1'b0; wr_busy_d1 <= 1'b0; @@ -108,7 +110,7 @@ module spisd_data ( end end - always_ff @(posedge clk_i, negedge rst_n_i) begin + always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin rd_comp_data <= '0; rd_right_cnt <= '0; diff --git a/rtl/ip/storage/spisd_init.sv b/rtl/ip/storage/spisd_init.sv index 6ad2a8f3..c5fd3728 100644 --- a/rtl/ip/storage/spisd_init.sv +++ b/rtl/ip/storage/spisd_init.sv @@ -28,46 +28,50 @@ module spisd_init ( input logic spisd_miso_i ); - localparam CMD0 = {8'h40, 8'h00, 8'h00, 8'h00, 8'h00, 8'h95}; - localparam CMD8 = {8'h48, 8'h00, 8'h00, 8'h01, 8'hAA, 8'h87}; - localparam CMD55 = {8'h77, 8'h00, 8'h00, 8'h00, 8'h00, 8'hFF}; - localparam ACMD41 = {8'h69, 8'h40, 8'h00, 8'h00, 8'h00, 8'hFF}; - localparam DIV_FREQ = 200; - localparam OVER_TIME_NUM = 25000; + localparam logic [47:0] Cmd0 = {8'h40, 8'h00, 8'h00, 8'h00, 8'h00, 8'h95}; + localparam logic [47:0] Cmd8 = {8'h48, 8'h00, 8'h00, 8'h01, 8'hAA, 8'h87}; + localparam logic [47:0] Cmd55 = {8'h77, 8'h00, 8'h00, 8'h00, 8'h00, 8'hFF}; + localparam logic [47:0] Acmd41 = {8'h69, 8'h40, 8'h00, 8'h00, 8'h00, 8'hFF}; + localparam int signed DivFreq = 32'sd200; + localparam int signed OverTimeNum = 32'sd25000; - localparam FSM_IDLE = 3'd0; - localparam FSM_SEND_CMD0 = 3'd1; - localparam FSM_WAIT_CMD0 = 3'd2; - localparam FSM_SEND_CMD8 = 3'd3; - localparam FSM_SEND_CMD55 = 3'd4; - localparam FSM_SEND_ACMD41 = 3'd5; - localparam FSM_INIT_DONE = 3'd6; + typedef enum logic [2:0] { + Idle = 3'd0, + SendCmd0 = 3'd1, + WaitCmd0 = 3'd2, + SendCmd8 = 3'd3, + SendCmd55 = 3'd4, + SendAcmd41 = 3'd5, + InitDone = 3'd6 + } spisd_init_state_e; logic s_div_clk_d, s_div_clk_q; logic [7:0] s_div_cnt_d, s_div_cnt_q; // 512 div logic [6:0] s_boot_cnt_d, s_boot_cnt_q; // count 128 - logic [2:0] s_fsm_d, s_fsm_q; + spisd_init_state_e s_fsm_d, s_fsm_q; + logic [2:0] s_fsm_bits_q; logic s_fir_clk_edge, s_sec_clk_edge; // Response signals. - logic r_resp_en; - logic [47:0] r_resp_data; - logic r_resp_flag; - logic [ 5:0] r_resp_bit_cnt; + logic s_resp_en; + logic [47:0] s_resp_data; + logic s_resp_flag; + logic [ 5:0] s_resp_bit_cnt; // utils - logic [ 5:0] r_cmd_bit_cnt; - logic [15:0] r_overflow_cnt; - logic r_overflow_en; + logic [ 5:0] s_cmd_bit_cnt; + logic [15:0] s_overflow_cnt; + logic s_overflow_en; // spi if - logic r_init_done; - logic r_spisd_cs, r_spisd_mosi; + logic s_init_done; + logic s_spisd_cs, s_spisd_mosi; - assign init_done_o = r_init_done; + assign init_done_o = s_init_done; assign spisd_clk_o = s_div_clk_q; - assign spisd_cs_o = r_spisd_cs; - assign spisd_mosi_o = r_spisd_mosi; + assign spisd_cs_o = s_spisd_cs; + assign spisd_mosi_o = s_spisd_mosi; // fir: fall sec: pos assign s_fir_clk_edge = s_div_clk_q && (s_div_cnt_q == '0); assign s_sec_clk_edge = (~s_div_clk_q) && (s_div_cnt_q == '0); + assign s_fsm_q = spisd_init_state_e'(s_fsm_bits_q); always_comb begin s_div_cnt_d = s_div_cnt_q; @@ -100,7 +104,7 @@ module spisd_init ( always_comb begin s_boot_cnt_d = s_boot_cnt_q; if (s_fir_clk_edge) begin - if (s_fsm_q == FSM_IDLE) begin + if (s_fsm_q == Idle) begin if (s_boot_cnt_q != '0) s_boot_cnt_d = s_boot_cnt_q - 1'b1; end else begin s_boot_cnt_d = '1; @@ -118,28 +122,30 @@ module spisd_init ( ); + // Response capture and command sequencing depend on edge-qualified ordered + // updates, so the processes remain intact to preserve SPI timing exactly. always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_resp_en <= '0; - r_resp_data <= '0; - r_resp_flag <= '0; - r_resp_bit_cnt <= '0; + s_resp_en <= '0; + s_resp_data <= '0; + s_resp_flag <= '0; + s_resp_bit_cnt <= '0; end else begin if (s_sec_clk_edge) begin - if (spisd_miso_i == 1'b0 && r_resp_flag == 1'b0) begin - r_resp_flag <= 1'b1; - r_resp_data <= {r_resp_data[46:0], spisd_miso_i}; - r_resp_bit_cnt <= r_resp_bit_cnt + 6'd1; - r_resp_en <= 1'b0; - end else if (r_resp_flag) begin - r_resp_data <= {r_resp_data[46:0], spisd_miso_i}; - r_resp_bit_cnt <= r_resp_bit_cnt + 6'd1; - if (r_resp_bit_cnt == 6'd47) begin - r_resp_flag <= 1'b0; - r_resp_bit_cnt <= '0; - r_resp_en <= 1'b1; + if (spisd_miso_i == 1'b0 && s_resp_flag == 1'b0) begin + s_resp_flag <= 1'b1; + s_resp_data <= {s_resp_data[46:0], spisd_miso_i}; + s_resp_bit_cnt <= s_resp_bit_cnt + 6'd1; + s_resp_en <= 1'b0; + end else if (s_resp_flag) begin + s_resp_data <= {s_resp_data[46:0], spisd_miso_i}; + s_resp_bit_cnt <= s_resp_bit_cnt + 6'd1; + if (s_resp_bit_cnt == 6'd47) begin + s_resp_flag <= 1'b0; + s_resp_bit_cnt <= '0; + s_resp_en <= 1'b1; end - end else r_resp_en <= 1'b0; + end else s_resp_en <= 1'b0; end end end @@ -147,38 +153,38 @@ module spisd_init ( always_comb begin s_fsm_d = s_fsm_q; case (s_fsm_q) - FSM_IDLE: begin - if (s_boot_cnt_q == '0) s_fsm_d = FSM_SEND_CMD0; + Idle: begin + if (s_boot_cnt_q == '0) s_fsm_d = SendCmd0; end - FSM_SEND_CMD0: begin - if (r_cmd_bit_cnt == 6'd47) s_fsm_d = FSM_WAIT_CMD0; + SendCmd0: begin + if (s_cmd_bit_cnt == 6'd47) s_fsm_d = WaitCmd0; end - FSM_WAIT_CMD0: begin - if (r_resp_en) begin - if (r_resp_data[47:40] == 8'h01) s_fsm_d = FSM_SEND_CMD8; - else s_fsm_d = FSM_IDLE; - end else if (r_overflow_en) s_fsm_d = FSM_IDLE; + WaitCmd0: begin + if (s_resp_en) begin + if (s_resp_data[47:40] == 8'h01) s_fsm_d = SendCmd8; + else s_fsm_d = Idle; + end else if (s_overflow_en) s_fsm_d = Idle; end - FSM_SEND_CMD8: begin - if (r_resp_en) begin - if (r_resp_data[19:16] == 4'b0001) s_fsm_d = FSM_SEND_CMD55; - else s_fsm_d = FSM_IDLE; + SendCmd8: begin + if (s_resp_en) begin + if (s_resp_data[19:16] == 4'b0001) s_fsm_d = SendCmd55; + else s_fsm_d = Idle; end end - FSM_SEND_CMD55: begin - if (r_resp_en) begin - if (r_resp_data[47:40] == 8'h01) s_fsm_d = FSM_SEND_ACMD41; + SendCmd55: begin + if (s_resp_en) begin + if (s_resp_data[47:40] == 8'h01) s_fsm_d = SendAcmd41; end end - FSM_SEND_ACMD41: begin - if (r_resp_en) begin - if (r_resp_data[47:40] == 8'h00) s_fsm_d = FSM_INIT_DONE; - else s_fsm_d = FSM_SEND_CMD55; + SendAcmd41: begin + if (s_resp_en) begin + if (s_resp_data[47:40] == 8'h00) s_fsm_d = InitDone; + else s_fsm_d = SendCmd55; end end - FSM_INIT_DONE: s_fsm_d = FSM_INIT_DONE; - default: s_fsm_d = FSM_IDLE; + InitDone: s_fsm_d = InitDone; + default: s_fsm_d = Idle; endcase end dffer #( @@ -188,87 +194,87 @@ module spisd_init ( .rst_n_i(rst_n_i), .en_i (s_fir_clk_edge), .dat_i (s_fsm_d), - .dat_o (s_fsm_q) + .dat_o (s_fsm_bits_q) ); - always_ff @(posedge clk_i, negedge rst_n_i) begin + always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_init_done <= '0; - r_spisd_cs <= '1; - r_spisd_mosi <= '1; + s_init_done <= '0; + s_spisd_cs <= '1; + s_spisd_mosi <= '1; - r_cmd_bit_cnt <= '0; - r_overflow_cnt <= '0; - r_overflow_en <= '0; + s_cmd_bit_cnt <= '0; + s_overflow_cnt <= '0; + s_overflow_en <= '0; end else begin if (s_fir_clk_edge) begin - r_overflow_en <= 1'b0; + s_overflow_en <= 1'b0; case (s_fsm_q) - FSM_IDLE: begin - r_spisd_cs <= 1'b1; - r_spisd_mosi <= 1'b1; + Idle: begin + s_spisd_cs <= 1'b1; + s_spisd_mosi <= 1'b1; end - FSM_SEND_CMD0: begin - r_spisd_cs <= 1'b0; - r_spisd_mosi <= CMD0[6'd47-r_cmd_bit_cnt]; - r_cmd_bit_cnt <= r_cmd_bit_cnt + 6'd1; - if (r_cmd_bit_cnt == 6'd47) r_cmd_bit_cnt <= '0; + SendCmd0: begin + s_spisd_cs <= 1'b0; + s_spisd_mosi <= Cmd0[6'd47-s_cmd_bit_cnt]; + s_cmd_bit_cnt <= s_cmd_bit_cnt + 6'd1; + if (s_cmd_bit_cnt == 6'd47) s_cmd_bit_cnt <= '0; end - FSM_WAIT_CMD0: begin - r_spisd_mosi <= 1'b1; - if (r_resp_en) r_spisd_cs <= 1'b1; + WaitCmd0: begin + s_spisd_mosi <= 1'b1; + if (s_resp_en) s_spisd_cs <= 1'b1; - r_overflow_cnt <= r_overflow_cnt + 1'b1; - if (r_overflow_cnt == OVER_TIME_NUM) r_overflow_en <= 1'b1; - if (r_overflow_en) r_overflow_cnt <= '0; + s_overflow_cnt <= s_overflow_cnt + 1'b1; + if (s_overflow_cnt == OverTimeNum) s_overflow_en <= 1'b1; + if (s_overflow_en) s_overflow_cnt <= '0; end - FSM_SEND_CMD8: begin - if (r_cmd_bit_cnt <= 6'd47) begin - r_cmd_bit_cnt <= r_cmd_bit_cnt + 6'd1; - r_spisd_cs <= 1'b0; - r_spisd_mosi <= CMD8[6'd47-r_cmd_bit_cnt]; + SendCmd8: begin + if (s_cmd_bit_cnt <= 6'd47) begin + s_cmd_bit_cnt <= s_cmd_bit_cnt + 6'd1; + s_spisd_cs <= 1'b0; + s_spisd_mosi <= Cmd8[6'd47-s_cmd_bit_cnt]; end else begin - r_spisd_mosi <= 1'b1; - if (r_resp_en) begin - r_spisd_cs <= 1'b1; - r_cmd_bit_cnt <= '0; + s_spisd_mosi <= 1'b1; + if (s_resp_en) begin + s_spisd_cs <= 1'b1; + s_cmd_bit_cnt <= '0; end end end - FSM_SEND_CMD55: begin - if (r_cmd_bit_cnt <= 6'd47) begin - r_cmd_bit_cnt <= r_cmd_bit_cnt + 6'd1; - r_spisd_cs <= 1'b0; - r_spisd_mosi <= CMD55[6'd47-r_cmd_bit_cnt]; + SendCmd55: begin + if (s_cmd_bit_cnt <= 6'd47) begin + s_cmd_bit_cnt <= s_cmd_bit_cnt + 6'd1; + s_spisd_cs <= 1'b0; + s_spisd_mosi <= Cmd55[6'd47-s_cmd_bit_cnt]; end else begin - r_spisd_mosi <= 1'b1; - if (r_resp_en) begin - r_spisd_cs <= 1'b1; - r_cmd_bit_cnt <= '0; + s_spisd_mosi <= 1'b1; + if (s_resp_en) begin + s_spisd_cs <= 1'b1; + s_cmd_bit_cnt <= '0; end end end - FSM_SEND_ACMD41: begin - if (r_cmd_bit_cnt <= 6'd47) begin - r_cmd_bit_cnt <= r_cmd_bit_cnt + 6'd1; - r_spisd_cs <= 1'b0; - r_spisd_mosi <= ACMD41[6'd47-r_cmd_bit_cnt]; + SendAcmd41: begin + if (s_cmd_bit_cnt <= 6'd47) begin + s_cmd_bit_cnt <= s_cmd_bit_cnt + 6'd1; + s_spisd_cs <= 1'b0; + s_spisd_mosi <= Acmd41[6'd47-s_cmd_bit_cnt]; end else begin - r_spisd_mosi <= 1'b1; - if (r_resp_en) begin - r_spisd_cs <= 1'b1; - r_cmd_bit_cnt <= '0; + s_spisd_mosi <= 1'b1; + if (s_resp_en) begin + s_spisd_cs <= 1'b1; + s_cmd_bit_cnt <= '0; end end end - FSM_INIT_DONE: begin - r_init_done <= 1'b1; - r_spisd_cs <= 1'b1; - r_spisd_mosi <= 1'b1; + InitDone: begin + s_init_done <= 1'b1; + s_spisd_cs <= 1'b1; + s_spisd_mosi <= 1'b1; end default: begin - r_spisd_cs <= 1'b1; - r_spisd_mosi <= 1'b1; + s_spisd_cs <= 1'b1; + s_spisd_mosi <= 1'b1; end endcase end diff --git a/rtl/ip/storage/spisd_read.sv b/rtl/ip/storage/spisd_read.sv index e9ca744c..45349c93 100644 --- a/rtl/ip/storage/spisd_read.sv +++ b/rtl/ip/storage/spisd_read.sv @@ -33,117 +33,119 @@ module spisd_read ( input logic spisd_miso_i ); - logic r_rd_en_d0; - logic r_rd_en_d1; - logic r_resp_en; - // logic [ 7:0] r_resp_data; - logic r_resp_flag; - logic [ 5:0] r_resp_bit_cnt; - logic r_rx_en_t; - logic [ 7:0] r_rx_data_t; - logic r_rx_flag; - logic [ 3:0] r_rx_bit_cnt; - logic [ 9:0] r_rx_data_cnt; - logic r_rx_finish_en; - logic [ 3:0] r_rd_ctrl_cnt; - logic [47:0] r_cmd_rd; - logic [ 5:0] r_cmd_bit_cnt; - logic r_rd_data_flag; + logic s_rd_en_d0; + logic s_rd_en_d1; + logic s_resp_en; + // logic [ 7:0] s_resp_data; + logic s_resp_flag; + logic [ 5:0] s_resp_bit_cnt; + logic s_rx_en_t; + logic [ 7:0] s_rx_data_t; + logic s_rx_flag; + logic [ 3:0] s_rx_bit_cnt; + logic [ 9:0] s_rx_data_cnt; + logic s_rx_finish_en; + logic [ 3:0] s_rd_ctrl_cnt; + logic [47:0] s_cmd_rd; + logic [ 5:0] s_cmd_bit_cnt; + logic s_rd_data_flag; logic s_pos_rd_en; - logic r_rd_data_vld; - logic [ 7:0] r_rd_data; - logic r_rd_busy; - logic r_spisd_cs; - logic r_spisd_mosi; + logic s_rd_data_vld; + logic [ 7:0] s_rd_data; + logic s_rd_busy; + logic s_spisd_cs; + logic s_spisd_mosi; - assign rd_data_vld_o = r_rd_data_vld; - assign rd_data_o = r_rd_data; - assign rd_busy_o = r_rd_busy; - assign spisd_cs_o = r_spisd_cs; - assign spisd_mosi_o = r_spisd_mosi; + assign rd_data_vld_o = s_rd_data_vld; + assign rd_data_o = s_rd_data; + assign rd_busy_o = s_rd_busy; + assign spisd_cs_o = s_spisd_cs; + assign spisd_mosi_o = s_spisd_mosi; - assign s_pos_rd_en = (~r_rd_en_d1) & r_rd_en_d0; + assign s_pos_rd_en = (~s_rd_en_d1) & s_rd_en_d0; + // The following edge-qualified SPI receive/control processes retain ordered + // reset/update priority; splitting them would risk changing byte timing. always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_rd_en_d0 <= 1'b0; - r_rd_en_d1 <= 1'b0; + s_rd_en_d0 <= 1'b0; + s_rd_en_d1 <= 1'b0; end else begin if (fir_clk_edge_i) begin - r_rd_en_d0 <= rd_req_i; - r_rd_en_d1 <= r_rd_en_d0; + s_rd_en_d0 <= rd_req_i; + s_rd_en_d1 <= s_rd_en_d0; end end end always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_resp_en <= '0; - // r_resp_data <= '0; - r_resp_flag <= '0; - r_resp_bit_cnt <= '0; + s_resp_en <= '0; + // s_resp_data <= '0; + s_resp_flag <= '0; + s_resp_bit_cnt <= '0; end else begin if (sec_clk_edge_i) begin - if (spisd_miso_i == 1'b0 && r_resp_flag == 1'b0) begin - r_resp_flag <= 1'b1; - // r_resp_data <= {r_resp_data[6:0], spisd_miso_i}; - r_resp_bit_cnt <= r_resp_bit_cnt + 6'd1; - r_resp_en <= 1'b0; - end else if (r_resp_flag) begin - // r_resp_data <= {r_resp_data[6:0], spisd_miso_i}; - r_resp_bit_cnt <= r_resp_bit_cnt + 6'd1; - if (r_resp_bit_cnt == 6'd7) begin - r_resp_flag <= 1'b0; - r_resp_bit_cnt <= '0; - r_resp_en <= 1'b1; + if (spisd_miso_i == 1'b0 && s_resp_flag == 1'b0) begin + s_resp_flag <= 1'b1; + // s_resp_data <= {s_resp_data[6:0], spisd_miso_i}; + s_resp_bit_cnt <= s_resp_bit_cnt + 6'd1; + s_resp_en <= 1'b0; + end else if (s_resp_flag) begin + // s_resp_data <= {s_resp_data[6:0], spisd_miso_i}; + s_resp_bit_cnt <= s_resp_bit_cnt + 6'd1; + if (s_resp_bit_cnt == 6'd7) begin + s_resp_flag <= 1'b0; + s_resp_bit_cnt <= '0; + s_resp_en <= 1'b1; end - end else r_resp_en <= 1'b0; + end else s_resp_en <= 1'b0; end end end always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_rx_en_t <= '0; - r_rx_data_t <= '0; - r_rx_flag <= '0; - r_rx_bit_cnt <= '0; - r_rx_data_cnt <= '0; - r_rx_finish_en <= '0; + s_rx_en_t <= '0; + s_rx_data_t <= '0; + s_rx_flag <= '0; + s_rx_bit_cnt <= '0; + s_rx_data_cnt <= '0; + s_rx_finish_en <= '0; end else begin if (sec_clk_edge_i) begin - r_rx_en_t <= 1'b0; - r_rx_finish_en <= 1'b0; - if (r_rd_data_flag && spisd_miso_i == 1'b0 && r_rx_flag == 1'b0) r_rx_flag <= 1'b1; - else if (r_rx_flag) begin - r_rx_bit_cnt <= r_rx_bit_cnt + 4'd1; - r_rx_data_t <= {r_rx_data_t[7:0], spisd_miso_i}; - if (r_rx_bit_cnt == 4'd7) begin - r_rx_bit_cnt <= '0; - r_rx_data_cnt <= r_rx_data_cnt + 1'b1; - if (r_rx_data_cnt <= 10'd511) r_rx_en_t <= 1'b1; - else if (r_rx_data_cnt == 10'd513) begin - r_rx_flag <= 1'b0; - r_rx_finish_en <= 1'b1; - r_rx_data_cnt <= '0; - r_rx_bit_cnt <= '0; + s_rx_en_t <= 1'b0; + s_rx_finish_en <= 1'b0; + if (s_rd_data_flag && spisd_miso_i == 1'b0 && s_rx_flag == 1'b0) s_rx_flag <= 1'b1; + else if (s_rx_flag) begin + s_rx_bit_cnt <= s_rx_bit_cnt + 4'd1; + s_rx_data_t <= {s_rx_data_t[7:0], spisd_miso_i}; + if (s_rx_bit_cnt == 4'd7) begin + s_rx_bit_cnt <= '0; + s_rx_data_cnt <= s_rx_data_cnt + 1'b1; + if (s_rx_data_cnt <= 10'd511) s_rx_en_t <= 1'b1; + else if (s_rx_data_cnt == 10'd513) begin + s_rx_flag <= 1'b0; + s_rx_finish_en <= 1'b1; + s_rx_data_cnt <= '0; + s_rx_bit_cnt <= '0; end end - end else r_rx_data_t <= '0; + end else s_rx_data_t <= '0; end end end always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_rd_data_vld <= '0; - r_rd_data <= '0; + s_rd_data_vld <= '0; + s_rd_data <= '0; end else begin if (fir_clk_edge_i) begin - if (r_rx_en_t) begin - r_rd_data_vld <= 1'b1; - r_rd_data <= r_rx_data_t; - end else r_rd_data_vld <= 1'b0; + if (s_rx_en_t) begin + s_rd_data_vld <= 1'b1; + s_rd_data <= s_rx_data_t; + end else s_rd_data_vld <= 1'b0; end end end @@ -151,50 +153,50 @@ module spisd_read ( always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_spisd_cs <= 1'b1; - r_spisd_mosi <= 1'b1; - r_rd_ctrl_cnt <= '0; - r_cmd_rd <= '0; - r_cmd_bit_cnt <= '0; - r_rd_busy <= '0; - r_rd_data_flag <= '0; + s_spisd_cs <= 1'b1; + s_spisd_mosi <= 1'b1; + s_rd_ctrl_cnt <= '0; + s_cmd_rd <= '0; + s_cmd_bit_cnt <= '0; + s_rd_busy <= '0; + s_rd_data_flag <= '0; end else begin if (fir_clk_edge_i) begin - case (r_rd_ctrl_cnt) + case (s_rd_ctrl_cnt) 4'd0: begin - r_rd_busy <= 1'b0; - r_spisd_cs <= 1'b1; - r_spisd_mosi <= 1'b1; + s_rd_busy <= 1'b0; + s_spisd_cs <= 1'b1; + s_spisd_mosi <= 1'b1; if (s_pos_rd_en) begin - r_cmd_rd <= {8'h51, rd_sec_addr_i, 8'hFF}; - r_rd_ctrl_cnt <= r_rd_ctrl_cnt + 4'd1; - r_rd_busy <= 1'b1; + s_cmd_rd <= {8'h51, rd_sec_addr_i, 8'hFF}; + s_rd_ctrl_cnt <= s_rd_ctrl_cnt + 4'd1; + s_rd_busy <= 1'b1; end end 4'd1: begin - if (r_cmd_bit_cnt <= 6'd47) begin - r_cmd_bit_cnt <= r_cmd_bit_cnt + 6'd1; - r_spisd_cs <= 1'b0; - r_spisd_mosi <= r_cmd_rd[6'd47-r_cmd_bit_cnt]; + if (s_cmd_bit_cnt <= 6'd47) begin + s_cmd_bit_cnt <= s_cmd_bit_cnt + 6'd1; + s_spisd_cs <= 1'b0; + s_spisd_mosi <= s_cmd_rd[6'd47-s_cmd_bit_cnt]; end else begin - r_spisd_mosi <= 1'b1; - if (r_resp_en) begin - r_rd_ctrl_cnt <= r_rd_ctrl_cnt + 4'd1; - r_cmd_bit_cnt <= '0; + s_spisd_mosi <= 1'b1; + if (s_resp_en) begin + s_rd_ctrl_cnt <= s_rd_ctrl_cnt + 4'd1; + s_cmd_bit_cnt <= '0; end end end 4'd2: begin - r_rd_data_flag <= 1'b1; - if (r_rx_finish_en) begin - r_rd_ctrl_cnt <= r_rd_ctrl_cnt + 4'd1; - r_rd_data_flag <= 1'b0; - r_spisd_cs <= 1'b1; + s_rd_data_flag <= 1'b1; + if (s_rx_finish_en) begin + s_rd_ctrl_cnt <= s_rd_ctrl_cnt + 4'd1; + s_rd_data_flag <= 1'b0; + s_spisd_cs <= 1'b1; end end default: begin - r_spisd_cs <= 1'b1; - r_rd_ctrl_cnt <= r_rd_ctrl_cnt + 4'd1; + s_spisd_cs <= 1'b1; + s_rd_ctrl_cnt <= s_rd_ctrl_cnt + 4'd1; end endcase end diff --git a/rtl/ip/storage/spisd_reg.sv b/rtl/ip/storage/spisd_reg.sv index e28715fb..8353b601 100644 --- a/rtl/ip/storage/spisd_reg.sv +++ b/rtl/ip/storage/spisd_reg.sv @@ -11,7 +11,7 @@ `ifndef RIBP_SPISD_DEF_SV `define RIBP_SPISD_DEF_SV -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_SPISD_MODE 8'h00 `define RIBP_SPISD_CLKDIV 8'h04 `define RIBP_SPISD_ADDR 8'h08 @@ -24,7 +24,7 @@ `endif module spisd_reg ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic init_done_i, @@ -32,8 +32,8 @@ module spisd_reg ( input logic wr_sync_done_i, output logic mode_o, output logic [1:0] clkdiv_o, - ribp_if.slave ribp, - ribp_if.master byp_rib + ribp_if.slave ribp, + ribp_if.master byp_rib // verilog_format: on ); // ribp diff --git a/rtl/ip/storage/spisd_write.sv b/rtl/ip/storage/spisd_write.sv index b3f4d62f..44f6c554 100644 --- a/rtl/ip/storage/spisd_write.sv +++ b/rtl/ip/storage/spisd_write.sv @@ -33,168 +33,170 @@ module spisd_write ( input logic spisd_miso_i ); - localparam HEAD_BYTE = 8'hFE; + localparam logic [7:0] HeadByte = 8'hFE; - logic r_wr_en_d0; - logic r_wr_en_d1; - logic r_resp_en; - // logic [ 7:0] r_resp_data; - logic r_resp_flag; - logic [ 5:0] r_resp_bit_cnt; - logic [ 3:0] r_wr_ctrl_cnt; - logic [47:0] r_cmd_wr; - logic [ 5:0] r_cmd_bit_cnt; - logic [ 3:0] r_bit_cnt; - logic [ 8:0] r_data_cnt; - logic [ 7:0] r_wr_data_t; - logic r_detect_done_flag; - logic [ 7:0] r_detect_data; + logic s_wr_en_d0; + logic s_wr_en_d1; + logic s_resp_en; + // logic [ 7:0] s_resp_data; + logic s_resp_flag; + logic [ 5:0] s_resp_bit_cnt; + logic [ 3:0] s_wr_ctrl_cnt; + logic [47:0] s_cmd_wr; + logic [ 5:0] s_cmd_bit_cnt; + logic [ 3:0] s_bit_cnt; + logic [ 8:0] s_data_cnt; + logic [ 7:0] s_wr_data_t; + logic s_detect_done_flag; + logic [ 7:0] s_detect_data; logic s_pos_wr_en; - logic r_wr_data_req; - logic r_wr_busy; - logic r_spisd_cs; - logic r_spisd_mosi; + logic s_wr_data_req; + logic s_wr_busy; + logic s_spisd_cs; + logic s_spisd_mosi; - assign wr_data_req_o = r_wr_data_req; - assign wr_busy_o = r_wr_busy; - assign spisd_cs_o = r_spisd_cs; - assign spisd_mosi_o = r_spisd_mosi; + assign wr_data_req_o = s_wr_data_req; + assign wr_busy_o = s_wr_busy; + assign spisd_cs_o = s_spisd_cs; + assign spisd_mosi_o = s_spisd_mosi; - assign s_pos_wr_en = (~r_wr_en_d1) & r_wr_en_d0; + assign s_pos_wr_en = (~s_wr_en_d1) & s_wr_en_d0; + // The following edge-qualified SPI transmit/control processes retain ordered + // reset/update priority; splitting them would risk changing byte timing. always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_wr_en_d0 <= 1'b0; - r_wr_en_d1 <= 1'b0; + s_wr_en_d0 <= 1'b0; + s_wr_en_d1 <= 1'b0; end else begin if (fir_clk_edge_i) begin - r_wr_en_d0 <= wr_req_i; - r_wr_en_d1 <= r_wr_en_d0; + s_wr_en_d0 <= wr_req_i; + s_wr_en_d1 <= s_wr_en_d0; end end end always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_resp_en <= '0; - // r_resp_data <= '0; - r_resp_flag <= '0; - r_resp_bit_cnt <= '0; + s_resp_en <= '0; + // s_resp_data <= '0; + s_resp_flag <= '0; + s_resp_bit_cnt <= '0; end else begin if (sec_clk_edge_i) begin - if (spisd_miso_i == 1'b0 && r_resp_flag == 1'b0) begin - r_resp_flag <= 1'b1; - // r_resp_data <= {r_resp_data[6:0], spisd_miso_i}; - r_resp_bit_cnt <= r_resp_bit_cnt + 6'd1; - r_resp_en <= 1'b0; - end else if (r_resp_flag) begin - // r_resp_data <= {r_resp_data[6:0], spisd_miso_i}; - r_resp_bit_cnt <= r_resp_bit_cnt + 6'd1; - if (r_resp_bit_cnt == 6'd7) begin - r_resp_flag <= 1'b0; - r_resp_bit_cnt <= '0; - r_resp_en <= 1'b1; + if (spisd_miso_i == 1'b0 && s_resp_flag == 1'b0) begin + s_resp_flag <= 1'b1; + // s_resp_data <= {s_resp_data[6:0], spisd_miso_i}; + s_resp_bit_cnt <= s_resp_bit_cnt + 6'd1; + s_resp_en <= 1'b0; + end else if (s_resp_flag) begin + // s_resp_data <= {s_resp_data[6:0], spisd_miso_i}; + s_resp_bit_cnt <= s_resp_bit_cnt + 6'd1; + if (s_resp_bit_cnt == 6'd7) begin + s_resp_flag <= 1'b0; + s_resp_bit_cnt <= '0; + s_resp_en <= 1'b1; end - end else r_resp_en <= 1'b0; + end else s_resp_en <= 1'b0; end end end always_ff @(posedge clk_i or negedge rst_n_i) begin - if (!rst_n_i) r_detect_data <= '0; + if (!rst_n_i) s_detect_data <= '0; else begin if (fir_clk_edge_i) begin - if (r_detect_done_flag) r_detect_data <= {r_detect_data[6:0], spisd_miso_i}; - else r_detect_data <= '0; + if (s_detect_done_flag) s_detect_data <= {s_detect_data[6:0], spisd_miso_i}; + else s_detect_data <= '0; end end end always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_spisd_cs <= 1'b1; - r_spisd_mosi <= 1'b1; - r_wr_ctrl_cnt <= '0; - r_wr_busy <= '0; - r_cmd_wr <= '0; - r_cmd_bit_cnt <= '0; - r_bit_cnt <= '0; - r_wr_data_t <= '0; - r_data_cnt <= '0; - r_wr_data_req <= '0; - r_detect_done_flag <= '0; + s_spisd_cs <= 1'b1; + s_spisd_mosi <= 1'b1; + s_wr_ctrl_cnt <= '0; + s_wr_busy <= '0; + s_cmd_wr <= '0; + s_cmd_bit_cnt <= '0; + s_bit_cnt <= '0; + s_wr_data_t <= '0; + s_data_cnt <= '0; + s_wr_data_req <= '0; + s_detect_done_flag <= '0; end else begin if (fir_clk_edge_i) begin - r_wr_data_req <= 1'b0; - case (r_wr_ctrl_cnt) + s_wr_data_req <= 1'b0; + case (s_wr_ctrl_cnt) 4'd0: begin - r_wr_busy <= 1'b0; - r_spisd_cs <= 1'b1; - r_spisd_mosi <= 1'b1; + s_wr_busy <= 1'b0; + s_spisd_cs <= 1'b1; + s_spisd_mosi <= 1'b1; if (s_pos_wr_en) begin - r_cmd_wr <= {8'h58, wr_sec_addr_i, 8'hFF}; - r_wr_ctrl_cnt <= r_wr_ctrl_cnt + 4'd1; - r_wr_busy <= 1'b1; + s_cmd_wr <= {8'h58, wr_sec_addr_i, 8'hFF}; + s_wr_ctrl_cnt <= s_wr_ctrl_cnt + 4'd1; + s_wr_busy <= 1'b1; end end 4'd1: begin - if (r_cmd_bit_cnt <= 6'd47) begin - r_cmd_bit_cnt <= r_cmd_bit_cnt + 6'd1; - r_spisd_cs <= 1'b0; - r_spisd_mosi <= r_cmd_wr[6'd47-r_cmd_bit_cnt]; + if (s_cmd_bit_cnt <= 6'd47) begin + s_cmd_bit_cnt <= s_cmd_bit_cnt + 6'd1; + s_spisd_cs <= 1'b0; + s_spisd_mosi <= s_cmd_wr[6'd47-s_cmd_bit_cnt]; end else begin - r_spisd_mosi <= 1'b1; - if (r_resp_en) begin - r_wr_ctrl_cnt <= r_wr_ctrl_cnt + 4'd1; - r_cmd_bit_cnt <= '0; - r_bit_cnt <= 4'd1; + s_spisd_mosi <= 1'b1; + if (s_resp_en) begin + s_wr_ctrl_cnt <= s_wr_ctrl_cnt + 4'd1; + s_cmd_bit_cnt <= '0; + s_bit_cnt <= 4'd1; end end end 4'd2: begin - r_bit_cnt <= r_bit_cnt + 4'd1; + s_bit_cnt <= s_bit_cnt + 4'd1; - if (r_bit_cnt >= 4'd8 && r_bit_cnt <= 4'd15) begin - r_spisd_mosi <= HEAD_BYTE[4'd15-r_bit_cnt]; - if (r_bit_cnt == 4'd14) r_wr_data_req <= 1'b1; - else if (r_bit_cnt == 4'd15) r_wr_ctrl_cnt <= r_wr_ctrl_cnt + 4'd1; + if (s_bit_cnt >= 4'd8 && s_bit_cnt <= 4'd15) begin + s_spisd_mosi <= HeadByte[4'd15-s_bit_cnt]; + if (s_bit_cnt == 4'd14) s_wr_data_req <= 1'b1; + else if (s_bit_cnt == 4'd15) s_wr_ctrl_cnt <= s_wr_ctrl_cnt + 4'd1; end end 4'd3: begin - r_bit_cnt <= r_bit_cnt + 4'd1; - if (r_bit_cnt == 4'd0) begin - r_spisd_mosi <= wr_data_i[4'd7-r_bit_cnt]; - r_wr_data_t <= wr_data_i; - end else r_spisd_mosi <= r_wr_data_t[4'd7-r_bit_cnt]; + s_bit_cnt <= s_bit_cnt + 4'd1; + if (s_bit_cnt == 4'd0) begin + s_spisd_mosi <= wr_data_i[4'd7-s_bit_cnt]; + s_wr_data_t <= wr_data_i; + end else s_spisd_mosi <= s_wr_data_t[4'd7-s_bit_cnt]; - if ((r_bit_cnt == 4'd6) && (r_data_cnt <= 9'd511)) r_wr_data_req <= 1'b1; - if (r_bit_cnt == 4'd7) begin - r_bit_cnt <= '0; - r_data_cnt <= r_data_cnt + 1'b1; - if (r_data_cnt == 9'd511) begin - r_data_cnt <= '0; - r_wr_ctrl_cnt <= r_wr_ctrl_cnt + 4'd1; + if ((s_bit_cnt == 4'd6) && (s_data_cnt <= 9'd511)) s_wr_data_req <= 1'b1; + if (s_bit_cnt == 4'd7) begin + s_bit_cnt <= '0; + s_data_cnt <= s_data_cnt + 1'b1; + if (s_data_cnt == 9'd511) begin + s_data_cnt <= '0; + s_wr_ctrl_cnt <= s_wr_ctrl_cnt + 4'd1; end end end 4'd4: begin - r_bit_cnt <= r_bit_cnt + 4'd1; - r_spisd_mosi <= 1'b1; - if (r_bit_cnt == 4'd15) r_wr_ctrl_cnt <= r_wr_ctrl_cnt + 4'd1; + s_bit_cnt <= s_bit_cnt + 4'd1; + s_spisd_mosi <= 1'b1; + if (s_bit_cnt == 4'd15) s_wr_ctrl_cnt <= s_wr_ctrl_cnt + 4'd1; end 4'd5: begin - if (r_resp_en) r_wr_ctrl_cnt <= r_wr_ctrl_cnt + 4'd1; + if (s_resp_en) s_wr_ctrl_cnt <= s_wr_ctrl_cnt + 4'd1; end 4'd6: begin - r_detect_done_flag <= 1'b1; - if (r_detect_data == 8'hFF) begin - r_wr_ctrl_cnt <= r_wr_ctrl_cnt + 4'd1; - r_detect_done_flag <= 1'b0; + s_detect_done_flag <= 1'b1; + if (s_detect_data == 8'hFF) begin + s_wr_ctrl_cnt <= s_wr_ctrl_cnt + 4'd1; + s_detect_done_flag <= 1'b0; end end default: begin - r_spisd_cs <= 1'b1; - r_wr_ctrl_cnt <= r_wr_ctrl_cnt + 4'd1; + s_spisd_cs <= 1'b1; + s_wr_ctrl_cnt <= s_wr_ctrl_cnt + 4'd1; end endcase end diff --git a/rtl/ip/storage/xpi_core.sv b/rtl/ip/storage/xpi_core.sv index 847a42c5..a268c11e 100644 --- a/rtl/ip/storage/xpi_core.sv +++ b/rtl/ip/storage/xpi_core.sv @@ -11,7 +11,7 @@ `include "xpi_define.svh" module xpi_core ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic mode_i, @@ -48,16 +48,18 @@ module xpi_core ( ); // verilog_format: on - // verilog_format: off - localparam FSM_IDLE = 3'd0; - localparam FSM_CMD = 3'd1; - localparam FSM_ADDR = 3'd2; - localparam FSM_DUM = 3'd3; - localparam FSM_TXDATA = 3'd4; - localparam FSM_RXDATA = 3'd5; - localparam FSM_DONE = 3'd6; - localparam FSM_HLVD = 3'd7; - // verilog_format: on + // One XPI transfer is active at a time. start_i or DMA flow control begins a + // transfer; done_o marks completion, while FIFO ready inputs provide pacing. + typedef enum logic [2:0] { + Idle = 3'd0, + Command = 3'd1, + Address = 3'd2, + Dummy = 3'd3, + TxData = 3'd4, + RxData = 3'd5, + Done = 3'd6, + HoldValid = 3'd7 + } xpi_state_e; // sclk logic s_sclk, s_sclk_en_d, s_sclk_en_q; @@ -73,7 +75,8 @@ module xpi_core ( logic s_tx_data_req_d, s_tx_data_req_q; logic s_rx_data_req_d, s_rx_data_req_q; // common - logic [2:0] s_fsm_d, s_fsm_q; + xpi_state_e s_fsm_d, s_fsm_q; + logic [2:0] s_fsm_bits_q; logic s_xfer_condi, s_xfer_sta_trg, s_xfer_end_trg; logic s_dma_xfer_start, s_dma_xfer_trg; logic [7:0] s_dma_xfer_datlen; @@ -81,6 +84,7 @@ module xpi_core ( assign xpi.sck_o = s_sclk; + assign s_fsm_q = xpi_state_e'(s_fsm_bits_q); always_comb begin xpi.nss_o = 4'b1111; xpi.nss_o[nss_i] = s_nss_q; @@ -109,8 +113,8 @@ module xpi_core ( assign s_xfer_condi = (~mode_i && start_i) || (mode_i && s_dma_xfer_trg); - assign s_xfer_sta_trg = s_fsm_q == FSM_IDLE && s_xfer_condi; - assign s_xfer_end_trg = s_fsm_q == FSM_DONE || s_fsm_q == FSM_HLVD; + assign s_xfer_sta_trg = s_fsm_q == Idle && s_xfer_condi; + assign s_xfer_end_trg = s_fsm_q == Done || s_fsm_q == HoldValid; assign s_dumlen = rdwr_i ? rdulen_i : tdulen_i; @@ -132,7 +136,7 @@ module xpi_core ( s_xpi_io_oe[0] = 1'b1; s_xpi_io_do = '0; unique case (s_fsm_q) - FSM_CMD: begin + Command: begin unique case (cmdtyp_i) `XPI_TYPE_SNGL: begin s_xpi_io_oe[0] = 1'b1; @@ -152,7 +156,7 @@ module xpi_core ( end endcase end - FSM_ADDR: begin + Address: begin unique case (adrtyp_i) `XPI_TYPE_SNGL: begin s_xpi_io_oe[0] = 1'b1; @@ -172,10 +176,10 @@ module xpi_core ( end endcase end - FSM_DUM, FSM_RXDATA: begin + Dummy, RxData: begin s_xpi_io_oe = '0; end - FSM_TXDATA: begin + TxData: begin unique case (dattyp_i) `XPI_TYPE_SNGL: begin s_xpi_io_oe[0] = 1'b1; @@ -214,25 +218,25 @@ module xpi_core ( rx_data_o = '0; done_o = 1'b0; unique case (s_fsm_q) - FSM_IDLE: begin + Idle: begin if (s_xfer_condi) begin s_nss_d = 1'b0; s_sclk_en_d = 1'b1; if (cmdtyp_i != `XPI_TYPE_NONE) begin - s_fsm_d = FSM_CMD; + s_fsm_d = Command; s_xfer_bit_cnt_d = {2'd0, cmdlen_i, 3'd0}; s_xfer_data_d = cmddat_i; end else if (adrtyp_i != `XPI_TYPE_NONE) begin - s_fsm_d = FSM_ADDR; + s_fsm_d = Address; s_xfer_bit_cnt_d = {2'd0, adrlen_i, 3'd0}; s_xfer_data_d = adrdat_i; end else if (s_dumlen != '0) begin - s_fsm_d = FSM_DUM; + s_fsm_d = Dummy; s_xfer_bit_cnt_d = s_dumlen; s_xfer_data_d = '0; end else if (dattyp_i != `XPI_TYPE_NONE) begin - if (rdwr_i) s_fsm_d = FSM_RXDATA; - else s_fsm_d = FSM_TXDATA; + if (rdwr_i) s_fsm_d = RxData; + else s_fsm_d = TxData; s_xfer_bit_cnt_d = {2'd0, datbit_i, 3'd0}; s_xfer_byte_cnt_d = s_xfer_datlen; if (tx_data_rdy_i) begin @@ -241,12 +245,12 @@ module xpi_core ( s_tx_data_req_d = 1'b1; end else s_xfer_data_d = '0; end else begin - s_fsm_d = FSM_DONE; + s_fsm_d = Done; s_sclk_en_d = 1'b0; end end end - FSM_CMD: begin + Command: begin unique case (cmdtyp_i) `XPI_TYPE_SNGL: begin s_xfer_bit_cnt_d = s_xfer_bit_cnt_q - 8'd1; @@ -270,16 +274,16 @@ module xpi_core ( (cmdtyp_i == `XPI_TYPE_DUAL && s_xfer_bit_cnt_q == 8'd2) || (cmdtyp_i == `XPI_TYPE_QUAD && s_xfer_bit_cnt_q == 8'd4)) begin if (adrtyp_i != `XPI_TYPE_NONE) begin - s_fsm_d = FSM_ADDR; + s_fsm_d = Address; s_xfer_bit_cnt_d = {2'd0, adrlen_i, 3'd0}; s_xfer_data_d = adrdat_i; end else if (s_dumlen != '0) begin - s_fsm_d = FSM_DUM; + s_fsm_d = Dummy; s_xfer_bit_cnt_d = s_dumlen; s_xfer_data_d = '0; end else if (dattyp_i != `XPI_TYPE_NONE) begin - if (rdwr_i) s_fsm_d = FSM_RXDATA; - else s_fsm_d = FSM_TXDATA; + if (rdwr_i) s_fsm_d = RxData; + else s_fsm_d = TxData; s_xfer_bit_cnt_d = {2'd0, datbit_i, 3'd0}; s_xfer_byte_cnt_d = s_xfer_datlen; if (tx_data_rdy_i) begin @@ -288,12 +292,12 @@ module xpi_core ( s_tx_data_req_d = 1'b1; end else s_xfer_data_d = '0; end else begin - s_fsm_d = FSM_DONE; + s_fsm_d = Done; s_sclk_en_d = 1'b0; end end end - FSM_ADDR: begin + Address: begin unique case (adrtyp_i) `XPI_TYPE_SNGL: begin s_xfer_bit_cnt_d = s_xfer_bit_cnt_q - 8'd1; @@ -317,12 +321,12 @@ module xpi_core ( (adrtyp_i == `XPI_TYPE_DUAL && s_xfer_bit_cnt_q == 8'd2) || (adrtyp_i == `XPI_TYPE_QUAD && s_xfer_bit_cnt_q == 8'd4)) begin if (s_dumlen != '0) begin - s_fsm_d = FSM_DUM; + s_fsm_d = Dummy; s_xfer_bit_cnt_d = s_dumlen; s_xfer_data_d = '0; end else if (dattyp_i != `XPI_TYPE_NONE) begin - if (rdwr_i) s_fsm_d = FSM_RXDATA; - else s_fsm_d = FSM_TXDATA; + if (rdwr_i) s_fsm_d = RxData; + else s_fsm_d = TxData; s_xfer_bit_cnt_d = {2'd0, datbit_i, 3'd0}; s_xfer_byte_cnt_d = s_xfer_datlen; if (tx_data_rdy_i) begin @@ -331,18 +335,18 @@ module xpi_core ( s_tx_data_req_d = 1'b1; end else s_xfer_data_d = '0; end else begin - s_fsm_d = FSM_DONE; + s_fsm_d = Done; s_sclk_en_d = 1'b0; end end end - FSM_DUM: begin + Dummy: begin s_xfer_bit_cnt_d = s_xfer_bit_cnt_q - 8'd1; if (s_xfer_bit_cnt_q == 8'd1) begin if (dattyp_i != `XPI_TYPE_NONE) begin - if (rdwr_i) s_fsm_d = FSM_RXDATA; - else s_fsm_d = FSM_TXDATA; + if (rdwr_i) s_fsm_d = RxData; + else s_fsm_d = TxData; s_xfer_bit_cnt_d = {2'd0, datbit_i, 3'd0}; s_xfer_byte_cnt_d = s_xfer_datlen; if (tx_data_rdy_i) begin @@ -351,12 +355,12 @@ module xpi_core ( s_tx_data_req_d = 1'b1; end else s_xfer_data_d = '0; end else begin - s_fsm_d = FSM_DONE; + s_fsm_d = Done; s_sclk_en_d = 1'b0; end end end - FSM_TXDATA: begin + TxData: begin unique case (dattyp_i) `XPI_TYPE_SNGL: begin s_xfer_bit_cnt_d = s_xfer_bit_cnt_q - 8'd1; @@ -380,7 +384,7 @@ module xpi_core ( (dattyp_i == `XPI_TYPE_DUAL && s_xfer_bit_cnt_q == 8'd2) || (dattyp_i == `XPI_TYPE_QUAD && s_xfer_bit_cnt_q == 8'd4)) begin if (s_xfer_byte_cnt_q == 8'd1) begin - s_fsm_d = FSM_DONE; + s_fsm_d = Done; s_sclk_en_d = 1'b0; s_xfer_bit_cnt_d = 8'd2; // TODO: can config end else begin @@ -394,7 +398,7 @@ module xpi_core ( end end end - FSM_RXDATA: begin + RxData: begin unique case (dattyp_i) `XPI_TYPE_SNGL: begin s_xfer_bit_cnt_d = s_xfer_bit_cnt_q - 8'd1; @@ -455,7 +459,7 @@ module xpi_core ( end // xfer done if (s_xfer_byte_cnt_q == 8'd1) begin - s_fsm_d = FSM_DONE; + s_fsm_d = Done; s_sclk_en_d = 1'b0; s_xfer_bit_cnt_d = 8'd2; // TODO: can config end else begin @@ -464,9 +468,9 @@ module xpi_core ( end end end - FSM_DONE: begin + Done: begin if (s_xfer_bit_cnt_q == '0) begin - s_fsm_d = FSM_HLVD; + s_fsm_d = HoldValid; s_nss_d = 1'b1; s_xfer_bit_cnt_d = hlvlen_i; s_xfer_data_d = '0; @@ -474,9 +478,9 @@ module xpi_core ( s_xfer_bit_cnt_d = s_xfer_bit_cnt_q - 1'b1; end end - FSM_HLVD: begin + HoldValid: begin if (s_xfer_bit_cnt_q == '0) begin - s_fsm_d = FSM_IDLE; + s_fsm_d = Idle; done_o = 1'b1; end else begin s_xfer_bit_cnt_d = s_xfer_bit_cnt_q - 1'b1; @@ -504,7 +508,7 @@ module xpi_core ( .rst_n_i(rst_n_i), .en_i (s_xfer_sta_trg | s_sec_clk_edge | s_xfer_end_trg), .dat_i (s_fsm_d), - .dat_o (s_fsm_q) + .dat_o (s_fsm_bits_q) ); dfferh #( @@ -554,8 +558,8 @@ module xpi_core ( .clk_i(clk_i), .rst_n_i(rst_n_i), .en_i(s_xfer_sta_trg | - (s_fsm_q != FSM_RXDATA && s_sec_clk_edge) | - (s_fsm_q == FSM_RXDATA && s_fir_clk_edge) | + (s_fsm_q != RxData && s_sec_clk_edge) | + (s_fsm_q == RxData && s_fir_clk_edge) | s_xfer_end_trg), .dat_i(s_xfer_data_d), .dat_o(s_xfer_data_q) @@ -577,7 +581,7 @@ module xpi_core ( ) u_rx_data_req_dffer ( .clk_i (clk_i), .rst_n_i(rst_n_i), - .en_i ((s_fsm_q == FSM_RXDATA && s_fir_clk_edge) | s_rx_data_req_q), + .en_i ((s_fsm_q == RxData && s_fir_clk_edge) | s_rx_data_req_q), .dat_i (s_rx_data_req_d), .dat_o (s_rx_data_req_q) ); @@ -586,7 +590,7 @@ module xpi_core ( `ifndef SYNTHESIS a_xpi_read_pad_released : assert property (@(posedge clk_i) disable iff (!rst_n_i) - (s_fsm_q == FSM_DUM || s_fsm_q == FSM_RXDATA) |-> s_xpi_io_oe == '0); + (s_fsm_q == Dummy || s_fsm_q == RxData) |-> s_xpi_io_oe == '0); `endif `endif diff --git a/rtl/ip/storage/xpi_define.svh b/rtl/ip/storage/xpi_define.svh index d54e78c2..41a416d5 100644 --- a/rtl/ip/storage/xpi_define.svh +++ b/rtl/ip/storage/xpi_define.svh @@ -11,7 +11,7 @@ `ifndef RIBP_XPI_DEF_SV `define RIBP_XPI_DEF_SV -// verilog_format: off +// verilog_format: off -- preserve reviewed column alignment `define RIBP_XPI_CFGIDX 8'h00 `define RIBP_XPI_ACCMD 8'h04 `define RIBP_XPI_MMSTAD 8'h08 diff --git a/rtl/ip/storage/xpi_mm.sv b/rtl/ip/storage/xpi_mm.sv index ea219234..9c937333 100644 --- a/rtl/ip/storage/xpi_mm.sv +++ b/rtl/ip/storage/xpi_mm.sv @@ -11,7 +11,7 @@ `include "xpi_define.svh" module xpi_mm ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic [ 31:0] xpi_mmstad_i [0:`XPI_NSS_NUM-1], @@ -32,16 +32,16 @@ module xpi_mm ( input logic rx_pop_ready_i, // ctrl input logic xfer_done_i, - ribp_if.slave ribp + ribp_if.slave ribp // verilog_format: on ); - // verilog_format: off - localparam FSM_IDLE = 3'd0; - localparam FSM_WE_ST = 3'd1; - localparam FSM_WE = 3'd2; - localparam FSM_RD_ST = 3'd3; - localparam FSM_RD = 3'd4; - // verilog_format: on + typedef enum logic [2:0] { + Idle = 3'd0, + WriteStart = 3'd1, + Write = 3'd2, + ReadStart = 3'd3, + Read = 3'd4 + } xpi_mm_state_e; // ribp logic s_ribp_wr_hdshk, s_ribp_rd_hdshk; @@ -49,17 +49,17 @@ module xpi_mm ( logic s_ribp_rdata_en; logic [31:0] s_ribp_rdata_d, s_ribp_rdata_q; // ctrl - logic r_rd_st; - logic r_wr_st; - logic r_rdwr; - logic [ 2:0] r_fsm_state; - logic [31:0] r_addr; - logic [31:0] r_wr_data; - logic [ 2:0] r_xfer_byte_cnt; - logic [ 1:0] s_disp_addr_ofst; - logic [ 2:0] s_disp_byte_cnt; - logic [31:0] s_disp_wdata; - logic s_mem_valid_re; + logic s_rd_st; + logic s_wr_st; + logic s_rdwr; + xpi_mm_state_e s_fsm_state; + logic [31:0] s_addr; + logic [31:0] s_wr_data; + logic [ 2:0] s_xfer_byte_cnt; + logic [ 1:0] s_disp_addr_ofst; + logic [ 2:0] s_disp_byte_cnt; + logic [31:0] s_disp_wdata; + logic s_mem_valid_re; logic [`XPI_LNS_NUM-1:0] s_nss_d, s_nss_q; // ribp @@ -100,14 +100,14 @@ module xpi_mm ( // ctrl assign nss_o = s_nss_q; - assign rd_st_o = r_rd_st; - assign wr_st_o = r_wr_st; - assign rdwr_o = r_rdwr; - assign addr_o = r_addr; - assign xfer_byte_o = r_xfer_byte_cnt; + assign rd_st_o = s_rd_st; + assign wr_st_o = s_wr_st; + assign rdwr_o = s_rdwr; + assign addr_o = s_addr; + assign xfer_byte_o = s_xfer_byte_cnt; // tx fifo - assign tx_push_valid_o = r_fsm_state == FSM_WE_ST && tx_push_ready_i; - assign tx_push_data_o = r_wr_data; + assign tx_push_valid_o = s_fsm_state == WriteStart && tx_push_ready_i; + assign tx_push_data_o = s_wr_data; // HACK: @@ -141,60 +141,62 @@ module xpi_mm ( .re_o (s_mem_valid_re) ); - always_ff @(posedge clk_i, negedge rst_n_i) begin + // The transfer state has ordered request/reset updates in one process; retain + // it to preserve the current request-to-command cycle behavior exactly. + always_ff @(posedge clk_i or negedge rst_n_i) begin if (~rst_n_i) begin - r_fsm_state <= FSM_IDLE; - r_rd_st <= '0; - r_wr_st <= '0; - r_rdwr <= 1'b1; - r_addr <= '0; - r_wr_data <= '0; - r_xfer_byte_cnt <= '0; + s_fsm_state <= Idle; + s_rd_st <= '0; + s_wr_st <= '0; + s_rdwr <= 1'b1; + s_addr <= '0; + s_wr_data <= '0; + s_xfer_byte_cnt <= '0; end else begin - unique case (r_fsm_state) - FSM_IDLE: begin + unique case (s_fsm_state) + Idle: begin if (s_mem_valid_re) begin if (|ribp.wstrb) begin - r_fsm_state <= FSM_WE_ST; - r_addr <= {4'd0, ribp.addr[27:0]} + {30'd0, s_disp_addr_ofst}; - r_wr_data <= s_disp_wdata; - r_xfer_byte_cnt <= s_disp_byte_cnt; + s_fsm_state <= WriteStart; + s_addr <= {4'd0, ribp.addr[27:0]} + {30'd0, s_disp_addr_ofst}; + s_wr_data <= s_disp_wdata; + s_xfer_byte_cnt <= s_disp_byte_cnt; end else begin - r_fsm_state <= FSM_RD_ST; - r_addr <= {4'd0, ribp.addr[27:0]}; - r_wr_data <= ribp.wdata; // NOTE: no used - r_xfer_byte_cnt <= 3'd4; + s_fsm_state <= ReadStart; + s_addr <= {4'd0, ribp.addr[27:0]}; + s_wr_data <= ribp.wdata; // NOTE: no used + s_xfer_byte_cnt <= 3'd4; end end end - FSM_WE_ST: begin + WriteStart: begin if (tx_push_ready_i) begin - r_wr_st <= 1'b1; - r_rdwr <= 1'b0; - r_fsm_state <= FSM_WE; + s_wr_st <= 1'b1; + s_rdwr <= 1'b0; + s_fsm_state <= Write; end end - FSM_WE: begin - r_wr_st <= 1'b0; - if (xfer_done_i) r_fsm_state <= FSM_IDLE; + Write: begin + s_wr_st <= 1'b0; + if (xfer_done_i) s_fsm_state <= Idle; end - FSM_RD_ST: begin - r_rd_st <= 1'b1; - r_rdwr <= 1'b1; - r_fsm_state <= FSM_RD; + ReadStart: begin + s_rd_st <= 1'b1; + s_rdwr <= 1'b1; + s_fsm_state <= Read; end - FSM_RD: begin - r_rd_st <= 1'b0; - if (rx_pop_ready_i) r_fsm_state <= FSM_IDLE; + Read: begin + s_rd_st <= 1'b0; + if (rx_pop_ready_i) s_fsm_state <= Idle; end default: begin - r_fsm_state <= FSM_IDLE; - r_rd_st <= '0; - r_wr_st <= '0; - r_rdwr <= 1'b1; - r_addr <= '0; - r_wr_data <= '0; - r_xfer_byte_cnt <= '0; + s_fsm_state <= Idle; + s_rd_st <= '0; + s_wr_st <= '0; + s_rdwr <= 1'b1; + s_addr <= '0; + s_wr_data <= '0; + s_xfer_byte_cnt <= '0; end endcase end diff --git a/rtl/ip/storage/xpi_reg.sv b/rtl/ip/storage/xpi_reg.sv index d864b69e..1731ebf4 100644 --- a/rtl/ip/storage/xpi_reg.sv +++ b/rtl/ip/storage/xpi_reg.sv @@ -11,7 +11,7 @@ `include "xpi_define.svh" module xpi_reg ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, // reg @@ -239,7 +239,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ACCMD_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_accmd_block assign s_xpi_accmd_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ACCMD) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_accmd_d[i] = ribp.wdata[0]; @@ -258,7 +258,7 @@ module xpi_reg ( // 5000_0000 - 5FFF_FFFF - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_MMSTAD_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_mmstad_block assign s_xpi_mmstad_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_MMSTAD) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); always_comb begin @@ -282,7 +282,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_MMOFFST_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_mmoffst_block assign s_xpi_mmoffst_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_MMOFFST) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); @@ -307,7 +307,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_MODE_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_mode_block assign s_xpi_mode_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_MODE) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_mode_d[i] = ribp.wdata[0]; @@ -338,7 +338,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CLKDIV_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_clkdiv_block assign s_xpi_clkdiv_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_CLKDIV) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_clkdiv_d[i] = ribp.wdata[7:0]; @@ -356,7 +356,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RDWR_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_rdwr_block assign s_xpi_rdwr_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_RDWR) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_rdwr_d[i] = ribp.wdata[0]; @@ -374,7 +374,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_REVDAT_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_revdat_block assign s_xpi_revdat_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_REVDAT) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_revdat_d[i] = ribp.wdata[0]; @@ -392,7 +392,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_TXUPB_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_txupb_block assign s_xpi_txupb_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_TXUPB) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_txupb_d[i] = ribp.wdata[7:0]; @@ -410,7 +410,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_TXLOWB_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_txlowb_block assign s_xpi_txlowb_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_TXLOWB) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_txlowb_d[i] = ribp.wdata[7:0]; @@ -428,7 +428,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RXUPB_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_rxupb_block assign s_xpi_rxupb_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_RXUPB) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_rxupb_d[i] = ribp.wdata[5:0]; @@ -446,7 +446,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RXLOWB_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_rxlowb_block assign s_xpi_rxlowb_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_RXLOWB) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_rxlowb_d[i] = ribp.wdata[5:0]; @@ -468,7 +468,7 @@ module xpi_reg ( assign s_xpi_flush_val = ribp.wdata[0]; - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CMDTYP_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_cmdtyp_block assign s_xpi_cmdtyp_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_CMDTYP) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_cmdtyp_d[i] = ribp.wdata[1:0]; @@ -486,7 +486,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CMDLEN_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_cmdlen_block assign s_xpi_cmdlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_CMDLEN) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_cmdlen_d[i] = ribp.wdata[2:0]; @@ -504,7 +504,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_CMDDAT_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_cmddat_block assign s_xpi_cmddat_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_CMDDAT) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); always_comb begin @@ -528,7 +528,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ADRTYP_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_adrtyp_block assign s_xpi_adrtyp_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ADRTYP) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_adrtyp_d[i] = ribp.wdata[1:0]; @@ -546,7 +546,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ADRLEN_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_adrlen_block assign s_xpi_adrlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ADRLEN) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_adrlen_d[i] = ribp.wdata[2:0]; @@ -564,7 +564,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ADRDAT_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_adrdat_block assign s_xpi_adrdat_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ADRDAT) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); always_comb begin @@ -588,7 +588,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ALTTYP_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_alttyp_block assign s_xpi_alttyp_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ALTTYP) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_alttyp_d[i] = ribp.wdata[1:0]; @@ -606,7 +606,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ALTLEN_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_altlen_block assign s_xpi_altlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ALTLEN) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_altlen_d[i] = ribp.wdata[2:0]; @@ -624,7 +624,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_ALTDAT_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_altdat_block assign s_xpi_altdat_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_ALTDAT) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); always_comb begin @@ -648,7 +648,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_TDULEN_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_tdulen_block assign s_xpi_tdulen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_TDULEN) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_tdulen_d[i] = ribp.wdata[7:0]; @@ -666,7 +666,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_RDULEN_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_rdulen_block assign s_xpi_rdulen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_RDULEN) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_rdulen_d[i] = ribp.wdata[7:0]; @@ -684,7 +684,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_DATTYP_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_dattyp_block assign s_xpi_dattyp_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_DATTYP) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_dattyp_d[i] = ribp.wdata[1:0]; @@ -702,7 +702,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_DATLEN_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_datlen_block assign s_xpi_datlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_DATLEN) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_datlen_d[i] = ribp.wdata[7:0]; @@ -720,7 +720,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_DATBIT_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_datbit_block assign s_xpi_datbit_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_DATBIT) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_datbit_d[i] = ribp.wdata[2:0]; @@ -738,7 +738,7 @@ module xpi_reg ( ); - for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : XPI_HLVLEN_BLOCK + for (genvar i = 0; i < `XPI_NSS_NUM; i++) begin : xpi_hlvlen_block assign s_xpi_hlvlen_en[i] = s_ribp_wr_hdshk && (ribp.addr[7:0] == `RIBP_XPI_HLVLEN) && (`XPI_LNS_NUM'(i) == s_xpi_cfgidx_q); assign s_xpi_hlvlen_d[i] = ribp.wdata[7:0]; @@ -852,7 +852,7 @@ module xpi_reg ( .dat_o (s_ribp_ready_q) ); - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment assign s_ribp_rdata_en = s_ribp_rd_hdshk; always_comb begin rx_pop_valid_o = '0; diff --git a/rtl/ip/util/async_fifo.sv b/rtl/ip/util/async_fifo.sv index 7180254c..77f5ddf5 100644 --- a/rtl/ip/util/async_fifo.sv +++ b/rtl/ip/util/async_fifo.sv @@ -25,86 +25,91 @@ module async_fifo #( output logic [ DepthPower:0] elem_num_o ); - localparam int FIFO_DEPTH = 2 ** DepthPower; - localparam int PTR_WIDTH = DepthPower + 1; // extra bit for empty/full check + localparam int signed FifoDepth = 2 ** DepthPower; + localparam int signed PtrWidth = DepthPower + 1; // extra bit for empty/full check - logic [DataWidth-1:0] r_mem[0:FIFO_DEPTH-1]; - logic [PTR_WIDTH-1:0] r_wr_ptr_bin, r_rd_ptr_bin; - logic [PTR_WIDTH-1:0] r_wr_ptr_gray, r_rd_ptr_gray; - logic [PTR_WIDTH-1:0] r_wr_ptr_gray_sync[0:1]; - logic [PTR_WIDTH-1:0] r_rd_ptr_gray_sync[0:1]; - logic [PTR_WIDTH-1:0] s_rd_ptr_bin_sync; + logic [DataWidth-1:0] s_mem[0:FifoDepth-1]; + logic [PtrWidth-1:0] s_wr_ptr_bin, s_rd_ptr_bin; + logic [PtrWidth-1:0] s_wr_ptr_gray, s_rd_ptr_gray; + logic [PtrWidth-1:0] s_wr_ptr_gray_sync[0:1]; + logic [PtrWidth-1:0] s_rd_ptr_gray_sync[0:1]; + logic [PtrWidth-1:0] s_rd_ptr_bin_sync; - // wr logic + // CDC storage: write-domain data is retained for the independent read domain. + // Resets are independently asserted in their respective domains; Gray pointers + // cross through two-flop synchronizers and the extra bounded index bit detects + // empty/full. These always_ff blocks preserve inferred dual-clock RAM, pointer, + // and synchronizer semantics and cannot be replaced by single-clock Common DFFs. + // Write-domain memory process. always_ff @(posedge wr_clk_i) begin if (wr_en_i && !wr_full_o) begin - r_mem[r_wr_ptr_bin[DepthPower-1:0]] <= wr_data_i; + s_mem[s_wr_ptr_bin[DepthPower-1:0]] <= wr_data_i; end end always_ff @(posedge wr_clk_i or negedge wr_rst_n_i) begin if (!wr_rst_n_i) begin - r_wr_ptr_bin <= '0; - r_wr_ptr_gray <= '0; + s_wr_ptr_bin <= '0; + s_wr_ptr_gray <= '0; end else if (wr_en_i && !wr_full_o) begin - r_wr_ptr_bin <= r_wr_ptr_bin + 1'b1; - r_wr_ptr_gray <= bin2gray(r_wr_ptr_bin + 1'b1); + s_wr_ptr_bin <= s_wr_ptr_bin + 1'b1; + s_wr_ptr_gray <= bin2gray(s_wr_ptr_bin + 1'b1); end end - // rd logic + // Read-domain memory and pointer processes. always_ff @(posedge rd_clk_i or negedge rd_rst_n_i) begin if (!rd_rst_n_i) begin rd_data_o <= '0; end else if (rd_en_i && !rd_empty_o) begin - rd_data_o <= r_mem[r_rd_ptr_bin[DepthPower-1:0]]; + rd_data_o <= s_mem[s_rd_ptr_bin[DepthPower-1:0]]; end end always_ff @(posedge rd_clk_i or negedge rd_rst_n_i) begin if (!rd_rst_n_i) begin - r_rd_ptr_bin <= '0; - r_rd_ptr_gray <= '0; + s_rd_ptr_bin <= '0; + s_rd_ptr_gray <= '0; end else if (rd_en_i && !rd_empty_o) begin - r_rd_ptr_bin <= r_rd_ptr_bin + 1'b1; - r_rd_ptr_gray <= bin2gray(r_rd_ptr_bin + 1'b1); + s_rd_ptr_bin <= s_rd_ptr_bin + 1'b1; + s_rd_ptr_gray <= bin2gray(s_rd_ptr_bin + 1'b1); end end always_ff @(posedge rd_clk_i or negedge rd_rst_n_i) begin if (!rd_rst_n_i) begin - r_wr_ptr_gray_sync[0] <= '0; - r_wr_ptr_gray_sync[1] <= '0; + s_wr_ptr_gray_sync[0] <= '0; + s_wr_ptr_gray_sync[1] <= '0; end else begin - r_wr_ptr_gray_sync[0] <= r_wr_ptr_gray; - r_wr_ptr_gray_sync[1] <= r_wr_ptr_gray_sync[0]; + s_wr_ptr_gray_sync[0] <= s_wr_ptr_gray; + s_wr_ptr_gray_sync[1] <= s_wr_ptr_gray_sync[0]; end end always_ff @(posedge wr_clk_i or negedge wr_rst_n_i) begin if (!wr_rst_n_i) begin - r_rd_ptr_gray_sync[0] <= '0; - r_rd_ptr_gray_sync[1] <= '0; + s_rd_ptr_gray_sync[0] <= '0; + s_rd_ptr_gray_sync[1] <= '0; end else begin - r_rd_ptr_gray_sync[0] <= r_rd_ptr_gray; - r_rd_ptr_gray_sync[1] <= r_rd_ptr_gray_sync[0]; + s_rd_ptr_gray_sync[0] <= s_rd_ptr_gray; + s_rd_ptr_gray_sync[1] <= s_rd_ptr_gray_sync[0]; end end - assign wr_full_o = r_wr_ptr_gray == {~r_rd_ptr_gray_sync[1][PTR_WIDTH-1:PTR_WIDTH-2], - r_rd_ptr_gray_sync[1][PTR_WIDTH-3:0]}; + assign wr_full_o = s_wr_ptr_gray == {~s_rd_ptr_gray_sync[1][PtrWidth-1:PtrWidth-2], + s_rd_ptr_gray_sync[1][PtrWidth-3:0]}; - assign rd_empty_o = r_rd_ptr_gray == r_wr_ptr_gray_sync[1]; + assign rd_empty_o = s_rd_ptr_gray == s_wr_ptr_gray_sync[1]; - assign elem_num_o = r_wr_ptr_bin - s_rd_ptr_bin_sync; + assign elem_num_o = s_wr_ptr_bin - s_rd_ptr_bin_sync; - function automatic logic [PTR_WIDTH-1:0] bin2gray(input logic [PTR_WIDTH-1:0] bin); + function automatic logic [PtrWidth-1:0] bin2gray(input logic [PtrWidth-1:0] bin); return (bin >> 1) ^ bin; endfunction gray2bin #( - .DATA_WIDTH(PTR_WIDTH) + .DATA_WIDTH(PtrWidth) ) u_gray2bin ( - .gray_i(r_rd_ptr_gray_sync[1]), + .gray_i(s_rd_ptr_gray_sync[1]), .bin_o (s_rd_ptr_bin_sync) ); diff --git a/rtl/mini/dv/sva/axi4_protocol_sva.sv b/rtl/mini/dv/sva/axi4_interconnect_sva.sv similarity index 92% rename from rtl/mini/dv/sva/axi4_protocol_sva.sv rename to rtl/mini/dv/sva/axi4_interconnect_sva.sv index 7260836f..dde18692 100644 --- a/rtl/mini/dv/sva/axi4_protocol_sva.sv +++ b/rtl/mini/dv/sva/axi4_interconnect_sva.sv @@ -55,11 +55,11 @@ bind axi4_interconnect axi4_interconnect_sva #( ) u_axi4_interconnect_sva ( .clk_i (clk_i), .rst_n_i (rst_n_i), - .master_state_i (r_master_state), - .master_target_i (r_master_target), - .target_valid_i (r_target_valid), - .target_addr_sent_i(r_target_addr_sent), - .target_owner_i (r_target_owner), + .master_state_i (s_master_state), + .master_target_i (s_master_target), + .target_valid_i (s_target_valid), + .target_addr_sent_i(s_target_addr_sent), + .target_owner_i (s_target_owner), .user_bus_enable_i (user_bus_enable_i), .user_awready_i (m_awready[1]), .user_arready_i (m_arready[1]) diff --git a/rtl/mini/filelist/ip.fl b/rtl/mini/filelist/ip.fl index 52c56f99..2e78eccb 100644 --- a/rtl/mini/filelist/ip.fl +++ b/rtl/mini/filelist/ip.fl @@ -1,7 +1,6 @@ /ip/memory/psram_core.sv -/ip/memory/psram.sv -/ip/memory/opipsram.sv -/ip/memory/opipsram_core.sv +/ip/memory/ribp_psram.sv +/ip/memory/ribp_opipsram.sv /ip/storage/spisd_init.sv /ip/storage/spisd_read.sv /ip/storage/spisd_write.sv @@ -9,8 +8,8 @@ /ip/storage/spisd_cache.sv /ip/storage/spisd_core.sv /ip/storage/spisd_data.sv -/ip/storage/spisd.sv -/ip/storage/sdio.sv +/ip/storage/ribp_spisd.sv +/ip/storage/ribp_sdio.sv /ip/serial/i2c_filter.sv /ip/serial/i2c_core.sv /ip/serial/i2c_reg.sv @@ -20,7 +19,7 @@ /ip/serial/i2s_recv.sv /ip/serial/i2s_send.sv /ip/serial/i2s_core.sv -/ip/serial/i2s.sv +/ip/serial/ribp_i2s.sv /ip/serial/ws2812_if.sv /ip/serial/ws2812_reg.sv /ip/serial/ws2812_core.sv @@ -37,11 +36,11 @@ /ip/storage/xpi_mm.sv /ip/storage/xpi_clkgen.sv /ip/storage/xpi_core.sv -/ip/storage/xpi.sv +/ip/storage/ribp_xpi.sv /ip/peripheral/dma_core.sv -/ip/peripheral/dma.sv +/ip/peripheral/ribp_dma.sv /ip/peripheral/pll_ctrl_if.sv -/ip/peripheral/sysctrl.sv +/ip/peripheral/ribp_sysctrl.sv /ip/peripheral/clint_if.sv /ip/peripheral/clint_timebase.sv /ip/peripheral/clint_reg.sv @@ -50,11 +49,11 @@ /ip/memory/sdram_clkgen.sv /ip/memory/sdram_reg.sv /ip/memory/sdram_core.sv -/ip/memory/sdram.sv +/ip/memory/axi4_sdram.sv /ip/multimedia/dvp_define.svh /ip/multimedia/dvp_core.sv /ip/multimedia/dvp_reg.sv -/ip/multimedia/dvp.sv +/ip/multimedia/axi4s_dvp.sv /ip/peripheral/timer_core.sv /ip/peripheral/timer_reg.sv /ip/peripheral/ribp_timer.sv diff --git a/rtl/mini/filelist/top.fl b/rtl/mini/filelist/top.fl index b6d9071b..77e7dfe8 100644 --- a/rtl/mini/filelist/top.fl +++ b/rtl/mini/filelist/top.fl @@ -22,15 +22,17 @@ /top/onchip_ram.sv /top/ip_ribp_wrapper.sv /top/ip_apb_wrapper.sv -/top/bus.sv +/top/rib_bus.sv +/top/axi4_bus.sv /top/rcu.sv +/top/pll_rcu_controller.sv /top/mgmt_debug_reset.sv /top/mgmt_debug_wrapper.sv /top/mgmt_core_wrapper.sv -/top/user_core_design_template.sv +/top/user_core_design.sv /top/user_core_top.sv /top/user_ip_design_template.sv /top/user_ip_top.sv /top/user_ip_wrapper.sv /sva/rib_protocol_sva.sv -/sva/axi4_protocol_sva.sv +/sva/axi4_interconnect_sva.sv diff --git a/rtl/mini/formal/generate_formal_filelist.py b/rtl/mini/formal/generate_formal_filelist.py index b6ff2c03..4412d077 100644 --- a/rtl/mini/formal/generate_formal_filelist.py +++ b/rtl/mini/formal/generate_formal_filelist.py @@ -43,7 +43,7 @@ def source_files(target: str) -> list[Path]: TOP / "rib2ribp.sv", TOP / "rib_error_slave.sv", TOP / "rib2ram.sv", - TOP / "bus.sv", + TOP / "rib_bus.sv", SCRIPT_DIR / "bus_formal.sv", ] if target == "rib_adapter": @@ -67,7 +67,7 @@ def source_files(target: str) -> list[Path]: *common, COMMON_RTL / "cdc/cdc_sync.sv", PERIPHERAL / "pll_ctrl_if.sv", - PERIPHERAL / "sysctrl.sv", + PERIPHERAL / "ribp_sysctrl.sv", SCRIPT_DIR / "sysctrl_formal.sv", ] if target == "pll_rcu": @@ -82,6 +82,7 @@ def source_files(target: str) -> list[Path]: PERIPHERAL / "pll_ctrl_if.sv", PERIPHERAL / "clint_timebase.sv", TOP / "rcu.sv", + TOP / "pll_rcu_controller.sv", SCRIPT_DIR / "pll_rcu_formal.sv", ] if target == "gpio": diff --git a/rtl/mini/integration/clock_reset_domains.json b/rtl/mini/integration/clock_reset_domains.json index 12db4cac..17b3ea9a 100644 --- a/rtl/mini/integration/clock_reset_domains.json +++ b/rtl/mini/integration/clock_reset_domains.json @@ -68,7 +68,7 @@ "reset": "s_dvp_pclk_rst_n_sync", "reset_source": "rst_n_i", "reset_primitive": "rst_sync", - "path": "rtl/ip/multimedia/dvp.sv", + "path": "rtl/ip/multimedia/axi4s_dvp.sv", "instance": "u_dvp_pclk_rst_sync", "sta": { "source_port": "gpio_10_io_pad", @@ -84,7 +84,7 @@ "source": "system", "destination": "external", "primitive": "cdc_2phase", - "path": "rtl/mini/top/rcu.sv", + "path": "rtl/mini/top/pll_rcu_controller.sv", "instance": "u_pll_request_cdc" }, { @@ -92,7 +92,7 @@ "source": "external", "destination": "system", "primitive": "cdc_2phase", - "path": "rtl/mini/top/rcu.sv", + "path": "rtl/mini/top/pll_rcu_controller.sv", "instance": "u_pll_response_cdc" }, { @@ -108,7 +108,7 @@ "source": "system", "destination": "dvp", "primitive": "cdc_2phase", - "path": "rtl/ip/multimedia/dvp.sv", + "path": "rtl/ip/multimedia/axi4s_dvp.sv", "instance": "u_dvp_config_cdc" }, { @@ -116,7 +116,7 @@ "source": "dvp", "destination": "system", "primitive": "cdc_fifo_warm_flush", - "path": "rtl/ip/multimedia/dvp.sv", + "path": "rtl/ip/multimedia/axi4s_dvp.sv", "instance": "u_dvp_payload_fifo" }, { @@ -172,7 +172,7 @@ "source": "audio", "destination": "system", "primitive": "cdc_sync", - "path": "rtl/ip/peripheral/sysctrl.sv", + "path": "rtl/ip/peripheral/ribp_sysctrl.sv", "instance": "u_rtc_wake_sync" }, { diff --git a/rtl/mini/mk/formal.mk b/rtl/mini/mk/formal.mk index fffa2914..9969399a 100644 --- a/rtl/mini/mk/formal.mk +++ b/rtl/mini/mk/formal.mk @@ -39,7 +39,7 @@ FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \ $(RTL_PATH)/formal/clint_formal_props.sv \ $(RTL_PATH)/formal/dvp_formal.sv \ $(RTL_PATH)/formal/dvp_formal_props.sv \ - $(RTL_PATH)/top/bus.sv \ + $(RTL_PATH)/top/rib_bus.sv \ $(RTL_PATH)/top/rib_error_slave.sv \ $(RTL_PATH)/top/rib_if.sv \ $(RTL_PATH)/top/rib2ram.sv \ @@ -53,7 +53,7 @@ FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \ $(ROOT_PATH)/rtl/ip/peripheral/gpio_reg.sv \ $(ROOT_PATH)/rtl/ip/peripheral/ribp_gpio.sv \ $(ROOT_PATH)/rtl/ip/peripheral/pll_ctrl_if.sv \ - $(ROOT_PATH)/rtl/ip/peripheral/sysctrl.sv \ + $(ROOT_PATH)/rtl/ip/peripheral/ribp_sysctrl.sv \ $(ROOT_PATH)/rtl/ip/serial/ws2812_if.sv \ $(ROOT_PATH)/rtl/ip/serial/ws2812_reg.sv \ $(ROOT_PATH)/rtl/ip/serial/ws2812_core.sv \ @@ -83,9 +83,10 @@ FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \ $(ROOT_PATH)/rtl/ip/multimedia/dvp_define.svh \ $(ROOT_PATH)/rtl/ip/multimedia/dvp_core.sv \ $(ROOT_PATH)/rtl/ip/multimedia/dvp_reg.sv \ - $(ROOT_PATH)/rtl/ip/multimedia/dvp.sv \ + $(ROOT_PATH)/rtl/ip/multimedia/axi4s_dvp.sv \ $(ROOT_PATH)/rtl/managed/clusterip/common/rtl/clkrst/counter.sv \ $(RTL_PATH)/top/rcu.sv \ + $(RTL_PATH)/top/pll_rcu_controller.sv \ $(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/ribp_if.sv \ $(ROOT_PATH)/rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv \ $(ROOT_PATH)/rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv \ diff --git a/rtl/mini/top/axi4_bus.sv b/rtl/mini/top/axi4_bus.sv new file mode 100644 index 00000000..346d325d --- /dev/null +++ b/rtl/mini/top/axi4_bus.sv @@ -0,0 +1,192 @@ +// Copyright (c) 2023-2026 Yuchi Miao +// retroSoC is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. + +module axi4_bus ( + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + axi4_if.slave mgmt_axi4, + axi4_if.slave user_axi4, + axi4_if.slave dma_axi4, + axi4_if.master cfg_axi4, + axi4_if.master apb_axi4, +`ifdef HAVE_SRAM_IF + ram_if.master ram, +`endif + axi4_if.master sdram_axi4, + axi4_if.master psram_axi4, + axi4_if.master xpi_axi4, + axi4_if.master spisd_axi4, + input logic user_bus_enable_i, + output logic user_bus_idle_o, + input logic perf_enable_i, + input logic perf_clear_i, + output logic fault_valid_o, + output logic [31:0] fault_addr_o, + output logic [3:0] fault_wstrb_o, + output logic fault_reserved_o, + output logic fault_access_o, + output logic [1:0] fault_master_o, + output logic [2:0] fault_code_o, + output logic [63:0] perf_mgmt_wait_o, + output logic [63:0] perf_user_wait_o, + output logic [63:0] perf_dma_wait_o, + output logic [63:0] perf_ribp_wait_o, + output logic [63:0] perf_apb_wait_o, + output logic [63:0] perf_sdram_wait_o, + output logic [63:0] perf_psram_wait_o, + output logic [63:0] perf_flash_wait_o + // verilog_format: on +); + localparam int NumMasters = 3; + localparam int NumTargets = 9; + + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_master_axi4_if[NumMasters] ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_target_axi4_if[NumTargets] ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_ram_axi4_if ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + + axi4_connector u_mgmt_connector ( + .source(mgmt_axi4), + .sink (u_master_axi4_if[0]) + ); + + axi4_connector u_user_connector ( + .source(user_axi4), + .sink (u_master_axi4_if[1]) + ); + + axi4_connector u_dma_connector ( + .source(dma_axi4), + .sink (u_master_axi4_if[2]) + ); + + axi4_connector u_cfg_connector ( + .source(u_target_axi4_if[0]), + .sink (cfg_axi4) + ); + + axi4_connector u_apb_connector ( + .source(u_target_axi4_if[1]), + .sink (apb_axi4) + ); + + axi4_connector u_ram_connector ( + .source(u_target_axi4_if[2]), + .sink (u_ram_axi4_if) + ); + + axi4_connector u_sdram_connector ( + .source(u_target_axi4_if[3]), + .sink (sdram_axi4) + ); + + axi4_connector u_psram_connector ( + .source(u_target_axi4_if[4]), + .sink (psram_axi4) + ); + + axi4_connector u_xpi_connector ( + .source(u_target_axi4_if[5]), + .sink (xpi_axi4) + ); + + axi4_connector u_spisd_connector ( + .source(u_target_axi4_if[6]), + .sink (spisd_axi4) + ); + + axi4_interconnect #( + .NumMasters(NumMasters), + .NumTargets(NumTargets) + ) u_axi4_interconnect ( + .clk_i (clk_i), + .rst_n_i (rst_n_i), + .masters (u_master_axi4_if), + .targets (u_target_axi4_if), + .user_bus_enable_i(user_bus_enable_i), + .user_bus_idle_o (user_bus_idle_o), + .perf_enable_i (perf_enable_i), + .perf_clear_i (perf_clear_i), + .fault_valid_o (fault_valid_o), + .fault_addr_o (fault_addr_o), + .fault_wstrb_o (fault_wstrb_o), + .fault_reserved_o (fault_reserved_o), + .fault_access_o (fault_access_o), + .fault_master_o (fault_master_o), + .fault_code_o (fault_code_o), + .perf_mgmt_wait_o (perf_mgmt_wait_o), + .perf_user_wait_o (perf_user_wait_o), + .perf_dma_wait_o (perf_dma_wait_o), + .perf_ribp_wait_o (perf_ribp_wait_o), + .perf_apb_wait_o (perf_apb_wait_o), + .perf_sdram_wait_o(perf_sdram_wait_o), + .perf_psram_wait_o(perf_psram_wait_o), + .perf_flash_wait_o(perf_flash_wait_o) + ); + +`ifdef HAVE_SRAM_IF + axi42ram u_axi42ram ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .axi4 (u_ram_axi4_if), + .ram (ram) + ); +`else + axi4_error_slave #( + .Response(2'b11) + ) u_ram_error_slave ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .axi4 (u_ram_axi4_if) + ); +`endif + + axi4_error_slave #( + .Response(2'b11) + ) u_decode_error_slave ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .axi4 (u_target_axi4_if[7]) + ); + + axi4_error_slave #( + .Response(2'b10) + ) u_slave_error_slave ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .axi4 (u_target_axi4_if[8]) + ); +endmodule diff --git a/rtl/mini/top/axi4_interconnect.sv b/rtl/mini/top/axi4_interconnect.sv index c25d2220..1690570b 100644 --- a/rtl/mini/top/axi4_interconnect.sv +++ b/rtl/mini/top/axi4_interconnect.sv @@ -111,23 +111,26 @@ module axi4_interconnect #( logic [NumTargets-1:0][ 31:0] t_rdata; logic [NumTargets-1:0][ 1:0] t_rresp; - logic [NumMasters-1:0][ 1:0] r_master_state; - logic [NumMasters-1:0] r_master_write; - logic [NumMasters-1:0][TARGET_WIDTH-1:0] r_master_target; - logic [NumMasters-1:0][ 31:0] r_master_addr; - logic [NumMasters-1:0][ 7:0] r_master_len; - logic [NumMasters-1:0][ 2:0] r_master_size; - logic [NumMasters-1:0][ 1:0] r_master_burst; - logic [NumMasters-1:0] r_master_lock; - logic [NumMasters-1:0][ 3:0] r_master_cache; - logic [NumMasters-1:0][ 2:0] r_master_prot; - logic [NumMasters-1:0][3:0] r_master_qos, r_master_region; - logic [NumMasters-1:0] r_master_id, r_master_user; - logic [NumMasters-1:0] r_master_access_err; - logic [NumMasters-1:0][3:0] r_master_first_wstrb; + // These arrays encode coupled master/target arbitration priorities. Their + // consolidated sequential process preserves the established update order. + // Convert them to Common registers only with sequential-equivalence proof. + logic [NumMasters-1:0][ 1:0] s_master_state; + logic [NumMasters-1:0] s_master_write; + logic [NumMasters-1:0][TARGET_WIDTH-1:0] s_master_target; + logic [NumMasters-1:0][ 31:0] s_master_addr; + logic [NumMasters-1:0][ 7:0] s_master_len; + logic [NumMasters-1:0][ 2:0] s_master_size; + logic [NumMasters-1:0][ 1:0] s_master_burst; + logic [NumMasters-1:0] s_master_lock; + logic [NumMasters-1:0][ 3:0] s_master_cache; + logic [NumMasters-1:0][ 2:0] s_master_prot; + logic [NumMasters-1:0][3:0] s_master_qos, s_master_region; + logic [NumMasters-1:0] s_master_id, s_master_user; + logic [NumMasters-1:0] s_master_access_err; + logic [NumMasters-1:0][3:0] s_master_first_wstrb; - logic [NumTargets-1:0] r_target_valid, r_target_addr_sent; - logic [NumTargets-1:0][MASTER_WIDTH-1:0] r_target_owner; + logic [NumTargets-1:0] s_target_valid, s_target_addr_sent; + logic [NumTargets-1:0][MASTER_WIDTH-1:0] s_target_owner; logic [NumTargets-1:0][ NumMasters-1:0] s_target_req; logic [NumTargets-1:0][ NumMasters-1:0] s_target_grant; logic [NumTargets-1:0][MASTER_WIDTH-1:0] s_target_selected; @@ -139,8 +142,8 @@ module axi4_interconnect #( logic [NumMasters-1:0] s_protocol_legal, s_access_allowed; logic [NumMasters-1:0][TARGET_WIDTH-1:0] s_capture_target; - logic [ 63:0] r_perf_master_wait[NumMasters]; - logic [ 63:0] r_perf_target_wait[NumTargets]; + logic [ 63:0] s_perf_master_wait[NumMasters]; + logic [ 63:0] s_perf_target_wait[NumTargets]; function automatic logic [TARGET_WIDTH-1:0] decode_target(input logic [31:0] addr); if (`SOC_ADDR_IS_SDRAM(addr)) return TARGET_SDRAM; @@ -153,7 +156,7 @@ module axi4_interconnect #( return TARGET_DECERR; endfunction - for (genvar master = 0; master < NumMasters; master++) begin : GEN_MASTER_PORTS + for (genvar master = 0; master < NumMasters; master++) begin : gen_master_ports assign m_awvalid[master] = masters[master].awvalid; assign m_awaddr[master] = masters[master].awaddr; assign m_awlen[master] = masters[master].awlen; @@ -200,7 +203,7 @@ module axi4_interconnect #( assign m_rready[master] = masters[master].rready; end - for (genvar target = 0; target < NumTargets; target++) begin : GEN_TARGET_PORTS + for (genvar target = 0; target < NumTargets; target++) begin : gen_target_ports assign targets[target].awid = t_awid[target]; assign targets[target].awaddr = t_awaddr[target]; assign targets[target].awlen = t_awlen[target]; @@ -312,7 +315,7 @@ module axi4_interconnect #( s_master_fault_code = '0; for (int master = 0; master < NumMasters; master++) begin - if (r_master_state[master] == MASTER_IDLE) begin + if (s_master_state[master] == MASTER_IDLE) begin m_arready[master] = (master != 1) || user_bus_enable_i; m_awready[master] = ((master != 1) || user_bus_enable_i) && !m_arvalid[master]; if ((m_arvalid[master] && m_arready[master]) || @@ -320,44 +323,44 @@ module axi4_interconnect #( s_target_req[s_capture_target[master]][master] = 1'b1; end end - if (r_master_state[master] == MASTER_PENDING) begin - s_target_req[r_master_target[master]][master] = 1'b1; + if (s_master_state[master] == MASTER_PENDING) begin + s_target_req[s_master_target[master]][master] = 1'b1; end end for (int target = 0; target < NumTargets; target++) begin - s_target_advance[target] = !r_target_valid[target] && s_target_grant_valid[target]; - if (r_target_valid[target]) begin - automatic logic [MASTER_WIDTH-1:0] owner = r_target_owner[target]; - if (!r_target_addr_sent[target]) begin - if (r_master_write[owner]) begin + s_target_advance[target] = !s_target_valid[target] && s_target_grant_valid[target]; + if (s_target_valid[target]) begin + automatic logic [MASTER_WIDTH-1:0] owner = s_target_owner[target]; + if (!s_target_addr_sent[target]) begin + if (s_master_write[owner]) begin t_awvalid[target] = 1'b1; - t_awaddr[target] = r_master_addr[owner]; - t_awlen[target] = r_master_len[owner]; - t_awsize[target] = r_master_size[owner]; - t_awburst[target] = r_master_burst[owner]; - t_awlock[target] = r_master_lock[owner]; - t_awcache[target] = r_master_cache[owner]; - t_awprot[target] = r_master_prot[owner]; - t_awqos[target] = r_master_qos[owner]; - t_awregion[target] = r_master_region[owner]; - t_awid[target] = r_master_id[owner]; - t_awuser[target] = r_master_user[owner]; + t_awaddr[target] = s_master_addr[owner]; + t_awlen[target] = s_master_len[owner]; + t_awsize[target] = s_master_size[owner]; + t_awburst[target] = s_master_burst[owner]; + t_awlock[target] = s_master_lock[owner]; + t_awcache[target] = s_master_cache[owner]; + t_awprot[target] = s_master_prot[owner]; + t_awqos[target] = s_master_qos[owner]; + t_awregion[target] = s_master_region[owner]; + t_awid[target] = s_master_id[owner]; + t_awuser[target] = s_master_user[owner]; end else begin t_arvalid[target] = 1'b1; - t_araddr[target] = r_master_addr[owner]; - t_arlen[target] = r_master_len[owner]; - t_arsize[target] = r_master_size[owner]; - t_arburst[target] = r_master_burst[owner]; - t_arlock[target] = r_master_lock[owner]; - t_arcache[target] = r_master_cache[owner]; - t_arprot[target] = r_master_prot[owner]; - t_arqos[target] = r_master_qos[owner]; - t_arregion[target] = r_master_region[owner]; - t_arid[target] = r_master_id[owner]; - t_aruser[target] = r_master_user[owner]; + t_araddr[target] = s_master_addr[owner]; + t_arlen[target] = s_master_len[owner]; + t_arsize[target] = s_master_size[owner]; + t_arburst[target] = s_master_burst[owner]; + t_arlock[target] = s_master_lock[owner]; + t_arcache[target] = s_master_cache[owner]; + t_arprot[target] = s_master_prot[owner]; + t_arqos[target] = s_master_qos[owner]; + t_arregion[target] = s_master_region[owner]; + t_arid[target] = s_master_id[owner]; + t_aruser[target] = s_master_user[owner]; end - end else if (r_master_write[owner]) begin + end else if (s_master_write[owner]) begin t_wvalid[target] = m_wvalid[owner]; t_wdata[target] = m_wdata[owner]; t_wstrb[target] = m_wstrb[owner]; @@ -382,13 +385,13 @@ module axi4_interconnect #( end if (s_target_terminal[target]) begin s_master_terminal[owner] = 1'b1; - if ((r_master_write[owner] && (t_bresp[target] != `AXI4_RESP_OKAY)) || - (!r_master_write[owner] && (t_rresp[target] != `AXI4_RESP_OKAY))) begin + if ((s_master_write[owner] && (t_bresp[target] != `AXI4_RESP_OKAY)) || + (!s_master_write[owner] && (t_rresp[target] != `AXI4_RESP_OKAY))) begin s_master_fault[owner] = 1'b1; s_master_fault_code[owner] = (TARGET_WIDTH'(target) == TARGET_DECERR) ? `RIB_RESP_DECERR : (TARGET_WIDTH'(target) == TARGET_SLVERR) ? - (r_master_access_err[owner] ? `RIB_RESP_PROTERR : `RIB_RESP_BURSTERR) : + (s_master_access_err[owner] ? `RIB_RESP_PROTERR : `RIB_RESP_BURSTERR) : `RIB_RESP_SLVERR; end end @@ -448,7 +451,7 @@ module axi4_interconnect #( end end - assign user_bus_idle_o = r_master_state[1] == MASTER_IDLE; + assign user_bus_idle_o = s_master_state[1] == MASTER_IDLE; always_comb begin fault_valid_o = 1'b0; @@ -461,10 +464,10 @@ module axi4_interconnect #( for (int master = NumMasters - 1; master >= 0; master--) begin if (s_master_fault[master]) begin fault_valid_o = 1'b1; - fault_addr_o = r_master_addr[master]; - fault_wstrb_o = r_master_first_wstrb[master]; - fault_reserved_o = `SOC_ADDR_IS_RESERVED(r_master_addr[master]); - fault_access_o = r_master_access_err[master]; + fault_addr_o = s_master_addr[master]; + fault_wstrb_o = s_master_first_wstrb[master]; + fault_reserved_o = `SOC_ADDR_IS_RESERVED(s_master_addr[master]); + fault_access_o = s_master_access_err[master]; fault_master_o = 2'(master); fault_code_o = s_master_fault_code[master]; end @@ -473,71 +476,71 @@ module axi4_interconnect #( always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - r_master_state <= '0; - r_master_write <= '0; - r_master_target <= '0; - r_master_addr <= '0; - r_master_len <= '0; - r_master_size <= '0; - r_master_burst <= '0; - r_master_lock <= '0; - r_master_cache <= '0; - r_master_prot <= '0; - r_master_qos <= '0; - r_master_region <= '0; - r_master_id <= '0; - r_master_user <= '0; - r_master_access_err <= '0; - r_master_first_wstrb <= '0; - r_target_valid <= '0; - r_target_addr_sent <= '0; - r_target_owner <= '0; + s_master_state <= '0; + s_master_write <= '0; + s_master_target <= '0; + s_master_addr <= '0; + s_master_len <= '0; + s_master_size <= '0; + s_master_burst <= '0; + s_master_lock <= '0; + s_master_cache <= '0; + s_master_prot <= '0; + s_master_qos <= '0; + s_master_region <= '0; + s_master_id <= '0; + s_master_user <= '0; + s_master_access_err <= '0; + s_master_first_wstrb <= '0; + s_target_valid <= '0; + s_target_addr_sent <= '0; + s_target_owner <= '0; end else begin for (int master = 0; master < NumMasters; master++) begin - if (r_master_state[master] == MASTER_IDLE && + if (s_master_state[master] == MASTER_IDLE && ((m_arvalid[master] && m_arready[master]) || (m_awvalid[master] && m_awready[master]))) begin automatic logic read_req = m_arvalid[master] && m_arready[master]; - r_master_state[master] <= MASTER_PENDING; - r_master_write[master] <= !read_req; - r_master_target[master] <= s_capture_target[master]; - r_master_addr[master] <= read_req ? m_araddr[master] : m_awaddr[master]; - r_master_len[master] <= read_req ? m_arlen[master] : m_awlen[master]; - r_master_size[master] <= read_req ? m_arsize[master] : m_awsize[master]; - r_master_burst[master] <= read_req ? m_arburst[master] : m_awburst[master]; - r_master_lock[master] <= read_req ? m_arlock[master] : m_awlock[master]; - r_master_cache[master] <= read_req ? m_arcache[master] : m_awcache[master]; - r_master_prot[master] <= read_req ? m_arprot[master] : m_awprot[master]; - r_master_qos[master] <= read_req ? m_arqos[master] : m_awqos[master]; - r_master_region[master] <= read_req ? m_arregion[master] : m_awregion[master]; - r_master_id[master] <= read_req ? m_arid[master] : m_awid[master]; - r_master_user[master] <= read_req ? m_aruser[master] : m_awuser[master]; - r_master_access_err[master] <= !s_access_allowed[master]; - r_master_first_wstrb[master] <= '0; + s_master_state[master] <= MASTER_PENDING; + s_master_write[master] <= !read_req; + s_master_target[master] <= s_capture_target[master]; + s_master_addr[master] <= read_req ? m_araddr[master] : m_awaddr[master]; + s_master_len[master] <= read_req ? m_arlen[master] : m_awlen[master]; + s_master_size[master] <= read_req ? m_arsize[master] : m_awsize[master]; + s_master_burst[master] <= read_req ? m_arburst[master] : m_awburst[master]; + s_master_lock[master] <= read_req ? m_arlock[master] : m_awlock[master]; + s_master_cache[master] <= read_req ? m_arcache[master] : m_awcache[master]; + s_master_prot[master] <= read_req ? m_arprot[master] : m_awprot[master]; + s_master_qos[master] <= read_req ? m_arqos[master] : m_awqos[master]; + s_master_region[master] <= read_req ? m_arregion[master] : m_awregion[master]; + s_master_id[master] <= read_req ? m_arid[master] : m_awid[master]; + s_master_user[master] <= read_req ? m_aruser[master] : m_awuser[master]; + s_master_access_err[master] <= !s_access_allowed[master]; + s_master_first_wstrb[master] <= '0; end - if ((r_master_state[master] == MASTER_ACTIVE) && r_master_write[master] && - m_wvalid[master] && m_wready[master] && (r_master_first_wstrb[master] == '0)) begin - r_master_first_wstrb[master] <= m_wstrb[master]; + if ((s_master_state[master] == MASTER_ACTIVE) && s_master_write[master] && + m_wvalid[master] && m_wready[master] && (s_master_first_wstrb[master] == '0)) begin + s_master_first_wstrb[master] <= m_wstrb[master]; end - if (s_master_terminal[master]) r_master_state[master] <= MASTER_IDLE; + if (s_master_terminal[master]) s_master_state[master] <= MASTER_IDLE; end for (int target = 0; target < NumTargets; target++) begin - if (!r_target_valid[target] && s_target_grant_valid[target]) begin - r_target_valid[target] <= 1'b1; - r_target_addr_sent[target] <= 1'b0; - r_target_owner[target] <= s_target_selected[target]; - r_master_state[s_target_selected[target]] <= MASTER_ACTIVE; - end else if (r_target_valid[target] && !r_target_addr_sent[target]) begin - automatic logic [MASTER_WIDTH-1:0] owner = r_target_owner[target]; - if ((r_master_write[owner] && t_awvalid[target] && t_awready[target]) || - (!r_master_write[owner] && t_arvalid[target] && t_arready[target])) begin - r_target_addr_sent[target] <= 1'b1; + if (!s_target_valid[target] && s_target_grant_valid[target]) begin + s_target_valid[target] <= 1'b1; + s_target_addr_sent[target] <= 1'b0; + s_target_owner[target] <= s_target_selected[target]; + s_master_state[s_target_selected[target]] <= MASTER_ACTIVE; + end else if (s_target_valid[target] && !s_target_addr_sent[target]) begin + automatic logic [MASTER_WIDTH-1:0] owner = s_target_owner[target]; + if ((s_master_write[owner] && t_awvalid[target] && t_awready[target]) || + (!s_master_write[owner] && t_arvalid[target] && t_arready[target])) begin + s_target_addr_sent[target] <= 1'b1; end end if (s_target_terminal[target]) begin - r_target_valid[target] <= 1'b0; - r_target_addr_sent[target] <= 1'b0; + s_target_valid[target] <= 1'b0; + s_target_addr_sent[target] <= 1'b0; end end end @@ -545,39 +548,41 @@ module axi4_interconnect #( always_ff @(posedge clk_i or negedge rst_n_i) begin if (!rst_n_i) begin - for (int master = 0; master < NumMasters; master++) r_perf_master_wait[master] <= '0; - for (int target = 0; target < NumTargets; target++) r_perf_target_wait[target] <= '0; + for (int master = 0; master < NumMasters; master++) s_perf_master_wait[master] <= '0; + for (int target = 0; target < NumTargets; target++) s_perf_target_wait[target] <= '0; end else if (perf_clear_i) begin - for (int master = 0; master < NumMasters; master++) r_perf_master_wait[master] <= '0; - for (int target = 0; target < NumTargets; target++) r_perf_target_wait[target] <= '0; + for (int master = 0; master < NumMasters; master++) s_perf_master_wait[master] <= '0; + for (int target = 0; target < NumTargets; target++) s_perf_target_wait[target] <= '0; end else if (perf_enable_i) begin for (int master = 0; master < NumMasters; master++) begin - if ((r_master_state[master] != MASTER_IDLE) && !s_master_terminal[master] && - !(&r_perf_master_wait[master])) begin - r_perf_master_wait[master] <= r_perf_master_wait[master] + 1'b1; + if ((s_master_state[master] != MASTER_IDLE) && !s_master_terminal[master] && + !(&s_perf_master_wait[master])) begin + s_perf_master_wait[master] <= s_perf_master_wait[master] + 1'b1; end end for (int target = 0; target < NumTargets; target++) begin - if (r_target_valid[target] && !s_target_terminal[target] && - !(&r_perf_target_wait[target])) begin - r_perf_target_wait[target] <= r_perf_target_wait[target] + 1'b1; + if (s_target_valid[target] && !s_target_terminal[target] && + !(&s_perf_target_wait[target])) begin + s_perf_target_wait[target] <= s_perf_target_wait[target] + 1'b1; end end end end - assign perf_mgmt_wait_o = r_perf_master_wait[0]; - assign perf_user_wait_o = r_perf_master_wait[1]; - assign perf_dma_wait_o = r_perf_master_wait[2]; - assign perf_ribp_wait_o = r_perf_target_wait[TARGET_CFG]; - assign perf_apb_wait_o = r_perf_target_wait[TARGET_APB]; - assign perf_sdram_wait_o = r_perf_target_wait[TARGET_SDRAM]; - assign perf_psram_wait_o = r_perf_target_wait[TARGET_PSRAM]; - assign perf_flash_wait_o = r_perf_target_wait[TARGET_XPI]; + assign perf_mgmt_wait_o = s_perf_master_wait[0]; + assign perf_user_wait_o = s_perf_master_wait[1]; + assign perf_dma_wait_o = s_perf_master_wait[2]; + assign perf_ribp_wait_o = s_perf_target_wait[TARGET_CFG]; + assign perf_apb_wait_o = s_perf_target_wait[TARGET_APB]; + assign perf_sdram_wait_o = s_perf_target_wait[TARGET_SDRAM]; + assign perf_psram_wait_o = s_perf_target_wait[TARGET_PSRAM]; + assign perf_flash_wait_o = s_perf_target_wait[TARGET_XPI]; +`ifndef SYNTHESIS initial begin if (NumMasters != 3 || NumTargets != 9) begin $fatal(1, "axi4_interconnect: retroSoC topology requires three masters and nine targets"); end end +`endif endmodule diff --git a/rtl/mini/top/core_wrapper.sv b/rtl/mini/top/core_wrapper.sv index 1357a07d..9d88947b 100644 --- a/rtl/mini/top/core_wrapper.sv +++ b/rtl/mini/top/core_wrapper.sv @@ -9,17 +9,17 @@ // See the Mulan PSL v2 for more details. module core_wrapper ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic [31:0] irq_i, - input logic jtag_tck_i, - input logic jtag_tms_i, - input logic jtag_tdi_i, - input logic jtag_trst_n_i, - output logic jtag_tdo_o, - output logic debug_halted_o, - axi4_if.master axi4 + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic [31:0] irq_i, + input logic jtag_tck_i, + input logic jtag_tms_i, + input logic jtag_tdi_i, + input logic jtag_trst_n_i, + output logic jtag_tdo_o, + output logic debug_halted_o, + axi4_if.master axi4 // verilog_format: on ); diff --git a/rtl/mini/top/ip_apb_wrapper.sv b/rtl/mini/top/ip_apb_wrapper.sv index 9ea3d846..a01d1976 100644 --- a/rtl/mini/top/ip_apb_wrapper.sv +++ b/rtl/mini/top/ip_apb_wrapper.sv @@ -16,7 +16,7 @@ `include "archinfo_integration_metadata.svh" module ip_apb_wrapper ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic clk_aud_i, @@ -98,7 +98,7 @@ module ip_apb_wrapper ( ); `include "soc_apb_bridges.svh" - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment apb4_archinfo #( .VENDOR_ID (32'h0000_0000), .SOC_REVISION (32'h0001_0000), diff --git a/rtl/mini/top/ip_ribp_wrapper.sv b/rtl/mini/top/ip_ribp_wrapper.sv index 8c5350e8..1543847d 100644 --- a/rtl/mini/top/ip_ribp_wrapper.sv +++ b/rtl/mini/top/ip_ribp_wrapper.sv @@ -13,43 +13,43 @@ `include "rib_defs.svh" module ip_ribp_wrapper ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic clk_aud_i, - input logic rst_aud_n_i, - input logic debug_halted_i, - input logic timebase_tick_i, - axi4_if.slave cfg_axi4, - axi4_if.slave psram_axi4, - axi4_if.slave xpi_axi4, - axi4_if.slave spisd_axi4, - gpio_if.dut gpio, - user_gpio_if.padctrl user_gpio, - uart_if.dut uart, - psram_if.dut psram, - spi_if.dut spisd, - i2c_if.dut i2c0, - i2s_if.dut i2s, - ws2812_if.dut ws2812, - xpi_if.dut xpi, - axi4_if.master dma_axi4, - sysctrl_if.dut sysctrl, - pll_ctrl_if.sysctrl pll_ctrl, - ribp_if.master sdram_cfg_ribp, - dvp_if.dut dvp, - sdio_if.dut sdio, - opipsram_if.dut opipsram, - i2c_if.dut i2c1, - input logic fault_valid_i, - input logic [31:0] fault_addr_i, - input logic [3:0] fault_wstrb_i, - input logic fault_reserved_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic clk_aud_i, + input logic rst_aud_n_i, + input logic debug_halted_i, + input logic timebase_tick_i, + axi4_if.slave cfg_axi4, + axi4_if.slave psram_axi4, + axi4_if.slave xpi_axi4, + axi4_if.slave spisd_axi4, + gpio_if.dut gpio, + user_gpio_if.padctrl user_gpio, + uart_if.dut uart, + psram_if.dut psram, + spi_if.dut spisd, + i2c_if.dut i2c0, + i2s_if.dut i2s, + ws2812_if.dut ws2812, + xpi_if.dut xpi, + axi4_if.master dma_axi4, + sysctrl_if.dut sysctrl, + pll_ctrl_if.sysctrl pll_ctrl, + ribp_if.master sdram_cfg_ribp, + dvp_if.dut dvp, + sdio_if.dut sdio, + opipsram_if.dut opipsram, + i2c_if.dut i2c1, + input logic fault_valid_i, + input logic [31:0] fault_addr_i, + input logic [3:0] fault_wstrb_i, + input logic fault_reserved_i, output logic [`SOC_IRQ_RIBP_WIDTH-1:0] irq_o // verilog_format: on ); - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment // Generated RIBP target declarations preserve scalar-interface compatibility. `include "ribp_interfaces.svh" @@ -175,7 +175,7 @@ module ip_ribp_wrapper ( // Uses ClusterIP common ribp_if and register.sv dffr through generated bindings. `include "ribp_routes.svh" - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment // Generated IRQ ownership and core-vector bit assignments are topology checked. `include "ribp_irq_bindings.svh" diff --git a/rtl/mini/top/mgmt_core_wrapper.sv b/rtl/mini/top/mgmt_core_wrapper.sv index 604ad015..1b6ca31f 100644 --- a/rtl/mini/top/mgmt_core_wrapper.sv +++ b/rtl/mini/top/mgmt_core_wrapper.sv @@ -11,7 +11,7 @@ `include "mmap_define.svh" module mgmt_core_wrapper ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic [31:0] irq_i, @@ -51,7 +51,7 @@ module mgmt_core_wrapper ( logic [31:0] s_dbg_sbus_rdata; assign debug_halted_o = s_dbg_halted; - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment ahbl_if u_ahbl_if ( .hclk(clk_i), .hresetn(s_core_rst_n) diff --git a/rtl/mini/top/onchip_ram.sv b/rtl/mini/top/onchip_ram.sv index dc19bc53..f6384138 100644 --- a/rtl/mini/top/onchip_ram.sv +++ b/rtl/mini/top/onchip_ram.sv @@ -10,7 +10,7 @@ // 32x4KB=128KB module onchip_ram ( - // verilog_format: off + // verilog_format: off -- preserve aligned port declarations input logic clk_i, ram_if.slave ram // verilog_format: on @@ -19,39 +19,39 @@ module onchip_ram ( logic s_cs [31:0]; logic [31:0] s_rdata[0:31]; - // verilog_format: off - assign s_cs[0] = ~ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] & ~ram.addr[11] && ~ram.addr[10]; - assign s_cs[1] = ~ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] & ~ram.addr[11] && ram.addr[10]; - assign s_cs[2] = ~ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] & ram.addr[11] && ~ram.addr[10]; - assign s_cs[3] = ~ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] & ram.addr[11] && ram.addr[10]; - assign s_cs[4] = ~ram.addr[14] && ~ram.addr[13] && ram.addr[12] & ~ram.addr[11] && ~ram.addr[10]; - assign s_cs[5] = ~ram.addr[14] && ~ram.addr[13] && ram.addr[12] & ~ram.addr[11] && ram.addr[10]; - assign s_cs[6] = ~ram.addr[14] && ~ram.addr[13] && ram.addr[12] & ram.addr[11] && ~ram.addr[10]; - assign s_cs[7] = ~ram.addr[14] && ~ram.addr[13] && ram.addr[12] & ram.addr[11] && ram.addr[10]; - assign s_cs[8] = ~ram.addr[14] && ram.addr[13] && ~ram.addr[12] & ~ram.addr[11] && ~ram.addr[10]; - assign s_cs[9] = ~ram.addr[14] && ram.addr[13] && ~ram.addr[12] & ~ram.addr[11] && ram.addr[10]; - assign s_cs[10] = ~ram.addr[14] && ram.addr[13] && ~ram.addr[12] & ram.addr[11] && ~ram.addr[10]; - assign s_cs[11] = ~ram.addr[14] && ram.addr[13] && ~ram.addr[12] & ram.addr[11] && ram.addr[10]; - assign s_cs[12] = ~ram.addr[14] && ram.addr[13] && ram.addr[12] & ~ram.addr[11] && ~ram.addr[10]; - assign s_cs[13] = ~ram.addr[14] && ram.addr[13] && ram.addr[12] & ~ram.addr[11] && ram.addr[10]; - assign s_cs[14] = ~ram.addr[14] && ram.addr[13] && ram.addr[12] & ram.addr[11] && ~ram.addr[10]; - assign s_cs[15] = ~ram.addr[14] && ram.addr[13] && ram.addr[12] & ram.addr[11] && ram.addr[10]; - assign s_cs[16] = ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] & ~ram.addr[11] && ~ram.addr[10]; - assign s_cs[17] = ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] & ~ram.addr[11] && ram.addr[10]; - assign s_cs[18] = ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] & ram.addr[11] && ~ram.addr[10]; - assign s_cs[19] = ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] & ram.addr[11] && ram.addr[10]; - assign s_cs[20] = ram.addr[14] && ~ram.addr[13] && ram.addr[12] & ~ram.addr[11] && ~ram.addr[10]; - assign s_cs[21] = ram.addr[14] && ~ram.addr[13] && ram.addr[12] & ~ram.addr[11] && ram.addr[10]; - assign s_cs[22] = ram.addr[14] && ~ram.addr[13] && ram.addr[12] & ram.addr[11] && ~ram.addr[10]; - assign s_cs[23] = ram.addr[14] && ~ram.addr[13] && ram.addr[12] & ram.addr[11] && ram.addr[10]; - assign s_cs[24] = ram.addr[14] && ram.addr[13] && ~ram.addr[12] & ~ram.addr[11] && ~ram.addr[10]; - assign s_cs[25] = ram.addr[14] && ram.addr[13] && ~ram.addr[12] & ~ram.addr[11] && ram.addr[10]; - assign s_cs[26] = ram.addr[14] && ram.addr[13] && ~ram.addr[12] & ram.addr[11] && ~ram.addr[10]; - assign s_cs[27] = ram.addr[14] && ram.addr[13] && ~ram.addr[12] & ram.addr[11] && ram.addr[10]; - assign s_cs[28] = ram.addr[14] && ram.addr[13] && ram.addr[12] & ~ram.addr[11] && ~ram.addr[10]; - assign s_cs[29] = ram.addr[14] && ram.addr[13] && ram.addr[12] & ~ram.addr[11] && ram.addr[10]; - assign s_cs[30] = ram.addr[14] && ram.addr[13] && ram.addr[12] & ram.addr[11] && ~ram.addr[10]; - assign s_cs[31] = ram.addr[14] && ram.addr[13] && ram.addr[12] & ram.addr[11] && ram.addr[10]; + // verilog_format: off -- preserve aligned bank decode + assign s_cs[0] = ~ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] && ~ram.addr[11] && ~ram.addr[10]; + assign s_cs[1] = ~ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] && ~ram.addr[11] && ram.addr[10]; + assign s_cs[2] = ~ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] && ram.addr[11] && ~ram.addr[10]; + assign s_cs[3] = ~ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] && ram.addr[11] && ram.addr[10]; + assign s_cs[4] = ~ram.addr[14] && ~ram.addr[13] && ram.addr[12] && ~ram.addr[11] && ~ram.addr[10]; + assign s_cs[5] = ~ram.addr[14] && ~ram.addr[13] && ram.addr[12] && ~ram.addr[11] && ram.addr[10]; + assign s_cs[6] = ~ram.addr[14] && ~ram.addr[13] && ram.addr[12] && ram.addr[11] && ~ram.addr[10]; + assign s_cs[7] = ~ram.addr[14] && ~ram.addr[13] && ram.addr[12] && ram.addr[11] && ram.addr[10]; + assign s_cs[8] = ~ram.addr[14] && ram.addr[13] && ~ram.addr[12] && ~ram.addr[11] && ~ram.addr[10]; + assign s_cs[9] = ~ram.addr[14] && ram.addr[13] && ~ram.addr[12] && ~ram.addr[11] && ram.addr[10]; + assign s_cs[10] = ~ram.addr[14] && ram.addr[13] && ~ram.addr[12] && ram.addr[11] && ~ram.addr[10]; + assign s_cs[11] = ~ram.addr[14] && ram.addr[13] && ~ram.addr[12] && ram.addr[11] && ram.addr[10]; + assign s_cs[12] = ~ram.addr[14] && ram.addr[13] && ram.addr[12] && ~ram.addr[11] && ~ram.addr[10]; + assign s_cs[13] = ~ram.addr[14] && ram.addr[13] && ram.addr[12] && ~ram.addr[11] && ram.addr[10]; + assign s_cs[14] = ~ram.addr[14] && ram.addr[13] && ram.addr[12] && ram.addr[11] && ~ram.addr[10]; + assign s_cs[15] = ~ram.addr[14] && ram.addr[13] && ram.addr[12] && ram.addr[11] && ram.addr[10]; + assign s_cs[16] = ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] && ~ram.addr[11] && ~ram.addr[10]; + assign s_cs[17] = ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] && ~ram.addr[11] && ram.addr[10]; + assign s_cs[18] = ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] && ram.addr[11] && ~ram.addr[10]; + assign s_cs[19] = ram.addr[14] && ~ram.addr[13] && ~ram.addr[12] && ram.addr[11] && ram.addr[10]; + assign s_cs[20] = ram.addr[14] && ~ram.addr[13] && ram.addr[12] && ~ram.addr[11] && ~ram.addr[10]; + assign s_cs[21] = ram.addr[14] && ~ram.addr[13] && ram.addr[12] && ~ram.addr[11] && ram.addr[10]; + assign s_cs[22] = ram.addr[14] && ~ram.addr[13] && ram.addr[12] && ram.addr[11] && ~ram.addr[10]; + assign s_cs[23] = ram.addr[14] && ~ram.addr[13] && ram.addr[12] && ram.addr[11] && ram.addr[10]; + assign s_cs[24] = ram.addr[14] && ram.addr[13] && ~ram.addr[12] && ~ram.addr[11] && ~ram.addr[10]; + assign s_cs[25] = ram.addr[14] && ram.addr[13] && ~ram.addr[12] && ~ram.addr[11] && ram.addr[10]; + assign s_cs[26] = ram.addr[14] && ram.addr[13] && ~ram.addr[12] && ram.addr[11] && ~ram.addr[10]; + assign s_cs[27] = ram.addr[14] && ram.addr[13] && ~ram.addr[12] && ram.addr[11] && ram.addr[10]; + assign s_cs[28] = ram.addr[14] && ram.addr[13] && ram.addr[12] && ~ram.addr[11] && ~ram.addr[10]; + assign s_cs[29] = ram.addr[14] && ram.addr[13] && ram.addr[12] && ~ram.addr[11] && ram.addr[10]; + assign s_cs[30] = ram.addr[14] && ram.addr[13] && ram.addr[12] && ram.addr[11] && ~ram.addr[10]; + assign s_cs[31] = ram.addr[14] && ram.addr[13] && ram.addr[12] && ram.addr[11] && ram.addr[10]; assign ram.rdata = s_rdata[ram.addr[14:10]]; // verilog_format: on diff --git a/rtl/mini/top/pll_rcu_controller.sv b/rtl/mini/top/pll_rcu_controller.sv new file mode 100644 index 00000000..6a09d812 --- /dev/null +++ b/rtl/mini/top/pll_rcu_controller.sv @@ -0,0 +1,274 @@ +// Copyright (c) 2023-2026 Yuchi Miao +// retroSoC is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. + +module pll_rcu_controller #( + parameter int LockTimeout = 1024 +) ( + // verilog_format: off -- preserve aligned port declarations + input logic sys_clk_i, + input logic sys_rst_n_i, + input logic ext_clk_i, + input logic ext_rst_n_i, + input logic pll_lock_i, + input logic pll_capable_i, + output logic [2:0] pll_sel_o, + output logic pll_apply_o, + output logic select_ext_clk_o, + pll_ctrl_if.rcu pll_ctrl + // verilog_format: on +); + localparam logic [2:0] PLL_IDLE = 3'd0; + localparam logic [2:0] PLL_SAFE = 3'd1; + localparam logic [2:0] PLL_APPLY = 3'd2; + localparam logic [2:0] PLL_WAIT_LOCK = 3'd3; + localparam logic [2:0] PLL_SWITCH = 3'd4; + localparam logic [2:0] PLL_RESPOND = 3'd5; + + logic [2:0] s_req_sel; + logic s_req_valid, s_req_ready; + logic [7:0] s_rsp_data; + logic s_rsp_valid, s_rsp_ready; + logic [7:0] s_rsp_sys_data; + logic s_rsp_sys_valid; + logic [2:0] s_state_d, s_state_q; + logic [2:0] s_pll_sel_d, s_pll_sel_q; + logic s_pll_apply_d, s_pll_apply_q; + logic s_sel_ext_clk_d, s_sel_ext_clk_q; + logic [15:0] s_lock_count_d, s_lock_count_q; + logic [2:0] s_active_sel_d, s_active_sel_q; + logic s_active_valid_d, s_active_valid_q; + logic s_safe_clk_d, s_safe_clk_q; + logic s_lock_d, s_lock_q; + logic s_lock_seen_low_d, s_lock_seen_low_q; + logic [1:0] s_err_d, s_err_q; + logic s_rsp_valid_d, s_rsp_valid_q; + + cdc_2phase #( + .DATA_WIDTH(3) + ) u_pll_request_cdc ( + .src_clk_i (sys_clk_i), + .src_rst_n_i(sys_rst_n_i), + .src_data_i (pll_ctrl.req_sel_o), + .src_valid_i(pll_ctrl.req_valid_o), + .src_ready_o(pll_ctrl.req_ready_i), + .dst_clk_i (ext_clk_i), + .dst_rst_n_i(ext_rst_n_i), + .dst_data_o (s_req_sel), + .dst_valid_o(s_req_valid), + .dst_ready_i(s_req_ready) + ); + cdc_2phase #( + .DATA_WIDTH(8) + ) u_pll_response_cdc ( + .src_clk_i (ext_clk_i), + .src_rst_n_i(ext_rst_n_i), + .src_data_i (s_rsp_data), + .src_valid_i(s_rsp_valid_q), + .src_ready_o(s_rsp_ready), + .dst_clk_i (sys_clk_i), + .dst_rst_n_i(sys_rst_n_i), + .dst_data_o (s_rsp_sys_data), + .dst_valid_o(s_rsp_sys_valid), + .dst_ready_i(pll_ctrl.rsp_ready_o) + ); + + assign pll_ctrl.rsp_active_sel_i = s_rsp_sys_data[2:0]; + assign pll_ctrl.rsp_active_valid_i = s_rsp_sys_data[3]; + assign pll_ctrl.rsp_safe_clk_i = s_rsp_sys_data[4]; + assign pll_ctrl.rsp_pll_lock_i = s_rsp_sys_data[5]; + assign pll_ctrl.rsp_error_i = s_rsp_sys_data[7:6]; + assign pll_ctrl.rsp_valid_i = s_rsp_sys_valid; + assign pll_ctrl.capable_i = pll_capable_i; + assign s_req_ready = s_state_q == PLL_IDLE; + assign s_rsp_data = {s_err_q, s_lock_q, s_safe_clk_q, s_active_valid_q, s_active_sel_q}; + assign pll_sel_o = s_pll_sel_q; + assign pll_apply_o = s_pll_apply_q; + assign select_ext_clk_o = s_sel_ext_clk_q; + + always_comb begin + s_state_d = s_state_q; + s_pll_sel_d = s_pll_sel_q; + s_pll_apply_d = (s_state_q == PLL_APPLY) || (s_state_q == PLL_WAIT_LOCK); + s_sel_ext_clk_d = s_sel_ext_clk_q; + s_lock_count_d = s_lock_count_q; + s_active_sel_d = s_active_sel_q; + s_active_valid_d = s_active_valid_q; + s_safe_clk_d = s_safe_clk_q; + s_lock_d = s_lock_q; + s_lock_seen_low_d = s_lock_seen_low_q; + s_err_d = s_err_q; + s_rsp_valid_d = s_rsp_valid_q; + + unique case (s_state_q) + PLL_IDLE: begin + s_lock_seen_low_d = 1'b0; + if (s_req_valid) begin + s_pll_sel_d = s_req_sel; + s_sel_ext_clk_d = 1'b1; + s_err_d = 2'd0; + s_state_d = PLL_SAFE; + end + end + PLL_SAFE: begin + s_lock_seen_low_d = 1'b0; + s_sel_ext_clk_d = 1'b1; + s_safe_clk_d = 1'b1; + s_lock_d = 1'b0; + if (pll_capable_i) begin + s_state_d = PLL_APPLY; + end else begin + s_active_valid_d = 1'b0; + s_err_d = 2'd1; + s_state_d = PLL_RESPOND; + end + end + PLL_APPLY: begin + s_lock_count_d = '0; + s_lock_seen_low_d = 1'b0; + s_state_d = PLL_WAIT_LOCK; + end + PLL_WAIT_LOCK: begin + if (!pll_lock_i) begin + s_lock_seen_low_d = 1'b1; + end + if (s_lock_seen_low_q && pll_lock_i) begin + s_active_sel_d = s_pll_sel_q; + s_active_valid_d = 1'b1; + s_safe_clk_d = 1'b0; + s_lock_d = 1'b1; + s_err_d = 2'd0; + s_state_d = PLL_SWITCH; + end else if (s_lock_count_q == LockTimeout - 1) begin + s_active_valid_d = 1'b0; + s_safe_clk_d = 1'b1; + s_lock_d = 1'b0; + s_err_d = 2'd2; + s_state_d = PLL_RESPOND; + end else begin + s_lock_count_d = s_lock_count_q + 1'b1; + end + end + PLL_SWITCH: begin + s_sel_ext_clk_d = 1'b0; + s_state_d = PLL_RESPOND; + end + PLL_RESPOND: begin + s_rsp_valid_d = 1'b1; + if (s_rsp_valid_q && s_rsp_ready) begin + s_rsp_valid_d = 1'b0; + s_state_d = PLL_IDLE; + end + end + default: begin + s_state_d = PLL_IDLE; + end + endcase + end + + dffrc #( + .DATA_WIDTH(3), + .RESET_VAL (PLL_IDLE) + ) u_state_dffrc ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_state_d), + .dat_o (s_state_q) + ); + dffr #( + .DATA_WIDTH(3) + ) u_pll_sel_dffr ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_pll_sel_d), + .dat_o (s_pll_sel_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_pll_apply_dffr ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_pll_apply_d), + .dat_o (s_pll_apply_q) + ); + dffrc #( + .DATA_WIDTH(1), + .RESET_VAL (1'b1) + ) u_select_ext_clk_dffrc ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_sel_ext_clk_d), + .dat_o (s_sel_ext_clk_q) + ); + dffr #( + .DATA_WIDTH(16) + ) u_lock_count_dffr ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_lock_count_d), + .dat_o (s_lock_count_q) + ); + dffr #( + .DATA_WIDTH(3) + ) u_active_sel_dffr ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_active_sel_d), + .dat_o (s_active_sel_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_active_valid_dffr ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_active_valid_d), + .dat_o (s_active_valid_q) + ); + dffrc #( + .DATA_WIDTH(1), + .RESET_VAL (1'b1) + ) u_safe_clk_dffrc ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_safe_clk_d), + .dat_o (s_safe_clk_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_lock_dffr ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_lock_d), + .dat_o (s_lock_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_lock_seen_low_dffr ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_lock_seen_low_d), + .dat_o (s_lock_seen_low_q) + ); + dffr #( + .DATA_WIDTH(2) + ) u_error_dffr ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_err_d), + .dat_o (s_err_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_rsp_valid_dffr ( + .clk_i (ext_clk_i), + .rst_n_i(ext_rst_n_i), + .dat_i (s_rsp_valid_d), + .dat_o (s_rsp_valid_q) + ); +endmodule diff --git a/rtl/mini/top/rcu.sv b/rtl/mini/top/rcu.sv index fc6461bd..06d90e64 100644 --- a/rtl/mini/top/rcu.sv +++ b/rtl/mini/top/rcu.sv @@ -224,266 +224,3 @@ module rcu #( .dat_o (s_sys_clkdiv4_q) ); endmodule - -module pll_rcu_controller #( - parameter int LockTimeout = 1024 -) ( - input logic sys_clk_i, - input logic sys_rst_n_i, - input logic ext_clk_i, - input logic ext_rst_n_i, - input logic pll_lock_i, - input logic pll_capable_i, - output logic [2:0] pll_sel_o, - output logic pll_apply_o, - output logic select_ext_clk_o, - pll_ctrl_if.rcu pll_ctrl -); - localparam logic [2:0] PLL_IDLE = 3'd0; - localparam logic [2:0] PLL_SAFE = 3'd1; - localparam logic [2:0] PLL_APPLY = 3'd2; - localparam logic [2:0] PLL_WAIT_LOCK = 3'd3; - localparam logic [2:0] PLL_SWITCH = 3'd4; - localparam logic [2:0] PLL_RESPOND = 3'd5; - - logic [2:0] s_req_sel; - logic s_req_valid, s_req_ready; - logic [7:0] s_rsp_data; - logic s_rsp_valid, s_rsp_ready; - logic [7:0] s_rsp_sys_data; - logic s_rsp_sys_valid; - logic [2:0] s_state_d, s_state_q; - logic [2:0] s_pll_sel_d, s_pll_sel_q; - logic s_pll_apply_d, s_pll_apply_q; - logic s_sel_ext_clk_d, s_sel_ext_clk_q; - logic [15:0] s_lock_count_d, s_lock_count_q; - logic [2:0] s_active_sel_d, s_active_sel_q; - logic s_active_valid_d, s_active_valid_q; - logic s_safe_clk_d, s_safe_clk_q; - logic s_lock_d, s_lock_q; - logic s_lock_seen_low_d, s_lock_seen_low_q; - logic [1:0] s_err_d, s_err_q; - logic s_rsp_valid_d, s_rsp_valid_q; - - cdc_2phase #( - .DATA_WIDTH(3) - ) u_pll_request_cdc ( - .src_clk_i (sys_clk_i), - .src_rst_n_i(sys_rst_n_i), - .src_data_i (pll_ctrl.req_sel_o), - .src_valid_i(pll_ctrl.req_valid_o), - .src_ready_o(pll_ctrl.req_ready_i), - .dst_clk_i (ext_clk_i), - .dst_rst_n_i(ext_rst_n_i), - .dst_data_o (s_req_sel), - .dst_valid_o(s_req_valid), - .dst_ready_i(s_req_ready) - ); - cdc_2phase #( - .DATA_WIDTH(8) - ) u_pll_response_cdc ( - .src_clk_i (ext_clk_i), - .src_rst_n_i(ext_rst_n_i), - .src_data_i (s_rsp_data), - .src_valid_i(s_rsp_valid_q), - .src_ready_o(s_rsp_ready), - .dst_clk_i (sys_clk_i), - .dst_rst_n_i(sys_rst_n_i), - .dst_data_o (s_rsp_sys_data), - .dst_valid_o(s_rsp_sys_valid), - .dst_ready_i(pll_ctrl.rsp_ready_o) - ); - - assign pll_ctrl.rsp_active_sel_i = s_rsp_sys_data[2:0]; - assign pll_ctrl.rsp_active_valid_i = s_rsp_sys_data[3]; - assign pll_ctrl.rsp_safe_clk_i = s_rsp_sys_data[4]; - assign pll_ctrl.rsp_pll_lock_i = s_rsp_sys_data[5]; - assign pll_ctrl.rsp_error_i = s_rsp_sys_data[7:6]; - assign pll_ctrl.rsp_valid_i = s_rsp_sys_valid; - assign pll_ctrl.capable_i = pll_capable_i; - assign s_req_ready = s_state_q == PLL_IDLE; - assign s_rsp_data = {s_err_q, s_lock_q, s_safe_clk_q, s_active_valid_q, s_active_sel_q}; - assign pll_sel_o = s_pll_sel_q; - assign pll_apply_o = s_pll_apply_q; - assign select_ext_clk_o = s_sel_ext_clk_q; - - always_comb begin - s_state_d = s_state_q; - s_pll_sel_d = s_pll_sel_q; - s_pll_apply_d = (s_state_q == PLL_APPLY) || (s_state_q == PLL_WAIT_LOCK); - s_sel_ext_clk_d = s_sel_ext_clk_q; - s_lock_count_d = s_lock_count_q; - s_active_sel_d = s_active_sel_q; - s_active_valid_d = s_active_valid_q; - s_safe_clk_d = s_safe_clk_q; - s_lock_d = s_lock_q; - s_lock_seen_low_d = s_lock_seen_low_q; - s_err_d = s_err_q; - s_rsp_valid_d = s_rsp_valid_q; - - unique case (s_state_q) - PLL_IDLE: begin - s_lock_seen_low_d = 1'b0; - if (s_req_valid) begin - s_pll_sel_d = s_req_sel; - s_sel_ext_clk_d = 1'b1; - s_err_d = 2'd0; - s_state_d = PLL_SAFE; - end - end - PLL_SAFE: begin - s_lock_seen_low_d = 1'b0; - s_sel_ext_clk_d = 1'b1; - s_safe_clk_d = 1'b1; - s_lock_d = 1'b0; - if (pll_capable_i) begin - s_state_d = PLL_APPLY; - end else begin - s_active_valid_d = 1'b0; - s_err_d = 2'd1; - s_state_d = PLL_RESPOND; - end - end - PLL_APPLY: begin - s_lock_count_d = '0; - s_lock_seen_low_d = 1'b0; - s_state_d = PLL_WAIT_LOCK; - end - PLL_WAIT_LOCK: begin - if (!pll_lock_i) begin - s_lock_seen_low_d = 1'b1; - end - if (s_lock_seen_low_q && pll_lock_i) begin - s_active_sel_d = s_pll_sel_q; - s_active_valid_d = 1'b1; - s_safe_clk_d = 1'b0; - s_lock_d = 1'b1; - s_err_d = 2'd0; - s_state_d = PLL_SWITCH; - end else if (s_lock_count_q == LockTimeout - 1) begin - s_active_valid_d = 1'b0; - s_safe_clk_d = 1'b1; - s_lock_d = 1'b0; - s_err_d = 2'd2; - s_state_d = PLL_RESPOND; - end else begin - s_lock_count_d = s_lock_count_q + 1'b1; - end - end - PLL_SWITCH: begin - s_sel_ext_clk_d = 1'b0; - s_state_d = PLL_RESPOND; - end - PLL_RESPOND: begin - s_rsp_valid_d = 1'b1; - if (s_rsp_valid_q && s_rsp_ready) begin - s_rsp_valid_d = 1'b0; - s_state_d = PLL_IDLE; - end - end - default: begin - s_state_d = PLL_IDLE; - end - endcase - end - - dffrc #( - .DATA_WIDTH(3), - .RESET_VAL (PLL_IDLE) - ) u_state_dffrc ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_state_d), - .dat_o (s_state_q) - ); - dffr #( - .DATA_WIDTH(3) - ) u_pll_sel_dffr ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_pll_sel_d), - .dat_o (s_pll_sel_q) - ); - dffr #( - .DATA_WIDTH(1) - ) u_pll_apply_dffr ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_pll_apply_d), - .dat_o (s_pll_apply_q) - ); - dffrc #( - .DATA_WIDTH(1), - .RESET_VAL (1'b1) - ) u_select_ext_clk_dffrc ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_sel_ext_clk_d), - .dat_o (s_sel_ext_clk_q) - ); - dffr #( - .DATA_WIDTH(16) - ) u_lock_count_dffr ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_lock_count_d), - .dat_o (s_lock_count_q) - ); - dffr #( - .DATA_WIDTH(3) - ) u_active_sel_dffr ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_active_sel_d), - .dat_o (s_active_sel_q) - ); - dffr #( - .DATA_WIDTH(1) - ) u_active_valid_dffr ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_active_valid_d), - .dat_o (s_active_valid_q) - ); - dffrc #( - .DATA_WIDTH(1), - .RESET_VAL (1'b1) - ) u_safe_clk_dffrc ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_safe_clk_d), - .dat_o (s_safe_clk_q) - ); - dffr #( - .DATA_WIDTH(1) - ) u_lock_dffr ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_lock_d), - .dat_o (s_lock_q) - ); - dffr #( - .DATA_WIDTH(1) - ) u_lock_seen_low_dffr ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_lock_seen_low_d), - .dat_o (s_lock_seen_low_q) - ); - dffr #( - .DATA_WIDTH(2) - ) u_error_dffr ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_err_d), - .dat_o (s_err_q) - ); - dffr #( - .DATA_WIDTH(1) - ) u_rsp_valid_dffr ( - .clk_i (ext_clk_i), - .rst_n_i(ext_rst_n_i), - .dat_i (s_rsp_valid_d), - .dat_o (s_rsp_valid_q) - ); -endmodule diff --git a/rtl/mini/top/retrosoc.sv b/rtl/mini/top/retrosoc.sv index e2e65239..a9b6fea3 100644 --- a/rtl/mini/top/retrosoc.sv +++ b/rtl/mini/top/retrosoc.sv @@ -13,35 +13,35 @@ `include "soc_irq_config.svh" module retrosoc ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - input logic clk_aud_i, - input logic rst_aud_n_i, - input logic clkdiv4_i, - input logic timebase_tick_i, - pll_ctrl_if.sysctrl pll_ctrl, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, + input logic clk_aud_i, + input logic rst_aud_n_i, + input logic clkdiv4_i, + input logic timebase_tick_i, + pll_ctrl_if.sysctrl pll_ctrl, `ifdef HAVE_SRAM_IF - ram_if.master ram, + ram_if.master ram, `endif - gpio_if.soc_pad gpio, - input logic uart_rx_i, - output logic uart_tx_o, - xpi_if.dut xpi, - sdram_if.dut sdram, - input logic jtag_tck_i, - input logic jtag_tms_i, - input logic jtag_tdi_i, - input logic jtag_trst_n_i, - output logic jtag_tdo_o, - output logic wdg_reset_req_o, - output logic test_done_o, - output logic test_pass_o, - output logic [7:0] test_code_o + gpio_if.soc_pad gpio, + input logic uart_rx_i, + output logic uart_tx_o, + xpi_if.dut xpi, + sdram_if.dut sdram, + input logic jtag_tck_i, + input logic jtag_tms_i, + input logic jtag_tdi_i, + input logic jtag_trst_n_i, + output logic jtag_tdo_o, + output logic wdg_reset_req_o, + output logic test_done_o, + output logic test_pass_o, + output logic [7:0] test_code_o // verilog_format: on ); - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment // Generated fabric links use the common 32-bit AXI4 contract. `include "soc_fabric_interfaces.svh" ribp_if u_sdram_cfg_ribp_if (); diff --git a/rtl/mini/top/rib2apb.sv b/rtl/mini/top/rib2apb.sv index c000b594..2fe0c135 100644 --- a/rtl/mini/top/rib2apb.sv +++ b/rtl/mini/top/rib2apb.sv @@ -12,7 +12,7 @@ `include "rib_defs.svh" module rib2apb ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, rib_if.slave rib, diff --git a/rtl/mini/top/bus.sv b/rtl/mini/top/rib_bus.sv similarity index 80% rename from rtl/mini/top/bus.sv rename to rtl/mini/top/rib_bus.sv index 2c06eea1..d8eaeaa1 100644 --- a/rtl/mini/top/bus.sv +++ b/rtl/mini/top/rib_bus.sv @@ -12,36 +12,36 @@ `include "rib_defs.svh" module rib_bus ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, `ifdef HAVE_SRAM_IF - ram_if.master ram, + ram_if.master ram, `endif - ribp_if.slave mgmt_ribp, - rib_if.slave user_rib, - rib_if.slave dma_rib, - input logic user_bus_enable_i, - output logic user_bus_idle_o, - rib_if.master rib, - rib_if.master apb_rib, - input logic perf_enable_i, - input logic perf_clear_i, - output logic fault_valid_o, - output logic [31:0] fault_addr_o, - output logic [3:0] fault_wstrb_o, - output logic fault_reserved_o, - output logic fault_access_o, - output logic [1:0] fault_master_o, - output logic [2:0] fault_code_o, - output logic [63:0] perf_mgmt_wait_o, - output logic [63:0] perf_user_wait_o, - output logic [63:0] perf_dma_wait_o, - output logic [63:0] perf_ribp_wait_o, - output logic [63:0] perf_apb_wait_o, - output logic [63:0] perf_sdram_wait_o, - output logic [63:0] perf_psram_wait_o, - output logic [63:0] perf_flash_wait_o + ribp_if.slave mgmt_ribp, + rib_if.slave user_rib, + rib_if.slave dma_rib, + input logic user_bus_enable_i, + output logic user_bus_idle_o, + rib_if.master rib, + rib_if.master apb_rib, + input logic perf_enable_i, + input logic perf_clear_i, + output logic fault_valid_o, + output logic [31:0] fault_addr_o, + output logic [3:0] fault_wstrb_o, + output logic fault_reserved_o, + output logic fault_access_o, + output logic [1:0] fault_master_o, + output logic [2:0] fault_code_o, + output logic [63:0] perf_mgmt_wait_o, + output logic [63:0] perf_user_wait_o, + output logic [63:0] perf_dma_wait_o, + output logic [63:0] perf_ribp_wait_o, + output logic [63:0] perf_apb_wait_o, + output logic [63:0] perf_sdram_wait_o, + output logic [63:0] perf_psram_wait_o, + output logic [63:0] perf_flash_wait_o // verilog_format: on ); @@ -309,7 +309,7 @@ module rib_bus ( assign dma_rib.rsp_beat = u_mstr_rib_if.rsp_beat; assign dma_rib.rsp_last = u_mstr_rib_if.rsp_last; - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment assign s_last_addr = u_mstr_rib_if.cmd_addr + (u_mstr_rib_if.cmd_len == `RIB_LEN_INCR4 ? 32'd12 : 32'd0); assign s_len_legal = @@ -329,7 +329,7 @@ module rib_bus ( // verilog_format: on assign s_access_denied = (s_mstr_id_q == MSTR_USER) && ~s_user_access_allowed; - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment assign s_ribp_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied && s_burst_legal && `SOC_ADDR_IS_RIB_LEGACY_TARGET(u_mstr_rib_if.cmd_addr); assign s_apb_sel = u_mstr_rib_if.cmd_valid && ~s_cmd_accepted_q && ~s_access_denied && @@ -351,7 +351,7 @@ module rib_bus ( s_fault_code = `RIB_RESP_PROTERR; end else if (`SOC_ADDR_IS_RESERVED(u_mstr_rib_if.cmd_addr)) begin s_fault_code = `RIB_RESP_RESERVED; - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment end else if ((`SOC_ADDR_IS_RIB_LEGACY_TARGET(u_mstr_rib_if.cmd_addr) || `SOC_ADDR_IS_APB(u_mstr_rib_if.cmd_addr) || `SOC_ADDR_IS_RAM(u_mstr_rib_if.cmd_addr)) && @@ -686,186 +686,3 @@ module rib_bus ( assign perf_flash_wait_o = s_perf_flash_wait_q; endmodule - -module axi4_bus ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, - axi4_if.slave mgmt_axi4, - axi4_if.slave user_axi4, - axi4_if.slave dma_axi4, - axi4_if.master cfg_axi4, - axi4_if.master apb_axi4, -`ifdef HAVE_SRAM_IF - ram_if.master ram, -`endif - axi4_if.master sdram_axi4, - axi4_if.master psram_axi4, - axi4_if.master xpi_axi4, - axi4_if.master spisd_axi4, - input logic user_bus_enable_i, - output logic user_bus_idle_o, - input logic perf_enable_i, - input logic perf_clear_i, - output logic fault_valid_o, - output logic [31:0] fault_addr_o, - output logic [3:0] fault_wstrb_o, - output logic fault_reserved_o, - output logic fault_access_o, - output logic [1:0] fault_master_o, - output logic [2:0] fault_code_o, - output logic [63:0] perf_mgmt_wait_o, - output logic [63:0] perf_user_wait_o, - output logic [63:0] perf_dma_wait_o, - output logic [63:0] perf_ribp_wait_o, - output logic [63:0] perf_apb_wait_o, - output logic [63:0] perf_sdram_wait_o, - output logic [63:0] perf_psram_wait_o, - output logic [63:0] perf_flash_wait_o - // verilog_format: on -); - localparam int NumMasters = 3; - localparam int NumTargets = 9; - - axi4_if #( - .ADDR_WIDTH(32), - .DATA_WIDTH(32), - .ID_WIDTH (1), - .USER_WIDTH(1) - ) u_master_axi4_if[NumMasters] ( - .aclk (clk_i), - .aresetn(rst_n_i) - ); - - axi4_if #( - .ADDR_WIDTH(32), - .DATA_WIDTH(32), - .ID_WIDTH (1), - .USER_WIDTH(1) - ) u_target_axi4_if[NumTargets] ( - .aclk (clk_i), - .aresetn(rst_n_i) - ); - - axi4_if #( - .ADDR_WIDTH(32), - .DATA_WIDTH(32), - .ID_WIDTH (1), - .USER_WIDTH(1) - ) u_ram_axi4_if ( - .aclk (clk_i), - .aresetn(rst_n_i) - ); - - axi4_connector u_mgmt_connector ( - .source(mgmt_axi4), - .sink (u_master_axi4_if[0]) - ); - - axi4_connector u_user_connector ( - .source(user_axi4), - .sink (u_master_axi4_if[1]) - ); - - axi4_connector u_dma_connector ( - .source(dma_axi4), - .sink (u_master_axi4_if[2]) - ); - - axi4_connector u_cfg_connector ( - .source(u_target_axi4_if[0]), - .sink (cfg_axi4) - ); - - axi4_connector u_apb_connector ( - .source(u_target_axi4_if[1]), - .sink (apb_axi4) - ); - - axi4_connector u_ram_connector ( - .source(u_target_axi4_if[2]), - .sink (u_ram_axi4_if) - ); - - axi4_connector u_sdram_connector ( - .source(u_target_axi4_if[3]), - .sink (sdram_axi4) - ); - - axi4_connector u_psram_connector ( - .source(u_target_axi4_if[4]), - .sink (psram_axi4) - ); - - axi4_connector u_xpi_connector ( - .source(u_target_axi4_if[5]), - .sink (xpi_axi4) - ); - - axi4_connector u_spisd_connector ( - .source(u_target_axi4_if[6]), - .sink (spisd_axi4) - ); - - axi4_interconnect #( - .NumMasters(NumMasters), - .NumTargets(NumTargets) - ) u_axi4_interconnect ( - .clk_i (clk_i), - .rst_n_i (rst_n_i), - .masters (u_master_axi4_if), - .targets (u_target_axi4_if), - .user_bus_enable_i(user_bus_enable_i), - .user_bus_idle_o (user_bus_idle_o), - .perf_enable_i (perf_enable_i), - .perf_clear_i (perf_clear_i), - .fault_valid_o (fault_valid_o), - .fault_addr_o (fault_addr_o), - .fault_wstrb_o (fault_wstrb_o), - .fault_reserved_o (fault_reserved_o), - .fault_access_o (fault_access_o), - .fault_master_o (fault_master_o), - .fault_code_o (fault_code_o), - .perf_mgmt_wait_o (perf_mgmt_wait_o), - .perf_user_wait_o (perf_user_wait_o), - .perf_dma_wait_o (perf_dma_wait_o), - .perf_ribp_wait_o (perf_ribp_wait_o), - .perf_apb_wait_o (perf_apb_wait_o), - .perf_sdram_wait_o(perf_sdram_wait_o), - .perf_psram_wait_o(perf_psram_wait_o), - .perf_flash_wait_o(perf_flash_wait_o) - ); - -`ifdef HAVE_SRAM_IF - axi42ram u_axi42ram ( - .clk_i (clk_i), - .rst_n_i(rst_n_i), - .axi4 (u_ram_axi4_if), - .ram (ram) - ); -`else - axi4_error_slave #( - .Response(2'b11) - ) u_ram_error_slave ( - .clk_i (clk_i), - .rst_n_i(rst_n_i), - .axi4 (u_ram_axi4_if) - ); -`endif - - axi4_error_slave #( - .Response(2'b11) - ) u_decode_error_slave ( - .clk_i (clk_i), - .rst_n_i(rst_n_i), - .axi4 (u_target_axi4_if[7]) - ); - - axi4_error_slave #( - .Response(2'b10) - ) u_slave_error_slave ( - .clk_i (clk_i), - .rst_n_i(rst_n_i), - .axi4 (u_target_axi4_if[8]) - ); -endmodule diff --git a/rtl/mini/top/ribp2rib.sv b/rtl/mini/top/ribp2rib.sv index 230c6f94..ca2ee1a6 100644 --- a/rtl/mini/top/ribp2rib.sv +++ b/rtl/mini/top/ribp2rib.sv @@ -66,7 +66,7 @@ module ribp2rib #( endcase end - if (SyncReset) begin : GEN_SYNC_RESET + if (SyncReset) begin : gen_sync_reset dffsr #( .DATA_WIDTH(2) ) u_fsm_dffsr ( @@ -93,7 +93,7 @@ module ribp2rib #( .dat_i (ribp.wstrb), .dat_o (s_wstrb_q) ); - end else begin : GEN_ASYNC_RESET + end else begin : gen_async_reset dffr #( .DATA_WIDTH(2) ) u_fsm_dffr ( diff --git a/rtl/mini/top/user_core_design_template.sv b/rtl/mini/top/user_core_design.sv similarity index 94% rename from rtl/mini/top/user_core_design_template.sv rename to rtl/mini/top/user_core_design.sv index c9531dee..e8e1c6c9 100644 --- a/rtl/mini/top/user_core_design_template.sv +++ b/rtl/mini/top/user_core_design.sv @@ -22,11 +22,11 @@ module user_core_design #( parameter int ID = 5'd31 ) ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic [31:0] irq_i, - ribp_if.master ribp + ribp_if.master ribp // verilog_format: on ); diff --git a/rtl/mini/top/user_core_top.sv b/rtl/mini/top/user_core_top.sv index a2409968..6b460c94 100644 --- a/rtl/mini/top/user_core_top.sv +++ b/rtl/mini/top/user_core_top.sv @@ -11,7 +11,7 @@ `include "user_extensions.svh" module user_core_top ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic [ 31:0] irq_i, @@ -26,7 +26,7 @@ module user_core_top ( // Generated bindings preserve scalar user-core interfaces and isolation. `include "user_core_bindings.svh" - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment rib2axi4 u_rib2axi4 ( .clk_i (clk_i), .rst_n_i(rst_n_i), diff --git a/rtl/mini/top/user_extensions.svh b/rtl/mini/top/user_extensions.svh index 85a81d40..6dcce4eb 100644 --- a/rtl/mini/top/user_extensions.svh +++ b/rtl/mini/top/user_extensions.svh @@ -9,8 +9,8 @@ // MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. // See the Mulan PSL v2 for more details. -`ifndef USER_EXTENSIONS_DEF_SVH -`define USER_EXTENSIONS_DEF_SVH +`ifndef RETROSOC_USER_EXTENSIONS_SVH +`define RETROSOC_USER_EXTENSIONS_SVH `include "user_extensions_config.svh" diff --git a/rtl/mini/top/user_ip_design_template.sv b/rtl/mini/top/user_ip_design_template.sv index e9e99129..e80ed103 100644 --- a/rtl/mini/top/user_ip_design_template.sv +++ b/rtl/mini/top/user_ip_design_template.sv @@ -22,11 +22,11 @@ module user_ip_design_template #( parameter int ID = 8'd255 ) ( - // verilog_format: off - input logic clk_i, - input logic rst_n_i, + // verilog_format: off -- preserve reviewed column alignment + input logic clk_i, + input logic rst_n_i, user_gpio_if.user_ip gpio, - apb4_if.slave apb + apb4_if.slave apb // verilog_format: on ); diff --git a/rtl/mini/top/user_ip_top.sv b/rtl/mini/top/user_ip_top.sv index e1ca6e39..c85079a7 100644 --- a/rtl/mini/top/user_ip_top.sv +++ b/rtl/mini/top/user_ip_top.sv @@ -12,7 +12,7 @@ `include "user_extensions.svh" module user_ip_top ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic [`USER_IPSEL_WIDTH-1:0] sel_i, diff --git a/rtl/mini/top/user_ip_wrapper.sv b/rtl/mini/top/user_ip_wrapper.sv index 4fcf6274..d18ac084 100644 --- a/rtl/mini/top/user_ip_wrapper.sv +++ b/rtl/mini/top/user_ip_wrapper.sv @@ -11,7 +11,7 @@ `include "user_extensions.svh" module user_ip_wrapper ( - // verilog_format: off + // verilog_format: off -- preserve reviewed column alignment input logic clk_i, input logic rst_n_i, input logic [`USER_IPSEL_WIDTH-1:0] sel_i, diff --git a/rtl/rtl_style_audit.json b/rtl/rtl_style_audit.json new file mode 100644 index 00000000..2f0eca5e --- /dev/null +++ b/rtl/rtl_style_audit.json @@ -0,0 +1,284 @@ +{ + "schema_version": 1, + "policy": "docs/rtl-coding-style.md", + "profile": "owned", + "review_methods": [ + "automated static checks", + "tool-assisted source review", + "targeted simulation and formal source-list review" + ], + "reviewed_boundary_record": { + "owner": "retroSoC RTL maintainers", + "related_commit": "7a7c0b2973d3bbe92bb3c2bbb9808edc5181b641", + "expiry": "Expires before a behavior-changing or sequential-equivalence-verified refactor of an affected module.", + "removal_plan": "Use an isolated change with named validation evidence; do not treat this audit record as a warning baseline or a blanket waiver." + }, + "rules": [ + { + "id": "RTL-FILE", + "sections": [2], + "result": "compliant", + "evidence": "Primary-unit/file-name checks and canonical filelist review." + }, + { + "id": "RTL-SV", + "sections": [3], + "result": "compliant", + "evidence": "Restricted-SystemVerilog static checks and Verible lint." + }, + { + "id": "RTL-NAME", + "sections": [4], + "result": "compliant", + "evidence": "Full-profile naming enforcement and boundary review." + }, + { + "id": "RTL-STRUCT", + "sections": [5], + "result": "compliant", + "evidence": "Named-connection, generate-label, one-primary-unit, and filelist checks." + }, + { + "id": "RTL-COMB", + "sections": [6], + "result": "reviewed", + "evidence": "Combinational defaults and protocol-path source review." + }, + { + "id": "RTL-SEQ", + "sections": [6], + "result": "reviewed", + "evidence": "Reset, enable, FSM, inferred-memory, and sequential-priority review." + }, + { + "id": "RTL-WIDTH", + "sections": [7], + "result": "reviewed", + "evidence": "Verilator lint and width, signedness, and X/Z source review." + }, + { + "id": "RTL-CDC", + "sections": [8], + "result": "reviewed", + "evidence": "Clock/reset-domain metadata, CDC primitive review, and targeted tests." + }, + { + "id": "RTL-VERIFY", + "sections": [9], + "result": "reviewed", + "evidence": "Formal source-list checks, readiness checks, and directed simulations." + }, + { + "id": "RTL-FMT", + "sections": [10], + "result": "compliant", + "evidence": "Verible format, ASCII, whitespace, line-length, and paired-directive checks." + } + ], + "inventory": { + "rtl/ip/experimental": [ + "axi4f2ribp.sv", + "ribp_gpu.sv", + "wb2ribp.sv" + ], + "rtl/ip/interconnect": [ + "axi4l2ribp.sv", + "ribp2ribp.sv", + "ribp_regslice.sv" + ], + "rtl/ip/memory": [ + "axi4_sdram.sv", + "psram_core.sv", + "ribp_opipsram.sv", + "ribp_psram.sv", + "sdram_clkgen.sv", + "sdram_core.sv", + "sdram_reg.sv" + ], + "rtl/ip/multimedia": [ + "axi4s_dvp.sv", + "dvp_core.sv", + "dvp_define.svh", + "dvp_reg.sv" + ], + "rtl/ip/peripheral": [ + "clint_core.sv", + "clint_define.svh", + "clint_if.sv", + "clint_reg.sv", + "clint_timebase.sv", + "dma_core.sv", + "gpio_core.sv", + "gpio_define.svh", + "gpio_if.sv", + "gpio_reg.sv", + "pll_ctrl_if.sv", + "ribp_clint.sv", + "ribp_dma.sv", + "ribp_gpio.sv", + "ribp_sysctrl.sv", + "ribp_timer.sv", + "timer_core.sv", + "timer_define.svh", + "timer_reg.sv", + "user_gpio_if.sv" + ], + "rtl/ip/serial": [ + "i2c_core.sv", + "i2c_filter.sv", + "i2c_reg.sv", + "i2s_clkgen.sv", + "i2s_core.sv", + "i2s_define.svh", + "i2s_recv.sv", + "i2s_reg.sv", + "i2s_send.sv", + "ribp_i2c.sv", + "ribp_i2c_define.svh", + "ribp_i2s.sv", + "ribp_uart.sv", + "ribp_uart_define.svh", + "ribp_uart_rx.sv", + "ribp_uart_tx.sv", + "ribp_ws2812.sv", + "uart_baudgen.sv", + "uart_core.sv", + "uart_flow_ctrl.sv", + "uart_if.sv", + "uart_reg.sv", + "ws2812_core.sv", + "ws2812_define.svh", + "ws2812_if.sv", + "ws2812_reg.sv" + ], + "rtl/ip/storage": [ + "ribp_sdio.sv", + "ribp_spisd.sv", + "ribp_xpi.sv", + "spisd_cache.sv", + "spisd_core.sv", + "spisd_data.sv", + "spisd_init.sv", + "spisd_read.sv", + "spisd_reg.sv", + "spisd_write.sv", + "xpi_clkgen.sv", + "xpi_core.sv", + "xpi_define.svh", + "xpi_mm.sv", + "xpi_reg.sv" + ], + "rtl/ip/util": [ + "async_fifo.sv" + ], + "rtl/mini/top": [ + "ahbl2axi4.sv", + "ahbl2ribp.sv", + "apb4_if_bridge.sv", + "axi4_bus.sv", + "axi4_connector.sv", + "axi4_error_slave.sv", + "axi4_interconnect.sv", + "axi42apb.sv", + "axi42ram.sv", + "axi42ribp.sv", + "axi42ribp_burst.sv", + "core_wrapper.sv", + "gpio_pad_bridge.sv", + "ip_apb_wrapper.sv", + "ip_ribp_wrapper.sv", + "mgmt_core_wrapper.sv", + "mgmt_debug_reset.sv", + "mgmt_debug_wrapper.sv", + "onchip_ram.sv", + "pll_rcu_controller.sv", + "rcu.sv", + "retrosoc.sv", + "retrosoc_asic.sv", + "rib2apb.sv", + "rib2axi4.sv", + "rib2ram.sv", + "rib2ribp.sv", + "rib_bus.sv", + "rib_defs.svh", + "rib_error_slave.sv", + "rib_if.sv", + "ribp2axi4.sv", + "ribp2rib.sv", + "ribp_arbiter2.sv", + "soc_clock_config.svh", + "soc_common_cdc.sv", + "soc_common_fifo.sv", + "user_core_design.sv", + "user_core_top.sv", + "user_extensions.svh", + "user_ip_design_template.sv", + "user_ip_top.sv", + "user_ip_wrapper.sv" + ] + }, + "reviewed_boundaries": [ + { + "paths": [ + "rtl/ip/experimental/axi4f2ribp.sv", + "rtl/ip/experimental/ribp_gpu.sv", + "rtl/ip/experimental/wb2ribp.sv" + ], + "result": "inactive experimental source", + "rationale": "The modules remain primary-unit-aligned but are not active filelist inputs. Incomplete protocol behavior was not changed by style work." + }, + { + "paths": [ + "rtl/ip/memory/psram_core.sv", + "rtl/ip/memory/sdram_core.sv", + "rtl/ip/multimedia/dvp_core.sv", + "rtl/ip/multimedia/dvp_reg.sv", + "rtl/ip/storage/spisd_cache.sv", + "rtl/ip/storage/spisd_data.sv", + "rtl/ip/storage/spisd_init.sv", + "rtl/ip/storage/spisd_read.sv", + "rtl/ip/storage/spisd_write.sv", + "rtl/ip/storage/xpi_mm.sv" + ], + "result": "raw sequential storage retained", + "rationale": "Reset and update priorities, SPI/SDRAM timing, or inferred-memory behavior are cycle-sensitive. Replacing these processes with Common register primitives requires a separate sequential-equivalence proof and affected protocol simulation." + }, + { + "paths": [ + "rtl/ip/util/async_fifo.sv" + ], + "result": "retained implementation", + "rationale": "Dual-clock storage, Gray-pointer synchronization, and inferred-memory behavior cannot be replaced by single-clock Common registers without equivalence evidence." + }, + { + "paths": [ + "rtl/mini/top/axi4_interconnect.sv" + ], + "result": "retained implementation", + "rationale": "Priority-sensitive master, target, and performance state arrays remain unchanged pending separate sequential-equivalence proof." + }, + { + "paths": [ + "rtl/mini/top/onchip_ram.sv" + ], + "result": "technology boundary retained", + "rationale": "PDK SRAM cell and pin names remain compatible with the technology library." + }, + { + "paths": [ + "rtl/mini/top/soc_common_cdc.sv", + "rtl/mini/top/soc_common_fifo.sv" + ], + "result": "managed compatibility wrapper retained", + "rationale": "The narrow self-owned wrappers preserve required Verilator filename behavior while including managed Common source." + }, + { + "paths": [ + "rtl/mini/top/user_core_design.sv", + "rtl/mini/top/user_ip_design_template.sv" + ], + "result": "external template compatibility retained", + "rationale": "Template interfaces remain stable for externally distributed user designs." + } + ] +} diff --git a/scripts/check_rtl_style.py b/scripts/check_rtl_style.py index e004b654..83d3c978 100644 --- a/scripts/check_rtl_style.py +++ b/scripts/check_rtl_style.py @@ -16,6 +16,15 @@ INSTANCE_RE = re.compile( r"^\s*(?P[A-Za-z_][A-Za-z0-9_$]*)\s*(?:#\s*\([^;]*\)\s*)?" r"u_[A-Za-z_][A-Za-z0-9_$]*\s*\($" ) +PRIMARY_DECL_RE = re.compile( + r"^\s*(?:module|interface|package)\s+(?:automatic\s+)?" + r"(?P[A-Za-z_][A-Za-z0-9_$]*)\b", + re.MULTILINE, +) +FUNCTION_HEADER_RE = re.compile( + r"\bfunction\s+(?P
.*?)(?P;|\n)", + re.DOTALL, +) LEGACY_ALWAYS_RE = re.compile(r"\balways\s*@") DECL_RE = re.compile(r"\b(?:wire|tri|wand|wor)\b") FORBIDDEN_TOKEN_RE = { @@ -53,6 +62,39 @@ PARAM_RE = re.compile( ) UPPER_CAMEL_RE = re.compile(r"^[A-Z][A-Za-z0-9]*$") LOWER_SNAKE_RE = re.compile(r"^[a-z][a-z0-9]*(?:_[a-z0-9]+)*$") +EXPLICIT_FUNCTION_TYPE_RE = re.compile( + r"^automatic\s+(?:bit|logic|reg|byte|shortint|int|longint|integer|time|" + r"[A-Za-z_][A-Za-z0-9_$]*_(?:e|t))(?:\s+(?:signed|unsigned))?" + r"(?:\s*\[[^\]]+\])?\s+[A-Za-z_][A-Za-z0-9_$]*\s*\(" +) +REQUIRED_AUDIT_RULES = { + "RTL-FILE", + "RTL-SV", + "RTL-NAME", + "RTL-STRUCT", + "RTL-COMB", + "RTL-SEQ", + "RTL-WIDTH", + "RTL-CDC", + "RTL-VERIFY", + "RTL-FMT", +} + + +def diagnostic(rule: str, path: Path, message: str, line: int | None = None) -> str: + location = f"{path}:{line}" if line is not None else str(path) + return f"[{rule}] {location}: {message}" + + +def strip_comments(source: str) -> str: + """Remove comments while retaining line numbers for diagnostics.""" + source = re.sub( + r"/\*.*?\*/", + lambda match: "\n" * match.group(0).count("\n"), + source, + flags=re.DOTALL, + ) + return re.sub(r"//[^\n]*", "", source) def tracked_files(root: Path) -> list[Path]: @@ -140,46 +182,214 @@ def instance_issues(path: Path, source: str) -> list[str]: and not text.startswith("//") and not text.startswith("`") ): - issues.append(f"{path}:{cursor + 1}: positional port connection") + issues.append( + diagnostic( + "RTL-STRUCT-002", + path, + "positional port connection", + cursor + 1, + ) + ) break cursor += 1 return issues +def verification_only_lines(source: str) -> set[int]: + """Return lines excluded from synthesis by an explicit SYNTHESIS guard.""" + excluded_lines: set[int] = set() + stack: list[tuple[str, bool]] = [] + for number, line in enumerate(source.splitlines(), start=1): + directive = line.strip() + parent_excluded = stack[-1][1] if stack else False + if directive.startswith("`ifndef SYNTHESIS"): + stack.append(("ifndef-synthesis", True)) + elif directive.startswith("`ifdef SYNTHESIS"): + stack.append(("ifdef-synthesis", parent_excluded)) + elif directive.startswith(("`ifdef ", "`ifndef ", "`if ")): + stack.append(("other", parent_excluded)) + elif directive.startswith("`else") and stack: + kind, excluded = stack[-1] + if kind == "ifndef-synthesis": + stack[-1] = (kind, False) + elif kind == "ifdef-synthesis": + stack[-1] = (kind, True) + else: + stack[-1] = (kind, excluded) + elif directive.startswith("`endif") and stack: + stack.pop() + if stack and stack[-1][1]: + excluded_lines.add(number) + return excluded_lines + + +def declaration_issues(path: Path, source: str) -> list[str]: + parsed_source = strip_comments(source) + declarations = list(PRIMARY_DECL_RE.finditer(parsed_source)) + modules = [match for match in declarations if match.group(0).lstrip().startswith("module")] + if modules: + declarations = modules + if not declarations: + if "`include" in parsed_source and "managed" in source.lower(): + return [] + return [diagnostic("RTL-FILE-001", path, "missing primary design unit")] + primary = declarations[0] + if primary.group("name") != path.stem: + line = parsed_source.count("\n", 0, primary.start()) + 1 + return [ + diagnostic( + "RTL-FILE-002", + path, + f"primary design unit '{primary.group('name')}' must match the file name", + line, + ) + ] + return [] + + +def function_issues(path: Path, source: str) -> list[str]: + issues: list[str] = [] + parsed_source = strip_comments(source) + for match in FUNCTION_HEADER_RE.finditer(parsed_source): + header = re.sub(r"\s+", " ", match.group("header").strip()) + line = parsed_source.count("\n", 0, match.start()) + 1 + if not header.startswith("automatic "): + issues.append( + diagnostic( + "RTL-SV-008", + path, + "synthesizable function must be automatic", + line, + ) + ) + elif not EXPLICIT_FUNCTION_TYPE_RE.match(header): + issues.append( + diagnostic( + "RTL-SV-009", + path, + "function requires an explicit return type and typed arguments", + line, + ) + ) + return issues + + def check_file(path: Path, source: str, profile: str) -> list[str]: issues: list[str] = [] if profile == "owned": issues.extend(instance_issues(path, source)) + if path.suffix == ".sv": + issues.extend(declaration_issues(path, source)) + issues.extend(function_issues(path, source)) + verification_lines = verification_only_lines(source) format_disabled = False + format_disabled_line: int | None = None for number, line in enumerate(source.splitlines(), start=1): code = line.split("//", 1)[0] if "verilog_format: off" in line: + if format_disabled: + issues.append( + diagnostic( + "RTL-FMT-005", + path, + "nested verilog_format: off region", + number, + ) + ) + if "--" not in line: + issues.append( + diagnostic( + "RTL-FMT-007", + path, + "verilog_format: off requires an inline alignment rationale", + number, + ) + ) format_disabled = True + format_disabled_line = number format_exception = format_disabled if LEGACY_ALWAYS_RE.search(code): - issues.append(f"{path}:{number}: use always_ff/always_comb in owned RTL") + issues.append( + diagnostic( + "RTL-SEQ-001", + path, + "use always_ff/always_comb in owned RTL", + number, + ) + ) if re.search(r"\bwire\b", code) and not re.search(r"\binout\s+wire\b", code): - issues.append(f"{path}:{number}: explicit wire in owned RTL; justify net semantics") + issues.append( + diagnostic( + "RTL-STRUCT-005", + path, + "explicit wire in owned RTL; justify net semantics", + number, + ) + ) if LONG_LOCAL_RE.search(code): - issues.append(f"{path}:{number}: prefer the local short-name abbreviation") + issues.append( + diagnostic( + "RTL-NAME-009", + path, + "prefer the local short-name abbreviation", + number, + ) + ) + if re.search(r"\binitial\s+begin\b", code) and number not in verification_lines: + issues.append( + diagnostic( + "RTL-SV-007", + path, + "initial block must be isolated from synthesis", + number, + ) + ) if not format_exception: if any(character == "\t" for character in line): - issues.append(f"{path}:{number}: tabs are not permitted in owned RTL") + issues.append( + diagnostic("RTL-FMT-002", path, "tabs are not permitted", number) + ) if line.rstrip() != line: - issues.append(f"{path}:{number}: trailing whitespace") + issues.append(diagnostic("RTL-FMT-003", path, "trailing whitespace", number)) if any(ord(character) > 127 for character in line): - issues.append(f"{path}:{number}: non-ASCII character") + issues.append(diagnostic("RTL-FMT-001", path, "non-ASCII character", number)) if len(line) > 100: - issues.append(f"{path}:{number}: line exceeds 100 characters") + issues.append( + diagnostic("RTL-FMT-004", path, "line exceeds 100 characters", number) + ) for description, pattern in FORBIDDEN_TOKEN_RE.items(): if pattern.search(code): - issues.append(f"{path}:{number}: {description} is not permitted") + issues.append( + diagnostic("RTL-SV-001", path, f"{description} is not permitted", number) + ) if "verilog_format: on" in line: - format_disabled = False + if not format_disabled: + issues.append( + diagnostic( + "RTL-FMT-005", + path, + "verilog_format: on has no matching off", + number, + ) + ) + else: + format_disabled = False + format_disabled_line = None + if format_disabled: + issues.append( + diagnostic( + "RTL-FMT-005", + path, + "verilog_format: off has no matching on", + format_disabled_line, + ) + ) if source and not source.endswith("\n"): - issues.append(f"{path}: missing final newline") + issues.append(diagnostic("RTL-FMT-006", path, "missing final newline")) if UNNAMED_GENERATE_RE.search(source): - issues.append(f"{path}: generated if/for block must have a label") + issues.append( + diagnostic("RTL-STRUCT-006", path, "generated if/for block must have a label") + ) return issues @@ -196,7 +406,14 @@ def naming_issues(path: Path, source: str, manifest: dict[str, object]) -> list[ code = line.split("//", 1)[0] module_match = MODULE_RE.match(code) if module_match and not LOWER_SNAKE_RE.fullmatch(module_match.group("name")): - issues.append(f"{path}:{number}: module name must use lower_snake_case") + issues.append( + diagnostic( + "RTL-NAME-001", + path, + "module name must use lower_snake_case", + number, + ) + ) if re.match(r"^\s*interface\b", code): in_interface = True if re.match(r"^\s*function\b", code): @@ -205,12 +422,26 @@ def naming_issues(path: Path, source: str, manifest: dict[str, object]) -> list[ if port_match and not in_interface and not in_function: name = port_match.group("name") if not name.endswith(("_i", "_o", "_io")): - issues.append(f"{path}:{number}: port '{name}' needs _i, _o, or _io suffix") + issues.append( + diagnostic( + "RTL-NAME-002", + path, + f"port '{name}' needs _i, _o, or _io suffix", + number, + ) + ) interface_match = INTERFACE_INSTANCE_RE.match(code) if interface_match and not interface_match.group("name").startswith("u_") and ( interface_match.group("name") not in {"ribp", "ribl", "rib"} ): - issues.append(f"{path}:{number}: interface instance must start with u_") + issues.append( + diagnostic( + "RTL-NAME-004", + path, + "interface instance must start with u_", + number, + ) + ) macro_match = MACRO_RE.match(code) if macro_match: name = macro_match.group("name") @@ -220,9 +451,23 @@ def naming_issues(path: Path, source: str, manifest: dict[str, object]) -> list[ if not name.startswith("RETROSOC_") and not any( name.startswith(str(prefix)) for prefix in exceptions ) and not name.endswith(("_SV", "_SVH")): - issues.append(f"{path}:{number}: macro '{name}' needs a reviewed namespace") + issues.append( + diagnostic( + "RTL-NAME-008", + path, + f"macro '{name}' needs a reviewed namespace", + number, + ) + ) if re.search(r"\brst_ni\b", code): - issues.append(f"{path}:{number}: use project reset spelling rst_n_i") + issues.append( + diagnostic( + "RTL-NAME-003", + path, + "use project reset spelling rst_n_i", + number, + ) + ) if re.match(r"^\s*endfunction\b", code): in_function = False if re.match(r"^\s*endinterface\b", code): @@ -230,7 +475,9 @@ def naming_issues(path: Path, source: str, manifest: dict[str, object]) -> list[ for match in ENUM_TYPE_RE.finditer(source): if not match.group("name").endswith("_e"): line = source.count("\n", 0, match.start()) + 1 - issues.append(f"{path}:{line}: enum typedef must end in _e") + issues.append( + diagnostic("RTL-NAME-006", path, "enum typedef must end in _e", line) + ) for number, line in enumerate(lines, start=1): code = line.split("//", 1)[0] if re.search(r"\bparameter\b", code) and not re.search(r"\blocalparam\b", code): @@ -239,7 +486,12 @@ def naming_issues(path: Path, source: str, manifest: dict[str, object]) -> list[ if match.group("name") in {"DATA_WIDTH"}: continue issues.append( - f"{path}:{number}: parameter '{match.group('name')}' must use UpperCamelCase" + diagnostic( + "RTL-NAME-007", + path, + f"parameter '{match.group('name')}' must use UpperCamelCase", + number, + ) ) return issues @@ -265,12 +517,102 @@ def verible_issues(tool: str, paths: list[Path], root: Path) -> list[str]: return [line for line in result.stdout.splitlines() if line] +def audit_issues(root: Path, audit_path: Path, paths: list[Path]) -> list[str]: + """Validate that the committed audit covers the current owned source set.""" + try: + audit = json.loads(audit_path.read_text(encoding="utf-8")) + except (OSError, json.JSONDecodeError) as error: + return [diagnostic("RTL-AUDIT-001", audit_path, f"invalid audit record: {error}")] + if not isinstance(audit, dict): + return [diagnostic("RTL-AUDIT-001", audit_path, "audit record must be an object")] + + issues: list[str] = [] + if audit.get("schema_version") != 1: + issues.append(diagnostic("RTL-AUDIT-001", audit_path, "unsupported schema_version")) + if audit.get("profile") != "owned": + issues.append(diagnostic("RTL-AUDIT-001", audit_path, "audit must cover the owned profile")) + if audit.get("policy") != "docs/rtl-coding-style.md": + issues.append(diagnostic("RTL-AUDIT-001", audit_path, "audit must identify the RTL policy")) + boundary_record = audit.get("reviewed_boundary_record") + required_boundary_fields = {"owner", "related_commit", "expiry", "removal_plan"} + if not isinstance(boundary_record, dict) or not all( + isinstance(boundary_record.get(field), str) and boundary_record[field] + for field in required_boundary_fields + ): + issues.append( + diagnostic( + "RTL-AUDIT-001", + audit_path, + "reviewed boundaries require owner, related_commit, expiry, and removal_plan", + ) + ) + + inventory = audit.get("inventory") + audited_paths: set[Path] = set() + if not isinstance(inventory, dict): + issues.append(diagnostic("RTL-AUDIT-001", audit_path, "missing inventory object")) + else: + for directory, names in inventory.items(): + if not isinstance(directory, str) or not isinstance(names, list): + issues.append( + diagnostic("RTL-AUDIT-001", audit_path, "inventory entries must map paths to lists") + ) + continue + if not all(isinstance(name, str) for name in names): + issues.append( + diagnostic("RTL-AUDIT-001", audit_path, "inventory file names must be strings") + ) + continue + audited_paths.update(Path(directory) / name for name in names) + + expected_paths = set(paths) + missing = sorted(expected_paths - audited_paths) + extra = sorted(audited_paths - expected_paths) + if missing: + issues.append( + diagnostic( + "RTL-AUDIT-002", + audit_path, + f"inventory is missing owned source '{missing[0]}'", + ) + ) + if extra: + issues.append( + diagnostic( + "RTL-AUDIT-003", + audit_path, + f"inventory names non-owned source '{extra[0]}'", + ) + ) + + rules = audit.get("rules") + if not isinstance(rules, list): + issues.append(diagnostic("RTL-AUDIT-001", audit_path, "missing rules list")) + else: + rule_ids = { + rule.get("id") + for rule in rules + if isinstance(rule, dict) and isinstance(rule.get("id"), str) + } + missing_rules = sorted(REQUIRED_AUDIT_RULES - rule_ids) + if missing_rules: + issues.append( + diagnostic( + "RTL-AUDIT-004", + audit_path, + f"missing rule matrix entry '{missing_rules[0]}'", + ) + ) + return issues + + def main() -> int: parser = argparse.ArgumentParser(description=__doc__) parser.add_argument("--root", type=Path, required=True) parser.add_argument("--manifest", type=Path) parser.add_argument("--profile", default="owned", choices=("owned", "verification", "technology")) parser.add_argument("--baseline", type=Path) + parser.add_argument("--audit", type=Path) parser.add_argument("--verible-verilog-lint", default="verible-verilog-lint") parser.add_argument( "--changed-only", @@ -306,6 +648,9 @@ def main() -> int: issues = [issue for group in issues for issue in (group if isinstance(group, list) else [group])] if args.profile == "owned": issues.extend(verible_issues(args.verible_verilog_lint, profile_files, root)) + if args.audit: + audit_path = args.audit if args.audit.is_absolute() else root / args.audit + issues.extend(audit_issues(root, audit_path, profile_files)) baseline: set[str] = set() if args.baseline and args.baseline.is_file(): baseline = set(json.loads(args.baseline.read_text(encoding="utf-8"))) diff --git a/tests/test_dma.py b/tests/test_dma.py index d7355fd7..6f62f6d7 100644 --- a/tests/test_dma.py +++ b/tests/test_dma.py @@ -44,7 +44,7 @@ def test_dma_reports_bus_errors_and_transfers_exact_word_count(tmp_path: Path) - str(ROOT / "rtl/mini/top/rib_if.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/utils/fifo.sv"), - str(ROOT / "rtl/ip/peripheral/dma.sv"), + str(ROOT / "rtl/ip/peripheral/ribp_dma.sv"), str(ROOT / "rtl/ip/peripheral/dma_core.sv"), str(ROOT / "tests/rtl/dma_error_tb.sv"), "", diff --git a/tests/test_dvp.py b/tests/test_dvp.py index 409b91fe..8b4b9096 100644 --- a/tests/test_dvp.py +++ b/tests/test_dvp.py @@ -47,7 +47,7 @@ def test_dvp_capture_framing(tmp_path: Path) -> None: str(ROOT / "rtl/tech/tc_clk.sv"), str(ip / "dvp_core.sv"), str(ip / "dvp_reg.sv"), - str(ip / "dvp.sv"), + str(ip / "axi4s_dvp.sv"), str(ROOT / "tests/rtl/dvp_tb.sv"), ] source_list = tmp_path / "dvp.fl" diff --git a/tests/test_memory_map.py b/tests/test_memory_map.py index 9cf34e8b..0b94b678 100644 --- a/tests/test_memory_map.py +++ b/tests/test_memory_map.py @@ -158,7 +158,7 @@ def test_bus_fault_responder_handles_reserved_and_unmapped_addresses(tmp_path: P str(ROOT / "rtl/mini/top/rib2ribp.sv"), str(ROOT / "rtl/mini/top/rib_error_slave.sv"), str(ROOT / "rtl/mini/top/rib2ram.sv"), - str(ROOT / "rtl/mini/top/bus.sv"), + str(ROOT / "rtl/mini/top/rib_bus.sv"), str(ROOT / "tests/rtl/bus_fault_tb.sv"), "", ] @@ -212,7 +212,7 @@ def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> Non str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv"), str(ROOT / "rtl/ip/peripheral/pll_ctrl_if.sv"), - str(ROOT / "rtl/ip/peripheral/sysctrl.sv"), + str(ROOT / "rtl/ip/peripheral/ribp_sysctrl.sv"), str(ROOT / "tests/rtl/sysctrl_fault_tb.sv"), "", ] @@ -267,10 +267,11 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path: str(ROOT / "rtl/managed/clusterip/common/rtl/utils/edge_det.sv"), str(ROOT / "rtl/ip/peripheral/pll_ctrl_if.sv"), str(ROOT / "rtl/ip/peripheral/clint_timebase.sv"), - str(ROOT / "rtl/ip/peripheral/sysctrl.sv"), + str(ROOT / "rtl/ip/peripheral/ribp_sysctrl.sv"), str(ROOT / "rtl/tech/tc_clk.sv"), str(ROOT / "rtl/tech/tc_pll.sv"), str(ROOT / "rtl/mini/top/rcu.sv"), + str(ROOT / "rtl/mini/top/pll_rcu_controller.sv"), str(ROOT / "tests/rtl/pll_ctrl_tb.sv"), "", ] @@ -338,7 +339,7 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path: def test_sysctrl_does_not_expose_unused_i2c_or_qspi_select_registers() -> None: - rtl = (ROOT / "rtl/ip/peripheral/sysctrl.sv").read_text(encoding="utf-8") + rtl = (ROOT / "rtl/ip/peripheral/ribp_sysctrl.sv").read_text(encoding="utf-8") header = (ROOT / "crt/include/retrosoc/core/soc.h").read_text(encoding="utf-8") for symbol in ( diff --git a/tests/test_rib.py b/tests/test_rib.py index f9f18ea6..55fd90d9 100644 --- a/tests/test_rib.py +++ b/tests/test_rib.py @@ -49,7 +49,7 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None: str(ROOT / "rtl/mini/top/rib2ribp.sv"), str(ROOT / "rtl/mini/top/rib_error_slave.sv"), str(ROOT / "rtl/mini/top/rib2ram.sv"), - str(ROOT / "rtl/mini/top/bus.sv"), + str(ROOT / "rtl/mini/top/rib_bus.sv"), str(ROOT / "tests/rtl/rib_bus_tb.sv"), "", ] diff --git a/tests/test_rtl_style.py b/tests/test_rtl_style.py index f4bf51d8..e8fd0e4c 100644 --- a/tests/test_rtl_style.py +++ b/tests/test_rtl_style.py @@ -8,6 +8,7 @@ from pathlib import Path ROOT = Path(__file__).resolve().parents[1] SCRIPT = ROOT / "scripts/check_rtl_style.py" +AUDIT = ROOT / "rtl/rtl_style_audit.json" def run_style( @@ -119,7 +120,7 @@ def test_owned_style_accepts_project_naming_contract(tmp_path: Path) -> None: result = run_style( tmp_path, "`define RETROSOC_TEST__VALUE 1\n" - "module test_module(\n" + "module test(\n" " input logic clk_i,\n" " output logic data_o\n" ");\n" @@ -135,7 +136,7 @@ def test_owned_style_accepts_project_naming_contract(tmp_path: Path) -> None: def test_owned_style_allows_protocol_localparams(tmp_path: Path) -> None: result = run_style( tmp_path, - "module test_module #(parameter int DataWidth = 32) (" + "module test #(parameter int DataWidth = 32) (" "input logic clk_i, output logic data_o);\n" " localparam logic [1:0] FSM_IDLE = 2'd0;\n" " localparam logic [1:0] FSM_RESP = 2'd1;\n" @@ -151,7 +152,7 @@ def test_owned_style_allows_interface_members_and_include_guards(tmp_path: Path) tmp_path, "`ifndef GPIO_DEFINE_SVH\n" "`define GPIO_DEFINE_SVH\n" - "interface test_if ();\n" + "interface test ();\n" " logic cmd_valid;\n" " modport dut(input cmd_valid);\n" "endinterface\n" @@ -159,3 +160,119 @@ def test_owned_style_allows_interface_members_and_include_guards(tmp_path: Path) enforce_naming=True, ) assert result.returncode == 0, result.stderr + + +def test_owned_style_rejects_mismatched_primary_design_unit(tmp_path: Path) -> None: + result = run_style( + tmp_path, + "module wrong_name(input logic clk_i, output logic data_o);\n" + " assign data_o = clk_i;\n" + "endmodule\n", + ) + assert result.returncode == 1 + assert "RTL-FILE-002" in result.stderr + + +def test_owned_style_rejects_synthesizable_initial_block(tmp_path: Path) -> None: + result = run_style( + tmp_path, + "module test(input logic clk_i, output logic data_o);\n" + " initial begin\n" + " data_o = clk_i;\n" + " end\n" + "endmodule\n", + ) + assert result.returncode == 1 + assert "RTL-SV-007" in result.stderr + + +def test_owned_style_allows_verification_only_initial_block(tmp_path: Path) -> None: + result = run_style( + tmp_path, + "module test(input logic clk_i, output logic data_o);\n" + " assign data_o = clk_i;\n" + "`ifndef SYNTHESIS\n" + " initial begin\n" + " if (clk_i) $error(\"unexpected clock\");\n" + " end\n" + "`endif\n" + "endmodule\n", + ) + assert result.returncode == 0, result.stderr + + +def test_owned_style_rejects_unpaired_format_directive(tmp_path: Path) -> None: + result = run_style( + tmp_path, + "module test(input logic clk_i, output logic data_o);\n" + " // verilog_format: on\n" + " assign data_o = clk_i;\n" + "endmodule\n", + ) + assert result.returncode == 1 + assert "RTL-FMT-005" in result.stderr + + +def test_owned_style_requires_formatter_exception_rationale(tmp_path: Path) -> None: + result = run_style( + tmp_path, + "module test(input logic clk_i, output logic data_o);\n" + " // verilog_format: off\n" + " assign data_o = clk_i;\n" + " // verilog_format: on\n" + "endmodule\n", + ) + assert result.returncode == 1 + assert "RTL-FMT-007" in result.stderr + + +def test_owned_style_requires_automatic_typed_functions(tmp_path: Path) -> None: + result = run_style( + tmp_path, + "module test(input logic clk_i, output logic data_o);\n" + " function logic invert(input logic value_i);\n" + " return !value_i;\n" + " endfunction\n" + " assign data_o = invert(clk_i);\n" + "endmodule\n", + ) + assert result.returncode == 1 + assert "RTL-SV-008" in result.stderr + + +def test_owned_style_audit_matches_current_inventory() -> None: + audit = json.loads(AUDIT.read_text(encoding="utf-8")) + assert audit["schema_version"] == 1 + assert audit["policy"] == "docs/rtl-coding-style.md" + assert audit["profile"] == "owned" + assert { + "owner", + "related_commit", + "expiry", + "removal_plan", + }.issubset(audit["reviewed_boundary_record"]) + + audited_paths = { + str(Path(directory) / name) + for directory, names in audit["inventory"].items() + for name in names + } + actual_paths = { + str(path.relative_to(ROOT)) + for root in (ROOT / "rtl/ip", ROOT / "rtl/mini/top") + for path in root.rglob("*") + if path.is_file() and path.suffix in {".sv", ".svh"} + } + assert audited_paths == actual_paths + assert { + "RTL-FILE", + "RTL-SV", + "RTL-NAME", + "RTL-STRUCT", + "RTL-COMB", + "RTL-SEQ", + "RTL-WIDTH", + "RTL-CDC", + "RTL-VERIFY", + "RTL-FMT", + }.issubset({rule["id"] for rule in audit["rules"]}) diff --git a/tests/test_script_tools.py b/tests/test_script_tools.py index 7a3ae716..33bbccf8 100644 --- a/tests/test_script_tools.py +++ b/tests/test_script_tools.py @@ -246,7 +246,7 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non i2c = parse_filelists([i2c_filelist], require_files=False) clint = parse_filelists([clint_filelist], require_files=False) assert "+define+SV_ASSRT_DISABLE" in bus.defines - assert ROOT / "rtl/mini/top/bus.sv" in bus.files + assert ROOT / "rtl/mini/top/rib_bus.sv" in bus.files assert ROOT / "rtl/mini/top/rib_if.sv" in bus.files assert ROOT / "rtl/mini/top/ribp2rib.sv" in bus.files assert ROOT / "rtl/mini/top/rib_error_slave.sv" in bus.files @@ -256,10 +256,11 @@ def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> Non assert ROOT / "rtl/mini/top/rib2apb.sv" in rib2apb.files assert ROOT / "rtl/mini/formal/rib2apb_formal.sv" in rib2apb.files assert ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv" in rib2apb.files - assert ROOT / "rtl/ip/peripheral/sysctrl.sv" in sysctrl.files + assert ROOT / "rtl/ip/peripheral/ribp_sysctrl.sv" in sysctrl.files assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_sync.sv" in sysctrl.files assert ROOT / "rtl/mini/formal/sysctrl_formal.sv" in sysctrl.files assert ROOT / "rtl/mini/top/rcu.sv" in pll_rcu.files + assert ROOT / "rtl/mini/top/pll_rcu_controller.sv" in pll_rcu.files assert ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv" in pll_rcu.files assert ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv" in pll_rcu.files assert ROOT / "rtl/ip/peripheral/gpio_core.sv" in gpio.files @@ -586,7 +587,7 @@ def test_format_file_scope_is_tracked_and_self_owned() -> None: Path("Makefile"), Path("configs/ci/example.mk"), Path("rtl/mini/top/retrosoc.sv"), - Path("rtl/ip/peripheral/sysctrl.sv"), + Path("rtl/ip/peripheral/ribp_sysctrl.sv"), Path("rtl/tech/tc_clk.sv"), Path("rtl/demo/reference.v"), Path("tests/rtl/bus_fault_tb.sv"), @@ -601,7 +602,7 @@ def test_format_file_scope_is_tracked_and_self_owned() -> None: ] assert format_files(paths, "rtl") == [ Path("rtl/demo/reference.v"), - Path("rtl/ip/peripheral/sysctrl.sv"), + Path("rtl/ip/peripheral/ribp_sysctrl.sv"), Path("rtl/mini/top/retrosoc.sv"), Path("rtl/tech/tc_clk.sv"), Path("tests/rtl/bus_fault_tb.sv"), diff --git a/tests/test_sdram.py b/tests/test_sdram.py index 144577e8..3750b41d 100644 --- a/tests/test_sdram.py +++ b/tests/test_sdram.py @@ -43,7 +43,7 @@ def test_sdram_controller_preserves_full_and_masked_writes(tmp_path: Path) -> No str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), str(ROOT / "rtl/mini/top/axi42ribp_burst.sv"), str(ROOT / "rtl/mini/top/ribp_arbiter2.sv"), - str(ROOT / "rtl/ip/memory/sdram.sv"), + str(ROOT / "rtl/ip/memory/axi4_sdram.sv"), str(ROOT / "rtl/ip/memory/sdram_clkgen.sv"), str(ROOT / "rtl/ip/memory/sdram_reg.sv"), str(ROOT / "rtl/ip/memory/sdram_core.sv"), @@ -109,7 +109,7 @@ def test_sdram_controller_preserves_data_with_micron_timing_model(tmp_path: Path str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), str(ROOT / "rtl/mini/top/axi42ribp_burst.sv"), str(ROOT / "rtl/mini/top/ribp_arbiter2.sv"), - str(ROOT / "rtl/ip/memory/sdram.sv"), + str(ROOT / "rtl/ip/memory/axi4_sdram.sv"), str(ROOT / "rtl/ip/memory/sdram_clkgen.sv"), str(ROOT / "rtl/ip/memory/sdram_reg.sv"), str(ROOT / "rtl/ip/memory/sdram_core.sv"), diff --git a/tests/test_ws2812.py b/tests/test_ws2812.py index 2a81879d..fc221802 100644 --- a/tests/test_ws2812.py +++ b/tests/test_ws2812.py @@ -100,7 +100,7 @@ def test_ws2812_accepts_dma_fixed_destination_backpressure(tmp_path: Path) -> No str(ROOT / "rtl/mini/top/rib_if.sv"), str(common / "utils/register.sv"), str(common / "utils/fifo.sv"), - str(ROOT / "rtl/ip/peripheral/dma.sv"), + str(ROOT / "rtl/ip/peripheral/ribp_dma.sv"), str(ROOT / "rtl/ip/peripheral/dma_core.sv"), str(serial / "ws2812_if.sv"), str(serial / "ws2812_reg.sv"), diff --git a/tests/test_xpi_io.py b/tests/test_xpi_io.py index a1490bd4..3c965432 100644 --- a/tests/test_xpi_io.py +++ b/tests/test_xpi_io.py @@ -39,7 +39,7 @@ def test_xpi_releases_data_pads_while_receiving(tmp_path: Path) -> None: f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}", str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), - str(ROOT / "rtl/ip/storage/xpi.sv"), + str(ROOT / "rtl/ip/storage/ribp_xpi.sv"), str(ROOT / "rtl/ip/storage/xpi_clkgen.sv"), str(ROOT / "rtl/ip/storage/xpi_core.sv"), str(ROOT / "tests/rtl/xpi_io_tb.sv"),