diff --git a/AGENTS.md b/AGENTS.md index 7ffd5a89..cf951102 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -22,7 +22,7 @@ truth wins. records approved Required-rule deviations. - [crt/README.md](crt/README.md) defines the freestanding RISC-V runtime and SDK layout; [app/README.md](app/README.md) defines application composition. -- `Makefile`, `rtl/mini/mk/software.mk`, committed `configs/*.mk`, and the +- `Makefile`, `rtl/mk/software.mk`, committed `configs/*.mk`, and the GitHub workflows define the active build and regression behavior. - `quality/embedded_c_policy.json`, `quality/warnings/`, and `quality/metrics/policy.json` define the active quality policy. @@ -77,7 +77,9 @@ README that states its ownership, source of truth, and validation expectations. `bringup`, `debug`, and `shell`; each profile is declared in `app/apps//app.mk`. The `debug` application is an RTL debug-transport acceptance image, not a user-facing firmware profile. -- Do not add new dependencies on `crt/inc`, retired `tiny` names, or legacy +- Tiny is a distinct wired MCU product under `rtl/tiny`; `SOC=TINY` selects its + IHP130 profile and AXI4/APB4 integration. +- Do not add new dependencies on `crt/inc`, retired SDK `tiny` names, or legacy `rs_*.h`/`tiny*.h` include paths. - Treat `app/coremark/coremark-main`, `app/fatfs/ff16`, `app/lvgl/lvgl-main`, and managed ports as third-party or managed code. Update them through their diff --git a/Makefile b/Makefile index 2f2a9328..38eb7c69 100644 --- a/Makefile +++ b/Makefile @@ -29,7 +29,7 @@ $(error HAVE_DEBUG has been removed; the Hazard3 Debug Module is always enabled) endif SOC ?= MINI -MINI_MODE ?= PRODUCT +MINI_MODE ?= $(if $(filter MINI,$(SOC)),PRODUCT,NONE) SIMU ?= VCS SYNTH ?= NONE SYNTH_RECIPE ?= balanced @@ -44,7 +44,7 @@ SRAM_SIZE_KIB ?= $(if $(filter ICS55,$(PDK)),128,32) PDK_BEHAV ?= NO HAVE_SVA ?= NO APU_ENABLE_P7 ?= NO -HAVE_HP ?= YES +HAVE_HP ?= $(if $(filter TINY,$(SOC)),NO,YES) HP_CONFIG ?= rv64imafdc_zicbom_max BUILD_RELEASE ?= NO JTAG_IDCODE ?= DEADBEEF @@ -65,7 +65,7 @@ RTL_SIM_TIMEOUT ?= -1 SIM_FIRMWARE_NAME ?= $(FIRMWARE_NAME) SIM_SUCCESS_MARKER ?= SIM_TEST_PASS -RTL_PATH := $(ROOT_PATH)/rtl/mini +RTL_PATH := $(ROOT_PATH)/rtl/$(shell printf '%s' '$(SOC)' | tr '[:upper:]' '[:lower:]') RTL_TOP ?= retrosoc_tb @@ -218,8 +218,8 @@ else FLOW_FILELIST_DIR := $(SIM_BUILD_ROOT)/filelists endif -VALID_SOC := MINI -VALID_MINI_MODE := PRODUCT MPW +VALID_SOC := MINI TINY +VALID_MINI_MODE := PRODUCT MPW NONE VALID_SIMU := VCS VERILATOR IVERILOG VALID_SYNTH := NONE YOSYS VALID_SYNTH_RECIPE := balanced area speed @@ -282,11 +282,18 @@ $(error NPU_P5_ACCEPTANCE and NPU_P6_ACCEPTANCE are mutually exclusive) endif endif +ifeq ($(SOC),MINI) +ifeq ($(MINI_MODE),NONE) +$(error SOC=MINI requires MINI_MODE=PRODUCT or MPW) +endif ifeq ($(MINI_MODE),PRODUCT) ifneq ($(HAVE_HP),YES) $(error MINI_MODE=PRODUCT requires HAVE_HP=YES) endif endif +else +include $(ROOT_PATH)/rtl/tiny/mk/config.mk +endif MISSING_LOCAL_RTL_FILES := $(filter-out $(wildcard $(LOCAL_RTL_FILES)),$(LOCAL_RTL_FILES)) ifneq ($(strip $(MISSING_LOCAL_RTL_FILES)),) @@ -395,7 +402,9 @@ ifeq ($(APU_ENABLE_P7), YES) DEF_LIST += +define+APU_ENABLE_P7 endif -ifeq ($(MINI_MODE), PRODUCT) +ifeq ($(SOC), TINY) + DEF_LIST += +define+RETROSOC_SOC__TINY +else ifeq ($(MINI_MODE), PRODUCT) DEF_LIST += +define+MINI_PRODUCT else DEF_LIST += +define+MINI_MPW @@ -405,8 +414,10 @@ ifeq ($(SYNTH), YOSYS) DEF_LIST += +define+SYNTHESIS endif -include rtl/mini/Makefile +include $(RTL_PATH)/Makefile +ifeq ($(SOC),MINI) include rtl/mini/mk/formal.mk +endif ifeq ($(SIMU),IVERILOG) PERF_LOG ?= $(IVERILOG_BEHV_DIR)/sim.log @@ -416,15 +427,21 @@ endif ifeq ($(SYNTH), YOSYS) include physical/smoke/syn/yosys/yosys.mk +ifeq ($(SOC),MINI) include physical/smoke/syn/yosys/ga2d_block.mk include physical/smoke/syn/yosys/apu_block.mk endif +endif ifeq ($(STA), OPENSTA) include physical/smoke/sta/opensta/opensta.mk endif -include physical/librelane/Makefile +ifeq ($(SOC),TINY) +include physical/librelane/tiny/Makefile +else +include physical/librelane/mini/Makefile +endif include physical/ecc/Makefile .PHONY: crypto-p0-constants crypto-p0-rtl crypto-p0-baseline crypto-p0-report @@ -486,7 +503,7 @@ crypto-p2-report: manifest apu-block-filelist apu-block-synth apu-block-sta apu-block-report apu-block-evidence apu-block-clean \ pin-map check-pin-map soc-topology check-soc-topology user-extensions check-user-extensions \ check-clock-reset-domains tech-cell-test rtl-lint check-rtl-lint \ - formal formal-bus formal-rib-adapter formal-rib2apb formal-gpio formal-ws2812 formal-uart formal-i2c formal-timer formal-dvp formal-i2s formal-onchip-ram formal-opipsram formal-dma formal-apu formal-apu-kws formal-apu-p9 formal-gateway-a formal-sdio formal-clean formal-doctor \ + formal formal-bus formal-rib-adapter formal-rib2apb formal-gpio formal-ws2812 formal-uart formal-i2c formal-timer formal-dvp formal-i2s formal-onchip-ram formal-opipsram formal-dma formal-apu formal-apu-kws formal-apu-p9 formal-gateway-a formal-sdio formal-clean formal-doctor \ rtl-style-check-all rtl-readiness-check rtl-readiness-check-all vexii-generate .NOTPARALLEL: setup @@ -619,7 +636,7 @@ config: doctor: @python3 $(ROOT_PATH)/scripts/doctor.py \ --root $(ROOT_PATH) --simu $(SIMU) --synth $(SYNTH) --sta $(STA) \ - --pdk $(PDK) --have-sram-macro $(HAVE_SRAM_MACRO) \ + --pdk $(PDK) --soc $(SOC) --have-sram-macro $(HAVE_SRAM_MACRO) \ --formal $(FORMAL) --lock $(LOCK_FILE) benchmark-report: firmware @@ -641,7 +658,13 @@ hp-performance-check: --lp $(LP_COREMARK_REPORT) --hp $(HP_COREMARK_REPORT) \ --minimum-ratio $(HP_PERF_MIN_RATIO) --output $(META_DIR)/lp-hp-performance.json +ifeq ($(SOC),TINY) +setup: setup-tiny +setup-tiny: + python3 $(ROOT_PATH)/scripts/setup_tiny.py +else setup: setup-mpw setup-vexiiriscv setup-clusterip setup-ip setup-pdk setup-app +endif setup-regression: $(MAKE) CONFIG=configs/ci/ihp130.mk setup @@ -1158,19 +1181,22 @@ commercial-package: $(MPW_VARIANT_DEP) $(FILELIST_STAMP) manifest --variant-root $(VARIANT_ROOT) --output-dir $(VARIANT_ROOT)/commercial/input regress-smoke: - python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite smoke --pdk IHP130 + python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite smoke --pdk IHP130 $(if $(filter TINY,$(SOC)),--soc TINY) regress-rtl: - python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite rtl --pdk IHP130 + python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite rtl --pdk IHP130 $(if $(filter TINY,$(SOC)),--soc TINY) regress-pr: - python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr --pdk IHP130 $(if $(filter YES,$(REGRESS_NETSIM_BOOT_ONLY)),--netsim-boot-only) + python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr --pdk IHP130 $(if $(filter TINY,$(SOC)),--soc TINY) $(if $(filter YES,$(REGRESS_NETSIM_BOOT_ONLY)),--netsim-boot-only) +ifneq ($(SOC),TINY) python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr --pdk GF180 $(if $(filter YES,$(REGRESS_NETSIM_BOOT_ONLY)),--netsim-boot-only) python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr --pdk SKY130 $(if $(filter YES,$(REGRESS_NETSIM_BOOT_ONLY)),--netsim-boot-only) python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr --pdk ICS55 $(if $(filter YES,$(REGRESS_NETSIM_BOOT_ONLY)),--netsim-boot-only) +endif + regress-nightly: - python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite nightly + python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite nightly $(if $(filter TINY,$(SOC)),--soc TINY) sim-asm: asm $(MAKE) SIM_FIRMWARE_NAME=$(ASM_FIRMWARE_NAME) sim diff --git a/README.md b/README.md index 1bea8428..cce7bc5f 100644 --- a/README.md +++ b/README.md @@ -66,6 +66,19 @@ under the [Mulan Permissive Software License, Version 2](LICENSE). ## Repository Layout +**Mini and Tiny have independent integration flows.** Mini combines a +low-power Hazard3 management hart and a VexiiRiscv application hart; its separate +MPW profile retains selectable-core compatibility. [Tiny](docs/ip/tiny-soc.md) +is a wired MCU with one Hazard3 RV32IMC hart, 128 KiB SRAM, AXI4/APB4 and no +wireless IP. Tiny first targets IHP130; [Std and Pro](docs/soc-family-positioning.md) +remain roadmap products. Qualification is determined by each profile's retained +verification and physical reports. + +The [Tiny Gen1 datasheet](publications/datasheets/tiny/README.md) provides the +independent product, register, software and evidence reference using the +established publication layout. Its build does not require Mini's HP or +multimedia inputs. + | Path | Contents | | --- | --- | | [`rtl/`](rtl) | SoC RTL, CPU integration, peripherals, interfaces, testbenches, and technology wrappers. | @@ -209,6 +222,40 @@ Select the interactive shell application without editing source files: make CONFIG=configs/ci/ihp130-shell.mk firmware ``` +### Build and simulate Tiny + +```sh +make CONFIG=configs/ci/ihp130-tiny.mk setup +make CONFIG=configs/ci/ihp130-tiny.mk doctor +make CONFIG=configs/ci/ihp130-tiny.mk firmware sim +make CONFIG=configs/ci/ihp130-tiny.mk SIMU=IVERILOG firmware sim +``` + +Tiny uses its own source lists and product maps under `rtl/tiny`. Its firmware +loads into on-chip SRAM without PSRAM/SDRAM initialization. The first release +uses a fixed 24 MHz clock and disables atomic instructions. Wireless, external +RAM, HP cores, accelerators and advanced low-power modes remain deferred. + +## Configurations and common flows + +Start from a [committed profile](configs/README.md). These are selected entry +points, not the complete profile or application inventory. + +| Profile | Purpose | +| --- | --- | +| [IHP130 Tiny](configs/ci/ihp130-tiny.mk) | Single-hart wired MCU, 128 KiB SRAM, pin-level Flash boot and automated acceptance. | +| [IHP130 Mini](configs/ci/ihp130.mk) | Manual bring-up with 32 KiB macro-backed SRAM. | +| [GF180](configs/ci/gf180.mk) / [SKY130](configs/ci/sky130.mk) | Alternative PDK profiles with 32 KiB macro-backed SRAM. | +| [ICS55](configs/ci/ics55.mk) | Regression-compatible profile with SRAM and PLL disabled. | +| [Interactive shell](configs/ci/ihp130-shell.mk) | Shell firmware with CSR support enabled. | +| [Hazard3 debug](configs/ci/ihp130-debug.mk) | JTAG acceptance using Verilator, OpenOCD, and GDB. | +| [HP Linux](configs/ci/ihp130-hp.mk) | HP image/bundle flow; outside the supported PR matrix. | +| [APU LP/HP](configs/ci/ihp130-apu.mk) | Audio and KWS evidence flow with ownership handoff to HP. | +| [CoreMark](configs/benchmark/ihp130-hazard3-coremark.mk) | Fixed LP SRAM benchmark with the product HP core present. | +| [Mini MPW](configs/cluster/mini-mpw.mk) | Legacy C0-C3/user-IP compatibility, separate from the product ABI. | + +After the corresponding setup, use these common commands: + ## Common Flows All commands use a committed profile. `make config` prints the effective configuration and diff --git a/app/README.md b/app/README.md index 3121d2a7..ccda5e6d 100644 --- a/app/README.md +++ b/app/README.md @@ -146,3 +146,10 @@ make regress-nightly See the [repository README](../README.md) for prerequisites, supported configurations, and build artifact locations. + +For `SOC=TINY`, `bringup` and `ci_smoke` use the MCU acceptance composition. It +boots through XPI into SRAM, checks CPU C/A behavior and bus exceptions, DMA +(including UART requests), interrupts, RTC, GPIO, UART1 and I2C error completion, +then verifies watchdog reset by completing after the next NOR boot. It uses +SYSCTRL terminal status. The small `asm/tiny_boot.S` image separately qualifies +the synthesized SRAM/pad path; it is not a replacement for the full RTL test. diff --git a/app/apps/bringup/tiny.mk b/app/apps/bringup/tiny.mk new file mode 100644 index 00000000..fd133f66 --- /dev/null +++ b/app/apps/bringup/tiny.mk @@ -0,0 +1,3 @@ +APP_SRCS += $(ROOT_PATH)/app/apps/ci_smoke/tiny.c +APP_CFLAGS += -Os +APP_SRCS += $(ROOT_PATH)/app/apps/ci_smoke/mcu_acceptance.S \ No newline at end of file diff --git a/app/apps/ci_smoke/mcu_acceptance.S b/app/apps/ci_smoke/mcu_acceptance.S new file mode 100644 index 00000000..2da87716 --- /dev/null +++ b/app/apps/ci_smoke/mcu_acceptance.S @@ -0,0 +1,31 @@ +/* Copyright (c) 2026 Yuchi Miao; SPDX-License-Identifier: MulanPSL-2.0 */ + .section .text + .balign 4 + .global rs_mcu_compressed_probe + .type rs_mcu_compressed_probe,@function +rs_mcu_compressed_probe: + .option push + .option rvc + c.li a0, 21 + c.slli a0, 1 + c.jr ra + .option pop + .size rs_mcu_compressed_probe, .-rs_mcu_compressed_probe + + .balign 4 + .global rs_mcu_atomic_probe + .type rs_mcu_atomic_probe,@function +rs_mcu_atomic_probe: + /* lr.w a0,(a0): must trap because the Tiny A extension is disabled. */ + .word 0x1005252f + ret + .size rs_mcu_atomic_probe, .-rs_mcu_atomic_probe + + .balign 4 + .global rs_mcu_unmapped_probe + .type rs_mcu_unmapped_probe,@function +rs_mcu_unmapped_probe: + li a0, 0x38000000 + lw a0, 0(a0) + ret + .size rs_mcu_unmapped_probe, .-rs_mcu_unmapped_probe diff --git a/app/apps/ci_smoke/mcu_acceptance.h b/app/apps/ci_smoke/mcu_acceptance.h new file mode 100644 index 00000000..3f05d234 --- /dev/null +++ b/app/apps/ci_smoke/mcu_acceptance.h @@ -0,0 +1,10 @@ +#ifndef RETROSOC_MCU_ACCEPTANCE_H +#define RETROSOC_MCU_ACCEPTANCE_H + +#include + +uint32_t rs_mcu_compressed_probe(void); +void rs_mcu_atomic_probe(uint32_t *address); +void rs_mcu_unmapped_probe(void); + +#endif diff --git a/app/apps/ci_smoke/tiny.c b/app/apps/ci_smoke/tiny.c new file mode 100644 index 00000000..a4ebef1e --- /dev/null +++ b/app/apps/ci_smoke/tiny.c @@ -0,0 +1,278 @@ +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mcu_acceptance.h" + +static _Alignas(64) uint32_t rs_mcu_source[80]; +static _Alignas(64) uint32_t rs_mcu_destination[80]; +static volatile uint32_t rs_mcu_irq_count; +static volatile uint32_t rs_mcu_exception_count; +static volatile bool rs_mcu_handler_failed; + +static void rs_mcu_finish(bool pass, uint8_t code) { + printf("Tiny acceptance %s code=%u\n", pass ? "passed" : "failed", code); + rs_sysctrl_write_test_status(pass, code); + /* The terminal status must retain the first accepted full-word write. */ + rs_sysctrl_write_test_status(!pass, UINT8_C(255)); + for (;;) { + } +} + +static void rs_mcu_exception(uintptr_t mcause, uintptr_t stack_pointer) { + volatile uint32_t *const frame = (volatile uint32_t *)stack_pointer; + + if ((mcause != UINT32_C(2)) && (mcause != UINT32_C(5))) { + rs_mcu_handler_failed = true; + } + ++rs_mcu_exception_count; + /* system_irq.S saves MEPC in slot 11 of the RV32 trap frame. Both test + * instructions are explicitly 32 bits; normal exceptions do not use this handler. */ + frame[11] += UINT32_C(4); +} + +static void rs_mcu_timer_irq(uintptr_t mcause, uintptr_t stack_pointer) { + (void)mcause; + (void)stack_pointer; + ++rs_mcu_irq_count; + if (rs_timer_interrupt_clear(RS_TIMER_0, RS_TIMER_INTERRUPT_ALL) != RS_OK) { + rs_mcu_handler_failed = true; + } +} + +static bool rs_mcu_dma(void) { + rs_dma_config_t config = { + .kind = RS_DMA_KIND_MM_TO_MM, + .request = RS_DMA_REQUEST_SOFTWARE, + .source = (uintptr_t)rs_mcu_source, + .destination = (uintptr_t)rs_mcu_destination, + .byte_count = UINT32_C(259), + .width = RS_DMA_WIDTH_32, + .source_increment = true, + .destination_increment = true, + .priority = 0U, + .burst_beats = 16U, + }; + + for (uint32_t index = 0U; index < 80U; ++index) { + rs_mcu_source[index] = UINT32_C(0xa519c300) ^ index; + rs_mcu_destination[index] = UINT32_C(0xcccccccc); + } + if ((rs_dma_configure(4U, &config) != RS_EINVAL) || + (rs_dma_configure(RS_DMA_CHANNEL_BULK, &config) != RS_OK) || + (rs_dma_start(RS_DMA_CHANNEL_BULK) != RS_OK) || + (rs_dma_wait(RS_DMA_CHANNEL_BULK, RS_TIMEOUT_DEFAULT) != RS_OK)) { + return false; + } + for (uint32_t index = 0U; index < 64U; ++index) { + if (rs_mcu_source[index] != rs_mcu_destination[index]) { + return false; + } + } + if (rs_mcu_destination[64] != + ((rs_mcu_source[64] & UINT32_C(0x00ffffff)) | UINT32_C(0xcc000000))) { + return false; + } + config.kind = RS_DMA_KIND_MM_TO_STREAM; + config.request = RS_DMA_REQUEST_I2S_TX; + return rs_dma_config_validate(0U, &config) != RS_OK; +} + +static bool rs_mcu_interrupts(void) { + uint32_t timeout = UINT32_C(20000); + + if ((rs_irq_enable_external(RS_SOC_EXT_IRQ_TIMER0, rs_mcu_timer_irq) != RS_OK) || + (rs_timer_interrupt_enable(RS_TIMER_0, RS_TIMER_INTERRUPT_TIMEOUT) != RS_OK) || + (rs_timer_interrupt_test(RS_TIMER_0, RS_TIMER_INTERRUPT_TIMEOUT) != RS_OK)) { + return false; + } + __RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE); + while ((rs_mcu_irq_count == 0U) && (timeout != 0U)) { + --timeout; + } + __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE); + return (rs_mcu_irq_count == 1U) && !rs_mcu_handler_failed && + (rs_irq_disable_external(RS_SOC_EXT_IRQ_TIMER0) == RS_OK); +} + +static bool rs_mcu_io(void) { + const rs_gpio_config_t output = { + .mode = RS_GPIO_MODE_OUTPUT, + .pull = RS_GPIO_PULL_NONE, + .trigger = RS_GPIO_TRIGGER_NONE, + .output_high = false, + }; + const rs_uart_config_t loopback = { + .source_clock_hz = RS_CPU_CLOCK_HZ, + .baud_rate = UART_BPS, + .data_bits = 8U, + .stop_bits = 1U, + .parity = RS_UART_PARITY_NONE, + .rx_watermark = 1U, + .rx_timeout_bits = 16U, + .tx_enable = true, + .rx_enable = true, + .loopback_enable = true, + }; + const uint32_t transmit[4] = {UINT32_C(0x54), UINT32_C(0x49), UINT32_C(0x4e), UINT32_C(0x59)}; + uint32_t receive[4] = {0U}; + rs_uart_timing_t timing; + bool high; + uint32_t timeout = UINT32_C(10000); + uint8_t payload = UINT8_C(0x55); + const rs_i2c_transfer_t transfer = { + .address = UINT16_C(0x50), + .tx_data = &payload, + .tx_length = 1U, + }; + rs_i2c_status_t status; + + if ((rs_gpio_configure(15U, &output) != RS_OK) || (rs_gpio_write(15U, true) != RS_OK) || + (rs_gpio_read(15U, &high) != RS_OK) || !high || (rs_gpio_write(15U, false) != RS_OK) || + (rs_gpio_read(15U, &high) != RS_OK) || high) { + return false; + } + if ((rs_uart_configure(&loopback, RS_TIMEOUT_DEFAULT) != RS_OK) || + (rs_uart_write_dma(transmit, 4U, RS_TIMEOUT_DEFAULT) != RS_OK) || + (rs_uart_read_dma(receive, 4U, RS_TIMEOUT_DEFAULT) != RS_OK)) { + return false; + } + for (uint32_t index = 0U; index < 4U; ++index) { + if (transmit[index] != receive[index]) { + return false; + } + } + if ((rs_uart_init(RS_CPU_CLOCK_HZ, UART_BPS) != RS_OK) || + (rs_uart_timing_calculate(RS_CPU_CLOCK_HZ, UART_BPS, &timing) != RS_OK)) { + return false; + } + /* UART1 uses the same register ABI; the current shared high-level UART + * API selects UART0. Exercise UART1 PIO and its internal loopback here. */ + RS_SOC_REG32(RS_SOC_APB4_UART1_BASE, UINT32_C(0x00)) = timing.baud_integer; + RS_SOC_REG32(RS_SOC_APB4_UART1_BASE, UINT32_C(0x04)) = timing.baud_fraction; + RS_SOC_REG32(RS_SOC_APB4_UART1_BASE, UINT32_C(0x08)) = UINT32_C(3); + RS_SOC_REG32(RS_SOC_APB4_UART1_BASE, UINT32_C(0x0c)) = UINT32_C(7); + RS_SOC_REG32(RS_SOC_APB4_UART1_BASE, UINT32_C(0x10)) = UINT32_C(0x5a); + while (((RS_SOC_REG32(RS_SOC_APB4_UART1_BASE, UINT32_C(0x18)) & UINT32_C(0x40)) != 0U) && + (timeout != 0U)) { + --timeout; + } + if ((timeout == 0U) || ((RS_SOC_REG32(RS_SOC_APB4_UART1_BASE, UINT32_C(0x14)) & + UINT32_C(0xff)) != UINT32_C(0x5a))) { + return false; + } + /* There is no slave on the pulled-up acceptance board: a real address + * transaction must terminate as NACK rather than stick waiting on the bus. */ + for (uint32_t bus = 0U; bus < 2U; ++bus) { + const rs_i2c_bus_t instance = (bus == 0U) ? RS_I2C_BUS_0 : RS_I2C_BUS_1; + if ((rs_i2c_init(instance, RS_CPU_CLOCK_HZ, UINT32_C(100000)) != RS_OK) || + (rs_i2c_transfer(instance, &transfer, RS_TIMEOUT_DEFAULT) != RS_EIO) || + (rs_i2c_get_status(instance, &status) != RS_OK) || + ((status.errors & RS_I2C_ERROR_ADDR_NACK) == 0U)) { + return false; + } + } + return true; +} + +static bool rs_mcu_rtc(void) { + const rs_rtc_config_t config = { + .second_cycles = UINT32_C(4096), + .calibration_ppm = 0, + .interrupt_enable = 0U, + .wake_enable = 0U, + .enable = true, + }; + const rs_rtc_time_t value = {.seconds = UINT64_C(1234), .subsecond = 0U}; + rs_rtc_time_t observed; + + return (rs_rtc_probe() == RS_OK) && (rs_rtc_configure(&config, RS_TIMEOUT_DEFAULT) == RS_OK) && + (rs_rtc_set_time(&value, RS_TIMEOUT_DEFAULT) == RS_OK) && + (rs_rtc_get_time(&observed, RS_TIMEOUT_DEFAULT) == RS_OK) && + (observed.seconds >= value.seconds); +} + +int main(void) { + rs_archinfo_t info; + rs_onchip_sram_info_t memory; + rs_sysctrl_fault_status_t fault; + rs_watchdog_status_t watchdog; + uint64_t before; + uint64_t after; + const rs_watchdog_config_t watchdog_config = { + .prescale_divider = 1U, + .timeout_ticks = UINT32_C(20000), + .window_min_ticks = 0U, + .early_warning_ticks = 0U, + .window_enable = false, + .early_warning_enable = false, + .debug_freeze_enable = true, + }; + + if (rs_uart_init(RS_CPU_CLOCK_HZ, UART_BPS) != RS_OK) { + rs_mcu_finish(false, 1U); + } + printf("Hello retroSoC! Tiny MCU\n"); + if (rs_watchdog_get_status(&watchdog, RS_TIMEOUT_DEFAULT) != RS_OK) { + rs_mcu_finish(false, 2U); + } + if (watchdog.reset_count != 0U) { + rs_mcu_finish(true, 0U); + } + if ((rs_archinfo_read(&info) != RS_OK) || (rs_archinfo_validate_build(&info) != RS_OK) || + (info.soc_id != RS_SOC_ID) || (info.topology != UINT32_C(0x20200001)) || + (rs_onchip_sram_probe(&memory) != RS_OK) || (memory.memory_bytes != UINT32_C(131072)) || + (memory.data_bytes != 4U) || (memory.bank_count != 32U)) { + rs_mcu_finish(false, 3U); + } + if ((rs_mcu_compressed_probe() != 42U) || ((__RV_CSR_READ(CSR_MISA) & UINT32_C(1)) != 0U) || + (rs_irq_register_exception(2U, rs_mcu_exception) != RS_OK) || + (rs_irq_register_exception(5U, rs_mcu_exception) != RS_OK)) { + rs_mcu_finish(false, 4U); + } + rs_mcu_atomic_probe(rs_mcu_source); + rs_mcu_unmapped_probe(); + if ((rs_mcu_exception_count != 2U) || rs_mcu_handler_failed || + (rs_sysctrl_get_fault_status(&fault) != RS_OK) || !fault.pending || + (fault.address != UINT32_C(0x38000000)) || (rs_sysctrl_clear_fault() != RS_OK)) { + rs_mcu_finish(false, 5U); + } + if (!rs_mcu_dma()) { + rs_mcu_finish(false, 6U); + } + if ((rs_clint_get_time(&before) != RS_OK) || (rs_clint_get_time(&after) != RS_OK) || + (after <= before) || !rs_mcu_interrupts()) { + rs_mcu_finish(false, 7U); + } + if (!rs_mcu_rtc() || (rs_pwm_probe() != RS_OK) || + (rs_sysctrl_set_hp_release(true) != RS_ENOTSUP)) { + rs_mcu_finish(false, 8U); + } + if (!rs_mcu_io()) { + rs_mcu_finish(false, 10U); + } + printf("Tiny CPU/DMA/IRQ/RTC/I/O passed; exercising watchdog reset\n"); + if ((rs_watchdog_configure(&watchdog_config) != RS_OK) || + (rs_watchdog_start(RS_TIMEOUT_DEFAULT) != RS_OK)) { + rs_mcu_finish(false, 9U); + } + for (;;) { + } +} diff --git a/app/apps/ci_smoke/tiny.mk b/app/apps/ci_smoke/tiny.mk new file mode 100644 index 00000000..fd133f66 --- /dev/null +++ b/app/apps/ci_smoke/tiny.mk @@ -0,0 +1,3 @@ +APP_SRCS += $(ROOT_PATH)/app/apps/ci_smoke/tiny.c +APP_CFLAGS += -Os +APP_SRCS += $(ROOT_PATH)/app/apps/ci_smoke/mcu_acceptance.S \ No newline at end of file diff --git a/app/asm/tiny_boot.S b/app/asm/tiny_boot.S new file mode 100644 index 00000000..93accb14 --- /dev/null +++ b/app/asm/tiny_boot.S @@ -0,0 +1,58 @@ +/* Copyright (c) 2026 Yuchi Miao; SPDX-License-Identifier: MulanPSL-2.0 */ +#include "retrosoc/generated/memory_map.h" + +/* Small gate-level acceptance image. Executes through the real XPI pins, + * checks both ends of SRAM and byte strobes, then checks APB/UART/SYSCTRL. + * The full SDK/application acceptance runs separately in both RTL simulators. */ + .section .text + .global _start +_start: + li t0, RS_SOC_SRAM_BASE + li t1, 0x12345678 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, failed + li t0, RS_SOC_SRAM_END - 3 + sw t1, 0(t0) + li t2, 0xab + sb t2, 1(t0) + lw t2, 0(t0) + li t1, 0x1234ab78 + bne t1, t2, failed + + li s0, RS_SOC_APB4_UART0_BASE + li t0, 26 + sw t0, 0(s0) + li t0, 11 + sw t0, 4(s0) + li t0, 3 + sw t0, 8(s0) + sw t0, 12(s0) + la s1, message +print_loop: + lbu s2, 0(s1) + beqz s2, passed +wait_uart: + lw t0, 24(s0) + andi t0, t0, 32 + bnez t0, wait_uart + sw s2, 16(s0) + addi s1, s1, 1 + j print_loop +passed: + /* Let the serial output drain before setting the terminal verdict. */ + lw t0, 24(s0) + andi t0, t0, 4 + bnez t0, passed + li t0, RS_SOC_APB4_SYSCTRL_BASE + li t1, 0x80000001 + sw t1, RS_SOC_SYSCTRL_TEST_STATUS_OFFSET(t0) +halt: + j halt +failed: + li t0, RS_SOC_APB4_SYSCTRL_BASE + li t1, 0x80000100 + sw t1, RS_SOC_SYSCTRL_TEST_STATUS_OFFSET(t0) + j halt +message: + .asciz "Hello retroSoC! Tiny netlist boot\n" diff --git a/configs/README.md b/configs/README.md index a6096149..251b6212 100644 --- a/configs/README.md +++ b/configs/README.md @@ -51,3 +51,12 @@ macro must select either this mode or a qualified macro timing model. For supported profiles and commands, see the root [README](../README.md) and [agent contract](../AGENTS.md). + +## Tiny MCU + +`ci/ihp130-tiny.mk` selects `SOC=TINY`, one RV32IMC Hazard3 (A disabled), +128 KiB SRAM, AXI32/APB4, four DMA channels and the wired peripheral subset. +The profile uses 24 MHz, `HAVE_HP=NO`, `MINI_MODE=NONE`, CSR-enabled RV32IM +firmware and `ld2_all_sram`. Both `bringup` and `ci_smoke` select Tiny acceptance +firmware. Icarus and Verilator use the same pin-level Flash model. Other PDKs, +wireless, external RAM and HP applications are rejected by the Tiny config gate. diff --git a/configs/ci/ihp130-tiny.mk b/configs/ci/ihp130-tiny.mk new file mode 100644 index 00000000..af7ad6d3 --- /dev/null +++ b/configs/ci/ihp130-tiny.mk @@ -0,0 +1,18 @@ +SOC := TINY +MINI_MODE := NONE +PDK := IHP130 +SIMU := VERILATOR +HAVE_PLL := NO +HAVE_SRAM_IF := YES +HAVE_SRAM_MACRO := YES +SRAM_SIZE_KIB := 128 +HAVE_HP := NO +HAVE_SVA := NO +EXT_CLK_HZ := 24000000 +AUD_CLK_HZ := 24000000 +CLINT_TIMEBASE_HZ := 1000000 +ISA := RV32IM +HAVE_CSR := YES +APP := bringup +LINK_TYPE := ld2_all_sram +RTL_TOP := retrosoc_tiny_tb \ No newline at end of file diff --git a/crt/README.md b/crt/README.md index 5dddb374..dbd81f2f 100644 --- a/crt/README.md +++ b/crt/README.md @@ -167,7 +167,7 @@ on it. ## Build Integration The central software build assembles the runtime sources in -[`../rtl/mini/mk/software.mk`](../rtl/mini/mk/software.mk). It selects the +[`../rtl/mk/software.mk`](../rtl/mk/software.mk). It selects the RISC-V ISA, optional CSR interrupt support, linker layout, and the application profile. Applications add their own sources after the common runtime is selected. @@ -226,3 +226,17 @@ hardware validation. For the complete firmware, simulation, synthesis, and timing flow, see the [repository README](../README.md). + +## Product composition + +Tiny uses the same `rs_` SDK and selects its generated memory, IRQ and capability +headers through the committed profile. The generated memory-map header includes +Tiny capability metadata, so public DMA headers report four channels without +requiring an application to reproduce private compiler flags. Unavailable IP +drivers are omitted; Tiny SYSCTRL rejects unsupported lifecycle/PLL operations +before MMIO. Startup skips external-RAM initialization and loads into SRAM. + +`` provides `rs_watchdog_configure`, `rs_watchdog_start`, +`rs_watchdog_service`, `rs_watchdog_get_status` and `rs_watchdog_clear_reset_cause`, +with SDK status values and bounded command waits. These wrappers preserve the +locked watchdog register ABI. diff --git a/crt/arch/riscv/startup.S b/crt/arch/riscv/startup.S index 8f580d18..dc0789c5 100644 --- a/crt/arch/riscv/startup.S +++ b/crt/arch/riscv/startup.S @@ -17,6 +17,7 @@ _start: /* Direct Mode: All exceptions set pc to BASE */ csrc CSR_MTVEC, 0x3 #endif +#ifndef RS_SOC_TINY # wait psram reset done la a0, _flash_wait_start la a1, 2000 @@ -25,6 +26,8 @@ wait_psram_reset: addi a0, a0, 4 blt a0, a1, wait_psram_reset +#endif + # ===== Startup Stage 1 ===== # init the regfile # zero-initialize register file @@ -68,6 +71,7 @@ wait_psram_reset: # when code LMA is different with VMA # test: using psram before loading +#ifndef RS_SOC_TINY # Define the addresses .equ GPIO_ALT_ENABLE, RS_SOC_APB4_GPIO_ADMIN_BASE + 0x34 .equ GPIO_ALT_SELECT, RS_SOC_APB4_GPIO_ADMIN_BASE + 0x38 @@ -98,6 +102,8 @@ PSRAM_READY_WAIT: andi t1, t1, PSRAM_READY beqz t1, PSRAM_READY_WAIT +#endif + app_loader_start: la a0, _ram_lma la a1, _ram_vma diff --git a/crt/include/retrosoc/hal/dma_regs.h b/crt/include/retrosoc/hal/dma_regs.h index 85d7e855..ccf87f06 100644 --- a/crt/include/retrosoc/hal/dma_regs.h +++ b/crt/include/retrosoc/hal/dma_regs.h @@ -77,11 +77,15 @@ #define RS_DMA_ERROR_READ UINT32_C(0x00000040) #define RS_DMA_ERROR_STREAM_LAST UINT32_C(0x00000100) -#define RS_DMA_CHANNEL_COUNT 8U -#define RS_DMA_CHANNEL_HP 6U -#define RS_DMA_CHANNEL_RESERVED 7U -#define RS_DMA_MAX_BURST_BEATS 16U -#define RS_DMA_DATA_WIDTH_BITS 32U +#ifdef RS_SOC_TINY +#define RS_DMA_CHANNEL_COUNT 4U +#else +#define RS_DMA_CHANNEL_COUNT 8U +#endif +#define RS_DMA_CHANNEL_HP 6U +#define RS_DMA_CHANNEL_RESERVED 7U +#define RS_DMA_MAX_BURST_BEATS 16U +#define RS_DMA_DATA_WIDTH_BITS 32U #define RS_DMA_CHANNEL_OFFSET(channel, offset) \ (RS_DMA_CH_BASE + ((uint32_t)(channel)*RS_DMA_CH_STRIDE) + (offset)) diff --git a/crt/include/retrosoc/hal/watchdog.h b/crt/include/retrosoc/hal/watchdog.h index de5b28aa..caa6c7b4 100644 --- a/crt/include/retrosoc/hal/watchdog.h +++ b/crt/include/retrosoc/hal/watchdog.h @@ -1,5 +1,18 @@ #ifndef RETROSOC_WDG_H #define RETROSOC_WDG_H +#include + +#include + +typedef wdg_config_t rs_watchdog_config_t; +typedef wdg_snapshot_t rs_watchdog_status_t; + +rs_status_t rs_watchdog_configure(const rs_watchdog_config_t *config); +rs_status_t rs_watchdog_start(rs_timeout_t timeout); +rs_status_t rs_watchdog_service(rs_timeout_t timeout); +rs_status_t rs_watchdog_get_status(rs_watchdog_status_t *status, rs_timeout_t timeout); +rs_status_t rs_watchdog_clear_reset_cause(rs_timeout_t timeout); + void ip_wdg_test(int argc, char **argv); #endif diff --git a/crt/src/core/archinfo.c b/crt/src/core/archinfo.c index fdf385ff..cab76e0b 100644 --- a/crt/src/core/archinfo.c +++ b/crt/src/core/archinfo.c @@ -39,7 +39,20 @@ rs_status_t rs_archinfo_validate_build(const rs_archinfo_t *info) { .config_id = ARCHINFO_INTEGRATION_CONFIG_ID, }; +#ifdef RS_SOC_TINY + if ((info == NULL) || (info->soc_id != RS_SOC_ID) || + (info->component_id != ARCHINFO_COMPONENT_ID_VALUE) || + (info->ip_version != ARCHINFO_IP_VERSION_VALUE) || + (((info->capability & ARCHINFO_CAPABILITY_ABI_MASK) >> ARCHINFO_CAPABILITY_ABI_SHIFT) != + ARCHINFO_ABI_VERSION) || + (expectation.check_build_id && (info->build_id != expectation.build_id)) || + (info->config_id != expectation.config_id)) { + return RS_EFORMAT; + } + return RS_OK; +#else return rs_archinfo_status(archinfo_validate(info, &expectation)); +#endif } rs_status_t rs_archinfo_read_device_id(uint32_t device_id[4]) { diff --git a/crt/src/hal/dma_math.c b/crt/src/hal/dma_math.c index 6c74e12a..99c35ca6 100644 --- a/crt/src/hal/dma_math.c +++ b/crt/src/hal/dma_math.c @@ -18,6 +18,11 @@ static bool rs_dma_address_valid(uintptr_t address, uint32_t byte_count, bool in } static bool rs_dma_request_valid(const rs_dma_config_t *config) { +#ifdef RS_SOC_TINY + if (config->kind != RS_DMA_KIND_MM_TO_MM) { + return false; + } +#endif switch (config->kind) { case RS_DMA_KIND_MM_TO_MM: return (config->request == RS_DMA_REQUEST_SOFTWARE) || @@ -91,6 +96,11 @@ rs_status_t rs_dma_tcd_validate(uint32_t channel, const rs_dma_tcd_t *tcd) { kind = (tcd->control >> RS_DMA_TCD_KIND_SHIFT) & UINT32_C(0x7); request = (tcd->control >> RS_DMA_TCD_REQUEST_SHIFT) & UINT32_C(0xF); burst = (tcd->control >> RS_DMA_TCD_BURST_SHIFT) & UINT32_C(0x1F); +#ifdef RS_SOC_TINY + if (kind != (uint32_t)RS_DMA_KIND_MM_TO_MM) { + return RS_ENOTSUP; + } +#endif if ((kind > (uint32_t)RS_DMA_KIND_STREAM_TO_MM) || (request > (uint32_t)RS_DMA_REQUEST_CRYPTO_OUT) || (burst > RS_DMA_MAX_BURST_BEATS) || ((tcd->source & UINT32_C(0x3)) != UINT32_C(0)) || diff --git a/crt/src/hal/i2c.c b/crt/src/hal/i2c.c index f8acab29..48c59260 100644 --- a/crt/src/hal/i2c.c +++ b/crt/src/hal/i2c.c @@ -454,7 +454,7 @@ rs_status_t rs_i2c_write_dma(rs_i2c_bus_t bus, uint16_t address, bool ten_bit_ad const uint32_t channel = (bus == RS_I2C_BUS_0) ? RS_DMA_CHANNEL_I2C0 : RS_DMA_CHANNEL_I2C1; const rs_dma_request_t request = (bus == RS_I2C_BUS_0) ? RS_DMA_REQUEST_I2C0_TX : RS_DMA_REQUEST_I2C1_TX; - rs_dma_config_t dma_config; + rs_dma_config_t dma_config = {0}; if (!rs_i2c_bus_valid(bus) || (data == NULL) || (workspace == NULL) || (length == 0U) || (length > RS_I2C_DMA_MAX_BYTES)) { @@ -499,7 +499,7 @@ rs_status_t rs_i2c_read_dma(rs_i2c_bus_t bus, uint16_t address, bool ten_bit_add const uint32_t channel = (bus == RS_I2C_BUS_0) ? RS_DMA_CHANNEL_I2C0 : RS_DMA_CHANNEL_I2C1; const rs_dma_request_t request = (bus == RS_I2C_BUS_0) ? RS_DMA_REQUEST_I2C0_RX : RS_DMA_REQUEST_I2C1_RX; - rs_dma_config_t dma_config; + rs_dma_config_t dma_config = {0}; if (!rs_i2c_bus_valid(bus) || (data == NULL) || (workspace == NULL) || (length == 0U) || (length > RS_I2C_DMA_MAX_BYTES)) { diff --git a/crt/src/hal/sysctrl.c b/crt/src/hal/sysctrl.c index 5849ad07..7d150cfd 100644 --- a/crt/src/hal/sysctrl.c +++ b/crt/src/hal/sysctrl.c @@ -86,6 +86,12 @@ static rs_status_t rs_sysctrl_perf_offsets(rs_sysctrl_perf_counter_t counter, ui return RS_EINVAL; } +#ifdef RS_SOC_TINY + if ((counter != RS_SYSCTRL_PERF_MGMT_WAIT) && (counter != RS_SYSCTRL_PERF_DMA_WAIT)) { + return RS_ENOTSUP; + } +#endif + switch (counter) { case RS_SYSCTRL_PERF_MGMT_WAIT: *low_offset = RS_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET; @@ -215,6 +221,9 @@ rs_status_t rs_sysctrl_clear_user_core_config_error(void) { } rs_status_t rs_sysctrl_get_pll_config(uint8_t *selection) { +#ifdef RS_SOC_TINY + return RS_ENOTSUP; +#endif if (selection == NULL) { return RS_EINVAL; } @@ -224,6 +233,9 @@ rs_status_t rs_sysctrl_get_pll_config(uint8_t *selection) { } rs_status_t rs_sysctrl_set_pll_config(uint8_t selection) { +#ifdef RS_SOC_TINY + return RS_ENOTSUP; +#endif if (((uint32_t)selection & ~RS_SYSCTRL_PLL_SELECTION_MASK) != 0U) { return RS_EINVAL; } @@ -232,16 +244,25 @@ rs_status_t rs_sysctrl_set_pll_config(uint8_t selection) { } rs_status_t rs_sysctrl_apply_pll_config(void) { +#ifdef RS_SOC_TINY + return RS_ENOTSUP; +#endif *rs_sysctrl_register(RS_SYSCTRL_PLL_CMD_OFFSET) = RS_SYSCTRL_PLL_CMD_APPLY; return RS_OK; } rs_status_t rs_sysctrl_clear_pll_error(void) { +#ifdef RS_SOC_TINY + return RS_ENOTSUP; +#endif *rs_sysctrl_register(RS_SYSCTRL_PLL_CMD_OFFSET) = RS_SYSCTRL_PLL_CMD_CLEAR_ERROR; return RS_OK; } rs_status_t rs_sysctrl_get_pll_status(rs_sysctrl_pll_status_t *status) { +#ifdef RS_SOC_TINY + return RS_ENOTSUP; +#endif uint32_t value; if (status == NULL) { @@ -282,6 +303,9 @@ rs_status_t rs_sysctrl_clear_fault(void) { } rs_status_t rs_sysctrl_set_hp_release(bool release) { +#ifdef RS_SOC_TINY + return RS_ENOTSUP; +#endif rs_sysctrl_hp_status_t status; if ((rs_sysctrl_get_hp_status(&status) != RS_OK) || !status.present) { @@ -295,6 +319,9 @@ rs_status_t rs_sysctrl_set_hp_release(bool release) { } rs_status_t rs_sysctrl_get_hp_status(rs_sysctrl_hp_status_t *status) { +#ifdef RS_SOC_TINY + return RS_ENOTSUP; +#endif uint32_t value; if (status == NULL) { @@ -311,6 +338,9 @@ rs_status_t rs_sysctrl_get_hp_status(rs_sysctrl_hp_status_t *status) { } rs_status_t rs_sysctrl_select_hp_debug(bool select_hp) { +#ifdef RS_SOC_TINY + return RS_ENOTSUP; +#endif rs_sysctrl_hp_status_t status; uint32_t value; diff --git a/crt/src/hal/uart.c b/crt/src/hal/uart.c index 909776d6..88f92081 100644 --- a/crt/src/hal/uart.c +++ b/crt/src/hal/uart.c @@ -279,7 +279,7 @@ rs_status_t rs_uart_irq_test(uint32_t mask) { } rs_status_t rs_uart_write_dma(const uint32_t *words, size_t count, rs_timeout_t timeout) { - rs_dma_config_t config; + rs_dma_config_t config = {0}; size_t index; rs_status_t status; @@ -314,7 +314,7 @@ rs_status_t rs_uart_write_dma(const uint32_t *words, size_t count, rs_timeout_t } rs_status_t rs_uart_read_dma(uint32_t *words, size_t count, rs_timeout_t timeout) { - rs_dma_config_t config; + rs_dma_config_t config = {0}; rs_status_t status; if ((words == NULL) || (count == 0U) || (count > (UINT32_MAX / sizeof(*words)))) { diff --git a/crt/src/hal/watchdog.c b/crt/src/hal/watchdog.c index f93e90dc..6ae4ed3f 100644 --- a/crt/src/hal/watchdog.c +++ b/crt/src/hal/watchdog.c @@ -7,6 +7,41 @@ #define RS_WDG_COMMAND_TIMEOUT UINT32_C(1024) +static rs_status_t rs_watchdog_status(wdg_status_t status) { + switch (status) { + case WDG_STATUS_OK: + return RS_OK; + case WDG_STATUS_INVALID_ARGUMENT: + return RS_EINVAL; + case WDG_STATUS_TIMEOUT: + return RS_ETIMEOUT; + case WDG_STATUS_INCOMPATIBLE: + return RS_EFORMAT; + default: + return RS_EIO; + } +} + +rs_status_t rs_watchdog_configure(const rs_watchdog_config_t *config) { + return rs_watchdog_status(wdg_configure((uintptr_t)RS_SOC_APB4_WDG_BASE, config)); +} + +rs_status_t rs_watchdog_start(rs_timeout_t timeout) { + return rs_watchdog_status(wdg_start((uintptr_t)RS_SOC_APB4_WDG_BASE, timeout)); +} + +rs_status_t rs_watchdog_service(rs_timeout_t timeout) { + return rs_watchdog_status(wdg_service((uintptr_t)RS_SOC_APB4_WDG_BASE, timeout)); +} + +rs_status_t rs_watchdog_get_status(rs_watchdog_status_t *status, rs_timeout_t timeout) { + return rs_watchdog_status(wdg_snapshot((uintptr_t)RS_SOC_APB4_WDG_BASE, status, timeout)); +} + +rs_status_t rs_watchdog_clear_reset_cause(rs_timeout_t timeout) { + return rs_watchdog_status(wdg_clear_reset_cause((uintptr_t)RS_SOC_APB4_WDG_BASE, timeout)); +} + void ip_wdg_test(int argc, char **argv) { static const wdg_config_t config = { .prescale_divider = 1U, diff --git a/docs/README.md b/docs/README.md index a424cf1e..d977a1ec 100644 --- a/docs/README.md +++ b/docs/README.md @@ -3,6 +3,9 @@ This directory contains repository-level engineering policy that supplements the root README and subsystem guides. +- [Tiny MCU](ip/tiny-soc.md) defines the independent wired Tiny product, AXI4/APB4, SRAM-only startup and IHP130 acceptance. +- [Tiny Gen1 datasheet](../publications/datasheets/tiny/README.md) describes the independently built product, register, software and qualification-boundary reference. + - [Contributing](../CONTRIBUTING.md) describes community discussion, development, review, validation evidence, and maintainer responsibilities. - [git-workflow.md](git-workflow.md) defines branch and commit conventions, diff --git a/docs/engineering.md b/docs/engineering.md index 91d21250..d0db8885 100644 --- a/docs/engineering.md +++ b/docs/engineering.md @@ -4,6 +4,7 @@ | Tier | Profile | Automated coverage | | --- | --- | --- | +| Pull request | `configs/ci/ihp130-tiny.mk` | Tiny firmware, Verilator/Icarus, lint; local Yosys, netlist and OpenSTA | | Smoke | `configs/ci/ihp130.mk` | strict Verilator RTL lint, firmware, Verilator SVA compilation, Icarus assembly self-test | | Pull request | `configs/ci/ihp130.mk` | strict Verilator RTL lint, firmware, Verilator, Icarus | | Pull request | `configs/ci/ihp130-debug.mk` | Verilator remote-bitbang JTAG DTM, Debug Module, OpenOCD, and GDB acceptance | diff --git a/docs/ip/README.md b/docs/ip/README.md index 8af7ebef..b204f619 100644 --- a/docs/ip/README.md +++ b/docs/ip/README.md @@ -4,6 +4,8 @@ This directory owns architecture, register ABI, software contract, and verification documentation for self-owned retroSoC peripheral IP and platform extension interfaces. +- [Tiny MCU](tiny-soc.md) defines the independent wired Tiny product, AXI4/APB4, SRAM-only startup and IHP130 acceptance. + - [timer.md](timer.md) defines the dual APB4 general timer. - [sysctrl.md](sysctrl.md) defines the APB4 SystemCtrl register ABI, control-plane contracts, HAL, and verification. - [resource-controller.md](resource-controller.md) defines root-managed resource ownership, IRQ routing, and cache-maintenance handoff. diff --git a/docs/ip/tiny-soc-verification.md b/docs/ip/tiny-soc-verification.md new file mode 100644 index 00000000..bb5447f9 --- /dev/null +++ b/docs/ip/tiny-soc-verification.md @@ -0,0 +1,146 @@ +# Tiny MCU Verification Record + +This record accompanies the [frozen Tiny contract](tiny-soc.md). It describes +local implementation evidence from 2026-09-25, not a release or silicon signoff. +The working tree is uncommitted and the readiness status remains `prototype`. + +## Configuration and artifact roots + +The selected profile is `configs/ci/ihp130-tiny.mk`: IHP130, 128 KiB SRAM, +24 MHz, RV32IM firmware on an RV32IMC hart with A disabled. Runs below used +`BUILD_TIMESTAMP=2026-09-25-12-00`: + +- Default `bringup`: `build/ihp130-tiny-2026-09-25-12-00-d6009644a134/`. +- `APP=ci_smoke`: `build/ihp130-tiny-2026-09-25-12-00-044d45791ef7/`. +- `APP=ci_smoke HAVE_SVA=YES`: + `build/ihp130-tiny-2026-09-25-12-00-6874f2ffdf11/`. + +Configuration digests identify settings and the dependency lock, not a clean +source revision. A release requires rerunning from its reviewed commit. + +## Functional and quality checks + +| Check | Evidence/boundary | +| --- | --- | +| Tiny maps and source isolation | Generated address, IRQ, pad and clock/reset inputs validate; source closure excludes Mini product RTL, RIB/RIBP and HP generation. | +| AXI fabric, both simulators | Directed tests cover competing CPU/DMA requests, W-before-AW, delayed W, response backpressure, ID/RLAST, 16-beat bursts, 4 KiB crossing, alignment, reserved regions and continued operation after errors. | +| Tiny SYSCTRL, both simulators | APB tests cover unsupported controls, partial terminal writes, sticky first status, counter snapshots, first-fault retention, W1C, RTC wake and reset. | +| Verilator full firmware | `SIM_TEST_PASS`; the CI composition also passes with SVA enabled. Pin-level NOR, compressed instructions, disabled atomics, load faults, SRAM discovery, memory/UART DMA, external timer IRQ, CLINT time, RTC, GPIO, UART1 loopback, I2C NACK and watchdog reboot are exercised. | +| Icarus full firmware | Final expanded CI firmware passes at 3,705,751 cycles, matching the SVA-enabled Verilator run. | +| Icarus synthesized boot | `netsim-boot` passes at 29,362 cycles using the compact assembly image. Covers pin-level NOR, SRAM first/last words, byte writes, UART and terminal status; does not establish full C-firmware gate-level coverage. | +| SDK gates | C formatting, embedded-C policy and host tests pass, including Tiny channel/endpoint rejection compiled from the real DMA validator. No new Required-rule MISRA deviation is recorded; these partial checks do not certify MISRA conformance. | +| Focused Python tests | 112 tests passed across Tiny, address/pad generation and build/regression tooling. Shared debug-reset and SRAM/DMA register-parity checks also pass. After fixing parameterization/publication compatibility and preparing the existing MPW/device-model inputs, all 54 non-reference failures selected for rerun pass. | +| RTL policy | Changed RTL formatting, full owned RTL style audit and readiness metadata pass. Global formatting limitations are listed below. | +| Reproducibility | Dependency lock validation, Ruff, PR/nightly dry-runs and `git diff --check` pass. Tiny source packaging exports the Tiny top, actual filelist and its core timing SDC. | + +The full-firmware verdict is authoritative only when both the tool result and +`result-sim-check.json` pass. UART text alone is not sufficient. Assembly netlist +acceptance uses the same strict terminal marker policy. + +## Synthesis and timing + +For the CI composition, Yosys completed with the IHP130 technology libraries +and 32 `tc_sram_1024x32` banks. The `balanced` report records 207,739 cells and +9,798,326.725198 square micrometers of library area. The area includes the +instantiated memory/pad hierarchy and is not a placed die-area estimate. + +OpenSTA completed with the selected slow library corner and the 41.666666667 ns +system clock. Reported setup WNS is **-455.18 ns**, setup TNS is +**-13,049,600 ns**, and hold WNS/TNS are zero. The worst path starts at the +synchronized system-reset register and reaches peripheral FIFO storage through +the high-fanout reset distribution. This is an open physical/timing issue; +24 MHz is a functional target, not a timing-qualified operating point. + +Reports reside under the CI variant's `syn/yosys/rpt/` and `sta/opensta/`. +The metric collector understands the Tiny top and timestamp-prefixed Yosys JSON +reports. Metrics remain in `observe` mode; no warning or metric baseline has +been edited to accept this feature. + +## Commands and remaining coverage + +The build/verification commands were run with the profile and timestamp above: + +```sh +make CONFIG=configs/ci/ihp130-tiny.mk doctor firmware sim +make CONFIG=configs/ci/ihp130-tiny.mk APP=ci_smoke HAVE_SVA=YES firmware sim +make CONFIG=configs/ci/ihp130-tiny.mk APP=ci_smoke SIMU=IVERILOG firmware sim +make CONFIG=configs/ci/ihp130-tiny.mk APP=ci_smoke SYNTH=YOSYS synth +make CONFIG=configs/ci/ihp130-tiny.mk APP=ci_smoke SIMU=IVERILOG netsim-boot +make CONFIG=configs/ci/ihp130-tiny.mk APP=ci_smoke STA=OPENSTA sta +make CONFIG=configs/ci/ihp130-tiny.mk metrics package +make sw-format-check sw-policy-check sw-host-test rtl-style-check-all rtl-readiness-check +python3 -m pytest -q tests/test_tiny.py tests/test_memory_map.py tests/test_pin_map.py tests/test_script_tools.py +python3 scripts/regress.py --root . --suite pr --pdk IHP130 --netsim-boot-only +``` + +The combined IHP130 regression stops in its Mini phase because the locked +VexiiRiscv checkout is absent. Tiny can be selected independently with +`--soc TINY`, or `make CONFIG=configs/ci/ihp130-tiny.mk regress-pr`. +The initial full Pytest run completed with 1,234 passed, 26 failed, 19 skipped +and 71 errors. Parameterization/format-sensitive expectations and the Mini +publication's constant/cast parsing were corrected; the affected cases were +rerun successfully. MPW/device-model inputs and a writable test ccache resolved +additional environment failures. The remaining 16 cases require the absent +locked FLAC corpus, MLPerf Tiny models or TensorFlow oracle sources. These are +not Tiny setup dependencies. The full suite was not rerun after the focused +corrections; it is not reported as a clean full-suite pass. + +The initial run, focused results, combined-regression failure and remaining +reference-input case list are retained under the CI variant's +`meta/validation/`. +Global RTL/Make formatting checks encounter existing APU/accelerator files +outside this change. Changed-file formatting is checked independently. + +Remaining qualification includes reset-tree/timing closure, placement/routing, +PVT/MMMC, CDC/RDC signoff, silicon and power measurements, full C netlist +acceptance, a Tiny-specific external OpenOCD session, positive external I2C +slave transactions and comprehensive pad-level PWM/RTC coverage. Wireless, +retention, secure boot and other PDKs remain explicit deferred features. + +## Shared-path migration follow-up + +Mini now references the canonical shared RTL, `scripts/rtl` helpers and +`rtl/mk/software.mk` directly. The 21 Mini compatibility links and seven Tiny +helper links have been removed. Filelists, simulator/formal/synthesis rules, +Python imports, tests, publication tooling and ownership documents use the new +paths. No Git file-type changes remain. Historical warning baselines are +unchanged. + +The resolved Mini `commonip.fl`, `ip.fl` and `top.fl` retain the same 299 +unique sources in the same order. `netlist_support.fl` retains its two sources; +`inc.fl` adds `rtl/ip/core`. All relocated shared RTL content hashes match the +pre-migration snapshot. This follow-up changes paths, not RTL behavior or the +public hardware/software interface. + +Validation after removing the links: + +- 245 focused tests passed: 144 build/generator/topology/style/Tiny tests, + 96 publication/LibreLane tests and five debug-reset/SRAM simulations. + Full-suite collection succeeds with 1,356 tests; the full suite was not + rerun because of the reference-input gaps documented above. +- Mini `configs/ci/ihp130.mk` address/pad/topology/clock-reset checks and firmware + build pass. Its Verilator compile reaches HP generation and stops because + the locked VexiiRiscv checkout is missing; full Mini simulation and the + combined regression remain unverified. +- Tiny `configs/ci/ihp130-tiny.mk`, `APP=ci_smoke HAVE_SVA=YES`, firmware and + Verilator simulation pass again at 3,705,751 cycles. Full Icarus, synthesis + and STA were not repeated for this path-only follow-up. +- Eleven Python CLI entrypoints work outside the repository directory. + Mini SRAM formal filelist generation, `sv2v` conversion, filelist combination + and dependency generation pass using the canonical shared paths, including + the relocated SRAM header. Formal proofs were not rerun. +- Ruff, owned RTL style, readiness metadata, 251 local Markdown links and + `git diff --check` pass. The Make formatter still reports existing EOF and + formal-command indentation differences in APU/GA2D/formal fragments; those + unrelated differences were preserved. + +Run logs, exact commands and path snapshots are retained under +`build/ihp130-2026-09-25-12-00-9903b3d112b7/meta/validation/shared-path-migration/`. +No C register/API change or additional MISRA deviation belongs to this +follow-up; the SDK gates from the implementation record above were not rerun. + +## Next review + +```text +Use $retrosoc-mini-feature-review in review mode for feature tiny-soc. Review the current worktree diff against docs/ip/tiny-soc.md and docs/ip/tiny-soc-verification.md. Verify Tiny isolation, default Mini compatibility, AXI/APB/error/reset behavior and the SDK ABI. Treat the observed reset-fanout timing deficit and missing APU/NPU/VexiiRiscv inputs as explicit qualification gaps; do not claim timing closure or alter warning/metric baselines. +``` diff --git a/docs/ip/tiny-soc.md b/docs/ip/tiny-soc.md new file mode 100644 index 00000000..8bf7dd1f --- /dev/null +++ b/docs/ip/tiny-soc.md @@ -0,0 +1,193 @@ +# retroSoC Tiny MCU Contract + +## Purpose and research boundary + +This contract freezes the approved Tiny wired-MCU first release. Tiny owns its +integration in `rtl/tiny`; Mini remains a separate product. The committed +`configs/ci/ihp130-tiny.mk` profile is the reproducible implementation boundary. +The design was approved on 2026-09-25. Source presence does not establish +verification, timing closure, silicon qualification, or low-power performance. + +The [RP2350](https://www.raspberrypi.com/products/rp2350/) is a Hazard3-based MCU +reference for software, SRAM, and deterministic I/O. Its dual-core, security, +USB, and PIO features are not Tiny requirements. The +[CAST SRAM controller](https://www.cast-inc.com/peripherals/memory-controllers/sram-ctrl) +illustrates native AXI synchronous SRAM and documented verification delivery; +no commercial implementation or qualification is reused. + +## Requirements and non-goals + +- TINY-001: one Hazard3 hart, RV32IMC with A disabled, mandatory debug support; + existing RV32IM firmware remains the default compiler target. +- TINY-002: native 32-bit AXI4 data and APB4 control. The CPU's native AHB-Lite + terminates at a direct AXI adapter. No RIB/RIBP source or interface is part of + Tiny's compilation or elaboration closure. +- TINY-003: 128 KiB technology-backed SRAM, XPI NOR boot, no external RAM + dependency. Reset vector is `0x00000000`; SRAM begins at `0x30000000`. +- TINY-004: 32 GPIO, two UARTs, two I2C controllers, two general timers, + CLINT, four DMA channels, PWM, RTC, watchdog, SYSCTRL and architecture info. +- TINY-005: IHP130, 24 MHz system clock, no PLL, 1 MHz CLINT timebase. CPU, + AXI, APB, RTC and watchdog share the system clock. +- TINY-006: Tiny must build independently of MPW, HP CPU generation and + multimedia inputs. Shared SDK APIs retain the `rs_` namespace. +- TINY-007: no wireless IP, radio-specific host integration, or wireless stack. + +Deferred: RV32 A atomics, RTOS ports, authenticated boot, retention/power gating, +independent sleep clock, 256–512 KiB SRAM, USB, SDIO, standalone general SPI, +I2S, CAN, ADC, multimedia accelerators and other PDK qualification. XPI retains +the existing four-chip-select interface; initial pin-level acceptance uses NOR +on NSS0. The unpopulated chip selects are not qualified device configurations. + +## Selected architecture and interfaces + +`retrosoc_tiny` integrates the CPU, two-master fabric, SRAM, XPI and one APB +island. `retrosoc_tiny_asic` owns technology pads; `retrosoc_tiny_tb` owns device +models and terminal verdicts. Product maps, filelists and bindings belong to +Tiny; reusable core/debug, memory and bus utilities belong to shared RTL IP. + +AXI has 32-bit addresses/data and one-bit ID/USER. CPU and DMA share one +globally active read or write transaction. Round-robin ownership changes only +after B or RLAST handshake; accepted W traffic cannot change owners. Backpressure +must preserve VALID payloads. Memory accepts naturally aligned 1/2/4-byte INCR +transactions of 1–16 beats within a target and 4 KiB page. MMIO accepts one-beat +FIXED/INCR accesses. Unsupported size/burst/lock/alignment or crossing returns +SLVERR; absent regions return DECERR. Rejected reads return the advertised +number of response beats; rejected writes drain their accepted data before B. + +APB uses full setup/access phases, PSTRB and PSLVERR. Registers retain their +existing IP offset, access and reset contracts. A missing peripheral has no +successful decode. GPIO alternate functions retain the selected Mini mappings; +unsupported alternate functions drive neither pads nor peripheral requests. +UART TX/RX and XPI have dedicated pins. + +## DMA and interrupt contract + +DMA retains the V2 manual register ABI, direct and TCD modes, 32-bit transfers, +up-to-16-beat memory bursts and existing completion/error/W1C/abort semantics. +Four channels are available: 0 UART0, 1 I2C0, 2 I2C1, 3 bulk/XPI. UART1 uses +PIO/IRQ. Stream endpoints and requests for omitted devices are unsupported and +must fail validation rather than wait indefinitely. Capability discovery and +SDK range checks must agree with hardware. + +CLINT software/timer occupy core bits 0/1. Reused external sources keep Mini +core-bit numbering: UART0 2, timer0 3, timer1 4, I2C0 7, XPI 9, PWM 11, +RTC 13, watchdog 14, GPIO 18, I2C1 19, DMA 20, UART1 26. The vector has 32 +bits (30 Hazard3 external inputs); all omitted sources are zero. + +## Register and software ABI + +Tiny maps reuse the addresses of implemented Mini peripherals, Flash alias and +XPI aperture. Generated outputs contain address/IRQ/capability metadata and +linker regions, not new generated IP register definitions. SVH/C register pairs +remain handwritten and checked for parity. Hardware identity must describe Tiny, +one MCU hart, 128 KiB SRAM and actual capabilities. + +Tiny SYSCTRL preserves fault capture, performance enable/clear and TEST_STATUS +at the existing offsets. The first full-word TEST_STATUS write with bit 31 set +is sticky until system reset; bit 0 is pass and bits 15:8 are the result code. +Unsupported Mini lifecycle/clock controls fail safely; they do not enable HP or +user-core behavior. Unavailable IP drivers are omitted from the Tiny firmware composition. +Unsupported SYSCTRL lifecycle/PLL operations and DMA channel/endpoint requests +return an error before MMIO. GPIO alternate modes follow the Tiny pin map. + +The `bringup` and `ci_smoke` applications select product-specific entrypoints. +Startup skips PSRAM setup on Tiny and uses `ld2_all_sram`: code/data copy from +Flash into SRAM, with SRAM BSS and stack. IRQ/CSR support is enabled. Public +headers remain under ``; retired `tiny*.h` paths are not restored. + +## Clock, reset and lifecycle + +External reset is asynchronously asserted and synchronously released. Watchdog +reset restarts the system. Debug hart reset waits for the CPU AXI adapter to +be idle; it must not abandon an accepted transaction. JTAG and asynchronous +external inputs retain the approved Common synchronizer/handshake boundaries. +There is no cross-domain system bus or dynamic clock switching in this release. +RTC/WDG run at the configured system frequency and provide no independent +deep-sleep guarantee. SRAM contents are not initialized by reset. + +## Errors, observability and security + +Decode/protocol faults complete with AXI errors and feed sticky SYSCTRL fault +information. DMA records errors and supports bounded software waits and abort. +Counters and terminal-test status permit firmware and simulation diagnosis. +Watchdog provides whole-system recovery from a nonresponsive target; this +release makes no unrestricted AXI liveness, secure-boot, production-entropy, +isolation, or safety-certification claim. + +## Development order and acceptance + +### TINY-P0 — Freeze Tiny MCU Contract + +Record the approved requirements here and update document indexes. Acceptance: +reviewable specification, valid links and `git diff --check`. + +### TINY-P1 — Product Selection and Shared Infrastructure + +Add SOC=TINY, the committed profile, dependency selection and shared build/IP +boundaries. Preserve Mini defaults. Acceptance: configuration/generator tests, +dependency lock validation, no implicit Tiny dependency on Mini product RTL. + +### TINY-P2 — AXI4/APB4 Tiny RTL + +Implement the hierarchy and contracts above. Acceptance: lint, standalone AXI, +APB, memory, reset and IRQ checks; no RIB/RIBP in the resolved source closure. + +### TINY-P3 — SDK Boot and System Verification + +Implement generated capabilities, SRAM-only startup, HAL selection and firmware. +Acceptance: both simulators boot through pin-level NOR and emit SIM_TEST_PASS; +test SRAM boundaries, DMA, peripherals, IRQ, disabled A, C instructions and debug. + +### TINY-P4 — IHP130 Qualification and Documentation + +Add Tiny to IHP130 regression without replacing Mini coverage. Run format/style, +lint, software policy/host tests, Ruff, Pytest, firmware and supported regressions. +Run Yosys, Icarus netlist and OpenSTA; archive macro mapping, area, cell count, +24 MHz timing and warnings under the configuration's build variant. Check docs +and example commands. Record unrun/failed gates explicitly; do not promote +warning baselines or metrics policy as part of this feature. + +## Reproducible commands and current evidence + +Use the committed profile, and preserve one `BUILD_TIMESTAMP` when commands +must share artifacts: + +```sh +make CONFIG=configs/ci/ihp130-tiny.mk setup doctor +make CONFIG=configs/ci/ihp130-tiny.mk firmware sim +make CONFIG=configs/ci/ihp130-tiny.mk SIMU=IVERILOG firmware sim +make CONFIG=configs/ci/ihp130-tiny.mk SYNTH=YOSYS synth +make CONFIG=configs/ci/ihp130-tiny.mk SIMU=IVERILOG netsim-boot +make CONFIG=configs/ci/ihp130-tiny.mk STA=OPENSTA sta +make CONFIG=configs/ci/ihp130-tiny.mk metrics package +python3 scripts/regress.py --root . --suite pr --pdk IHP130 --soc TINY --dry-run +``` + +`netsim-boot` runs the dedicated `app/asm/tiny_boot.S` gate-level image. It checks +pin-level NOR boot, both ends of physical SRAM, a byte-lane write, UART and the +SYSCTRL terminal result. It requires `SIM_TEST_PASS`; this is separate from the +complete SDK/IRQ/DMA/watchdog acceptance in both RTL simulators. `netsim` retains +the full firmware option. The shared SRAM IP's capability register describes +the IP's native superset; end-to-end requests must obey Tiny's narrower fabric +contract above. + +Tiny uses two-cycle AHB ERROR completion so Hazard3 can trap AXI failures. The +shared core/bridge parameters retain Mini's existing default behavior. Tiny +ArchInfo reports SOC_ID `0x54494e59`, topology `0x20200001`, and FEATURES0 +`0x00007ffe`: bits 1/2 SRAM interface/macro, 3 AXI, 4 APB, 5 DMA, 6 UART, +7 I2C, 8 PWM, 9 RTC, 10 watchdog, 11 GPIO, 12 CLINT, 13 timers and 14 XPI. +Bit 0 (PLL) is zero. Tiny FAULT_DETAIL contains the raw AXI response (2/3), +FAULT_STATUS reason is 1 for decode and 2 for slave/protocol errors, +and FAULT_MASTER uses 0 for CPU and 1 for DMA; no RIB encoding is exported. +The public watchdog API is `rs_watchdog_*` with `rs_status_t` and bounded waits. + +The [verification record](tiny-soc-verification.md) distinguishes successful +functional checks from missing reference inputs and physical closure. The +product remains `prototype`: negative pre-layout reset-fanout timing must not +be presented as a qualified 24 MHz implementation. + +## Commercial delivery gaps + +Current-revision verification and physical reports govern readiness. Reusable +VIP, coverage closure, full CDC/RDC, DFT/MBIST, PVT/MMMC, post-layout timing, +power characterization, regulatory and silicon qualification remain separate. diff --git a/docs/misra-c-2012.md b/docs/misra-c-2012.md index 31c3604f..79556fec 100644 --- a/docs/misra-c-2012.md +++ b/docs/misra-c-2012.md @@ -32,8 +32,10 @@ and reviewed evidence for the applicable rules. - Use `rs_status_t` for fallible operations. Prefer bounded string/format APIs and timeout-based register waits. Dynamic allocation is not permitted in self-owned embedded C. -- New `tiny` identifiers, legacy include paths, and prohibited library calls +- Retired `tiny`-prefixed SDK identifiers, legacy include paths, and prohibited library calls are not allowed outside the compatibility files explicitly listed by policy. + The Tiny product name in prose/string literals and `RS_SOC_TINY` product + selection do not restore those retired SDK interfaces. The standard is referenced by name and category only. Consult the licensed MISRA publication for the complete rule text and applicability guidance; do diff --git a/docs/rtl-coding-style-compliance.md b/docs/rtl-coding-style-compliance.md index 824a6b44..785d578a 100644 --- a/docs/rtl-coding-style-compliance.md +++ b/docs/rtl-coding-style-compliance.md @@ -10,7 +10,7 @@ validated without changing functional behavior. The owned profile in [`rtl/rtl_style_manifest.json`](../rtl/rtl_style_manifest.json) is the source of truth for the reviewed source set. It includes `rtl/ip/**` and -`rtl/mini/top/**`, but excludes managed, generated, PDK, formal, device-model, +`rtl/mini/top/**` and `rtl/tiny/top/**`, but excludes managed, generated, PDK, formal, device-model, and third-party sources. [`rtl/rtl_style_audit.json`](../rtl/rtl_style_audit.json) records the exact diff --git a/docs/rtl-coding-style.md b/docs/rtl-coding-style.md index 1629983b..d60be5dc 100644 --- a/docs/rtl-coding-style.md +++ b/docs/rtl-coding-style.md @@ -10,7 +10,7 @@ differ: retroSoC uses `clk_i` and `rst_n_i`, not `rst_ni`. ## 1. Scope and rule levels -The owned profile applies to `rtl/ip/**` and `rtl/mini/top/**`. Formal, +The owned profile applies to `rtl/ip/**`, `rtl/mini/top/**`, and `rtl/tiny/top/**`. Formal, device-model, PDK, generated, managed, and third-party sources use the profiles declared in [`rtl/rtl_style_manifest.json`](../rtl/rtl_style_manifest.json). diff --git a/docs/soc-family-positioning.md b/docs/soc-family-positioning.md index 486e3b67..813029cd 100644 --- a/docs/soc-family-positioning.md +++ b/docs/soc-family-positioning.md @@ -3,9 +3,9 @@ ## Status and Scope This document defines the intended Tiny, Mini, Std, and Pro product ladder. -It is a product roadmap, not a statement of implemented repository support. -The current build system accepts only `SOC=MINI`, and the committed Mini -profiles remain the executable source of truth. +Tiny and Mini have executable build profiles; Std and Pro remain roadmap +targets. Committed product profiles and retained validation evidence define +implemented support. Tiny first targets IHP130 as a wired MCU. Mini is the family anchor. It establishes the common product model: an open RISC-V SoC in which a small, always-available Hazard3 management core owns @@ -14,8 +14,8 @@ add application processors and accelerators without transferring final lifecycle control to Linux. Tiny reduces this model to an MCU-class device and does not require a separate application processor. -All frequencies, memory sizes, bus widths, accelerator rates, and software -features below are product targets. They require separate RTL integration, +Except for the explicitly identified executable baselines, frequencies, memory +sizes, bus widths, accelerator rates, and software features below are product targets. They require separate RTL integration, driver enablement, verification, and physical qualification before they can be advertised for a device or PDK. @@ -47,45 +47,36 @@ nodes, protocol bridges, and smart-home edge endpoints. It is MCU-first: boot latency, sleep behavior, deterministic I/O, security, package cost, and usable energy per event take precedence over Linux compatibility. -Tiny has two productization profiles: +The first executable product is **Tiny-MCU**, an independent wired MCU +integration in `rtl/tiny`, selected with `configs/ci/ihp130-tiny.mk`. It has no +wireless IP, wireless protocol stack, or radio-specific companion integration. +Tiny-Connect, BLE, IEEE 802.15.4 and Wi-Fi are deferred product research. -- **Tiny-MCU** contains no radio and targets wired control or products that do - not need connectivity on every unit. -- **Tiny-Connect** provides Bluetooth Low Energy and IEEE 802.15.4 capability. - The open digital-RTL baseline should expose a qualified SPI or SDIO host, - interrupt, reset, wake, and power-sequencing interface to a certified radio. - On-die or co-packaged RF becomes a product option only after suitable RF IP, - analog integration, PDK support, and regulatory qualification exist. +### First-release Architecture -Wi-Fi 6 is an optional upper Tiny-Connect SKU rather than a baseline -requirement. This avoids imposing its RF, memory, and active-power costs on -802.15.4 and Bluetooth endpoint products. - -### Recommended Architecture - -| Area | Product target | +| Area | Tiny MCU baseline | | --- | --- | -| CPU | One Hazard3 RV32IMAC core at 64-160 MHz, subject to PDK qualification | -| On-chip memory | 256-512 KiB banked SRAM, boot ROM, and 8-32 KiB retention SRAM | -| Code storage | QSPI flash with execute-in-place and authenticated recovery boot | -| Memory model | No MMU and no external DRAM dependency | -| Interconnect | 32-bit RIB; bounded `INCR4` support for DMA and XIP, without a full AXI4 fabric | -| Software | Freestanding SDK, bare metal, and Zephyr- or FreeRTOS-class RTOS ports | -| Low power | Clock gating, switchable SRAM banks, RTC/event wake, retention, and a separately measured deep-sleep state | -| Security | Immutable boot root, signed boot, OTP key material, PMP, TRNG, and symmetric/hash acceleration | -| Edge I/O | UART, SPI, I2C, PWM, ADC, I2S/PDM, USB full speed, and CAN FD selected by package profile | +| CPU | One Hazard3 RV32IMC hart; A extension disabled until atomic bus semantics are qualified | +| On-chip memory | 128 KiB macro-backed SRAM; 256–512 KiB and retention SRAM deferred | +| Code storage | XPI NOR boot, loaded into SRAM; authenticated recovery boot deferred | +| Memory model | No MMU, HP hart, or external DRAM/PSRAM dependency | +| Interconnect | 32-bit AXI4 data plane and APB4 control; no RIB/RIBP | +| Software | Existing freestanding SDK, RV32IM compiler target, CSR/IRQ-enabled acceptance firmware | +| Clock/reset | 24 MHz system clock, no PLL, 1 MHz CLINT timebase, watchdog and JTAG reset | +| Edge I/O | 32 GPIO, two UARTs, two I2C controllers, two timers, four DMA channels, PWM, RTC, watchdog and XPI | -No power-current number should be published until it is measured on a -qualified physical implementation with the wake sources and retention state -specified. Tiny's acceptance criteria should include sleep-to-active latency, -energy per sensing/reporting cycle, and certified-radio interoperability, not -only CPU benchmarks. +The normative [Tiny MCU contract](ip/tiny-soc.md) defines the AXI subset, +address/interrupt ABI, startup, errors and phased acceptance. Independent +low-power clocks, clock/power gating, retention, secure boot, RTOS ports, USB, +SDIO, standalone general SPI, CAN and ADC remain future work. No measured +frequency ceiling, power-current, wake-latency or security claim follows from +this initial functional profile. ### Commercial Reference Points | Commercial SoC | Relevant axis | Position relative to Tiny | | --- | --- | --- | -| [Espressif ESP32-H2](https://www.espressif.com/en/products/socs/esp32-h2) | Low-power RV32 MCU with Bluetooth LE and IEEE 802.15.4 | Primary Tiny-Connect endpoint and Thread/Zigbee market reference | +| [Espressif ESP32-H2](https://www.espressif.com/en/products/socs/esp32-h2) | Low-power RV32 MCU with Bluetooth LE and IEEE 802.15.4 | Deferred Tiny-Connect research reference | | [Espressif ESP32-C6](https://www.espressif.com/en/products/socs/esp32-c6) | RV32 high- and low-power cores with Wi-Fi 6, Bluetooth LE, and IEEE 802.15.4 | Upper connectivity reference; RF and protocol integration are well beyond a radio-companion Tiny baseline | | [Raspberry Pi RP2350](https://www.raspberrypi.com/products/rp2350/) | Dual Hazard3 option, 520 KiB SRAM, security, USB, and programmable I/O | Closest open-core MCU and deterministic-I/O reference, without integrated radio | | [ST STM32U5](https://www.st.com/en/microcontrollers-microprocessors/stm32u5-series.html) | Ultra-low-power secure MCU family with large embedded memory and graphics options | Energy-efficiency, security, and industrial MCU ecosystem reference rather than an ISA-equivalent peer | @@ -416,7 +407,7 @@ software quality. | Tier | Claim gate | | --- | --- | -| Tiny | Measured active and sleep power, bounded wake latency, secure-boot validation, and qualified edge-connectivity operation | +| Tiny | First release: wired-MCU boot, AXI/APB/DMA/IRQ and IHP130 evidence; future low-power/security claims require separate measurements and qualification | | Mini | Repeatable Linux boot, at least 64 MiB usable main memory, native memory bursts, and management-controlled start/stop recovery | | Std | Full AXI4 ordering tests, coherent accelerator traffic, 1080p60 graphical desktop, audio playback, and NPU inference under concurrent DMA load | | Pro | Four-hart coherent SMP stress, RV64 distribution boot, more-than-4-GiB memory validation, and concurrent GPU/NPU/video operation | diff --git a/physical/README.md b/physical/README.md index f5f85a29..4c0642c1 100644 --- a/physical/README.md +++ b/physical/README.md @@ -7,7 +7,9 @@ drivers. - `pdk/` contains the locked PDK setup helpers and managed PDK checkouts. - `smoke/syn/` contains Yosys synthesis and source-export integration. - `smoke/sta/` contains OpenSTA constraints and timing integration. -- `librelane/` contains the open-source IHP130 core-hardening and full-chip pad-ring flows. +- `librelane/` contains the open-source IHP130 implementation flows, organized + per product line: `librelane/mini/` (core hardening and full-chip pad ring) + and `librelane/tiny/` (Tiny full-chip pad ring). - `ecc/` contains the open-source ICS55 padless-core hardening flow backed by the locked ECOS Chip Compiler release. - `commercial/` contains licensed-tool orchestration and flow logic. PDKs, diff --git a/physical/commercial/scripts/generate_timing_contract.py b/physical/commercial/scripts/generate_timing_contract.py index 7f1defbd..cd0f9938 100644 --- a/physical/commercial/scripts/generate_timing_contract.py +++ b/physical/commercial/scripts/generate_timing_contract.py @@ -12,7 +12,7 @@ from typing import Any ROOT = Path(__file__).resolve().parents[3] sys.path.insert(0, str(ROOT)) -from rtl.mini.pin_map.generate_pin_map import read_map # noqa: E402 +from scripts.rtl.generate_pin_map import read_map # noqa: E402 from scripts.check_clock_reset_domains import validate # noqa: E402 from scripts.setup_helpers import atomic_write # noqa: E402 diff --git a/physical/librelane/README.md b/physical/librelane/README.md index eb7bcf54..0e40a59a 100644 --- a/physical/librelane/README.md +++ b/physical/librelane/README.md @@ -1,50 +1,27 @@ # LibreLane IHP130 Flows -This directory owns the open-source IHP130 implementation entry points for two -independent `retrosoc` deliverables: +This directory groups the open-source LibreLane/IHP130 implementation flows by +product line: -- `librelane-core` hardens `retrosoc_core`, a padless logical macro with the - canonical external pin contract and the three USB packet SRAM macros. -- `librelane-chip` implements the bare-die `retrosoc_asic` package-facing SoC, - including its pad ring, bondpads, fillers, corners, seal ring, and the same - SRAM macros. +- [`mini/`](mini/README.md) hardens the Mini SoC deliverables (`retrosoc_core` + padless macro and the bare-die `retrosoc_asic` pad-ring chip) for + `SOC=MINI` profiles such as `configs/ci/ihp130.mk`. +- [`tiny/`](tiny/README.md) implements the bare-die Tiny MCU + (`retrosoc_tiny_asic`, pad-ring chip only) for `SOC=TINY` with + `configs/ci/ihp130-tiny.mk`. +- `bondpad/` holds the shared 70 um bondpad LEF collateral used by both chip + flows. -These are separate single-level runs. The chip flow does not consume the core -run as a hierarchical macro, so either artifact can be developed and reviewed -without a two-level integration dependency. - -The flow consumes the committed `configs/ci/ihp130.mk` profile, canonical SoC -pin map, and IHP-Open-PDK revision in `dependencies/dependencies.lock.json`. -LibreLane reads the upstream `ihp-sg13g2/libs.tech/librelane` configuration -directly through manual-PDK mode. Generated RTL, SDC, configuration, run -databases, reports, and final views are written below the selected -`build//physical/librelane/{core,chip}/` directory. - -Use the LibreLane 3.0.5 environment supplied by the development shell: - -```sh -make CONFIG=configs/ci/ihp130.mk librelane-doctor -make CONFIG=configs/ci/ihp130.mk librelane-core -make CONFIG=configs/ci/ihp130.mk librelane-chip -make CONFIG=configs/ci/ihp130.mk librelane-core-package -make CONFIG=configs/ci/ihp130.mk librelane-package -``` - -The chip target places all 111 signal pads, 80 core/IO power and ground pads, -four corners, I/O fillers, and 70 um bondpads. It is a bare-die plan, not a -QFN/BGA package definition. The SDC constrains the external clock at 72 MHz; -mid-PnR timing report passes are skipped because LibreLane 3.0.5 emits 1000 -expanded paths per group, while final post-RCX multi-corner STA remains enabled. +The top-level `Makefile` includes `mini/Makefile` or `tiny/Makefile` according +to `SOC`, so the target names (`librelane-doctor`, `librelane-chip`, +`librelane-package`, and the Mini-only `librelane-core`) are uniform across +product lines. +Both lines require the LibreLane 3.0.5 development environment, the locked +IHP-Open-PDK checkout under `physical/pdk/`, and the locked OpenSTA 3.0.0. `PDK=GF180`, `PDK=SKY130`, and `PDK=ICS55` are intentionally rejected until their technology-specific LibreLane adapters, pad cells, macro collateral, and -signoff decks are qualified. The target split is technology-neutral so those -adapters can reuse the core/chip interface when they are ready. - -IHP SG13G2 does not currently provide pad cells implementing retroSoC's -programmable pull-up, pull-down, or Schmitt controls. The IHP implementation -uses input-only, 4 mA output, and 4 mA bidirectional cells; unsupported GPIO -pad-control features must not be represented as production-qualified behavior. +signoff decks are qualified. A successful open-source run is evidence for implementation development, not a foundry production-signoff claim. Release review still requires qualified diff --git a/physical/librelane/Makefile b/physical/librelane/mini/Makefile similarity index 96% rename from physical/librelane/Makefile rename to physical/librelane/mini/Makefile index d15e4ea2..97b94091 100644 --- a/physical/librelane/Makefile +++ b/physical/librelane/mini/Makefile @@ -1,11 +1,11 @@ -LIBRELANE_FLOW_ROOT := $(ROOT_PATH)/physical/librelane +LIBRELANE_FLOW_ROOT := $(ROOT_PATH)/physical/librelane/mini LIBRELANE_TARGET ?= chip -LIBRELANE_RUN_ROOT := $(VARIANT_ROOT)/physical/librelane/$(LIBRELANE_TARGET) +LIBRELANE_RUN_ROOT := $(VARIANT_ROOT)/physical/librelane/mini/$(LIBRELANE_TARGET) LIBRELANE_INPUT_DIR := $(LIBRELANE_RUN_ROOT)/input LIBRELANE_RTL := $(LIBRELANE_INPUT_DIR)/retrosoc_asic_sources.sv LIBRELANE_SDC := $(LIBRELANE_INPUT_DIR)/retrosoc_$(LIBRELANE_TARGET).sdc LIBRELANE_BONDPAD_GDS := $(LIBRELANE_INPUT_DIR)/bondpad_70x70.gds -LIBRELANE_BONDPAD_LEF := $(LIBRELANE_FLOW_ROOT)/bondpad/bondpad_70x70.lef +LIBRELANE_BONDPAD_LEF := $(ROOT_PATH)/physical/librelane/bondpad/bondpad_70x70.lef LIBRELANE_CONFIG := $(LIBRELANE_RUN_ROOT)/config.json LIBRELANE_LOG := $(LIBRELANE_RUN_ROOT)/librelane.log LIBRELANE_RESULT := $(LIBRELANE_RUN_ROOT)/result.json @@ -65,7 +65,7 @@ endif librelane-check-pdk: @test '$(PDK)' = IHP130 || { \ - echo 'physical/librelane currently implements only PDK=IHP130' >&2; exit 2; } + echo 'physical/librelane/mini currently implements only PDK=IHP130' >&2; exit 2; } @test '$(HAVE_PLL)' = NO || { \ echo 'the IHP130 LibreLane flow has no qualified crystal PAD' >&2; exit 2; } diff --git a/physical/librelane/mini/README.md b/physical/librelane/mini/README.md new file mode 100644 index 00000000..9e51a651 --- /dev/null +++ b/physical/librelane/mini/README.md @@ -0,0 +1,52 @@ +# Mini LibreLane IHP130 Flows + +This directory owns the Mini product line's open-source IHP130 implementation +entry points for two independent `retrosoc` deliverables: + +- `librelane-core` hardens `retrosoc_core`, a padless logical macro with the + canonical external pin contract and the three USB packet SRAM macros. +- `librelane-chip` implements the bare-die `retrosoc_asic` package-facing SoC, + including its pad ring, bondpads, fillers, corners, seal ring, and the same + SRAM macros. + +These are separate single-level runs. The chip flow does not consume the core +run as a hierarchical macro, so either artifact can be developed and reviewed +without a two-level integration dependency. + +The flow consumes the committed `configs/ci/ihp130.mk` profile, canonical SoC +pin map, and IHP-Open-PDK revision in `dependencies/dependencies.lock.json`. +LibreLane reads the upstream `ihp-sg13g2/libs.tech/librelane` configuration +directly through manual-PDK mode. Generated RTL, SDC, configuration, run +databases, reports, and final views are written below the selected +`build//physical/librelane/mini/{core,chip}/` directory. + +Use the LibreLane 3.0.5 environment supplied by the development shell: + +```sh +make CONFIG=configs/ci/ihp130.mk librelane-doctor +make CONFIG=configs/ci/ihp130.mk librelane-core +make CONFIG=configs/ci/ihp130.mk librelane-chip +make CONFIG=configs/ci/ihp130.mk librelane-core-package +make CONFIG=configs/ci/ihp130.mk librelane-package +``` + +The chip target places all 111 signal pads, 80 core/IO power and ground pads, +four corners, I/O fillers, and 70 um bondpads. It is a bare-die plan, not a +QFN/BGA package definition. The SDC constrains the external clock at 72 MHz; +mid-PnR timing report passes are skipped because LibreLane 3.0.5 emits 1000 +expanded paths per group, while final post-RCX multi-corner STA remains enabled. + +`PDK=GF180`, `PDK=SKY130`, and `PDK=ICS55` are intentionally rejected until +their technology-specific LibreLane adapters, pad cells, macro collateral, and +signoff decks are qualified. The target split is technology-neutral so those +adapters can reuse the core/chip interface when they are ready. + +IHP SG13G2 does not currently provide pad cells implementing retroSoC's +programmable pull-up, pull-down, or Schmitt controls. The IHP implementation +uses input-only, 4 mA output, and 4 mA bidirectional cells; unsupported GPIO +pad-control features must not be represented as production-qualified behavior. + +A successful open-source run is evidence for implementation development, not a +foundry production-signoff claim. Release review still requires qualified +foundry decks, package and bond planning, electrical/ESD review, and approved +waivers. diff --git a/physical/librelane/pad_cfg.tcl b/physical/librelane/mini/pad_cfg.tcl similarity index 100% rename from physical/librelane/pad_cfg.tcl rename to physical/librelane/mini/pad_cfg.tcl diff --git a/physical/librelane/pdn_cfg.tcl b/physical/librelane/mini/pdn_cfg.tcl similarity index 100% rename from physical/librelane/pdn_cfg.tcl rename to physical/librelane/mini/pdn_cfg.tcl diff --git a/physical/librelane/scripts/doctor.py b/physical/librelane/mini/scripts/doctor.py similarity index 97% rename from physical/librelane/scripts/doctor.py rename to physical/librelane/mini/scripts/doctor.py index b38f3980..73b65449 100755 --- a/physical/librelane/scripts/doctor.py +++ b/physical/librelane/mini/scripts/doctor.py @@ -11,10 +11,10 @@ import sys from pathlib import Path -ROOT = Path(__file__).resolve().parents[3] +ROOT = Path(__file__).resolve().parents[4] sys.path.insert(0, str(ROOT)) from librelane.flows import Flow # noqa: E402 -from rtl.mini.pin_map.generate_pin_map import IHP130_POWER_PAD_COUNTS # noqa: E402 +from scripts.rtl.generate_pin_map import IHP130_POWER_PAD_COUNTS # noqa: E402 from scripts.setup_helpers import atomic_write # noqa: E402 diff --git a/physical/librelane/scripts/generate_chip_config.py b/physical/librelane/mini/scripts/generate_chip_config.py similarity index 97% rename from physical/librelane/scripts/generate_chip_config.py rename to physical/librelane/mini/scripts/generate_chip_config.py index 6a9a1709..b1370d4f 100755 --- a/physical/librelane/scripts/generate_chip_config.py +++ b/physical/librelane/mini/scripts/generate_chip_config.py @@ -11,9 +11,9 @@ import sys from pathlib import Path -ROOT = Path(__file__).resolve().parents[3] +ROOT = Path(__file__).resolve().parents[4] sys.path.insert(0, str(ROOT)) -from rtl.mini.pin_map.generate_pin_map import ( # noqa: E402 +from scripts.rtl.generate_pin_map import ( # noqa: E402 IHP130_POWER_PAD_COUNTS, Pad, ihp130_pad_instance, @@ -206,7 +206,7 @@ def build_config(args: argparse.Namespace) -> dict[str, object]: "SIGNOFF_SDC_FILE": config_path(args.sdc, config_dir), "FALLBACK_SDC": config_path(args.sdc, config_dir), "STA_EXTRA_CORNER_TCL_FILE": config_path( - ROOT / "physical/librelane/sta_report_limit.tcl", config_dir + ROOT / "physical/librelane/mini/sta_report_limit.tcl", config_dir ), "CLOCK_PORT": list(CLOCK_PORTS), "CLOCK_PERIOD": 1_000_000_000 / args.ext_clk_hz, @@ -259,7 +259,7 @@ def build_config(args: argparse.Namespace) -> dict[str, object]: "CORE_AREA": [365, 365, 7635, 7635], "PL_TARGET_DENSITY_PCT": 45, "PDN_CORE_RING_CONNECT_TO_PADS": True, - "PAD_CFG": config_path(ROOT / "physical/librelane/pad_cfg.tcl", config_dir), + "PAD_CFG": config_path(ROOT / "physical/librelane/mini/pad_cfg.tcl", config_dir), "PAD_BONDPAD_NAME": "bondpad_70x70", "EXTRA_GDS": [config_path(args.bondpad_gds, config_dir)], "EXTRA_LEFS": [config_path(args.bondpad_lef, config_dir)], diff --git a/physical/librelane/scripts/generate_sdc.py b/physical/librelane/mini/scripts/generate_sdc.py similarity index 96% rename from physical/librelane/scripts/generate_sdc.py rename to physical/librelane/mini/scripts/generate_sdc.py index 73f8d583..17485866 100755 --- a/physical/librelane/scripts/generate_sdc.py +++ b/physical/librelane/mini/scripts/generate_sdc.py @@ -9,9 +9,9 @@ import sys from pathlib import Path -ROOT = Path(__file__).resolve().parents[3] +ROOT = Path(__file__).resolve().parents[4] sys.path.insert(0, str(ROOT)) -from rtl.mini.pin_map.generate_pin_map import Pad, ihp130_pad_instance, read_map # noqa: E402 +from scripts.rtl.generate_pin_map import Pad, ihp130_pad_instance, read_map # noqa: E402 from scripts.check_clock_reset_domains import validate # noqa: E402 from scripts.setup_helpers import atomic_write # noqa: E402 @@ -91,7 +91,7 @@ def render(args: argparse.Namespace) -> str: groups[clock]["outputs"].append(pad.name) lines = [ - "# Generated by physical/librelane/scripts/generate_sdc.py; do not edit.", + "# Generated by physical/librelane/mini/scripts/generate_sdc.py; do not edit.", "current_design $::env(DESIGN_NAME)", "set_units -time ns", "", diff --git a/physical/librelane/scripts/package.py b/physical/librelane/mini/scripts/package.py similarity index 100% rename from physical/librelane/scripts/package.py rename to physical/librelane/mini/scripts/package.py diff --git a/physical/librelane/sram_blackboxes.vh b/physical/librelane/mini/sram_blackboxes.vh similarity index 100% rename from physical/librelane/sram_blackboxes.vh rename to physical/librelane/mini/sram_blackboxes.vh diff --git a/physical/librelane/sta_report_limit.tcl b/physical/librelane/mini/sta_report_limit.tcl similarity index 100% rename from physical/librelane/sta_report_limit.tcl rename to physical/librelane/mini/sta_report_limit.tcl diff --git a/physical/librelane/tiny/Makefile b/physical/librelane/tiny/Makefile new file mode 100644 index 00000000..63fa0ebd --- /dev/null +++ b/physical/librelane/tiny/Makefile @@ -0,0 +1,133 @@ +LIBRELANE_FLOW_ROOT := $(ROOT_PATH)/physical/librelane/tiny +LIBRELANE_RUN_ROOT := $(VARIANT_ROOT)/physical/librelane/tiny/chip +LIBRELANE_INPUT_DIR := $(LIBRELANE_RUN_ROOT)/input +LIBRELANE_RTL := $(LIBRELANE_INPUT_DIR)/retrosoc_tiny_asic_sources.sv +LIBRELANE_SDC := $(LIBRELANE_INPUT_DIR)/retrosoc_tiny_chip.sdc +LIBRELANE_BONDPAD_GDS := $(LIBRELANE_INPUT_DIR)/bondpad_70x70.gds +LIBRELANE_BONDPAD_LEF := $(ROOT_PATH)/physical/librelane/bondpad/bondpad_70x70.lef +LIBRELANE_CONFIG := $(LIBRELANE_RUN_ROOT)/config.json +LIBRELANE_LOG := $(LIBRELANE_RUN_ROOT)/librelane.log +LIBRELANE_RESULT := $(LIBRELANE_RUN_ROOT)/result.json +LIBRELANE_META_RESULT := $(META_DIR)/librelane-chip.json +LIBRELANE_DOCTOR_RESULT := $(META_DIR)/librelane-chip-doctor.json +LIBRELANE_FINAL_DIR := $(LIBRELANE_RUN_ROOT)/final +LIBRELANE_ARCHIVE := $(LIBRELANE_RUN_ROOT)/retrosoc-tiny-ihp130-chip.tar.gz +LIBRELANE_RUN_TAG ?= current +LIBRELANE_PDK_ROOT := $(ROOT_PATH)/physical/pdk/IHP-Open-PDK +LIBRELANE_PDK := ihp-sg13g2 +LIBRELANE_SCL := sg13g2_stdcell +LIBRELANE_PAD := sg13g2_io +LIBRELANE_KLAYOUT_PATH := $(LIBRELANE_PDK_ROOT)/$(LIBRELANE_PDK)/libs.tech/klayout +LIBRELANE_BONDPAD_SCRIPT := $(LIBRELANE_PDK_ROOT)/$(LIBRELANE_PDK)/libs.tech/klayout/tech/scripts/bondpad.py +LIBRELANE_PDN := $(LIBRELANE_FLOW_ROOT)/pdn_cfg.tcl +LIBRELANE_SRAM_VH := $(LIBRELANE_FLOW_ROOT)/sram_blackboxes.vh +LIBRELANE_STA_REPORT_LIMIT := $(LIBRELANE_FLOW_ROOT)/sta_report_limit.tcl +LIBRELANE_CLOCK_DOMAINS := $(RTL_PATH)/integration/clock_reset_domains.json +LIBRELANE_PIN_MAP := $(RTL_PATH)/pin_map/pin_map.json +LIBRELANE_TRACKED_RTL := $(shell git -C $(ROOT_PATH) ls-files \ + 'rtl/**/*.sv' 'rtl/**/*.svh' 'rtl/**/*.v' 'rtl/**/*.vh') + +LIBRELANE_SOURCE_PYTHON ?= /usr/bin/python3 +LIBRELANE_PYTHON ?= python3 +LIBRELANE_COMMAND := $(LIBRELANE_PYTHON) -m librelane +# LibreLane 3.0.5 writes 1000 expanded paths per group at every mid-PnR STA. +# Final multi-corner RCX STA remains mandatory; skip only the redundant reports. +LIBRELANE_MID_PNR_SKIP ?= --skip OpenROAD.STAMidPNR + +ifneq ($(filter librelane-input librelane-doctor librelane-chip \ + librelane-openroad librelane-klayout librelane-package,$(MAKECMDGOALS)),) +FLOW_PYTHON := $(LIBRELANE_SOURCE_PYTHON) +endif + +LIBRELANE_FEATURE_ARGS := \ + $(if $(filter YES,$(HAVE_PLL)),--have-pll) \ + $(if $(filter YES,$(HAVE_SRAM_IF)),--have-sram-if) \ + $(if $(filter YES,$(HAVE_SRAM_MACRO)),--have-sram-macro) \ + $(if $(filter YES,$(HAVE_SVA)),--have-sva) + +LIBRELANE_CONFIG_DEPS := $(LIBRELANE_RTL) $(LIBRELANE_SDC) \ + $(LIBRELANE_PDN) $(LIBRELANE_SRAM_VH) \ + $(LIBRELANE_STA_REPORT_LIMIT) $(LIBRELANE_BONDPAD_GDS) $(LIBRELANE_BONDPAD_LEF) \ + $(LIBRELANE_FLOW_ROOT)/scripts/generate_chip_config.py + +.PHONY: librelane-check-pdk librelane-input librelane-doctor librelane-chip \ + librelane-openroad librelane-klayout librelane-package + +librelane-check-pdk: + @test '$(PDK)' = IHP130 || { \ + echo 'physical/librelane/tiny currently implements only PDK=IHP130' >&2; exit 2; } + @test '$(HAVE_PLL)' = NO || { \ + echo 'the IHP130 LibreLane flow has no qualified crystal PAD' >&2; exit 2; } + +$(LIBRELANE_RTL): $(FILELIST_STAMP) $(LIBRELANE_TRACKED_RTL) \ + $(ROOT_PATH)/physical/smoke/syn/tools/export_soc_sources.py | librelane-check-pdk + @mkdir -p $(@D) + $(FLOW_PYTHON) $(ROOT_PATH)/physical/smoke/syn/tools/export_soc_sources.py sv \ + --output-dir $(@D) --soc TINY --pdk IHP130 --simu $(SIMU) \ + --jtag-idcode $(JTAG_IDCODE) \ + --ext-clk-hz $(EXT_CLK_HZ) --aud-clk-hz $(AUD_CLK_HZ) \ + --clint-timebase-hz $(CLINT_TIMEBASE_HZ) \ + --source-filelist-dir $(GENERATED_FL_DIR) \ + --librelane-safe \ + $(LIBRELANE_FEATURE_ARGS) + +$(LIBRELANE_SDC): $(LIBRELANE_FLOW_ROOT)/scripts/generate_sdc.py \ + $(LIBRELANE_CLOCK_DOMAINS) $(LIBRELANE_PIN_MAP) | librelane-check-pdk + @mkdir -p $(@D) + $(FLOW_PYTHON) $(LIBRELANE_FLOW_ROOT)/scripts/generate_sdc.py \ + --domains $(LIBRELANE_CLOCK_DOMAINS) --pin-map $(LIBRELANE_PIN_MAP) \ + --ext-clk-hz $(EXT_CLK_HZ) --output $@ + +$(LIBRELANE_BONDPAD_GDS): $(LIBRELANE_BONDPAD_SCRIPT) | librelane-check-pdk + @mkdir -p $(@D) + KLAYOUT_PATH=$(LIBRELANE_KLAYOUT_PATH) klayout -n sg13g2 -zz \ + -r $(LIBRELANE_BONDPAD_SCRIPT) -rd diameter=70.0 -rd shape=square \ + -rd output=$@ + @test -s $@ + +$(LIBRELANE_CONFIG): $(LIBRELANE_CONFIG_DEPS) + $(FLOW_PYTHON) $(LIBRELANE_FLOW_ROOT)/scripts/generate_chip_config.py \ + --pin-map $(LIBRELANE_PIN_MAP) --rtl $(LIBRELANE_RTL) --sdc $(LIBRELANE_SDC) \ + --pdn $(LIBRELANE_PDN) --bondpad-gds $(LIBRELANE_BONDPAD_GDS) \ + --bondpad-lef $(LIBRELANE_BONDPAD_LEF) --sram-vh $(LIBRELANE_SRAM_VH) \ + --ext-clk-hz $(EXT_CLK_HZ) --sram-size-kib $(SRAM_SIZE_KIB) \ + $(if $(filter YES,$(HAVE_SRAM_MACRO)),--have-sram-macro) \ + --output $@ + +librelane-input: $(LIBRELANE_CONFIG) + +$(LIBRELANE_DOCTOR_RESULT): $(LIBRELANE_CONFIG) \ + $(LIBRELANE_FLOW_ROOT)/scripts/doctor.py + @mkdir -p $(@D) + $(LIBRELANE_PYTHON) $(LIBRELANE_FLOW_ROOT)/scripts/doctor.py \ + --root $(ROOT_PATH) --config $(LIBRELANE_CONFIG) --lock $(LOCK_FILE) \ + --pin-map $(LIBRELANE_PIN_MAP) --pdk-root $(LIBRELANE_PDK_ROOT) --output $@ + +librelane-doctor: $(LIBRELANE_DOCTOR_RESULT) + +librelane-chip: librelane-doctor manifest + $(FLOW_PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool librelane \ + --log $(LIBRELANE_LOG) --result $(LIBRELANE_RESULT) --cwd $(LIBRELANE_RUN_ROOT) -- \ + $(LIBRELANE_COMMAND) $(LIBRELANE_CONFIG) --manual-pdk --pdk $(LIBRELANE_PDK) \ + --pdk-root $(LIBRELANE_PDK_ROOT) --scl $(LIBRELANE_SCL) --pad $(LIBRELANE_PAD) \ + --run-tag $(LIBRELANE_RUN_TAG) --overwrite --jobs $(JOBS) $(LIBRELANE_MID_PNR_SKIP) \ + --condensed --hide-progress-bar --save-views-to $(LIBRELANE_FINAL_DIR) + @mkdir -p $(META_DIR) + @cp $(LIBRELANE_RESULT) $(LIBRELANE_META_RESULT) + +librelane-openroad: librelane-doctor + cd $(LIBRELANE_RUN_ROOT) && $(LIBRELANE_COMMAND) $(LIBRELANE_CONFIG) --manual-pdk \ + --pdk $(LIBRELANE_PDK) --pdk-root $(LIBRELANE_PDK_ROOT) \ + --scl $(LIBRELANE_SCL) --pad $(LIBRELANE_PAD) \ + --run-tag $(LIBRELANE_RUN_TAG) --last-run --flow OpenInOpenROAD + +librelane-klayout: librelane-doctor + cd $(LIBRELANE_RUN_ROOT) && $(LIBRELANE_COMMAND) $(LIBRELANE_CONFIG) --manual-pdk \ + --pdk $(LIBRELANE_PDK) --pdk-root $(LIBRELANE_PDK_ROOT) \ + --scl $(LIBRELANE_SCL) --pad $(LIBRELANE_PAD) \ + --run-tag $(LIBRELANE_RUN_TAG) --last-run --flow OpenInKLayout + +librelane-package: librelane-chip + $(FLOW_PYTHON) $(LIBRELANE_FLOW_ROOT)/scripts/package.py \ + --root $(ROOT_PATH) --variant-root $(VARIANT_ROOT) \ + --run-root $(LIBRELANE_RUN_ROOT) --output $(LIBRELANE_ARCHIVE) diff --git a/physical/librelane/tiny/README.md b/physical/librelane/tiny/README.md new file mode 100644 index 00000000..a050916f --- /dev/null +++ b/physical/librelane/tiny/README.md @@ -0,0 +1,52 @@ +# Tiny LibreLane IHP130 Chip Flow + +This directory owns the Tiny product line's open-source IHP130 implementation +entry point: `librelane-chip` implements the bare-die `retrosoc_tiny_asic` +MCU, including its pad ring, bondpads, fillers, corners, seal ring, and the +32 on-chip SRAM bank macros. + +The flow consumes the committed `configs/ci/ihp130-tiny.mk` profile, the +canonical Tiny pin map (`rtl/tiny/pin_map/pin_map.json`), the Tiny clock/reset +inventory (`rtl/tiny/integration/clock_reset_domains.json`), and the +IHP-Open-PDK revision in `dependencies/dependencies.lock.json`. LibreLane reads +the upstream `ihp-sg13g2/libs.tech/librelane` configuration directly through +manual-PDK mode. Generated RTL, SDC, configuration, run databases, reports, and +final views are written below `build//physical/librelane/tiny/chip/`. + +Use the LibreLane 3.0.5 development shell (`~/squashfs-root/AppRun`) and put +the locked OpenSTA 3.0.0 first on `PATH`: + +```sh +~/squashfs-root/AppRun bash -c 'export PATH=/nfs/home/miaoyuchi/artifact-opensta/bin:$PATH; cd ' +make CONFIG=configs/ci/ihp130-tiny.mk librelane-doctor +make CONFIG=configs/ci/ihp130-tiny.mk librelane-chip +make CONFIG=configs/ci/ihp130-tiny.mk librelane-package +``` + +## Pad Ring + +The Tiny pin map declares 52 signal PADs (external clock/reset, JTAG, two +UARTs, 32 GPIOs, and the quad-XPI NOR flash interface). Tiny ships a reduced +supply set of 8 VDD + 8 VSS + 8 IOVDD + 8 IOVSS (two pairs of each per side), +84 placed PADs in total. The reduction from the Mini line's 24/24/16/16 follows +the taped-out Basilisk IHP SG13G2 SoC pad frame (68 signals with 24/24/16/16 +supplies feeding a Linux-capable CVA6 at a much higher clock and IO rate): +Tiny's 24 MHz Hazard3 core draws a few mA, and even with all 52 4 mA outputs +switching simultaneously each IO supply pair carries only ~26 mA. + +The side assignment is south = clock/reset/JTAG/UART, north = XPI, +east = GPIO[15:0], west = GPIO[31:16]; the `power_pads` counts come from +`rtl/tiny/pin_map/pin_map.json` and must match `pad_cfg.tcl`. + +## Constraints + +The SDC constrains the external clock at 24 MHz and JTAG at 10 MHz, defines a +generated system clock at the top-level clock buffer, and keeps the two groups +asynchronous. Mid-PnR timing report passes are skipped because LibreLane 3.0.5 +emits 1000 expanded paths per group; final post-RCX multi-corner STA remains +enabled. + +A successful open-source run is evidence for implementation development, not a +foundry production-signoff claim. Release review still requires qualified +foundry decks, package and bond planning, electrical/ESD review, and approved +waivers. diff --git a/physical/librelane/tiny/pad_cfg.tcl b/physical/librelane/tiny/pad_cfg.tcl new file mode 100644 index 00000000..6202685c --- /dev/null +++ b/physical/librelane/tiny/pad_cfg.tcl @@ -0,0 +1,17 @@ +# IHP SG13G2 supply pads are physical-only cells and are not retained by Yosys. +# Tiny ships two core and two IO supply pairs per pad-ring side (8/8/8/8). +foreach {kind master count} { + vdd sg13g2_IOPadVdd 8 + vss sg13g2_IOPadVss 8 + iovdd sg13g2_IOPadIOVdd 8 + iovss sg13g2_IOPadIOVss 8 +} { + for {set index 0} {$index < $count} {incr index} { + set instance_name [format {%s_pads[%d].%s_pad} $kind $index $kind] + set db_block [ord::get_db_block] + if {[$db_block findInst $instance_name] == "NULL"} { + make_instance $instance_name $master + } + } +} +source $::env(SCRIPTS_DIR)/openroad/common/pad_cfg.tcl diff --git a/physical/librelane/tiny/pdn_cfg.tcl b/physical/librelane/tiny/pdn_cfg.tcl new file mode 100644 index 00000000..51e3f682 --- /dev/null +++ b/physical/librelane/tiny/pdn_cfg.tcl @@ -0,0 +1,193 @@ +# Copyright 2025-2026 LibreLane Contributors and retroSoC Authors +# SPDX-License-Identifier: Apache-2.0 +# Tiny IHP130 chip PDN: LibreLane default sg13g2 topology (M1 rails connect to +# the TopMetal1 stripe network directly) plus a macro grid that ties the SRAM +# banks' Metal4 power columns into the stripe network with Metal5 cross straps. + +source $::env(SCRIPTS_DIR)/openroad/common/io.tcl +source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl +set_global_connections + +# Use the PDK-native alternating routing directions (H/V/H/V/H). +set secondary_supplies [] +foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) { + if {$vdd != $::env(VDD_NET)} { + lappend secondary_supplies $vdd + set db_net [[ord::get_db_block] findNet $vdd] + if {$db_net == "NULL"} { + set net [odb::dbNet_create [ord::get_db_block] $vdd] + $net setSpecial + $net setSigType "POWER" + } + } + if {$gnd != $::env(GND_NET)} { + lappend secondary_supplies $gnd + set db_net [[ord::get_db_block] findNet $gnd] + if {$db_net == "NULL"} { + set net [odb::dbNet_create [ord::get_db_block] $gnd] + $net setSpecial + $net setSigType "GROUND" + } + } +} + +# I/O rails are pad-ring internal and are absent from the synthesized top-level. +foreach {net signal_type} {IOVDD POWER IOVSS GROUND} { + set db_net [[ord::get_db_block] findNet $net] + if {$db_net == "NULL"} { + set db_net [odb::dbNet_create [ord::get_db_block] $net] + $db_net setSpecial + $db_net setSigType $signal_type + } +} + +# IHP IO cells carry both core and external-IO power rails on lower-case pins. +add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern vdd -power +add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern vss -ground +add_global_connection -net IOVDD -inst_pattern .* -pin_pattern iovdd -power +add_global_connection -net IOVSS -inst_pattern .* -pin_pattern iovss -ground +global_connect -verbose + +# connect_by_abutment assigns IHP pad rails to corner-local *_RING nets. Rebind +# those physical pad and filler pins so the PDN knows they are VDD/VSS terminals. +proc reconnect_ihp_padring_rails {block} { + foreach {net_name pin_name} { + VDD vdd + VSS vss + IOVDD iovdd + IOVSS iovss + } { + set net [$block findNet $net_name] + foreach inst [$block getInsts] { + set master_name [[$inst getMaster] getName] + if {![string match "sg13g2_IOPad*" $master_name] && + ![string match "sg13g2_Filler*" $master_name] && + ![string match "sg13g2_Corner*" $master_name]} { + continue + } + foreach iterm [$inst getITerms] { + if {[[$iterm getMTerm] getName] != $pin_name} { + continue + } + odb::dbITerm_disconnect $iterm + odb::dbITerm_connect $iterm $net + } + } + } +} +reconnect_ihp_padring_rails [ord::get_db_block] + +set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \ + -secondary_power $secondary_supplies + +set stdcell_grid_args [list] +if {$::env(PDN_ENABLE_PINS) == 1} { + lappend stdcell_grid_args -pins "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)" +} +define_pdn_grid \ + -name stdcell_grid \ + -starts_with POWER \ + -voltage_domain CORE \ + {*}$stdcell_grid_args + +add_pdn_stripe \ + -grid stdcell_grid \ + -layer $::env(PDN_VERTICAL_LAYER) \ + -width $::env(PDN_VWIDTH) \ + -pitch $::env(PDN_VPITCH) \ + -offset $::env(PDN_VOFFSET) \ + -spacing $::env(PDN_VSPACING) \ + -starts_with POWER \ + -extend_to_core_ring + +add_pdn_stripe \ + -grid stdcell_grid \ + -layer $::env(PDN_HORIZONTAL_LAYER) \ + -width $::env(PDN_HWIDTH) \ + -pitch $::env(PDN_HPITCH) \ + -offset $::env(PDN_HOFFSET) \ + -spacing $::env(PDN_HSPACING) \ + -starts_with POWER \ + -extend_to_core_ring + +# A low-metal ring just inside the core edge collects the Metal1 rails; the +# top-metal stripe mesh bridges to it where the stripes cross the ring legs. +add_pdn_ring \ + -grid stdcell_grid \ + -layers "Metal2 Metal3" \ + -widths "0.52 0.52" \ + -spacings "0.8 0.8" \ + -core_offsets "1.6 1.6" \ + -starts_with POWER \ + -add_connect + +if {$::env(PDN_ENABLE_RAILS) == 1} { + add_pdn_stripe \ + -grid stdcell_grid \ + -layer $::env(PDN_RAIL_LAYER) \ + -width $::env(PDN_RAIL_WIDTH) \ + -followpins \ + -extend_to_core_ring + add_pdn_connect -grid stdcell_grid -layers "Metal1 Metal2" + add_pdn_connect -grid stdcell_grid -layers "Metal1 Metal3" + # The rail network meets the top-metal mesh at the low ring legs and at + # every Metal1 rail / TopMetal1 stripe crossing (covers the standard-cell + # channels between SRAM banks as well). + add_pdn_connect -grid stdcell_grid -layers "Metal3 TopMetal1" + add_pdn_connect -grid stdcell_grid -layers "Metal1 TopMetal1" + add_pdn_connect -grid stdcell_grid -layers "Metal2 TopMetal2" +} + +if {$::env(PDN_CORE_RING) == 1} { + add_pdn_ring \ + -grid stdcell_grid \ + -layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)" \ + -widths "$::env(PDN_CORE_RING_VWIDTH) $::env(PDN_CORE_RING_HWIDTH)" \ + -spacings "$::env(PDN_CORE_RING_VSPACING) $::env(PDN_CORE_RING_HSPACING)" \ + -core_offsets "$::env(PDN_CORE_RING_VOFFSET) $::env(PDN_CORE_RING_HOFFSET)" \ + -connect_to_pads \ + -connect_to_pad_layers TopMetal2 \ + -add_connect +} + +# Tiny hardens a single SRAM master: the 128 KiB on-chip RAM banks. Their power +# pins are vertical Metal4 columns spanning the bank height; horizontal Metal5 +# straps cross every column and hand off to the stdcell TopMetal1 stripes +# outside the bank boundary. +set sram_cells [list \ + RM_IHPSG13_1P_1024x32_c2_bm_bist] + +define_pdn_grid \ + -macro \ + -cells $sram_cells \ + -name sram_bank_grid \ + -grid_over_boundary \ + -voltage_domains CORE \ + -starts_with POWER + +add_pdn_ring \ + -grid sram_bank_grid \ + -layers "Metal2 Metal3" \ + -widths "0.52 0.52" \ + -spacings "0.8 0.8" \ + -core_offsets "1.6 1.6" \ + -starts_with POWER \ + -add_connect + +add_pdn_stripe \ + -grid sram_bank_grid \ + -layer Metal5 \ + -width 2.5 \ + -pitch 67.24 \ + -offset 10.0 \ + -spacing 2.5 \ + -starts_with POWER + +add_pdn_connect -grid sram_bank_grid -layers "Metal4 Metal5" +add_pdn_connect -grid sram_bank_grid -layers "Metal5 TopMetal1" +add_pdn_connect -grid sram_bank_grid -layers "Metal2 TopMetal1" +add_pdn_connect -grid sram_bank_grid -layers "Metal3 TopMetal1" +add_pdn_connect -grid sram_bank_grid -layers "TopMetal1 TopMetal2" +# Rails trapped in the channels between banks tie into the bank rings. +add_pdn_connect -grid sram_bank_grid -layers "Metal1 Metal2" +add_pdn_connect -grid sram_bank_grid -layers "Metal1 Metal3" diff --git a/physical/librelane/tiny/scripts/doctor.py b/physical/librelane/tiny/scripts/doctor.py new file mode 100644 index 00000000..58ce9c31 --- /dev/null +++ b/physical/librelane/tiny/scripts/doctor.py @@ -0,0 +1,165 @@ +#!/usr/bin/env python3 +"""Validate the local LibreLane/IHP130 environment and Tiny chip configuration.""" + +from __future__ import annotations + +import argparse +import json +import shutil +import subprocess +import sys +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[4] +sys.path.insert(0, str(ROOT)) +from librelane.flows import Flow # noqa: E402 +from scripts.rtl.generate_pin_map import read_power_pad_counts # noqa: E402 +from scripts.setup_helpers import atomic_write # noqa: E402 + + +EXPECTED_LIBRELANE_VERSION = "LibreLane v3.0.5" +EXPECTED_OPENSTA_VERSION = "3.0.0" +EXPECTED_SIGNAL_PADS = 52 + + +def command_output(command: list[str]) -> str: + return subprocess.check_output(command, text=True, stderr=subprocess.STDOUT).strip() + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--root", type=Path, required=True) + parser.add_argument("--config", type=Path, required=True) + parser.add_argument("--lock", type=Path, required=True) + parser.add_argument("--pin-map", type=Path, required=True) + parser.add_argument("--pdk-root", type=Path, required=True) + parser.add_argument("--output", type=Path, required=True) + args = parser.parse_args() + errors: list[str] = [] + details: dict[str, object] = {} + + for tool in ("librelane", "klayout", "sta"): + path = shutil.which(tool) + details[f"{tool}_path"] = path + if path is None: + errors.append(f"required tool is missing: {tool}") + + if shutil.which("librelane") is not None: + version = command_output( + [sys.executable, "-m", "librelane", "--version"] + ).splitlines()[0] + details["librelane_version"] = version + if version != EXPECTED_LIBRELANE_VERSION: + errors.append(f"expected {EXPECTED_LIBRELANE_VERSION}, found {version or ''}") + + if shutil.which("sta") is not None: + version = command_output(["sta", "-version"]) + details["opensta_version"] = version + if version != EXPECTED_OPENSTA_VERSION: + errors.append( + f"expected OpenSTA {EXPECTED_OPENSTA_VERSION}, " + f"found {version or ''}" + ) + + lock = json.loads(args.lock.read_text(encoding="utf-8")) + expected_pdk_revision = lock["sources"]["pdk_ihp130"]["revision"] + details["locked_pdk_revision"] = expected_pdk_revision + + pdk_checkout = args.pdk_root.resolve() + if not (pdk_checkout / ".git").exists(): + errors.append(f"IHP PDK checkout is missing: {pdk_checkout}") + else: + revision = command_output(["git", "-C", str(pdk_checkout), "rev-parse", "HEAD"]) + details["pdk_revision"] = revision + if revision != expected_pdk_revision: + errors.append(f"expected IHP PDK {expected_pdk_revision}, found {revision}") + + required = ( + args.config, + pdk_checkout / "ihp-sg13g2/libs.tech/librelane/config.tcl", + pdk_checkout / "ihp-sg13g2/libs.tech/klayout/tech/drc/ihp-sg13g2.drc", + pdk_checkout / "ihp-sg13g2/libs.tech/klayout/tech/scripts/sealring.py", + pdk_checkout / "ihp-sg13g2/libs.ref/sg13g2_io/spice/sg13g2_io.spice", + ) + for path in required: + if not path.is_file(): + errors.append(f"required LibreLane/IHP file is missing: {path}") + + try: + power_counts = read_power_pad_counts(args.pin_map) + except (OSError, ValueError, json.JSONDecodeError) as error: + power_counts = None + errors.append(f"failed to read power PAD counts: {error}") + + config: dict[str, object] = {} + flow_name = "" + if args.config.is_file(): + try: + config = json.loads(args.config.read_text(encoding="utf-8")) + meta = config.get("meta", {}) + if not isinstance(meta, dict) or not isinstance(meta.get("flow"), str): + raise ValueError("config meta.flow must name a LibreLane flow") + flow_name = meta["flow"] + except (OSError, ValueError, json.JSONDecodeError) as error: + errors.append(f"failed to read LibreLane configuration: {error}") + + if args.config.is_file() and not errors: + try: + flow_class = Flow.factory.get(flow_name) + if flow_class is None: + raise ValueError(f"unknown LibreLane flow: {flow_name}") + flow = flow_class( + str(args.config.resolve()), + pdk="ihp-sg13g2", + pdk_root=str(pdk_checkout), + scl="sg13g2_stdcell", + pad="sg13g2_io", + design_dir=str(args.config.resolve().parent), + ) + details["flow"] = flow_name + details["config_design"] = flow.config["DESIGN_NAME"] + details["drc_runset"] = str(flow.config["KLAYOUT_DRC_RUNSET"]) + details["lvs_setup"] = str(flow.config["NETGEN_SETUP"]) + details["pad_spice"] = [str(path) for path in flow.config["PAD_SPICE_MODELS"]] + except Exception as error: # LibreLane reports structured configuration exceptions. + errors.append(f"LibreLane {flow_name or 'unknown'} configuration failed to load: {error}") + + if config: + if details.get("config_design") not in (None, "retrosoc_tiny_asic"): + errors.append( + f"Tiny chip flow expects DESIGN_NAME retrosoc_tiny_asic, " + f"found {details['config_design']}" + ) + placed = [ + item + for side in ("PAD_SOUTH", "PAD_EAST", "PAD_NORTH", "PAD_WEST") + for item in config.get(side, []) + ] + details["placed_pad_count"] = len(placed) + if flow_name == "Chip" and power_counts is not None: + expected = EXPECTED_SIGNAL_PADS + sum(power_counts.values()) + if len(placed) != expected or len(placed) != len(set(placed)): + errors.append( + f"expected {expected} unique placed signal/power PADs, found {len(placed)}" + ) + elif flow_name != "Chip": + errors.append(f"Tiny supports only the Chip flow, found {flow_name}") + + result = { + "schema_version": 1, + "status": "passed" if not errors else "failed", + "errors": errors, + "details": details, + } + atomic_write(args.output, json.dumps(result, indent=2, sort_keys=True) + "\n") + if errors: + for error in errors: + print(f"ERROR: {error}", file=sys.stderr) + return 1 + print(f"LibreLane doctor passed: {args.output}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/physical/librelane/tiny/scripts/generate_chip_config.py b/physical/librelane/tiny/scripts/generate_chip_config.py new file mode 100644 index 00000000..782be724 --- /dev/null +++ b/physical/librelane/tiny/scripts/generate_chip_config.py @@ -0,0 +1,295 @@ +#!/usr/bin/env python3 +"""Generate the IHP130 LibreLane Chip configuration for the Tiny SoC.""" + +from __future__ import annotations + +import argparse +import json +import os +import re +import sys +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[4] +sys.path.insert(0, str(ROOT)) +from scripts.rtl.generate_pin_map import ( # noqa: E402 + POWER_PAD_KINDS, + Pad, + ihp130_pad_instance, + read_map, + read_power_pad_counts, +) +from scripts.setup_helpers import atomic_write # noqa: E402 + + +SIDE_ORDER = ("south", "east", "north", "west") +EXPECTED_SIGNAL_PADS = 52 +CLOCK_PORTS = ("extclk_i_pad", "jtag_tck_i_pad") +SRAM_MASTER = "RM_IHPSG13_1P_1024x32_c2_bm_bist" +SRAM_INSTANCE = "u_soc.u_sram.gen_memory.gen_bank[{index}].u_ram.u_mem" +SRAM_COLUMNS = 8 +SRAM_ORIGIN = (400, 600) +# Detailed routing requires an M2 track inside each bank's 0.26 um bottom-edge +# pin stubs: the bank y origin must keep residue {0, 0.24} mod 0.42 um (the M2 +# vertical track pitch); a y pitch of 504 um (1200 x 0.42) preserves it per row. +SRAM_PITCH = (480, 504) +DIE_AREA = [0, 0, 4700, 4700] +CORE_AREA = [365, 365, 4335, 4335] + + +def config_path(path: Path, base: Path) -> str: + return f"dir::{os.path.relpath(path.resolve(), base.resolve())}" + + +def signal_side(pad: Pad) -> str: + name = pad.name + if name.startswith("gpio_"): + return "east" if pad.index is not None and pad.index < 16 else "west" + if name.startswith("xpi_"): + return "north" + return "south" + + +def power_instances(counts: dict[str, int], side_index: int) -> list[str]: + per_side: dict[str, int] = {} + for kind in POWER_PAD_KINDS: + count = counts[kind] + if count % len(SIDE_ORDER) != 0: + raise ValueError( + f"power_pads.{kind}={count} cannot be distributed across " + f"{len(SIDE_ORDER)} pad-ring sides" + ) + per_side[kind] = count // len(SIDE_ORDER) + result: list[str] = [] + for local_index in range(per_side["vdd"]): + for kind in ("vdd", "vss"): + index = (side_index * per_side[kind]) + local_index + result.append(f"{kind}_pads[{index}].{kind}_pad") + for local_index in range(per_side["iovdd"]): + for kind in ("iovdd", "iovss"): + index = (side_index * per_side[kind]) + local_index + result.append(f"{kind}_pads[{index}].{kind}_pad") + return result + + +def interleave(signals: list[str], supplies: list[str]) -> list[str]: + result: list[str] = [] + signal_index = 0 + for supply_index, supply in enumerate(supplies): + target = round(((supply_index + 1) * len(signals)) / (len(supplies) + 1)) + result.extend(signals[signal_index:target]) + signal_index = target + result.append(supply) + result.extend(signals[signal_index:]) + return result + + +def sram_instances(capacity_kib: int) -> dict[str, tuple[list[int], str]]: + if capacity_kib <= 0 or capacity_kib % 4 != 0: + raise ValueError("SRAM_SIZE_KIB must be a positive multiple of 4") + instances: dict[str, tuple[list[int], str]] = {} + for index in range(capacity_kib // 4): + column, row = index % SRAM_COLUMNS, index // SRAM_COLUMNS + location = [ + SRAM_ORIGIN[0] + column * SRAM_PITCH[0], + SRAM_ORIGIN[1] + row * SRAM_PITCH[1], + ] + instances[SRAM_INSTANCE.format(index=index)] = (location, "N") + return instances + + +def macro_config(instances: dict[str, tuple[list[int], str]], header: str) -> dict[str, object]: + base = "pdk_dir::libs.ref/sg13g2_sram" + master = SRAM_MASTER + return { + "gds": [f"{base}/gds/{master}.gds"], + "lef": [f"{base}/lef/{master}.lef"], + "vh": [header], + "spice": [f"{base}/cdl/{master}.cdl"], + "lib": { + "*_typ_1p20V_25C": [f"{base}/lib/{master}_typ_1p20V_25C.lib"], + "*_fast_1p32V_m40C": [f"{base}/lib/{master}_fast_1p32V_m55C.lib"], + "*_slow_1p08V_125C": [f"{base}/lib/{master}_slow_1p08V_125C.lib"], + }, + "instances": { + name: {"location": location, "orientation": orientation} + for name, (location, orientation) in instances.items() + }, + } + + +def macro_hooks(instances: dict[str, tuple[list[int], str]]) -> list[str]: + hooks: list[str] = [] + for instance in instances: + bracket_start = instance.find("[") + if bracket_start >= 0: + bracket_end = instance.index("]", bracket_start) + instance_pattern = ( + re.escape(instance[:bracket_start]) + + ".*" + + instance[bracket_start + 1 : bracket_end] + + ".*" + + re.escape(instance[bracket_end + 1 :]) + ) + else: + instance_pattern = re.escape(instance) + hooks.extend( + [ + f"{instance_pattern} VDD VSS VDDARRAY! VSS!", + f"{instance_pattern} VDD VSS VDD! VSS!", + ] + ) + return hooks + + +def build_config(args: argparse.Namespace) -> dict[str, object]: + pads, _ = read_map(args.pin_map) + power_counts = read_power_pad_counts(args.pin_map) + signal_instances: dict[str, list[str]] = {side: [] for side in SIDE_ORDER} + for pad in pads: + instance = ihp130_pad_instance(pad) + if instance is None: + raise ValueError(f"IHP130 physical PAD mapping is missing for {pad.name}") + signal_instances[signal_side(pad)].append(instance) + + flattened = [item for side in SIDE_ORDER for item in signal_instances[side]] + if len(flattened) != EXPECTED_SIGNAL_PADS: + raise ValueError( + f"expected {EXPECTED_SIGNAL_PADS} signal PADs, got {len(flattened)}" + ) + if len(flattened) != len(set(flattened)): + raise ValueError("physical signal PAD instances are not unique") + + pad_sides = { + side.upper(): interleave(signal_instances[side], power_instances(power_counts, index)) + for index, side in enumerate(SIDE_ORDER) + } + all_placed = [item for side in SIDE_ORDER for item in pad_sides[side.upper()]] + expected_total = len(flattened) + sum(power_counts.values()) + if len(all_placed) != expected_total or len(all_placed) != len(set(all_placed)): + raise ValueError( + "PAD ring placement does not cover every signal and power PAD exactly once" + ) + + config_dir = args.output.resolve().parent + sram_header = config_path(args.sram_vh, config_dir) + active_sram_instances = sram_instances(args.sram_size_kib) if args.have_sram_macro else {} + macros = ( + {SRAM_MASTER: macro_config(active_sram_instances, sram_header)} + if active_sram_instances + else {} + ) + + return { + "meta": {"version": 3, "flow": "Chip"}, + "DESIGN_NAME": "retrosoc_tiny_asic", + "VERILOG_FILES": [config_path(args.rtl, config_dir)], + "USE_SLANG": True, + "SLANG_ARGUMENTS": ["--keep-hierarchy"], + "VERILOG_POWER_DEFINE": None, + "SYNTH_SHARE_RESOURCES": False, + "SYNTH_HIERARCHY_MODE": "deferred_flatten", + "SYNTH_KEEP_HIERARCHY_MODULES": [ + "sg13g2_IOPadVdd", + "sg13g2_IOPadVss", + "sg13g2_IOPadIOVdd", + "sg13g2_IOPadIOVss", + ], + "YOSYS_LOG_LEVEL": "WARNING", + "SYNTH_STRATEGY": "AREA 3", + # Hotspots sit at the SRAM bank pin edges; detailed routing resolves the + # moderate estimated overflow. The signoff bar remains detailed-routing + # DRC, post-RCX multi-corner STA, KLayout DRC, and netgen LVS. + "GRT_ALLOW_CONGESTION": True, + # This OpenROAD build's antenna analysis leaks/stalls on the Tiny netlist + # (check_antennas -verbose ballooned to 248 GB RSS; repair_antennas did + # not converge in 100 minutes). Skip the report/repair steps; antenna + # coverage is a documented gap for this flow revision. + "RUN_ANTENNA_REPAIR": False, + # Hazard3 with EXTENSION_A=0 (RV32IM) leaves x_amo_phase undriven by + # design; every use is masked by a constant-false guard. Waive the + # three benign "used but has no driver" check errors. + "ERROR_ON_SYNTH_CHECKS": False, + "RUN_POST_GPL_DESIGN_REPAIR": False, + "RUN_CTS": False, + "RUN_POST_CTS_RESIZER_TIMING": False, + "EXTRA_EXCLUDED_CELLS": ["sg13g2_IOPad*"], + "PRIMARY_GDSII_STREAMOUT_TOOL": "klayout", + "PNR_SDC_FILE": config_path(args.sdc, config_dir), + "SIGNOFF_SDC_FILE": config_path(args.sdc, config_dir), + "FALLBACK_SDC": config_path(args.sdc, config_dir), + "STA_EXTRA_CORNER_TCL_FILE": config_path( + ROOT / "physical/librelane/tiny/sta_report_limit.tcl", config_dir + ), + "CLOCK_PORT": list(CLOCK_PORTS), + "CLOCK_PERIOD": 1_000_000_000 / args.ext_clk_hz, + "VDD_NETS": ["VDD"], + "GND_NETS": ["VSS"], + "FP_SIZING": "absolute", + "PDN_CORE_RING": True, + "PDN_CORE_RING_VWIDTH": 15, + "PDN_CORE_RING_HWIDTH": 15, + "PDN_CORE_RING_VSPACING": 5, + "PDN_CORE_RING_HSPACING": 5, + "PDN_ENABLE_PINS": True, + "ERROR_ON_PDN_VIOLATIONS": True, + "PDN_CFG": config_path(args.pdn, config_dir), + "MACROS": macros, + "PDN_MACRO_CONNECTIONS": macro_hooks(active_sram_instances), + "MAGIC_GDS_FLATGLOB": [ + "lvsres_*", + "VIA_M1_*", + "VIA_M2_*", + "*_CELL_CORNER", + "RSC_*", + "*_CELL_SUB", + ], + "PAD_SOUTH": pad_sides["SOUTH"], + "PAD_EAST": pad_sides["EAST"], + "PAD_NORTH": pad_sides["NORTH"], + "PAD_WEST": pad_sides["WEST"], + "DIE_AREA": DIE_AREA, + "CORE_AREA": CORE_AREA, + "PL_TARGET_DENSITY_PCT": 45, + "PDN_CORE_RING_CONNECT_TO_PADS": True, + "PAD_CFG": config_path(ROOT / "physical/librelane/tiny/pad_cfg.tcl", config_dir), + "PAD_BONDPAD_NAME": "bondpad_70x70", + "EXTRA_GDS": [config_path(args.bondpad_gds, config_dir)], + "EXTRA_LEFS": [config_path(args.bondpad_lef, config_dir)], + "IGNORE_DISCONNECTED_MODULES": ["bondpad_70x70"], + "MAGIC_EXT_UNIQUE": "notopports", + } + + +def positive_integer(value: str) -> int: + parsed = int(value) + if parsed <= 0: + raise argparse.ArgumentTypeError("value must be positive") + return parsed + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--pin-map", type=Path, required=True) + parser.add_argument("--rtl", type=Path, required=True) + parser.add_argument("--sdc", type=Path, required=True) + parser.add_argument("--pdn", type=Path, required=True) + parser.add_argument("--bondpad-gds", type=Path, required=True) + parser.add_argument("--bondpad-lef", type=Path, required=True) + parser.add_argument("--sram-vh", type=Path, required=True) + parser.add_argument("--ext-clk-hz", type=positive_integer, required=True) + parser.add_argument("--have-sram-macro", action="store_true") + parser.add_argument("--sram-size-kib", type=positive_integer, default=128) + parser.add_argument("--output", type=Path, required=True) + args = parser.parse_args() + try: + config = build_config(args) + atomic_write(args.output, json.dumps(config, indent=2, sort_keys=True) + "\n") + except (OSError, ValueError, json.JSONDecodeError) as error: + parser.error(str(error)) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/physical/librelane/tiny/scripts/generate_sdc.py b/physical/librelane/tiny/scripts/generate_sdc.py new file mode 100644 index 00000000..49084619 --- /dev/null +++ b/physical/librelane/tiny/scripts/generate_sdc.py @@ -0,0 +1,172 @@ +#!/usr/bin/env python3 +"""Generate pad-aware timing constraints for the Tiny IHP130 Chip flow.""" + +from __future__ import annotations + +import argparse +import json +import sys +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[4] +sys.path.insert(0, str(ROOT)) +from scripts.rtl.generate_pin_map import Pad, ihp130_pad_instance, read_map # noqa: E402 +from scripts.check_clock_reset_domains import validate # noqa: E402 +from scripts.setup_helpers import atomic_write # noqa: E402 + + +CLOCK_PADS = { + "external": "extclk_i_pad", + "jtag": "jtag_tck_i_pad", +} +RESET_PADS = {"ext_rst_n_i_pad", "jtag_trst_n_i_pad"} +IHP130_SYSTEM_CLOCK_PIN = "u_clock_buffer.u_sg13g2_buf_1/X" +JTAG_PERIOD_NS = 100.0 + + +def positive_integer(value: str) -> int: + parsed = int(value) + if parsed <= 0: + raise argparse.ArgumentTypeError("value must be positive") + return parsed + + +def timing_clock(pad: Pad) -> str: + if pad.name.startswith("jtag_"): + return "jtag" + return "external" + + +def logical_directions(pad: Pad) -> tuple[bool, bool]: + input_kinds = {"tri_input", "schmitt_input"} + output_kinds = {"tri_output", "peripheral_output"} + bidir_kinds = {"full", "peripheral_bidir", "xpi_data"} + if pad.kind in input_kinds: + return True, False + if pad.kind in output_kinds: + return False, True + if pad.kind in bidir_kinds: + return True, True + return False, False + + +def render(args: argparse.Namespace) -> str: + validate(args.domains, ROOT) + pads, _ = read_map(args.pin_map) + by_name = {pad.name: pad for pad in pads} + for name in CLOCK_PADS.values(): + if name not in by_name: + raise ValueError(f"clock PAD is missing from the pin map: {name}") + + periods = { + "external": 1_000_000_000 / args.ext_clk_hz, + "jtag": JTAG_PERIOD_NS, + } + groups: dict[str, dict[str, list[str]]] = { + name: {"inputs": [], "outputs": []} for name in periods + } + excluded = set(CLOCK_PADS.values()) | RESET_PADS + for pad in pads: + if pad.name in excluded: + continue + is_input, is_output = logical_directions(pad) + clock = timing_clock(pad) + if is_input: + groups[clock]["inputs"].append(pad.name) + if is_output: + groups[clock]["outputs"].append(pad.name) + + lines = [ + "# Generated by physical/librelane/tiny/scripts/generate_sdc.py; do not edit.", + "current_design $::env(DESIGN_NAME)", + "set_units -time ns", + "", + "proc require_pins {label name} {", + " set objects [get_pins -quiet $name]", + ' if {$objects eq ""} { error "required SDC pin is missing: $label ($name)" }', + " return $objects", + "}", + "proc require_ports {label name} {", + " set objects [get_ports -quiet $name]", + ' if {$objects eq ""} { error "required SDC port is missing: $label ($name)" }', + " return $objects", + "}", + "", + ] + for name, pad_name in CLOCK_PADS.items(): + instance = ihp130_pad_instance(by_name[pad_name]) + if instance is None: + raise ValueError(f"clock PAD has no IHP130 physical instance: {pad_name}") + lines.append( + f'set clk_{name}_pin [require_pins "clock {name}" {{{instance}/p2c}}]' + ) + lines.append( + f"create_clock -name clk_{name} -period {periods[name]:.12g} $clk_{name}_pin" + ) + lines.append("") + + lines.extend( + [ + f'set clk_system_pin [require_pins "clock system" {{{IHP130_SYSTEM_CLOCK_PIN}}}]', + "create_generated_clock -name clk_system -source $clk_external_pin " + "-divide_by 1 $clk_system_pin", + "", + "set_clock_groups -name retrosoc_async -asynchronous \\", + " -group [get_clocks {clk_external clk_system}] \\", + " -group [get_clocks {clk_jtag}]", + "", + "set all_retrosoc_clocks [get_clocks {clk_external clk_system clk_jtag}]", + "set_clock_uncertainty -setup 0.2 $all_retrosoc_clocks", + "set_clock_uncertainty -hold 0.1 $all_retrosoc_clocks", + "set_clock_transition 0.1 $all_retrosoc_clocks", + "set_timing_derate -early 0.95", + "set_timing_derate -late 1.05", + "set_max_fanout 10 [current_design]", + "", + ] + ) + + for reset in sorted(RESET_PADS): + lines.extend( + [ + f'set reset_{reset} [require_ports "reset {reset}" {{{reset}}}]', + f"set_false_path -from $reset_{reset}", + "", + ] + ) + + for clock, port_groups in groups.items(): + delay = periods[clock] * 0.2 + for direction, ports in port_groups.items(): + if not ports: + continue + variable = f"{clock}_{direction}" + lines.append(f"set {variable} [get_ports {{{' '.join(ports)}}}]") + if direction == "inputs": + lines.append(f"set_input_delay -min 0 -clock clk_{clock} ${variable}") + lines.append(f"set_input_delay -max {delay:.12g} -clock clk_{clock} ${variable}") + else: + lines.append(f"set_output_delay -min 0 -clock clk_{clock} ${variable}") + lines.append(f"set_output_delay -max {delay:.12g} -clock clk_{clock} ${variable}") + lines.append(f"set_load 0.006 ${variable}") + lines.append("") + return "\n".join(lines) + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--domains", type=Path, required=True) + parser.add_argument("--pin-map", type=Path, required=True) + parser.add_argument("--ext-clk-hz", type=positive_integer, required=True) + parser.add_argument("--output", type=Path, required=True) + args = parser.parse_args() + try: + atomic_write(args.output, render(args)) + except (OSError, ValueError, json.JSONDecodeError) as error: + parser.error(str(error)) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/physical/librelane/tiny/scripts/package.py b/physical/librelane/tiny/scripts/package.py new file mode 100644 index 00000000..0b1e5796 --- /dev/null +++ b/physical/librelane/tiny/scripts/package.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python3 +"""Create a checksummed Tiny LibreLane implementation delivery archive.""" + +from __future__ import annotations + +import argparse +import hashlib +import shutil +import tarfile +import tempfile +from pathlib import Path + + +def hash_file(path: Path) -> str: + digest = hashlib.sha256() + with path.open("rb") as source: + while block := source.read(1024 * 1024): + digest.update(block) + return digest.hexdigest() + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--root", type=Path, required=True) + parser.add_argument("--variant-root", type=Path, required=True) + parser.add_argument("--run-root", type=Path, required=True) + parser.add_argument("--output", type=Path, required=True) + args = parser.parse_args() + root = args.root.resolve() + variant_root = args.variant_root.resolve() + run_root = args.run_root.resolve() + required = ( + run_root / "config.json", + run_root / "result.json", + run_root / "final", + run_root / "runs/current", + variant_root / "meta/manifest.json", + variant_root / "meta/librelane-chip-doctor.json", + variant_root / "meta/librelane-chip.json", + root / "dependencies/dependencies.lock.json", + ) + missing = [str(path) for path in required if not path.exists()] + if missing: + parser.error("missing LibreLane delivery input(s): " + ", ".join(missing)) + + args.output.parent.mkdir(parents=True, exist_ok=True) + with tempfile.TemporaryDirectory(prefix="retrosoc-librelane-package-") as temporary: + staging = Path(temporary) / "retrosoc-tiny-ihp130-chip" + shutil.copytree(run_root / "final", staging / "final") + shutil.copytree(run_root / "runs/current", staging / "evidence/run") + shutil.copy2(run_root / "config.json", staging / "evidence/config.json") + shutil.copy2(run_root / "result.json", staging / "evidence/result.json") + shutil.copy2(variant_root / "meta/manifest.json", staging / "evidence/manifest.json") + shutil.copy2( + variant_root / "meta/librelane-chip-doctor.json", + staging / "evidence/librelane-doctor.json", + ) + shutil.copy2( + variant_root / "meta/librelane-chip.json", + staging / "evidence/librelane-chip.json", + ) + shutil.copy2( + root / "dependencies/dependencies.lock.json", + staging / "evidence/dependencies.lock.json", + ) + files = sorted(path for path in staging.rglob("*") if path.is_file()) + sums = "\n".join(f"{hash_file(path)} {path.relative_to(staging)}" for path in files) + (staging / "SHA256SUMS").write_text(sums + "\n", encoding="utf-8") + with tarfile.open(args.output, "w:gz") as archive: + archive.add(staging, arcname=staging.name) + print(f"created LibreLane delivery: {args.output}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/physical/librelane/tiny/sram_blackboxes.vh b/physical/librelane/tiny/sram_blackboxes.vh new file mode 100644 index 00000000..b30513a0 --- /dev/null +++ b/physical/librelane/tiny/sram_blackboxes.vh @@ -0,0 +1,25 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 +// Synthesis-only header for the locked IHP SRAM macro physical views. + +(* blackbox *) +module RM_IHPSG13_1P_1024x32_c2_bm_bist ( + input wire A_CLK, + input wire A_MEN, + input wire A_WEN, + input wire A_REN, + input wire [ 9:0] A_ADDR, + input wire [31:0] A_DIN, + input wire A_DLY, + output wire [31:0] A_DOUT, + input wire [31:0] A_BM, + input wire A_BIST_CLK, + input wire A_BIST_EN, + input wire A_BIST_MEN, + input wire A_BIST_WEN, + input wire A_BIST_REN, + input wire [ 9:0] A_BIST_ADDR, + input wire [31:0] A_BIST_DIN, + input wire [31:0] A_BIST_BM +); +endmodule diff --git a/physical/librelane/tiny/sta_report_limit.tcl b/physical/librelane/tiny/sta_report_limit.tcl new file mode 100644 index 00000000..57a9270c --- /dev/null +++ b/physical/librelane/tiny/sta_report_limit.tcl @@ -0,0 +1,35 @@ +# LibreLane 3.0.5 hard-codes 1000 expanded paths per clock group. Cap only +# report enumeration; worst-slack/TNS analysis still covers the full graph. +set ::retrosoc_sta_group_path_count 10 +puts "\[INFO\] OpenSTA executable: [info nameofexecutable]" +rename report_checks ::retrosoc_report_checks +proc report_checks {args} { + set count_index [lsearch -exact $args -group_path_count] + if {$count_index >= 0} { + set value_index [expr {$count_index + 1}] + if {$value_index < [llength $args]} { + lset args $value_index $::retrosoc_sta_group_path_count + } + } else { + lappend args -group_path_count $::retrosoc_sta_group_path_count + } + uplevel 1 [list ::retrosoc_report_checks {*}$args] +} + +rename report_check_types ::retrosoc_report_check_types +proc report_check_types {args} { + set violator_index [lsearch -exact $args -violators] + if {$violator_index >= 0} { + set args [lreplace $args $violator_index $violator_index] + } + uplevel 1 [list ::retrosoc_report_check_types {*}$args] +} + +rename report_parasitic_annotation ::retrosoc_report_parasitic_annotation +proc report_parasitic_annotation {args} { + set detail_index [lsearch -exact $args -report_unannotated] + if {$detail_index >= 0} { + set args [lreplace $args $detail_index $detail_index] + } + uplevel 1 [list ::retrosoc_report_parasitic_annotation {*}$args] +} diff --git a/physical/pdk/README.md b/physical/pdk/README.md index 79eecb5b..fcea32e8 100644 --- a/physical/pdk/README.md +++ b/physical/pdk/README.md @@ -30,7 +30,8 @@ the locked HD library submodule; OpenRAM's build-space and Ciel inputs are recorded in the macro artifact rather than added to the SoC PDK checkout. The IHP130 dependency is also the technology source for the independent -`physical/librelane/` core-hardening and full-chip pad-ring flows. The locked +`physical/librelane/{mini,tiny}/` core-hardening and full-chip pad-ring flows. +The locked checkout includes the upstream `libs.tech/librelane` standard-cell, pad, extraction, DRC, LVS, filler, bondpad, and seal-ring configuration; LibreLane consumes it directly in manual-PDK mode. The other three open PDKs do not yet diff --git a/physical/smoke/sta/opensta/generate_sdc.py b/physical/smoke/sta/opensta/generate_sdc.py index 808b8e8c..b7b1eb42 100644 --- a/physical/smoke/sta/opensta/generate_sdc.py +++ b/physical/smoke/sta/opensta/generate_sdc.py @@ -12,7 +12,7 @@ from typing import Any ROOT = Path(__file__).resolve().parents[4] sys.path.insert(0, str(ROOT)) -from rtl.mini.pin_map.generate_pin_map import read_map # noqa: E402 +from scripts.rtl.generate_pin_map import read_map # noqa: E402 from scripts.check_clock_reset_domains import validate # noqa: E402 from scripts.setup_helpers import atomic_write # noqa: E402 diff --git a/physical/smoke/sta/opensta/opensta.mk b/physical/smoke/sta/opensta/opensta.mk index 75f9363d..2073f969 100644 --- a/physical/smoke/sta/opensta/opensta.mk +++ b/physical/smoke/sta/opensta/opensta.mk @@ -1,5 +1,6 @@ OPENSTA ?= sta +OPENSTA_TOP ?= $(if $(filter TINY,$(SOC)),retrosoc_tiny_asic,retrosoc_asic) OPENSTA_THREADS ?= $(JOBS) OPENSTA_NETLIST ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v OPENSTA_REPORT ?= $(STA_BUILD_ROOT)/retrosoc_sta.log @@ -8,8 +9,8 @@ OPENSTA_METRICS ?= $(STA_BUILD_ROOT)/timing_metrics.rpt OPENSTA_CONFIG ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.config OPENSTA_SDC ?= $(STA_BUILD_ROOT)/retrosoc_core.sdc OPENSTA_SDC_GEN := $(ROOT_PATH)/physical/smoke/sta/opensta/generate_sdc.py -OPENSTA_DOMAIN_MAP := $(ROOT_PATH)/rtl/mini/integration/clock_reset_domains.json -OPENSTA_PIN_MAP := $(ROOT_PATH)/rtl/mini/pin_map/pin_map.json +OPENSTA_DOMAIN_MAP := $(RTL_PATH)/integration/clock_reset_domains.json +OPENSTA_PIN_MAP := $(RTL_PATH)/pin_map/pin_map.json include $(ROOT_PATH)/physical/smoke/sta/opensta/pdk_timing.mk @@ -36,7 +37,7 @@ sta: $(OPENSTA_SDC) | manifest } python3 $(ROOT_PATH)/scripts/run_flow.py --tool opensta --log $(OPENSTA_LOG) \ --result $(STA_BUILD_ROOT)/result-sta.json \ - --env OPENSTA_NETLIST=$(OPENSTA_NETLIST) --env OPENSTA_LIBERTY=$(OPENSTA_LIBERTY) \ + --env OPENSTA_TOP=$(OPENSTA_TOP) --env OPENSTA_NETLIST=$(OPENSTA_NETLIST) --env OPENSTA_LIBERTY=$(OPENSTA_LIBERTY) \ --env 'OPENSTA_LINK_LIBS=$(OPENSTA_LINK_LIBS)' --env 'OPENSTA_SRAM_LIBS=$(OPENSTA_SRAM_LIBS)' \ --env OPENSTA_SDC=$(OPENSTA_SDC) --env OPENSTA_REPORT=$(OPENSTA_REPORT) \ --env OPENSTA_METRICS=$(OPENSTA_METRICS) -- \ diff --git a/physical/smoke/sta/opensta/opensta.tcl b/physical/smoke/sta/opensta/opensta.tcl index 0a9a1593..d852b3d7 100644 --- a/physical/smoke/sta/opensta/opensta.tcl +++ b/physical/smoke/sta/opensta/opensta.tcl @@ -14,7 +14,11 @@ if {[info exists ::env(OPENSTA_SRAM_LIBS)] && $::env(OPENSTA_SRAM_LIBS) ne ""} { } } read_verilog $::env(OPENSTA_NETLIST) -link_design retrosoc_asic +set top_design retrosoc_asic +if {[info exists ::env(OPENSTA_TOP)] && $::env(OPENSTA_TOP) ne ""} { + set top_design $::env(OPENSTA_TOP) +} +link_design $top_design read_sdc $::env(OPENSTA_SDC) report_checks -path_delay min_max -sort_by_slack -slack_max 0.0 -group_path_count 1000 -endpoint_path_count 1000 > $::env(OPENSTA_REPORT) diff --git a/physical/smoke/syn/tools/export_apu_block_filelist.py b/physical/smoke/syn/tools/export_apu_block_filelist.py index fa18eed5..e0d8e067 100644 --- a/physical/smoke/syn/tools/export_apu_block_filelist.py +++ b/physical/smoke/syn/tools/export_apu_block_filelist.py @@ -18,10 +18,9 @@ from pathlib import Path REPO_ROOT = Path(__file__).resolve().parents[4] -SCRIPT_DIR = REPO_ROOT / "rtl/mini/script" -sys.path.insert(0, str(SCRIPT_DIR)) -from filelist import FileList, parse_filelists, write_filelist # noqa: E402 -from generate_filelist import generate_all # noqa: E402 +sys.path.insert(0, str(REPO_ROOT)) +from scripts.rtl.filelist import FileList, parse_filelists, write_filelist # noqa: E402 +from rtl.mini.script.generate_filelist import generate_all # noqa: E402 APU_SOURCE_MARKERS = ("/ip/multimedia/apu_", "/ip/multimedia/apb4_apu.sv") diff --git a/physical/smoke/syn/tools/export_soc_sources.py b/physical/smoke/syn/tools/export_soc_sources.py index eb547525..9230ea48 100644 --- a/physical/smoke/syn/tools/export_soc_sources.py +++ b/physical/smoke/syn/tools/export_soc_sources.py @@ -13,13 +13,10 @@ from pathlib import Path REPO_ROOT = Path(__file__).resolve().parents[4] -SCRIPT_DIR = REPO_ROOT / "rtl/mini/script" -INTEGRATION_DIR = REPO_ROOT / "rtl/mini/integration" -sys.path.insert(0, str(SCRIPT_DIR)) -sys.path.insert(0, str(INTEGRATION_DIR)) -from filelist import FileList, atomic_write, parse_filelists # noqa: E402 -from generate_filelist import generate_all # noqa: E402 -from generate_user_extensions import generate as generate_user_extensions # noqa: E402 +sys.path.insert(0, str(REPO_ROOT)) +from scripts.rtl.filelist import FileList, atomic_write, parse_filelists # noqa: E402 +from rtl.mini.script.generate_filelist import generate_all # noqa: E402 +from rtl.mini.integration.generate_user_extensions import generate as generate_user_extensions # noqa: E402 INCLUDE_RE = re.compile(r'^\s*`include\s+"([^"]+)"') @@ -69,6 +66,20 @@ def configured_filelist( *, require_files: bool = True, ) -> FileList: + if getattr(args, "soc", "MINI") == "TINY": + directory = getattr(args, "source_filelist_dir", None) + if directory is None: + raise ValueError("Tiny export requires --source-filelist-dir") + names = ("def.fl", "inc.fl", "commonip.fl", "clusterip.fl", "ip.fl", + "tech.fl", "core_hazard3.fl", "top.fl") + filelist = parse_filelists((directory / name for name in names), require_files=require_files) + if "+define+RETROSOC_SOC__TINY" not in filelist.defines: + raise ValueError("Tiny export requires Tiny source lists") + if "+define+SYNTHESIS" not in filelist.defines: + filelist.defines.append("+define+SYNTHESIS") + return filelist + if args.dynamic_core_filelist is None or args.dynamic_ip_filelist is None: + raise ValueError("Mini export requires dynamic core and IP filelists") names: list[str | Path] = [] for name in ( "memory_map_filelist", @@ -271,7 +282,7 @@ def metadata_file(value: str) -> tuple[Path, Path]: def parse_args() -> argparse.Namespace: parser = argparse.ArgumentParser(description="Export configured retroSoC RTL sources") parser.add_argument("mode", choices=("tar", "sv")) - parser.add_argument("--soc", default="MINI", choices=("MINI",)) + parser.add_argument("--soc", default="MINI", choices=("MINI", "TINY")) parser.add_argument("--pdk", default="IHP130", choices=("IHP130", "ICS55", "SKY130", "GF180")) parser.add_argument("--simu", default="VCS", choices=("VCS", "VERILATOR", "IVERILOG")) parser.add_argument("--have-pll", action="store_true") @@ -285,18 +296,19 @@ def parse_args() -> argparse.Namespace: parser.add_argument( "--dynamic-core-filelist", type=Path, - required=True, + required=False, ) parser.add_argument( "--dynamic-ip-filelist", type=Path, - required=True, + required=False, ) parser.add_argument("--memory-map-filelist", type=Path) parser.add_argument("--soc-topology-filelist", type=Path) parser.add_argument("--user-extensions-filelist", type=Path) parser.add_argument("--pin-map-filelist", type=Path) parser.add_argument("--archinfo-incdir", type=Path) + parser.add_argument("--source-filelist-dir", type=Path) parser.add_argument("--librelane-safe", action="store_true") parser.add_argument("--metadata-file", type=metadata_file, action="append", default=[]) parser.add_argument("--output-dir", type=Path, default=REPO_ROOT / "export") @@ -312,15 +324,16 @@ def main() -> int: with tempfile.TemporaryDirectory(prefix="retrosoc-filelists-") as temporary: generated_dir = Path(temporary) user_extensions_dir = generated_dir / "user_extensions" - generate_all(generated_dir, build_defines(args)) - if args.user_extensions_filelist is None: + if args.soc == "MINI": + generate_all(generated_dir, build_defines(args)) + if args.soc == "MINI" and args.user_extensions_filelist is None: generate_user_extensions( REPO_ROOT / "rtl/mini/integration/user_extensions.json", user_extensions_dir, ) filelist = configured_filelist(args, generated_dir, user_extensions_dir) if args.mode == "sv": - output = export_dir / "retrosoc_asic_sources.sv" + output = export_dir / ("retrosoc_tiny_asic_sources.sv" if args.soc == "TINY" else "retrosoc_asic_sources.sv") write_single_sv(filelist, output, librelane_safe=args.librelane_safe) else: output = write_tar(filelist, export_dir, args.soc, dict(args.metadata_file)) diff --git a/physical/smoke/syn/yosys/apu_block.mk b/physical/smoke/syn/yosys/apu_block.mk index 0a996df2..41480be2 100644 --- a/physical/smoke/syn/yosys/apu_block.mk +++ b/physical/smoke/syn/yosys/apu_block.mk @@ -98,7 +98,7 @@ APU_BLOCK_STA_RESULT := $(APU_BLOCK_STA)/result-sta.json APU_BLOCK_SYN_RESULT := $(APU_BLOCK_SYN)/result-synth.json $(APU_BLOCK_FL): $(APU_BLOCK_EXPORTER) $(FILELIST_TEMPLATES) \ - $(RTL_PATH)/script/generate_filelist.py $(RTL_PATH)/script/filelist.py + $(RTL_PATH)/script/generate_filelist.py $(ROOT_PATH)/scripts/rtl/filelist.py @mkdir -p $(APU_BLOCK_FL_DIR) python3 $(APU_BLOCK_EXPORTER) --output-dir $(APU_BLOCK_FL_DIR) \ $(foreach define,$(DEF_LIST),--define $(define)) diff --git a/physical/smoke/syn/yosys/ga2d_block.mk b/physical/smoke/syn/yosys/ga2d_block.mk index 7e1d4e58..507f92b7 100644 --- a/physical/smoke/syn/yosys/ga2d_block.mk +++ b/physical/smoke/syn/yosys/ga2d_block.mk @@ -48,7 +48,7 @@ endif # active DEF_LIST but without the SoC generated-include chain, so the block # flow does not depend on the HP/pin-map generation stamps. $(GA2D_BLOCK_FL_DIR)/.stamp: $(RTL_PATH)/script/generate_filelist.py \ - $(RTL_PATH)/script/filelist.py \ + $(ROOT_PATH)/scripts/rtl/filelist.py \ $(sort $(wildcard $(ROOT_PATH)/rtl/filelist/pdk_*.fl) \ $(wildcard $(RTL_PATH)/filelist/*.fl) $(RTL_PATH)/lint.msg) $(FLOW_PYTHON) $(RTL_PATH)/script/generate_filelist.py \ @@ -57,11 +57,11 @@ $(GA2D_BLOCK_FL_DIR)/.stamp: $(RTL_PATH)/script/generate_filelist.py \ @touch $@ $(GA2D_BLOCK_FLIST): $(GA2D_BLOCK_FL_DIR)/.stamp $(MEMORY_MAP_STAMP) - @python3 $(RTL_PATH)/script/comb.py \ + @python3 $(ROOT_PATH)/scripts/rtl/comb.py \ -f $(GA2D_BLOCK_FL_DIR)/def.fl \ -f $(MEMORY_MAP_FILELIST) \ -f $(GA2D_BLOCK_FL_DIR)/ga2d_block.fl --output $@ - @python3 $(RTL_PATH)/script/filelist_deps.py -f $@ \ + @python3 $(ROOT_PATH)/scripts/rtl/filelist_deps.py -f $@ \ --extra $(MEMORY_MAP_FILELIST) \ --target $(GA2D_BLOCK_NETLIST) --output $(GA2D_BLOCK_DEPFILE) diff --git a/physical/smoke/syn/yosys/yosys.mk b/physical/smoke/syn/yosys/yosys.mk index 9971b6ab..38802fce 100644 --- a/physical/smoke/syn/yosys/yosys.mk +++ b/physical/smoke/syn/yosys/yosys.mk @@ -19,18 +19,19 @@ # Directories # directory of the path to the last called Makefile (this one) -YOSYS_DIR := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST))))) -YOSYS_BUILD := $(SYN_BUILD_ROOT) -YOSYS_OUT := $(YOSYS_BUILD)/out -YOSYS_TMP := $(YOSYS_BUILD)/tmp -YOSYS_RPT := $(YOSYS_BUILD)/rpt +YOSYS_DIR := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST))))) +YOSYS_BUILD := $(SYN_BUILD_ROOT) +YOSYS_OUT := $(YOSYS_BUILD)/out +YOSYS_TMP := $(YOSYS_BUILD)/tmp +YOSYS_RPT := $(YOSYS_BUILD)/rpt YOSYS_TIMEOUT ?= 10800 include $(YOSYS_DIR)/synth_config.mk ifeq ($(origin YOSYS_TARGET_PERIOD_PS),undefined) YOSYS_TARGET_PERIOD_PS := $(shell python3 $(ROOT_PATH)/scripts/yosys_period.py \ - --domains $(ROOT_PATH)/rtl/mini/integration/clock_reset_domains.json) + --domains $(RTL_PATH)/integration/clock_reset_domains.json \ + --domain $(if $(filter TINY,$(SOC)),system,hp)) ifeq ($(strip $(YOSYS_TARGET_PERIOD_PS)),) $(error Failed to derive YOSYS_TARGET_PERIOD_PS from the clock/reset inventory) endif @@ -49,8 +50,8 @@ YOSYS_SCRIPTS := $(wildcard $(YOSYS_DIR)/script/*) $(YOSYS_DIR)/synth_config.mk -include $(YOSYS_DEPFILE) $(SV_FLIST): $(MPW_VARIANT_STAMP) $(FILELIST_STAMP) - @python3 $(RTL_PATH)/script/comb.py $(RTL_FLIST) --output $(SV_FLIST) - @python3 $(RTL_PATH)/script/filelist_deps.py $(RTL_FLIST) --target $(NETLIST) \ + @python3 $(ROOT_PATH)/scripts/rtl/comb.py $(RTL_FLIST) --output $(SV_FLIST) + @python3 $(ROOT_PATH)/scripts/rtl/filelist_deps.py $(RTL_FLIST) --target $(NETLIST) \ --output $(YOSYS_DEPFILE) gen_synth_filelist: $(SV_FLIST) @@ -79,4 +80,4 @@ $(NETLIST_DEBUG): $(NETLIST) synth_clean: python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(YOSYS_BUILD) -.PHONY: gen_synth_filelist synth_clean synth +.PHONY: gen_synth_filelist synth_clean synth \ No newline at end of file diff --git a/publications/README.md b/publications/README.md index bd0eea19..f1f86943 100644 --- a/publications/README.md +++ b/publications/README.md @@ -12,6 +12,15 @@ These edits do not advance `mini.json.source_revision` or relabel an existing PDF. Review and commit the implementation snapshot before producing a matching new PDF; the source-drift check remains mandatory. +## Tiny Gen1 datasheet + +The independent [Tiny Gen1 publication](datasheets/tiny/README.md) uses the same +visual language with Tiny-only configuration, register/IRQ/pad extraction, +fourteen IP chapters and its own source/structure/evidence checks. Run +`python3 publications/build_tiny_datasheet.py setup`, then `build` or `check`. +Its output and `latest-tiny` record are separate; the existing Mini entrypoint, +templates, configuration, review and delivered PDF are unchanged. + ## Mini datasheet The prototype chip brand is **Rill（清溪）**. Its bilingual label replaces the diff --git a/publications/build_datasheet.py b/publications/build_datasheet.py index 32e65d85..266417ae 100644 --- a/publications/build_datasheet.py +++ b/publications/build_datasheet.py @@ -146,9 +146,9 @@ def collect_data(config: dict[str, Any], *, check_snapshot: bool = True) -> dict product = profiles["profile"] if product.get("MINI_MODE") != "PRODUCT" or product.get("HAVE_HP") != "YES": raise ValueError("datasheet requires the reviewed dual-hart PRODUCT profile") - address = load_generator("datasheet_memory", "rtl/mini/address_map/generate_memory_map.py") + address = load_generator("datasheet_memory", "scripts/rtl/generate_memory_map.py") topology = load_generator("datasheet_topology", "rtl/mini/integration/generate_soc_topology.py") - pinmap = load_generator("datasheet_pins", "rtl/mini/pin_map/generate_pin_map.py") + pinmap = load_generator("datasheet_pins", "scripts/rtl/generate_pin_map.py") reset, regions, _ = address.read_map(ROOT / MAP, int(product["SRAM_SIZE_KIB"])) _, _, _, gpio, _, _, irqs, policies = topology.read_topology(ROOT / TOPOLOGY, ROOT / MAP) pads, _ = pinmap.read_map(ROOT / PINS) diff --git a/publications/build_tiny_datasheet.py b/publications/build_tiny_datasheet.py new file mode 100644 index 00000000..e4430552 --- /dev/null +++ b/publications/build_tiny_datasheet.py @@ -0,0 +1,240 @@ +#!/usr/bin/env python3 +"""Prepare, build and verify the independent Tiny Gen1 publication.""" +from __future__ import annotations + +import argparse +import hashlib +import json +import os +from pathlib import Path +import shutil +import subprocess +import sys +import tempfile +from datetime import datetime, timezone + +ROOT = Path(__file__).resolve().parents[1] +sys.path.insert(0, str(ROOT)) +from publications.tiny_reference import BOOK, MANAGED, collect, read, validate_configuration # noqa: E402 +from publications.package_reference import directory_hashes, package_records, validate_package_closure # noqa: E402 +from publications.structure_reference import validate_structure # noqa: E402 +from publications.report_changes import repository_footer_pages # noqa: E402 +from scripts.dependency_lock import load_lock # noqa: E402 +from scripts.install_toolchain import safe_extract # noqa: E402 +from scripts.setup_helpers import atomic_write, download_file, ensure_git_repo, sha256 # noqa: E402 + +CACHE = ROOT / ".cache/retrosoc/publications" +LATEST = CACHE / "latest-tiny" + + +def write(path: Path, value) -> None: + atomic_write(path, json.dumps(value, indent=2, ensure_ascii=False) + "\n") + + +def assets(lock: dict) -> dict: + for name in MANAGED: + spec = lock["sources"][name] + location = ROOT / spec["destination"] + if not (location / ".git").exists(): + raise ValueError(f"Tiny managed input absent: {name}; run setup") + revision = subprocess.check_output(["git", "-C", str(location), "rev-parse", "HEAD"], text=True).strip() + dirty = subprocess.check_output(["git", "-C", str(location), "status", "--porcelain"], text=True).strip() + if revision != spec["revision"] or dirty: + raise ValueError(f"Tiny managed input differs from its lock: {name}") + media = ROOT / lock["sources"]["publication_media"]["destination"] + manifest = read(media / "assets.json") + for path, expected in manifest["files"].items(): + if sha256(media / path) != expected: + raise ValueError(f"Tiny media digest mismatch: {path}") + validate_package_closure(ROOT, package_records(lock)) + return manifest + + +def prepare(lock: dict) -> None: + for name in sorted(MANAGED): + spec = lock["sources"][name] + ensure_git_repo(spec["url"], ROOT / spec["destination"], spec["revision"], update=False) + for package in package_records(lock): + archive = CACHE / "downloads" / f"{package['name']}-{package['version']}.tar.gz" + download_file(package["url"], archive, package["sha256"], update=False) + destination = ROOT / package["destination"] + manifest = destination / ".manifest.json" + if manifest.is_file() and read(manifest) == {"archive": package["sha256"], "files": directory_hashes(destination)}: + continue + if destination.exists(): + raise ValueError("Existing package cache differs from its lock; review the cache before replacing it") + destination.parent.mkdir(parents=True, exist_ok=True) + with tempfile.TemporaryDirectory(dir=destination.parent) as temp: + unpacked = Path(temp) / "content" + unpacked.mkdir() + safe_extract(archive, unpacked) + write(unpacked / ".manifest.json", {"archive": package["sha256"], "files": directory_hashes(unpacked)}) + unpacked.rename(destination) + assets(lock) + + +def inputs(data: dict) -> dict[str, str]: + paths = set(data["source_paths"]) + paths.update(p.relative_to(ROOT).as_posix() for p in (ROOT / BOOK).rglob("*") if p.suffix in {".typ", ".json"}) + paths.update(p.relative_to(ROOT).as_posix() for p in (ROOT / "publications/examples/tiny").glob("*.c")) + paths.update({"publications/build_tiny_datasheet.py", "publications/check_tiny_examples.py", "tests/test_publication_tiny.py", "publications/tiny_reference.py", "publications/register_reference.py", + "publications/waveform_reference.py", "publications/structure_reference.py", "publications/package_reference.py", + "publications/report_changes.py", "publications/page_reference.py", "scripts/rtl/generate_memory_map.py", + "scripts/rtl/generate_pin_map.py", "scripts/check_clock_reset_domains.py"}) + return {path: sha256(ROOT / path) for path in sorted(paths)} + + +def typst_binary(explicit: str | None, lock: dict) -> str: + executable = explicit or os.environ.get("TYPST") or shutil.which("typst") + if not executable: + raise ValueError("Typst not found; use --typst") + version = subprocess.check_output([executable, "--version"], text=True).strip() + if not version.startswith("typst " + lock["publication_tools"]["typst"]["version"] + " "): + raise ValueError("Tiny requires the locked Typst version") + return executable + + +def validate_output(out: Path, config: dict) -> Path: + out = out.resolve() + if not out.is_relative_to((ROOT / "build").resolve()): + raise ValueError("Tiny outputs must be inside build/") + previous = out / "manifest.json" + if previous.is_file() and read(previous).get("document", {}).get("document_id") != config["document_id"]: + raise ValueError("Tiny output cannot overwrite another product's build record") + return out + + +def validate_rendered_registers(data: dict, items: list) -> int: + expected = {(family, r["key"]) for family, value in data["registers"].items() for r in value["registers"]} + actual = [(r["family"], r["key"]) for r in items if isinstance(r, dict) and r.get("kind") == "tiny-register"] + if len(actual) != len(set(actual)) or set(actual) != expected: + raise ValueError("Tiny PDF omitted or duplicated a register definition") + return len(actual) + + +def build(config: dict, executable: str, out: Path | None = None) -> Path: + lock = load_lock() + media = assets(lock) + data = collect(config) + hashes = inputs(data) + signature = hashlib.sha256(json.dumps(hashes, sort_keys=True).encode()).hexdigest()[:12] + out = out or ROOT / "build" / f"datasheet-tiny-{datetime.now(timezone.utc):%Y-%m-%d-%H-%M}-{signature}" + out = validate_output(out, config) + out.mkdir(parents=True, exist_ok=True) + write(out / "data.json", data) + pdf = out / config["filename"] + epoch = int(datetime.fromisoformat(config["date"]).replace(tzinfo=timezone.utc).timestamp()) + options = ["--root", str(ROOT), "--font-path", "publications/media/fonts", "--ignore-system-fonts", + "--package-path", str(CACHE / "packages"), "--package-cache-path", str(CACHE / "packages"), + "--input", "data=/" + (out / "data.json").relative_to(ROOT).as_posix(), "--creation-timestamp", str(epoch)] + result = subprocess.run([executable, "compile", config["entrypoint"], str(pdf), *options], cwd=ROOT, text=True, capture_output=True, encoding="utf-8") + atomic_write(out / "typst.log", result.stdout + result.stderr) + if result.returncode or "warning:" in result.stderr: + raise ValueError("Tiny Typst build failed or warned:\n" + result.stderr) + query = '(headings:query(heading).map(h=>(level:h.level,outlined:h.outlined,title:h.body,label:repr(h.at("label",default:none)),page:h.location().page())),items:query(metadata).map(it=>it.value))' + result = subprocess.run([executable, "eval", query, "--in", config["entrypoint"], *options], cwd=ROOT, text=True, capture_output=True, encoding="utf-8") + if result.returncode or "warning:" in result.stderr: + raise ValueError("Tiny layout query failed:\n" + result.stderr) + layout = json.loads(result.stdout) + validate_structure(read(ROOT / BOOK / "structure-contract.json"), layout["headings"], data["chapter_index"]) + validate_rendered_registers(data, layout["items"]) + write(out / "document-structure.json", layout["headings"]) + write(out / "layout.json", layout["items"]) + write(out / "ip-pages.json", [r for r in layout["items"] if isinstance(r, dict) and r.get("kind") in {"ip-start", "ip-end"}]) + write(out / "waveform-audit.json", data["waveform_audit"]) + diagrams = [r for r in layout["items"] if isinstance(r, dict) and r.get("kind") == "tiny-diagram"] + write(out / "diagram-inventory.json", diagrams) + manifest = dict(document=config, inputs=hashes, assets=media, pdf_sha256=sha256(pdf), + publication_checkout=dict(head=subprocess.check_output(["git", "rev-parse", "HEAD"], cwd=ROOT, text=True).strip(), path=str(ROOT)), + typst=lock["publication_tools"]["typst"]["version"], media_revision=lock["sources"]["publication_media"]["revision"], + packages={p["identity"]: p["sha256"] for p in package_records(lock)}, + document_structure_sha256=sha256(out / "document-structure.json"), diagram_inventory_sha256=sha256(out / "diagram-inventory.json")) + write(out / "manifest.json", manifest) + atomic_write(LATEST, str(out) + "\n") + print(f"Built {pdf}") + return pdf + + +def check_pdf(pdf: Path, data: dict) -> dict: + from pypdf import PdfReader + import pdfplumber + manifest = read(pdf.parent / "manifest.json") + if sha256(pdf) != manifest["pdf_sha256"]: + raise ValueError("Tiny PDF digest does not match manifest") + for path, digest in manifest["inputs"].items(): + if sha256(ROOT / path) != digest: + raise ValueError(f"Tiny input changed after build: {path}") + reader = PdfReader(pdf) + if reader.metadata.title != data["document"]["title"] or data["document"]["document_id"] not in reader.metadata.keywords: + raise ValueError("Tiny PDF identity mismatch") + if repository_footer_pages(reader) != list(range(1, len(reader.pages) + 1)): + raise ValueError("Tiny repository footer missing") + layout = read(pdf.parent / "ip-pages.json") + register_count = validate_rendered_registers(data, read(pdf.parent / "layout.json")) + starts = [r["id"] for r in layout if r["kind"] == "ip-start"] + ends = [r["id"] for r in layout if r["kind"] == "ip-end"] + if starts != ends or starts != [r["id"] for r in data["chapter_index"]]: + raise ValueError("Tiny IP chapter coverage missing") + if not reader.outline: + raise ValueError("Tiny bookmarks missing") + internal = 0 + for page in reader.pages: + if not (page.extract_text() or "").strip(): + raise ValueError("Tiny PDF contains a blank/raster-only page") + for annotation in page.get("/Annots", []): + item = annotation.get_object() + destination = item.get("/Dest", item.get("/A", {}).get("/D")) + if destination is not None: + if isinstance(destination, list) and (not destination or destination[0].get_object().get("/Type") != "/Page"): + raise ValueError("Tiny link has no page destination") + internal += 1 + for ref in page["/Resources"].get("/Font", {}).get_object().values(): + font = ref.get_object() + child = font.get("/DescendantFonts", [font])[0].get_object() + descriptor = child.get("/FontDescriptor", {}).get_object() + if not any(key in descriptor for key in ("/FontFile", "/FontFile2", "/FontFile3")): + raise ValueError("Tiny font is not embedded") + with pdfplumber.open(pdf) as rendered: + for page in rendered.pages: + for char in page.chars: + if char["text"].strip() and char["size"] < 8.45: + raise ValueError(f"Tiny undersized text on page {page.page_number}: {char['text']}") + footer = page.crop((0, page.height - 45, page.width, page.height)).extract_text() or "" + if f"{page.page_number} / {len(rendered.pages)}" not in footer: + raise ValueError("Tiny printed footer numbering mismatch") + result = dict(pages=len(reader.pages), internal_links=internal, ip_chapters=len(starts), + pdf_sha256=manifest["pdf_sha256"], fonts_embedded=True, register_definitions=register_count, source_inputs=len(manifest["inputs"])) + write(pdf.parent / "check-report.json", result) + print("Tiny PDF checks passed:", result) + return result + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("command", choices=["setup", "build", "check"]) + parser.add_argument("--config", type=Path, default=ROOT / BOOK / "tiny.json") + parser.add_argument("--typst") + parser.add_argument("--output-dir", type=Path) + parser.add_argument("--pdf", type=Path) + parser.add_argument("--source-only", action="store_true") + args = parser.parse_args() + try: + config, lock = read(args.config), load_lock() + validate_configuration(config) + if args.command == "setup": + prepare(lock) + elif args.command == "build": + build(config, typst_binary(args.typst, lock), args.output_dir) + else: + data = collect(config) + if not args.source_only: + assets(lock) + check_pdf(args.pdf or Path(LATEST.read_text().strip()) / config["filename"], data) + print("Tiny source checks passed: configuration, 14 IPs, registers, maps, interrupts, pads and waveforms") + except (OSError, ValueError, KeyError, subprocess.CalledProcessError) as error: + parser.exit(1, f"tiny datasheet: {error}\n") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/publications/check_examples.py b/publications/check_examples.py index bda39b4f..9b79be92 100644 --- a/publications/check_examples.py +++ b/publications/check_examples.py @@ -20,7 +20,7 @@ def check_examples(compiler: str) -> int: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", diff --git a/publications/check_tiny_examples.py b/publications/check_tiny_examples.py new file mode 100644 index 00000000..1dfd183e --- /dev/null +++ b/publications/check_tiny_examples.py @@ -0,0 +1,38 @@ +"""Compile Tiny publication examples with Tiny-generated SDK metadata only.""" +from __future__ import annotations + +import argparse +from pathlib import Path +import subprocess +import sys +import tempfile + +ROOT = Path(__file__).resolve().parents[1] +sys.path.insert(0, str(ROOT)) +from scripts.generate_tiny import generate_bindings, read_topology # noqa: E402 +from scripts.rtl.generate_memory_map import generate # noqa: E402 + + +def check_examples(compiler: str) -> int: + with tempfile.TemporaryDirectory(prefix="retrosoc-tiny-examples-") as location: + generated = Path(location) + generate_bindings(read_topology(ROOT / "rtl/tiny/integration/soc_topology.json", ROOT / "rtl/tiny/address_map/memory_map.json"), generated) + generate(ROOT / "rtl/tiny/address_map/memory_map.json", generated / "memory_map", "YES", 128) + includes = [ROOT / "crt/include", generated / "include", generated / "memory_map/include"] + includes += [ROOT / f"rtl/managed/clusterip/{name}/sw/include" for name in ("archinfo", "pwm", "rtc", "wdg")] + command = [compiler, "-std=c11", "-ffreestanding", "-Wall", "-Wextra", "-Werror", "-fsyntax-only", "-DRS_SOC_TINY=1"] + for path in includes: + command += ["-I", str(path)] + examples = sorted((ROOT / "publications/examples/tiny").glob("*.c")) + if len(examples) != 13: + raise ValueError("Tiny example inventory changed; review the complete set") + for path in examples: + subprocess.run([*command, str(path)], check=True, cwd=ROOT) + print(f"Tiny SDK examples: {len(examples)} syntax checks passed") + return len(examples) + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--cc", default="gcc") + check_examples(parser.parse_args().cc) diff --git a/publications/datasheets/diagram-circuits.json b/publications/datasheets/diagram-circuits.json index b852700a..34c4b78b 100644 --- a/publications/datasheets/diagram-circuits.json +++ b/publications/datasheets/diagram-circuits.json @@ -8451,13 +8451,13 @@ ], "sources": [ "rtl/mini/top/retrosoc.sv", - "rtl/mini/top/onchip_ram.sv" + "rtl/ip/memory/onchip_ram.sv" ], "instance_source": { "file": "rtl/mini/top/retrosoc.sv", "name": "u_onchip_ram", "module": "onchip_ram", - "declaration_file": "rtl/mini/top/onchip_ram.sv" + "declaration_file": "rtl/ip/memory/onchip_ram.sv" } }, { @@ -8495,7 +8495,7 @@ } ], "sources": [ - "rtl/mini/top/onchip_ram.sv" + "rtl/ip/memory/onchip_ram.sv" ] } ], @@ -8562,11 +8562,11 @@ "style": "direct", "bindings": [ { - "file": "rtl/mini/top/onchip_ram.sv", + "file": "rtl/ip/memory/onchip_ram.sv", "text": ".data_i(s_mem_wdata[31:0])" }, { - "file": "rtl/mini/top/onchip_ram.sv", + "file": "rtl/ip/memory/onchip_ram.sv", "text": ".data_i(s_mem_wdata[63:32])" } ], @@ -10929,13 +10929,13 @@ ], "sources": [ "rtl/mini/top/retrosoc.sv", - "rtl/mini/top/onchip_ram.sv" + "rtl/ip/memory/onchip_ram.sv" ], "instance_source": { "file": "rtl/mini/top/retrosoc.sv", "name": "u_onchip_ram", "module": "onchip_ram", - "declaration_file": "rtl/mini/top/onchip_ram.sv" + "declaration_file": "rtl/ip/memory/onchip_ram.sv" } }, { diff --git a/publications/datasheets/register-profiles.json b/publications/datasheets/register-profiles.json index a42833da..b0519628 100644 --- a/publications/datasheets/register-profiles.json +++ b/publications/datasheets/register-profiles.json @@ -1430,10 +1430,10 @@ "sram": { "document": "docs/ip/onchip-sram.md", "defines": [ - "rtl/mini/top/onchip_ram_define.svh" + "rtl/ip/memory/onchip_ram_define.svh" ], "rtl": [ - "rtl/mini/top/onchip_ram_reg.sv" + "rtl/ip/memory/onchip_ram_reg.sv" ], "parameters": { "Present": 1, diff --git a/publications/datasheets/sections/processor-details.typ b/publications/datasheets/sections/processor-details.typ index fcb3334d..b23b6bb0 100644 --- a/publications/datasheets/sections/processor-details.typ +++ b/publications/datasheets/sections/processor-details.typ @@ -58,7 +58,7 @@ the existing non-coherent buffer protocol. LP and HP configuration differences d two harts into a symmetric cache-coherent SMP platform. #block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[ #set text(size:9pt) - #source("rtl/mini/top/mgmt_core_wrapper.sv",title:"LP instance") · + #source("rtl/ip/core/mgmt_core_wrapper.sv",title:"LP instance") · #source("scripts/vexiiriscv/GenerateRetroSocHp.scala",title:"HP configuration/PMA") · #source("scripts/generate_vexiiriscv.py",title:"Artifact manifest") · #source("app/ports/linux/linux/retrosoc_hp.dts",title:"HP platform properties") diff --git a/publications/datasheets/sections/software-runtime.typ b/publications/datasheets/sections/software-runtime.typ index 2a42d404..b852b9c5 100644 --- a/publications/datasheets/sections/software-runtime.typ +++ b/publications/datasheets/sections/software-runtime.typ @@ -41,7 +41,7 @@ The debug replacement sets the stack and calls main, without the generic PSRAM i relocation or BSS loop. The XPI flash-loader replacement sets the stack, clears BSS and calls main; if main returns it executes EBREAK and loops. Those compact entries are tied to their application/linker assumptions and do not establish a universal alternative startup sequence. -#source-note("rtl/mini/mk/software.mk",title:"Generic CRT, conditional IRQ objects and application CRT replacement") +#source-note("rtl/mk/software.mk",title:"Generic CRT, conditional IRQ objects and application CRT replacement") #source-note("crt/arch/riscv/startup.S",title:"Actual generic LP entry and PSRAM-ready loop") #source-note("app/apps/debug/startup.S",title:"Dedicated debug entry") #source-note("app/apps/xpi_flash_loader/startup.S",title:"Dedicated SRAM flash-loader entry") diff --git a/publications/datasheets/soc-architecture.json b/publications/datasheets/soc-architecture.json index 8bdf01ad..3310342f 100644 --- a/publications/datasheets/soc-architecture.json +++ b/publications/datasheets/soc-architecture.json @@ -13,7 +13,7 @@ "rtl/mini/top/apb4_periph.sv", "rtl/mini/top/apb4_system.sv", "rtl/mini/top/memory_pad_mux.sv", - "rtl/mini/top/mgmt_debug_wrapper.sv", + "rtl/ip/core/mgmt_debug_wrapper.sv", "rtl/mini/top/retrosoc.sv", "rtl/mini/top/soc_clock_reset_subsystem.sv", "rtl/mini/top/soc_data_plane.sv" @@ -168,7 +168,7 @@ "ips": [], "rotate": false, "clock": { - "file": "rtl/mini/top/mgmt_debug_wrapper.sv", + "file": "rtl/ip/core/mgmt_debug_wrapper.sv", "name": "u_jtag_rst_sync", "module": "rst_sync", "port": "clk_i", diff --git a/publications/datasheets/system-reference.json b/publications/datasheets/system-reference.json index aca9e73c..8a5cc233 100644 --- a/publications/datasheets/system-reference.json +++ b/publications/datasheets/system-reference.json @@ -132,7 +132,7 @@ "crt/include/retrosoc/hal/onchip_sram.h", "docs/ip/onchip-sram.md", "publications/examples/sram.c", - "rtl/mini/top/onchip_ram_reg.sv" + "rtl/ip/memory/onchip_ram_reg.sv" ], "tests": [ "tests/test_onchip_sram_register_parity.py" @@ -1065,7 +1065,7 @@ "applies_to": "Reviewed generic LP CRT; dedicated debug and XPI-loader startups have separate initialization contracts.", "sources": [ "crt/arch/riscv/startup.S", - "rtl/mini/mk/software.mk" + "rtl/mk/software.mk" ] } ], @@ -3253,7 +3253,7 @@ "rtl/managed/clusterip/common/rtl/utils/register.sv", "rtl/mini/top/clock_config_controller.sv", "rtl/mini/top/hp_lifecycle_controller.sv", - "rtl/mini/top/mgmt_core_wrapper.sv", + "rtl/ip/core/mgmt_core_wrapper.sv", "rtl/mini/top/resource_controller.sv", "rtl/mini/top/soc_clock_reset_subsystem.sv", "scripts/generate_vexiiriscv.py", @@ -5065,7 +5065,7 @@ "crt/src/service/test.c", "publications/datasheets/mini.json", "rtl/mini/integration/soc_topology.json", - "rtl/mini/mk/software.mk", + "rtl/mk/software.mk", "scripts/build_hp_linux.py", "scripts/regress.py", "app/ports/linux/init" @@ -5073,17 +5073,17 @@ "bindings": [ { "id": "csr-selection", - "file": "rtl/mini/mk/software.mk", + "file": "rtl/mk/software.mk", "text": "ifeq ($(HAVE_CSR),YES)\nDEF_VAL += -DCSR_ENABLE\nendif" }, { "id": "irq-objects", - "file": "rtl/mini/mk/software.mk", + "file": "rtl/mk/software.mk", "text": "ifeq ($(HAVE_CSR),YES)\nCRT_SRCS += $(ROOT_PATH)/crt/arch/riscv/system_irq.S\nCRT_SRCS += $(ROOT_PATH)/crt/src/core/system_irq_handler.c\nCRT_SRCS += $(ROOT_PATH)/crt/src/core/irq.c" }, { "id": "app-override", - "file": "rtl/mini/mk/software.mk", + "file": "rtl/mk/software.mk", "text": "ifneq ($(strip $(APP_CRT_SRCS)),)\nCRT_SRCS := $(APP_CRT_SRCS)\nendif" }, { @@ -5953,8 +5953,8 @@ "rtl/mini/top/fabric_monitor.sv", "rtl/mini/top/hp_subsystem.sv", "rtl/mini/top/memory_pad_mux.sv", - "rtl/mini/top/mgmt_debug_wrapper.sv", - "rtl/mini/top/onchip_ram.sv", + "rtl/ip/core/mgmt_debug_wrapper.sv", + "rtl/ip/memory/onchip_ram.sv", "rtl/mini/top/rcu.sv", "rtl/mini/top/resource_controller.sv", "rtl/mini/top/retrosoc.sv", diff --git a/publications/datasheets/tiny/README.md b/publications/datasheets/tiny/README.md new file mode 100644 index 00000000..f8865311 --- /dev/null +++ b/publications/datasheets/tiny/README.md @@ -0,0 +1,49 @@ +# Tiny Gen1 publication + +This directory owns the English **retroSoC Tiny Gen1 / Rill (清溪)** datasheet, +its independent v0.1 DRAFT identity, 14 IP chapters and 39 frozen structural +entries. It is a publication adapter, not an RTL or SDK register generator. + +The source of truth is `rtl/tiny`, `configs/ci/ihp130-tiny.mk`, the active shared +RTL/SDK and the locked Common/Hazard3/peripheral repositories. The reviewed +SHA belongs in [tiny.json](tiny.json). Address, IRQ and pad mappings are read +from Tiny's canonical inputs. The register profiles select only applicable +families; the owned SYSCTRL and ARCHINFO overrides are checked separately. + +## Build and check + +From the repository root, with the pinned publication Python dependencies and +Typst version available: + +```sh +python3 publications/build_tiny_datasheet.py setup +python3 publications/build_tiny_datasheet.py check --source-only +python3 publications/build_tiny_datasheet.py build --typst /path/to/locked/typst +python3 publications/build_tiny_datasheet.py check --pdf build//retrosoc-tiny-gen1-datasheet.pdf +python3 publications/check_tiny_examples.py --cc gcc +python3 -m pytest -q tests/test_publication_tiny.py tests/test_publication_registers.py tests/test_publication_waveforms.py +``` + +The optional `--config` selects a Tiny configuration file. Outputs belong to +`build/datasheet-tiny--/`. The only latest-build marker +written is `.cache/retrosoc/publications/latest-tiny`; Mini markers and products +are not replaced. Font/package caches are shared and hash-checked. Tiny setup +requires only the managed inputs it uses, not MPW, VexiiRiscv or accelerator data. + +## Content and validation boundary + +- [Layout supplement](style.md) defines the Tiny use of the approved Mini visual language. +- [Content review](content-review.md) records retained coverage and known gaps. +- [Chapter review](chapter-review.md) binds chapter/IP coverage to the delivered PDF. +- [Structure contract](structure-contract.json) freezes entry order and labels independently of page count. +- [Source contract](source-contract.json) binds numerical maps and critical behavior. +- [Evidence](evidence.json) distinguishes dated repository narratives from matching executed reports. + +The broad validation report and PDF hash accompany each build. Verify links, +source/parameter consistency, character sizes, outlines, complete register/IP +coverage and representative color/grayscale rendering. Repeat the build offline +and compare PDF bytes. New test counts must come from the current run. + +The 24 MHz configuration is not timing-qualified. Publication checks do not +establish simulation, physical, board or silicon qualification. Do not repair +RTL, relax checks, or change warning/metric baselines as a document workaround. diff --git a/publications/datasheets/tiny/catalog.json b/publications/datasheets/tiny/catalog.json new file mode 100644 index 00000000..f7f92f15 --- /dev/null +++ b/publications/datasheets/tiny/catalog.json @@ -0,0 +1,591 @@ +[ + { + "id": "xpi", + "family": "xpi", + "title": "XPI Universal Controller", + "depth": 3, + "regions": [ + "FLASH", + "APB4_XPI", + "XPI" + ], + "irqs": [ + "xpi" + ], + "summary": "Four-chip-select SDR serial-memory controller; pin-level boot uses NOR on NSS0.", + "features": [ + "Four chip selects; 16 programmable LUT sequences.", + "Single, dual and quad SDR phases; mapped reads plus indirect PIO/DMA and status polling.", + "64-word TX and RX staging FIFOs; device-specific commands and timing remain software responsibilities." + ], + "paragraphs": [ + "The Flash alias at address zero and XPI aperture route to the same command engine. They are address windows, not two independent memories. The boot setup is the implemented NOR profile on NSS0; other chip selects are not qualified board configurations.", + "Memory reads and indirect operations share the controlled transaction engine. A write to a mapped Flash address is not a Flash program command. Execute erase/program service from SRAM with all users of the affected memory quiesced.", + "LUT phase widths, dummy cycles, clock divider and device/page bounds must match the selected NOR. Unsupported modes, FIFO starvation and device timeout require status inspection and bounded recovery. The generic controller does not imply DDR, HyperBus or arbitrary-device compatibility." + ], + "steps": [ + "Identify the actual NOR and configure the supported slot, timing and LUT while idle.", + "Keep the executing service and its working state in SRAM before erase/program.", + "Configure source/destination ranges and the supported DMA request, then start and use a bounded wait.", + "Inspect engine/FIFO/device status, verify completion and contents as required before making an updated image executable." + ], + "nodes": [ + "APB registers / LUT", + "Mapped read frontend", + "Transaction / SDR PHY", + "TX / RX FIFOs", + "NSS[3:0] / SCK / DQ[3:0]" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "docs/ip/xpi.md", + "rtl/ip/storage/xpi_reg.sv", + "rtl/ip/storage/xpi_pkg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "sram", + "family": "sram", + "title": "On-Chip SRAM", + "depth": 3, + "regions": [ + "SRAM", + "APB4_SRAM" + ], + "irqs": [], + "summary": "128 KiB on-chip SRAM; AXI32 data and one APB discovery/counter window.", + "features": [ + "32 banks of 4 KiB in the selected profile.", + "32-bit AXI data, one-bit ID; byte writes and supported memory bursts.", + "SRAM code, data, BSS and stack; reset does not erase memory." + ], + "paragraphs": [ + "The Tiny top overrides the reusable SRAM to 128 KiB and 32-bit data. The native memory aperture is 0x30000000 through 0x3001FFFF. APB registers describe the integrated configuration and observations; they are not another storage aperture.", + "Technology macros are selected by the IHP130 profile. Logical bank capacity is not a claim of timing closure, yield or physical area. Preserve byte-lane and natural alignment rules, and keep transfers within the decoded aperture.", + "Reset clears control state, not SRAM contents. Startup copies initialized sections from Flash and clears BSS explicitly. Stack placement at the SRAM end does not establish a measured maximum stack demand." + ], + "steps": [ + "Probe memory size, bank count and data width before using a linked image.", + "Compare ELF/MAP section sizes, buffers and stack margin against the actual 128 KiB region.", + "Use naturally aligned memory transfers and preserve ownership while DMA is active.", + "Read/reset counters according to their register semantics; reset is not data sanitization." + ], + "nodes": [ + "AXI32 adapter", + "Bank / byte selection", + "32 x 4 KiB SRAM", + "APB discovery / counters" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "docs/ip/onchip-sram.md", + "rtl/ip/memory/onchip_ram_reg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "gpio", + "family": "gpio", + "title": "General-Purpose Input/Output (GPIO)", + "depth": 3, + "regions": [ + "APB4_GPIO", + "APB4_GPIO_ADMIN" + ], + "irqs": [ + "gpio" + ], + "summary": "32 physical GPIOs with management and restricted-user register windows.", + "features": [ + "Atomic set, clear and toggle outputs; mode, output-enable and open-drain control.", + "Per-pin interrupts and filtering; alternate functions from the Tiny pin map.", + "Both windows address the same pads, not two GPIO banks." + ], + "paragraphs": [ + "GPIO administration controls pad mode, filtering, masks and locks. The restricted window exposes only permitted data/event operations. The user-access mask starts clear; grant only the pins required by the application.", + "Tiny retains only its implemented alternate functions. Unavailable alternatives drive neither peripheral requests nor pads. UART TX/RX and XPI use dedicated pads and are not inferred from a Mini pin assignment.", + "Before changing a driven alternate function, disable its producer, release output enable and use the controller guard/ownership sequence. Electrical drive settings require a reviewed pad/board specification; a register field is not a voltage rating." + ], + "steps": [ + "Confirm the Tiny alternate-function map and external circuit.", + "Prepare output data before enabling the driver; set open-drain/pull behavior only as supported by the pad.", + "Clear observed event causes before enabling the intended interrupt mask.", + "Use atomic aliases for concurrent updates and apply irreversible locks only after validation." + ], + "nodes": [ + "APB user / admin", + "Mode / mask / locks", + "Data / event / filter", + "Alternate-function mux", + "32 shared GPIO pads" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "docs/ip/gpio.md", + "rtl/ip/peripheral/gpio_reg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "dma", + "family": "dma", + "title": "Direct Memory Access (DMA)", + "depth": 3, + "regions": [ + "APB4_DMA" + ], + "irqs": [ + "dma" + ], + "summary": "Four channel contexts share one AXI32 master; memory-mapped endpoints only.", + "features": [ + "Four channels; direct transfers and 64-byte linked TCDs.", + "32-bit transfers, up to 16 beats, 32-word FIFO per channel.", + "Request mask 0x07F9; stream modes are disabled in Tiny." + ], + "paragraphs": [ + "Channel conventions are 0 UART0, 1 I2C0, 2 I2C1 and 3 bulk/XPI. They are software allocation conventions for one shared engine. Reserve a channel and all buffers through completion or confirmed abort.", + "Only request 0 and requests 3 through 10 are enabled. UART1 has no DMA request binding. Request enum names for omitted peripherals in the shared SDK do not establish Tiny hardware support; invalid kinds/requests must be rejected.", + "The fabric admits only one read or write transaction globally. CPU and DMA contend for that admission; burst length times bus width is not sustained throughput. A software wait timeout does not prove the engine is idle.", + "TCDs remain 64 bytes and require 64-byte alignment. Stride fields and y_count do not advertise 2D transfers: current validation requires zero strides and at most one row. Do not modify a descriptor or data buffer while hardware may still consume it.", + "The CAPABILITY maximum-burst field currently casts the configured 16 beats to four bits and therefore reads zero. The implemented parameter and SDK limit remain 16. Treat this as a discovery-encoding limitation; do not infer a zero-length engine or a qualified performance result from that field." + ], + "steps": [ + "Check channel < 4, MM-to-MM kind, 32-bit width, nonzero bounded length and an enabled request.", + "Prepare aligned descriptors/buffers and publish them with the required memory ordering.", + "Configure, start, then wait with a bounded software budget; distinguish submission from completion.", + "On failure capture error address/response and progress, request abort, and confirm terminal/drained state before reuse." + ], + "nodes": [ + "APB / 4 channel state", + "TCD fetch / validation", + "4 x 32-word FIFOs", + "Shared AXI32 master", + "Memory / paced I/O windows" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "docs/ip/dma.md", + "rtl/ip/peripheral/dma_reg.sv", + "rtl/ip/peripheral/dma_pkg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "timer", + "family": "timer", + "title": "General-Purpose Timers (TIM0, TIM1)", + "depth": 3, + "regions": [ + "APB4_TIM0", + "APB4_TIM1" + ], + "irqs": [ + "timer0", + "timer1" + ], + "summary": "Two 32-bit timer instances with prescalers and interrupt support.", + "features": [ + "Free-running, periodic and one-shot modes.", + "16-bit prescalers and two compare channels per instance.", + "Debug-freeze integration; no additional advanced timer." + ], + "paragraphs": [ + "TIM0 and TIM1 share one register definition but have separate base addresses and IRQ bits. Program the selected timer against the actual 24 MHz system clock, not the CLINT microsecond timebase.", + "A delay API has both a requested time interval and a separate software polling budget. A zero polling budget or timeout is not proof that a previously running timer stopped.", + "Use documented status/W1C handling and capture event causes before rearming. Debug halt may stop counting when configured; it does not prevent all register access or provide a system-wide freeze." + ], + "steps": [ + "Stop the selected timer before changing prescale/reload/compare values.", + "Compute timing from its functional clock and check representable range.", + "Clear stale events, configure interrupt selection and start.", + "Acknowledge observed events, recheck pending state and verify stop on recovery." + ], + "nodes": [ + "APB register bank", + "Prescale / counter", + "Compare / reload", + "Event / debug-freeze" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "docs/ip/timer.md", + "rtl/ip/peripheral/timer_reg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "pwm", + "family": "pwm", + "title": "Pulse Width Modulation (PWM)", + "depth": 3, + "regions": [ + "APB4_PWM" + ], + "irqs": [ + "pwm" + ], + "summary": "Two internal timers and four waveform output channels with capture/fault control.", + "features": [ + "Four PWM outputs, two capture inputs and fault/synchronization routes.", + "Shadow configuration and documented update boundaries.", + "Functional clock parameter is 24 MHz in Tiny." + ], + "paragraphs": [ + "PWM outputs and capture/fault inputs are selected through Tiny GPIO alternate functions. The reusable block has timer/operator state, not an unrestricted programmable I/O processor.", + "Shadow values become active at the configured update event. Writing a duty field alone does not guarantee an immediate glitch-free transition. Establish safe output levels before enabling external power circuitry.", + "Capture entries and overflow status require coherent reads and explicit acknowledgement. Fault handling and debug-halt behavior must be checked with the actual pin route; no electrical frequency limit is qualified here." + ], + "steps": [ + "Probe ABI and use the actual system clock in timing calculations.", + "Keep outputs inactive while programming timer/operator/channel state.", + "Latch shadow values at the selected boundary, then enable output routes.", + "On fault, preserve status and disable/recover outputs before clearing the cause." + ], + "nodes": [ + "APB / shadow registers", + "Timer / operator update", + "4 waveform channels", + "Capture / fault / IRQ" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "rtl/managed/clusterip/pwm/doc/datasheet.md", + "rtl/managed/clusterip/pwm/rtl/pwm_reg.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_pkg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "rtc", + "family": "rtc", + "title": "Real-Time Clock (RTC)", + "depth": 3, + "regions": [ + "APB4_RTC" + ], + "irqs": [ + "rtc" + ], + "summary": "64-bit seconds, 1/256-second subsecond time, alarms and wake status.", + "features": [ + "Two alarms, periodic wake and calibration controls.", + "Atomic time snapshot and command/response interface.", + "Tiny clocks the RTC from the system clock, not a separate sleep crystal." + ], + "paragraphs": [ + "The managed RTC engine is configured for 24 MHz and is wired to the same system clock as the MCU. Its separate logical clock/reset ports do not establish an independent low-power timing source.", + "Time reads use the documented snapshot/command sequence. Poll command completion before assuming a write has taken effect. Alarm interrupt and wake signals are separate; SYSCTRL exposes both live and sticky wake observations.", + "Battery-backed retention, oscillator accuracy, calendar drift and deep-sleep operation remain unspecified. A digital counter resolution is not a measured time accuracy." + ], + "steps": [ + "Probe the engine and configure it against the actual clock.", + "Set time through the bounded command API and verify completion.", + "Configure alarm/periodic selections and clear prior causes before enabling events.", + "Read snapshots consistently and capture wake/IRQ causes before acknowledgement." + ], + "nodes": [ + "APB command bridge", + "Time / calibration", + "Alarm / periodic logic", + "Snapshot / IRQ / wake" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "rtl/managed/clusterip/rtc/doc/datasheet.md", + "rtl/managed/clusterip/rtc/rtl/rtc_reg.sv", + "rtl/managed/clusterip/rtc/rtl/rtc_pkg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "wdg", + "family": "wdg", + "title": "Watchdog (WDG)", + "depth": 3, + "regions": [ + "APB4_WDG" + ], + "irqs": [ + "watchdog_early_warning" + ], + "summary": "Window watchdog with early warning and whole-system reset request.", + "features": [ + "24 MHz system-clock reference in Tiny.", + "Two-key service, window checking and retained reset-cause observation.", + "Eight watchdog-clock reset-request cycles in this integration." + ], + "paragraphs": [ + "Configure timing and window policy while inactive, then start and service using the prescribed key sequence. An early or malformed service can request reset just as an expired timeout can.", + "Tiny routes the watchdog request into system reset generation. Its own reset/retention boundary is distinct from the reset it requests; the acceptance application checks retained reset_count on reboot.", + "Because the watchdog uses the same system clock, it does not guarantee recovery from a failed system clock or provide independent deep-sleep supervision. The current integration is not a safety certificate." + ], + "steps": [ + "Probe status and inspect retained reset cause before starting a new diagnostic campaign.", + "Program prescaler, timeout, window and warning policy while inactive.", + "Start once and service inside the allowed window with bounded checks.", + "After reset distinguish watchdog reboot from fresh power-on and retain diagnostic evidence." + ], + "nodes": [ + "APB command bridge", + "Prescale / window counter", + "Service-key checker", + "Warning / retained cause / reset" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "rtl/managed/clusterip/wdg/doc/datasheet.md", + "rtl/managed/clusterip/wdg/rtl/wdg_reg.sv", + "rtl/managed/clusterip/wdg/rtl/wdg_pkg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "uart0", + "family": "uart", + "title": "Management UART (UART0)", + "depth": 3, + "regions": [ + "APB4_UART0" + ], + "irqs": [ + "uart0" + ], + "summary": "Primary console UART with 64-byte transmit and receive FIFOs.", + "features": [ + "Fractional baud generation, 5-8 data bits, parity, break and diagnostics.", + "Dedicated TX/RX pads; UART0 DMA requests available.", + "RTS/CTS require the selected GPIO alternate routes." + ], + "paragraphs": [ + "The shared rs_uart_* convenience HAL targets UART0. It is the normal Tiny diagnostic console. Configure baud against 24 MHz and the permitted fractional divider range; sampling margin remains a board/peer requirement.", + "FIFO acceptance is not completed wire transmission. A UART write timeout can leave a transmitted/queued prefix. Preserve protocol framing and inspect RX error flags instead of blindly retrying an entire message.", + "The polling budget is consumed while the FIFO blocks progress and is shared across the call. It is not a duration in milliseconds and cannot bound a stalled bus access." + ], + "steps": [ + "Configure baud, framing and optional flow-control routing before enabling the peer.", + "Clear stale error/event state and use bounded FIFO operations.", + "Reserve channel 0 when using UART0 DMA, and follow buffer lifetime rules.", + "Wait for the required queue/serializer completion boundary before changing framing or disabling clocks." + ], + "nodes": [ + "APB / baud registers", + "64-byte TX FIFO / serializer", + "RX sampler / 64-byte FIFO", + "IRQ / error / DMA requests" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "docs/ip/uart.md", + "rtl/ip/serial/uart_reg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "uart1", + "family": "uart", + "title": "Second UART (UART1)", + "depth": 3, + "regions": [ + "APB4_UART1" + ], + "irqs": [ + "uart1" + ], + "summary": "Second UART instance with dedicated TX/RX and its own interrupt.", + "features": [ + "Same UART v3 register ABI and 64-byte FIFOs.", + "PIO/IRQ integration; no Tiny UART1 DMA request route.", + "CTS input is tied permissive; no dedicated RTS/CTS pad pair." + ], + "paragraphs": [ + "UART1 has its own base and core IRQ bit 26. The generic UART0 helper must not be mistaken for an instance-selecting UART1 API. Use the correct base/register contract or the documented Tiny loopback acceptance source.", + "The instance reuses the UART FIFO, divider, framing and error semantics. Tiny ties its CTS input low and leaves the DMA stall outputs unconnected to requests; shared register fields do not create the omitted routing.", + "Loopback acceptance is a source-level test facility. It does not qualify an external baud rate, cable, voltage domain or Linux driver." + ], + "steps": [ + "Select the UART1 base and confirm framing/divider settings before use.", + "Use PIO or core IRQ bit 26; do not allocate a UART0 DMA selector for UART1.", + "Handle RX error entries and use bounded TX/RX waits.", + "Confirm serializer idle before changing framing, then clear only captured interrupt causes." + ], + "nodes": [ + "UART1 APB bank", + "64-byte TX / RX FIFOs", + "Framing / fractional divider", + "Dedicated TX/RX / IRQ26" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "docs/ip/uart.md", + "rtl/ip/serial/uart_reg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "i2c", + "family": "i2c", + "title": "Inter-Integrated Circuit (I2C0, I2C1)", + "depth": 3, + "regions": [ + "APB4_I2C0", + "APB4_I2C1" + ], + "irqs": [ + "i2c0", + "i2c1" + ], + "summary": "Two controller-mode I2C instances with command/receive queues.", + "features": [ + "7-bit/10-bit addressing, repeated START and clock stretching.", + "Sixteen-entry command and RX queues; arbitration and recovery reporting.", + "DMA pacing uses channels 1 and 2 by software convention." + ], + "paragraphs": [ + "I2C0 and I2C1 share the register layout but have separate base addresses, GPIO alternate routes and IRQ bits. They are controllers, not target/slave peripherals. Board pull-ups and compatible voltage levels are required.", + "The queued command grammar and FIFO limits define how START, data, repeated START and STOP are submitted. A NACK is an observed protocol outcome; do not treat command FIFO acceptance as a successful bus transaction.", + "Use bounded transaction and recovery waits. Arbitration loss, stuck-low lines or clock stretching require inspection and a bus-safe recovery sequence rather than concurrent driving or automatic infinite retry." + ], + "steps": [ + "Select the bus, verify its GPIO route and calculate timing from 24 MHz.", + "Ensure the bus is released, clear stale events and configure supported address mode.", + "Submit the documented command sequence and inspect terminal/NACK/arbitration status.", + "Recover and release lines before retrying; preserve timeout/error context." + ], + "nodes": [ + "APB / timing / status", + "16-entry command queue", + "START / shift / STOP engine", + "RX queue / IRQ / DMA pacing" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "docs/ip/i2c.md", + "rtl/ip/serial/i2c_reg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "sysctrl", + "family": "sysctrl", + "title": "System Controller (SYSCTRL)", + "depth": 3, + "regions": [ + "APB4_SYSCTRL" + ], + "irqs": [], + "summary": "Tiny-owned control and first-fault/acceptance register bank.", + "features": [ + "Sticky first-fault address, master, response and saturating event count.", + "CPU/DMA wait-counter snapshot; live/sticky RTC wake status.", + "First full-word valid TEST_STATUS result remains sticky until reset." + ], + "paragraphs": [ + "Only the decoded Tiny offsets below are implemented. Compatibility identity reads do not create selectable cores, a PLL or an application processor. Other offsets fail; writes to read-only locations, unaligned accesses and partial writes return APB error.", + "FAULT_STATUS captures the first pending event. Clearing pending permits a subsequent fault record; FAULT_COUNT counts events independently and saturates. Capture address/master/response before clearing.", + "PERF_CTRL controls wait counters and snapshots. Read low/high words from the captured snapshot, not from independently changing live values. A wait count is not end-to-end throughput.", + "TEST_STATUS accepts a full-word write with VALID set only while the prior result is invalid. Reserved input bits are masked; the terminal result is not UART text. A later result cannot overwrite the first valid one before reset." + ], + "steps": [ + "Use the Tiny identity before choosing control operations.", + "Read and preserve pending fault status/address/master/detail before W1C acknowledgement.", + "Enable/capture CPU and DMA wait counters through PERF_CTRL and then read both snapshot words.", + "For automated acceptance write VALID, PASS and result code once; an earlier failure cannot be replaced by a later pass." + ], + "nodes": [ + "APB alignment / strobe gate", + "Tiny offset decoder", + "First-fault / snapshots", + "Sticky TEST_STATUS / RTC wake" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "rtl/tiny/top/tiny_sysctrl.sv", + "docs/ip/tiny-soc.md" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "clint", + "family": "clint", + "title": "Local Interrupt Controller (CLINT)", + "depth": 3, + "regions": [ + "APB4_CLINT" + ], + "irqs": [ + "clint_software", + "clint_timer" + ], + "summary": "Machine software interrupt and 64-bit timer for hart slot zero.", + "features": [ + "Core interrupt bits 0 and 1 are local software/timer causes.", + "1 MHz timebase derived from the 24 MHz system clock.", + "64-bit time and compare are accessed as RV32 words." + ], + "paragraphs": [ + "Tiny has one management hart and uses hart slot zero. CLINT is distinct from the external interrupt vector and does not provide a PLIC.", + "Read time using a coherent high/low/high retry sequence. Update compare with the documented safe word order so an intermediate value does not trigger an unintended interrupt.", + "The 1 MHz timebase supports timing measurements/deadlines, while peripheral dividers still use their own 24 MHz engine clock. A software busy-loop count is not this timebase." + ], + "steps": [ + "Use slot zero and the CLINT base from the generated Tiny map.", + "Read coherent time through the SDK helper.", + "Mask/prepare the timer cause and update compare in safe word order.", + "Handle and rearm the appropriate local cause; do not subtract two to form an external IRQ ordinal." + ], + "nodes": [ + "APB word accesses", + "64-bit time counter", + "Hart0 compare / MSIP", + "Local software / timer IRQ" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "docs/ip/clint.md", + "rtl/ip/peripheral/clint_reg.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + }, + { + "id": "archinfo", + "family": "archinfo", + "title": "Architecture Information (ARCHINFO)", + "depth": 3, + "regions": [ + "APB4_ARCHINFO" + ], + "irqs": [], + "summary": "Read-only Tiny identity and build/configuration discovery.", + "features": [ + "Tiny SOC_ID 0x54494E59; 128 KiB SRAM and 24 MHz reference clock.", + "Topology 0x20200001, features 0x00007FFE and technology 0x02010082.", + "No provisioned unique device ID is advertised." + ], + "paragraphs": [ + "The owned Tiny adapter replaces the managed block's fixed SoC identity while retaining its register ABI. BUILD_ID, CONFIG_ID and BUILD_STATUS are supplied by generated build metadata; they must not be published as default zero values for a built image.", + "Read and validate Tiny identity before interpreting product-specific capabilities or selecting a firmware layout. The build/profile identity is distinct from a silicon lot/serial number.", + "Device-ID inputs are tied invalid/read-disabled. Their register offsets do not establish a provisioned unique identity, secure key storage or production traceability." + ], + "steps": [ + "Read discovery through the SDK and validate the build identity.", + "Confirm Tiny SOC_ID, one-hart topology, 128 KiB memory and active capabilities.", + "Reject mismatched images/configurations before hardware initialization.", + "Read device ID only when qualified and enabled; this integration does not supply it." + ], + "nodes": [ + "APB read-only ABI", + "Build / config metadata", + "Tiny identity override", + "Capability / device-ID gate" + ], + "sources": [ + "rtl/tiny/top/retrosoc_tiny.sv", + "rtl/managed/clusterip/archinfo/doc/datasheet.md", + "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv", + "rtl/tiny/top/tiny_archinfo.sv" + ], + "evidence": "Source reviewed; current-commit matching raw qualification report not supplied." + } +] diff --git a/publications/datasheets/tiny/chapter-index.json b/publications/datasheets/tiny/chapter-index.json new file mode 100644 index 00000000..2596ed17 --- /dev/null +++ b/publications/datasheets/tiny/chapter-index.json @@ -0,0 +1,86 @@ +[ + { + "id": "xpi", + "family": "xpi", + "title": "XPI Universal Controller", + "depth": 3 + }, + { + "id": "sram", + "family": "sram", + "title": "On-Chip SRAM", + "depth": 3 + }, + { + "id": "gpio", + "family": "gpio", + "title": "General-Purpose Input/Output (GPIO)", + "depth": 3 + }, + { + "id": "dma", + "family": "dma", + "title": "Direct Memory Access (DMA)", + "depth": 3 + }, + { + "id": "timer", + "family": "timer", + "title": "General-Purpose Timers (TIM0, TIM1)", + "depth": 3 + }, + { + "id": "pwm", + "family": "pwm", + "title": "Pulse Width Modulation (PWM)", + "depth": 3 + }, + { + "id": "rtc", + "family": "rtc", + "title": "Real-Time Clock (RTC)", + "depth": 3 + }, + { + "id": "wdg", + "family": "wdg", + "title": "Watchdog (WDG)", + "depth": 3 + }, + { + "id": "uart0", + "family": "uart", + "title": "Management UART (UART0)", + "depth": 3 + }, + { + "id": "uart1", + "family": "uart", + "title": "Second UART (UART1)", + "depth": 3 + }, + { + "id": "i2c", + "family": "i2c", + "title": "Inter-Integrated Circuit (I2C0, I2C1)", + "depth": 3 + }, + { + "id": "sysctrl", + "family": "sysctrl", + "title": "System Controller (SYSCTRL)", + "depth": 3 + }, + { + "id": "clint", + "family": "clint", + "title": "Local Interrupt Controller (CLINT)", + "depth": 3 + }, + { + "id": "archinfo", + "family": "archinfo", + "title": "Architecture Information (ARCHINFO)", + "depth": 3 + } +] diff --git a/publications/datasheets/tiny/chapter-review.md b/publications/datasheets/tiny/chapter-review.md new file mode 100644 index 00000000..65609ab7 --- /dev/null +++ b/publications/datasheets/tiny/chapter-review.md @@ -0,0 +1,49 @@ +# Tiny Gen1 v0.1 DRAFT chapter review + +Source: `9c706ba0ff1da1028c299cfff573010a86dfd7ce`. PDF: **204 pages**, SHA-256 `44d2b6140395ab3adea6e1ca64ce72ba65fa4727213bfca136a6e47010958d4a`. + +All **39 frozen entries / 14 IP chapters** are reviewed below. Register, address, IRQ and pad values follow the Tiny implementation. The dated evidence narrative is not promoted to a current-commit report. See [content review](content-review.md), [layout rules](style.md) and the delivered validation record. + +| # | Chapter / page | Coverage and implementation | Basis | Recommendation | +| --- | --- | --- | --- | --- | +| 1 | Product Brief / 1 | Covered. Rill Tiny Gen1 identity and source-backed overview; prototype badge and timing qualification kept separate. | [tiny.json](../../../publications/datasheets/tiny/tiny.json), [ihp130-tiny.mk](../../../configs/ci/ihp130-tiny.mk) | Keep the two-column cover, logo reservation and partial Functional mark; do not promote it from host test counts. | +| 2 | Features / 1 | Covered. Rill Tiny Gen1 identity and source-backed overview; prototype badge and timing qualification kept separate. | [tiny.json](../../../publications/datasheets/tiny/tiny.json), [ihp130-tiny.mk](../../../configs/ci/ihp130-tiny.mk) | Keep the two-column cover, logo reservation and partial Functional mark; do not promote it from host test counts. | +| 3 | Configuration and Scope / 2 | Covered. IHP130, 128 KiB, 24 MHz target, four DMA channels; hardware RV32IMC versus default RV32IM firmware. | [ihp130-tiny.mk](../../../configs/ci/ihp130-tiny.mk), [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv) | Use the committed profile and identity; keep deferred interfaces and physical claims excluded. | +| 4 | Reading and Evidence Conventions / 2 | Covered. Product-specific organization, navigation or revision control; no additional hardware capability. | [datasheet.typ](../../../publications/datasheets/tiny/datasheet.typ), [structure-contract.json](../../../publications/datasheets/tiny/structure-contract.json) | Retain the declared scope, complete source links and independent Tiny identity when updating this section. | +| 5 | System Architecture / 17 | Covered. Product-specific organization, navigation or revision control; no additional hardware capability. | [datasheet.typ](../../../publications/datasheets/tiny/datasheet.typ), [structure-contract.json](../../../publications/datasheets/tiny/structure-contract.json) | Retain the declared scope, complete source links and independent Tiny identity when updating this section. | +| 6 | Processor and Integration / 17 | Covered. One RV32IMC MCU hart, A disabled, direct AHB-Lite/AXI32 adapter and debug reset boundary. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [mgmt_core_wrapper.sv](../../../rtl/ip/core/mgmt_core_wrapper.sv) | Retain actual wrapper parameters; do not infer firmware ISA flags from the hardware C extension. | +| 7 | Clock, Reset and Operating State / 18 | Covered. System and asynchronous JTAG domains; RTC/WDG share the system clock. | [clock_reset_domains.json](../../../rtl/tiny/integration/clock_reset_domains.json), [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv) | Obtain CDC/RDC and clock/power evidence separately; do not claim independent sleep timing. | +| 8 | Bus Transactions, Arbitration and Errors / 19 | Covered. One globally active transaction, round-robin acceptance, saved ownership, bounded legal bursts and error/drain behavior. | [tiny_axi4_fabric.sv](../../../rtl/tiny/top/tiny_axi4_fabric.sv), [axi4_error_slave.sv](../../../rtl/ip/interconnect/axi4_error_slave.sv) | Keep local IP capability separate from end-to-end fabric admission; no unlimited liveness guarantee. | +| 9 | Memory Map and Access Conventions / 21 | Covered. Twenty canonical address windows, including alias versus physical-capacity distinctions. | [memory_map.json](../../../rtl/tiny/address_map/memory_map.json) | Reconcile every source-map change; do not use unmapped holes as scratch memory. | +| 10 | Interrupt and DMA Request Routing / 22 | Covered. Fourteen allocated core causes, thirty external positions, enabled DMA request map and channel conventions. | [soc_topology.json](../../../rtl/tiny/integration/soc_topology.json), [dma_math.c](../../../crt/src/hal/dma_math.c) | Keep core input bits, external ordinals, CSR positions and DMA selectors distinct. | +| 11 | Peripherals / 23 | Covered. Fourteen IP chapters and 337 source-extracted register definitions, with instance-specific routing. | [catalog.json](../../../publications/datasheets/tiny/catalog.json), [tiny_reference.py](../../../publications/tiny_reference.py) | Update source inventory, frozen register keys and rendered-coverage checks together after reviewed ABI changes. | +| 12 | XPI Universal Controller / 24-40 | Covered. Four-chip-select SDR serial-memory controller; pin-level boot uses NOR on NSS0. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [xpi.md](../../../docs/ip/xpi.md), [xpi_reg.sv](../../../rtl/ip/storage/xpi_reg.sv) | Inspect engine/FIFO/device status, verify completion and contents as required before making an updated image executable. | +| 13 | On-Chip SRAM / 41-46 | Covered. 128 KiB on-chip SRAM; AXI32 data and one APB discovery/counter window. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [onchip-sram.md](../../../docs/ip/onchip-sram.md), [onchip_ram_reg.sv](../../../rtl/ip/memory/onchip_ram_reg.sv) | Keep Tiny fabric restrictions despite local WRAP/FIXED flags; reset does not initialize SRAM. | +| 14 | General-Purpose Input/Output (GPIO) / 47-62 | Covered. 32 physical GPIOs with management and restricted-user register windows. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [gpio.md](../../../docs/ip/gpio.md), [gpio_reg.sv](../../../rtl/ip/peripheral/gpio_reg.sv) | Use atomic aliases for concurrent updates and apply irreversible locks only after validation. | +| 15 | Direct Memory Access (DMA) / 63-76 | Covered. Four channel contexts share one AXI32 master; memory-mapped endpoints only. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [dma.md](../../../docs/ip/dma.md), [dma_reg.sv](../../../rtl/ip/peripheral/dma_reg.sv) | Retain the explicit zero-readback burst-field limitation and 16-beat implementation limit; a future ABI/RTL fix is separate work. Confirm drain before reusing buffers. | +| 16 | General-Purpose Timers (TIM0, TIM1) / 77-83 | Covered. Two 32-bit timer instances with prescalers and interrupt support. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [timer.md](../../../docs/ip/timer.md), [timer_reg.sv](../../../rtl/ip/peripheral/timer_reg.sv) | Acknowledge observed events, recheck pending state and verify stop on recovery. | +| 17 | Pulse Width Modulation (PWM) / 84-107 | Covered. Two internal timers and four waveform output channels with capture/fault control. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [datasheet.md](../../../rtl/managed/clusterip/pwm/doc/datasheet.md), [pwm_reg.sv](../../../rtl/managed/clusterip/pwm/rtl/pwm_reg.sv) | On fault, preserve status and disable/recover outputs before clearing the cause. | +| 18 | Real-Time Clock (RTC) / 108-120 | Covered. 64-bit seconds, 1/256-second subsecond time, alarms and wake status. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [datasheet.md](../../../rtl/managed/clusterip/rtc/doc/datasheet.md), [rtc_reg.sv](../../../rtl/managed/clusterip/rtc/rtl/rtc_reg.sv) | Read snapshots consistently and capture wake/IRQ causes before acknowledgement. | +| 19 | Watchdog (WDG) / 121-129 | Covered. Window watchdog with early warning and whole-system reset request. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [datasheet.md](../../../rtl/managed/clusterip/wdg/doc/datasheet.md), [wdg_reg.sv](../../../rtl/managed/clusterip/wdg/rtl/wdg_reg.sv) | After reset distinguish watchdog reboot from fresh power-on and retain diagnostic evidence. | +| 20 | Management UART (UART0) / 130-140 | Covered. Primary console UART with 64-byte transmit and receive FIFOs. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [uart.md](../../../docs/ip/uart.md), [uart_reg.sv](../../../rtl/ip/serial/uart_reg.sv) | Wait for the required queue/serializer completion boundary before changing framing or disabling clocks. | +| 21 | Second UART (UART1) / 141-142 | Covered. Second UART instance with dedicated TX/RX and its own interrupt. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [uart.md](../../../docs/ip/uart.md), [uart_reg.sv](../../../rtl/ip/serial/uart_reg.sv) | Confirm serializer idle before changing framing, then clear only captured interrupt causes. | +| 22 | Inter-Integrated Circuit (I2C0, I2C1) / 143-154 | Covered. Two controller-mode I2C instances with command/receive queues. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [i2c.md](../../../docs/ip/i2c.md), [i2c_reg.sv](../../../rtl/ip/serial/i2c_reg.sv) | Recover and release lines before retrying; preserve timeout/error context. | +| 23 | System Controller (SYSCTRL) / 155-162 | Covered. Tiny-owned control and first-fault/acceptance register bank. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [tiny_sysctrl.sv](../../../rtl/tiny/top/tiny_sysctrl.sv), [tiny-soc.md](../../../docs/ip/tiny-soc.md) | For automated acceptance write VALID, PASS and result code once; an earlier failure cannot be replaced by a later pass. | +| 24 | Local Interrupt Controller (CLINT) / 163-166 | Covered. Machine software interrupt and 64-bit timer for hart slot zero. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [clint.md](../../../docs/ip/clint.md), [clint_reg.sv](../../../rtl/ip/peripheral/clint_reg.sv) | Handle and rearm the appropriate local cause; do not subtract two to form an external IRQ ordinal. | +| 25 | Architecture Information (ARCHINFO) / 167-175 | Covered. Read-only Tiny identity and build/configuration discovery. | [retrosoc_tiny.sv](../../../rtl/tiny/top/retrosoc_tiny.sv), [datasheet.md](../../../rtl/managed/clusterip/archinfo/doc/datasheet.md), [archinfo_reg.sv](../../../rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv) | Read device ID only when qualified and enabled; this integration does not supply it. | +| 26 | Pins and Board Connections / 176 | Covered. Fifty-two logical signal pads and all thirty-two GPIO alternate-function rows. | [pin_map.json](../../../rtl/tiny/pin_map/pin_map.json), [soc_topology.json](../../../rtl/tiny/integration/soc_topology.json) | Supply package/board mapping and electrical constraints before treating these as physical pins. | +| 27 | Electrical, Package and Reliability Boundaries / 179 | Covered; physical evidence needed. Explicit missing-evidence table; no fabricated limits or package identifiers. | [tiny-soc-verification.md](../../../docs/ip/tiny-soc-verification.md), [evidence.json](../../../publications/datasheets/tiny/evidence.json) | Attach conditions, units, Min/Typ/Max meaning and matching characterization before publishing numerical ratings. | +| 28 | Software / 180 | Covered. Product-specific organization, navigation or revision control; no additional hardware capability. | [datasheet.typ](../../../publications/datasheets/tiny/datasheet.typ), [structure-contract.json](../../../publications/datasheets/tiny/structure-contract.json) | Retain the declared scope, complete source links and independent Tiny identity when updating this section. | +| 29 | Reset, Boot and Linker Layout / 180 | Covered. Tiny startup excludes PSRAM setup and relocates initialized code/data to SRAM with BSS/stack initialization. | [startup.S](../../../crt/arch/riscv/startup.S), [ld2_all_sram.lds](../../../crt/linker/ld2_all_sram.lds) | Use actual ELF/MAP and measured/worst-case stack demand; placement is not a memory-use measurement. | +| 30 | SDK, API Completion and Polling / 181 | Covered. Public SDK namespace and Tiny composition, operation-specific completion and bounded polling semantics. | [dma.c](../../../crt/src/hal/dma.c), [sysctrl.c](../../../crt/src/hal/sysctrl.c), [check_tiny_examples.py](../../../publications/check_tiny_examples.py) | Confirm each API completion state and distinguish timeout from idle or rollback. | +| 31 | DMA Descriptors and Buffer Lifetime / 182 | Covered. Seventeen C descriptor members, 64-byte layout/alignment, control positions, bounded HAL chain walking and buffer lifetime. | [dma.h](../../../crt/include/retrosoc/hal/dma.h), [dma_math.c](../../../crt/src/hal/dma_math.c), [dma.c](../../../crt/src/hal/dma.c) | Keep one-descriptor HAL submission/result writeback distinct from an autonomous queue; retain zero-burst default and unsupported-field qualifications. | +| 32 | Acceptance and Diagnostics / 184 | Covered. Source-bound acceptance stages, sticky terminal result and retained watchdog-reset early-pass branch. | [tiny.c](../../../app/apps/ci_smoke/tiny.c), [mcu_acceptance.S](../../../app/apps/ci_smoke/mcu_acceptance.S) | Control initial reset_count and preserve full simulator verdict; a warm reboot alone does not replay every test. | +| 33 | Implementation and Evidence / 185 | Covered. Independent Tiny setup/build/check flow; no Mini/HP/accelerator prerequisite. | [build_tiny_datasheet.py](../../../publications/build_tiny_datasheet.py), [generate_tiny.py](../../../scripts/generate_tiny.py), [tiny-soc-verification.md](../../../docs/ip/tiny-soc-verification.md) | Record actual tool/profile/stage outcomes and preserve missing-input failures. | +| 34 | Reproducible Development Flow / 185 | Covered. Independent Tiny setup/build/check flow; no Mini/HP/accelerator prerequisite. | [build_tiny_datasheet.py](../../../publications/build_tiny_datasheet.py), [generate_tiny.py](../../../scripts/generate_tiny.py), [tiny-soc-verification.md](../../../docs/ip/tiny-soc-verification.md) | Record actual tool/profile/stage outcomes and preserve missing-input failures. | +| 35 | Verification Status and Qualification Gaps / 186 | Covered. Dated repository narratives retained; slow-corner setup WNS -455.18 ns is not 24 MHz closure. | [tiny-soc-verification.md](../../../docs/ip/tiny-soc-verification.md) | Obtain exact-commit raw reports; keep failed, skipped and partial campaigns distinct. | +| 36 | Appendix: Global Register Index / 187 | Covered. Instance-qualified global lookup for every extracted register group and repeated index. | [register-profiles.json](../../../publications/datasheets/tiny/register-profiles.json), [register-contract.json](../../../publications/datasheets/tiny/register-contract.json) | Check unique expanded addresses and canonical register links after any map/group change. | +| 37 | Document Control / 203 | Covered. Product-specific organization, navigation or revision control; no additional hardware capability. | [datasheet.typ](../../../publications/datasheets/tiny/datasheet.typ), [structure-contract.json](../../../publications/datasheets/tiny/structure-contract.json) | Retain the declared scope, complete source links and independent Tiny identity when updating this section. | +| 38 | Revision History / 203 | Covered. Product-specific organization, navigation or revision control; no additional hardware capability. | [datasheet.typ](../../../publications/datasheets/tiny/datasheet.typ), [structure-contract.json](../../../publications/datasheets/tiny/structure-contract.json) | Retain the declared scope, complete source links and independent Tiny identity when updating this section. | +| 39 | Sources, License and Contact / 204 | Covered. Complete source identity, dependency/font/package hashes, document ID and author/contact retained. | [tiny.json](../../../publications/datasheets/tiny/tiny.json), [dependencies.lock.json](../../../dependencies/dependencies.lock.json) | Ship the matching manifest and raw validation report; document dates are not measurement dates. | + +Every row is source/document review. Matching current physical/board/silicon qualification remains unavailable; host publication tests do not change that state. diff --git a/publications/datasheets/tiny/content-review.md b/publications/datasheets/tiny/content-review.md new file mode 100644 index 00000000..14add1c8 --- /dev/null +++ b/publications/datasheets/tiny/content-review.md @@ -0,0 +1,31 @@ +# Tiny Gen1 v0.1 DRAFT content review + +The publication describes the independent IHP130 Tiny profile: one RV32IMC +Hazard3 with A disabled, RV32IM default firmware, 128 KiB SRAM, 24 MHz target, +four DMA channels and AXI32/APB4. Rill (清溪) is the selected prototype brand. +The font/palette/grid are inherited as design rules; product facts are not +inherited from Mini's descriptions or qualification records. + +| Area | Review and publication decision | Follow-up boundary | +| --- | --- | --- | +| CPU and startup | Publish the actual C/M extensions, disabled A, CSR-enabled firmware and Tiny guard around PSRAM setup. | Keep compiler target separate from implemented ISA; a reset vector is not a completed boot. | +| Fabric | Document one globally active CPU/DMA read or write, saved ownership, naturally aligned bounded bursts and terminal response/drain. | Do not claim arbitrary AXI4 features, independent read/write concurrency or unrestricted liveness. | +| Address/IRQ/pads | Derive all 20 regions, 14 allocated core causes and 52 logical signal pads; retain 32 GPIO alternate entries. | Logical pads are not package pin numbers or a board schematic. | +| IP/register scope | Fourteen chapters, thirteen unique register families; Tiny SYSCTRL is decoded independently and ARCHINFO overrides the SoC identity. | Reject missing/extra decode and defaults belonging to other products. | +| DMA | Four channels, request mask 0x07F9, no stream modes, 64-byte descriptors and source-derived field layout. | **Discovery discrepancy:** the four-bit maximum-burst field reads zero after truncating 16. Publish that value and the actual 16-beat limit separately; propose a future ABI/RTL review, do not change RTL here. | +| SRAM | 32 x 4 KiB banks, four data bytes, no reset erase. | Local FIXED/WRAP capability bits do not override the narrower Tiny fabric subset. | +| UART/I2C/timers | Reused family ABI with actual instances, routing and 24 MHz engine clock. UART1 is PIO/IRQ without a Tiny DMA route. | Generic UART HAL example is UART0; peripheral command acceptance is not necessarily completed I/O. | +| Supervision | RTC and watchdog share the system clock; WDG requests system reset and retains its own reset observation. | No independent sleep clock, battery-backed retention or clock-failure watchdog guarantee. | +| Acceptance | The application source performs CPU, fault, DMA, timer, RTC and I/O checks, then watchdog reboot. | A nonzero pre-existing watchdog reset count takes an early pass branch; controlled initial state is required. | +| Verification | Retain the dated repository narrative, including slow-corner setup WNS -455.18 ns at a 41.666666667 ns constraint. | Raw matching artifacts are not present in this publication workspace; no current-commit qualification is promoted. | +| Electrical/package/power | Preserve explicit missing-evidence tables and required measurement context. | No numerical production limits, die area, thermal rating or silicon claim is invented. | + +The existing Tiny verification document reports an originally uncommitted run +and a later path-migration follow-up. Neither automatically qualifies the source +SHA selected for this document. The final publication validation report records +only checks executed for this build; hardware campaign repair is separate work. + +The [chapter review](chapter-review.md) covers all frozen entries and gives +source/evidence/maintenance advice. Full registers and software guidance are +retained even when a board or physical result is unavailable. No Mini document, +version, review or PDF is updated by this addition. diff --git a/publications/datasheets/tiny/datasheet.typ b/publications/datasheets/tiny/datasheet.typ new file mode 100644 index 00000000..cd9d68c6 --- /dev/null +++ b/publications/datasheets/tiny/datasheet.typ @@ -0,0 +1,358 @@ +#import "style.typ": * +#import "diagrams.typ": architecture, flow, tcd-diagram +#import "waveforms.typ": timing +#import "ip-reference.typ": reference +#show: template + +#cover(evaluation:((name:"Available",fill:"full"),(name:"Functional",fill:"left-half"),(name:"Reproduced",fill:"empty"),(name:"Tapedout",fill:"empty")))[ + #text(9pt,weight:"semibold",fill:gold)[PRODUCT DATASHEET / #doc.status] + #v(rhythm.cover-gap) + #text(30pt,weight:"semibold")[retroSoC Tiny] + #linebreak() + #text(23pt,weight:"semibold",fill:gold)[Gen1] + #v(rhythm.cover-gap) + #text(13pt)[An Open-Source, Single-Core RISC-V MCU] + #v(rhythm.cover-meta-gap) + #grid(columns:(1fr,1fr), + [#text(font:("Inter","Noto Sans CJK SC"),weight:"bold",top-edge:0.7275390625em)[#doc.brand_name（#doc.brand_name_zh）] · v#doc.version \ #doc.date], + align(right)[#doc.author#link("mailto:"+doc.author_email)[(#doc.author_email)] \ #doc.maintainer]) + #v(rhythm.cover-rule-gap) + #line(length:100%,stroke:1.1pt+gold) += Product Brief +== Features + #columns(2,gutter:rhythm.cover-gutter)[ + #set par(leading:rhythm.cover-leading,spacing:rhythm.cover-spacing) + #set list(spacing:rhythm.cover-list-spacing) + *Compute and debug* + - One Hazard3 RISC-V hart: *RV32IMC*, A disabled. + - Default RV32IM firmware; IRQ/CSR support enabled. + - JTAG debug with coordinated hart reset. + + *Memory and interconnect* + - *128 KiB SRAM*, 32 banks of 4 KiB. + - Native AXI32 memory paths and one APB4 island. + - CPU and DMA share one active transaction globally. + - XPI NOR boot and SRAM-resident application layout. + + *DMA and control* + - *Four DMA channels*, 32-bit transfers, up to 16 beats. + - Direct and 64-byte linked-descriptor operation. + - Sticky first-fault records and CPU/DMA wait snapshots. + - Sticky automated firmware acceptance result. + #colbreak() + *Wired connectivity* + - 32 GPIOs with atomic output aliases and interrupts. + - Two FIFO UARTs; dedicated TX/RX pads. + - Two controller-mode I2C instances with 7/10-bit addressing. + - Four-chip-select XPI with single/dual/quad SDR phases. + + *Timing and supervision* + - Configured *24 MHz* system clock; no PLL. + - Two 32-bit general timers; four PWM outputs. + - 1 MHz CLINT timebase; local software/timer interrupts. + - RTC alarms/wake and window watchdog on the system clock. + + *Development boundary* + - Freestanding SDK and Tiny acceptance application. + - IHP130 macro/behavioral integration and simulation flows. + - No external RAM, wireless, HP core or multimedia accelerator. + ] + #v(1fr) + #note(below:0pt)[This DRAFT describes an implemented *prototype*. The 24 MHz configuration is a functional target, + *not a timing-qualified operating point*. Electrical, package, thermal, power and silicon qualification remain unprovided. + The partial Functional mark does not establish complete protocol or physical qualification.] +] +#pagebreak() +== Configuration and Scope +The main reference is #code(doc.profile). *Tiny is an independent wired MCU integration*; it is not a selectable Mini mode. +The reviewed implementation is identified by #code(doc.source_revision). An interface name, shared SDK declaration or mapped +offset does not establish an optional feature. Identify the product before using an inherited register or API name. +#ds-table("configuration",[Tiny reference configuration],([Item],[Selected value],[Boundary]),( + ([Product],[Tiny Gen1 / IHP130],[Prototype; one management MCU hart.]), + ([Hardware / firmware],[RV32IMC, A disabled / RV32IM],[Compressed execution is implemented; the default compiler target omits C.]), + ([Clock],[24 MHz; CLINT 1 MHz],[Functional targets; no PLL or qualified maximum-frequency rating.]), + ([Memory],[128 KiB SRAM],[External NOR for boot; no external RAM initialization dependency.]), + ([Bus / DMA],[AXI32/APB4; four channels],[One active read or write globally; memory-mapped endpoints only.]), + ([Firmware],code("APP=bringup; HAVE_CSR=YES; LINK_TYPE=ld2_all_sram"),[Tiny-specific acceptance entry point.])),widths:(0.8fr,1.55fr,1.75fr)) + +=== Implemented scope and deferred capabilities +The 14 IP chapters cover every decoded region and all allocated interrupt causes. UART and I2C instances retain distinct +addresses and wiring. The GPIO user/administration windows are views of one pad bank. A restricted register window is not +a claim of a separate security domain. + +Atomics, wireless, external RAM, USB, SDIO, standalone general SPI, I2S, CAN, ADC, accelerators, authenticated boot, +RTOS ports and independent deep-sleep timing are outside this release. Additional XPI chip selects remain available at +the interface, but the initial pin-level NOR acceptance uses NSS0; other populated-device configurations require evidence. +#source-note("docs/ip/tiny-soc.md",title:"Frozen Tiny requirements and non-goals") + +== Reading and Evidence Conventions +Addresses are byte addresses; register offsets are relative to their named instance/group. *Source reviewed*, *test available*, +*executed result* and *physical qualification* are separate states. Source links target the reviewed commit or locked managed +input. Diagrams describe digital structure and ordering; they do not specify measured latency or board timing. + +Use @tiny-addresses for memory windows, @tiny-irq for interrupt numbering, @tiny-register-index for address-first register +lookup, @tiny-boot for startup, @tiny-diagnostics for terminal results and @tiny-evidence for verification boundaries. +The document uses the approved Mini visual language; all product facts and source inventories here belong to Tiny. +#pagebreak() +#contents(depth:3) +#pagebreak() +#figure-directory(tables:true) +#pagebreak() +#figure-directory() +#pagebreak() + += System Architecture +== Processor and Integration +Hazard3 is hart zero. The shared wrapper selects the C and M extensions and disables A for Tiny. Its AHB-Lite bus terminates +at a direct AXI32 adapter. JTAG supports the implemented halt/resume, register and system-bus debug path; debug hart reset +waits for the adapter to become idle instead of abandoning an accepted transaction. + +The system has no application hart, MMU/Linux platform, hardware cache-coherent multicore organization or product extension +slots. CPU-visible SRAM, XPI and APB routes are the implemented interconnect. The single-hart architecture does not remove +the need for software/DMA buffer ownership and fences. +#architecture() +#source-note("rtl/tiny/top/retrosoc_tiny.sv",title:"Tiny product integration and parameters") +#source-note("rtl/ip/core/mgmt_core_wrapper.sv",title:"CPU ISA, AHB adapter and debug wrapper") + +== Clock, Reset and Operating State +CPU, AXI, APB, RTC and watchdog share the configured 24 MHz system clock. CLINT derives a 1 MHz tick. JTAG has its own +external clock and managed asynchronous debug crossing. Other asynchronous external inputs use their specified synchronizers; +the absence of a system-bus clock crossing is not complete CDC/RDC signoff. +#ds-table("clocks",[Declared Tiny clock/reset domains],([Domain],[Clock],[Reset],[Reset primitive]), + data.clocks.map(c=>(c.name,code(c.clock),code(c.reset),code(c.reset_primitive))),widths:(0.65fr,1.1fr,1.5fr,0.9fr)) +External reset is asynchronously asserted and synchronously released. The watchdog requests a whole-system restart while +retaining its own reset-cause information. Debug hart reset has a narrower scope. SRAM contents are *not initialized by reset*; +the runtime explicitly establishes initialized data and BSS. + +There is no dynamic frequency switching, independent sleep clock or guaranteed retention mode in this release. A watchdog +sharing the failed system clock cannot promise recovery from that clock failure. The existing RTL timing target must not be +advertised as a qualified voltage/frequency operating point. +#source-note("rtl/tiny/integration/clock_reset_domains.json",title:"Clock/reset inventory and debug crossings") + +== Bus Transactions, Arbitration and Errors +The two initiators are CPU and DMA. They share *one active read or write transaction globally*. The fabric saves source, +direction, address and attributes, forwards the request, and retains ownership until the terminal B or RLAST handshake. +Read/write request arbitration is round-robin; it is not a throughput guarantee or an unrestricted liveness guarantee. + +Memory transfers support naturally aligned 1/2/4-byte beats and up to 16 INCR beats. Single-beat FIXED is also admitted. +The complete address span must remain within one decoded target and one 4 KiB page without overflow. MMIO accepts only +one beat. The addressed register can impose stricter width/strobe rules; Tiny SYSCTRL requires aligned full-word writes. +#ds-table("bus-rules",[Transfer outcome and software consequence],([Condition],[Result],[Required handling]),( + ([Legal SRAM access],[Target response with saved ID/owner],[Do not reuse DMA buffers before completion.]), + ([XPI memory aperture],[Mapped reads; target controls memory-write rejection],[Programming uses the indirect command interface.]), + ([Illegal size/burst/lock/alignment/span],[SLVERR responder],[Correct the request; preserve diagnostic context.]), + ([Unmapped target],[DECERR responder],[Treat the address as unavailable, not scratch memory.]), + ([Unsupported APB offset/write],[PSLVERR, propagated as a bus error],[Do not retry an unsupported control indefinitely.])),widths:(1.1fr,1.4fr,1.65fr)) + +AW and W are independent. W is backpressured until the saved write address reaches its target; another requester cannot +take over accepted write data. Rejected reads return the advertised response beat count, and rejected writes drain their +accepted data before B. Backpressure requires valid payloads to remain stable. +#timing("axi4",[Representative AXI read response and backpressure; Tiny uses 32-bit data and one-bit ID.]) +#timing("apb4",[APB4 setup/access sequence with a wait state; address and write data remain stable.]) +#source-note("rtl/tiny/top/tiny_axi4_fabric.sv",title:"Saved ownership, admission and terminal handshake") +#source-note("rtl/ip/interconnect/axi4_error_slave.sv",title:"Error response and write-drain implementation") + +== Memory Map and Access Conventions +#ds-table("memory-map",[Canonical Tiny address windows],([Region],[Base],[Last address],[Size]), + data.regions.map(r=>(code(r.symbol),code(r.base_hex),code(r.end_hex),r.size_label)),widths:(1.2fr,1fr,1fr,0.65fr)) +The Flash alias and XPI aperture identify memory routing, not fitted NOR capacity. The selected acceptance device and slot +configuration remain separate. Only SRAM is the application RAM in this profile. Unsupported holes and omitted peripheral +addresses must not be probed speculatively or reused as memory. + +Register tables specify local offsets, access, reset and side effects. *W1C acknowledgement uses an explicit mask*; +read-modify-write can clear unrelated pending events. A live value or producer-dependent field need not equal its reset +assignment when software later reads it. Use coherent snapshots for multiword counters. + +== Interrupt and DMA Request Routing +#ds-table("irq-map",[Tiny interrupt wiring],([Source],[Core bit],[External ordinal],[Producer]), + data.interrupts.map(r=>(r.name,str(r.core_bit),if r.core_bit < 2 {[Local]} else {str(r.core_bit - 2)},code(r.signal))),widths:(1.05fr,0.5fr,0.7fr,1.95fr)) +Core bits 0/1 are CLINT software/timer causes. The other 30 positions feed Hazard3 external interrupt inputs; +*external ordinal equals core bit minus two*. All omitted producers are tied zero. A register index, DMA selector and +interrupt number are different namespaces. Core bits here number the wrapper input vector, not architectural CSR bit positions. +#ds-table("dma-routes",[Enabled DMA requests and software channel conventions],([Selector],[Endpoint],[Channel convention]),( + ([0],[Software-paced memory transfer],[3 bulk, or explicitly reserved free channel]), + ([3 / 4],[XPI transmit / receive],[3]),([5 / 6],[UART0 transmit / receive],[0]), + ([7 / 8],[I2C0 transmit / receive],[1]),([9 / 10],[I2C1 transmit / receive],[2])),widths:(0.7fr,2fr,1.4fr)) +UART1 uses PIO/IRQ. The shared SDK names other requests and channels, but Tiny must reject unavailable selections. +The current DMA transfer validator accepts 32-bit MM-to-MM work; stream modes are disabled. Serialize shared channel +conventions rather than assuming that each API owns a permanently independent engine. +#source-note("rtl/tiny/integration/soc_topology.json",title:"Interrupt and GPIO bindings") +#source-note("crt/src/hal/dma_math.c",title:"Tiny DMA kind/request validation") + +== Peripherals +Each IP starts on a new page. Repeated instances retain separate address/IRQ entries; their common register layout is +documented once. The fields below are extracted from the active common implementation with Tiny parameter overrides; +SYSCTRL and the ARCHINFO identity override are bound to Tiny-owned RTL. +#for entry in data.catalog {reference(entry)} + +== Pins and Board Connections +The following is a *logical signal-pad inventory*, not a package pin numbering or an approved PCB schematic. Pad cells, +power/ground pins, voltage domains and package bonding require the selected physical implementation. +#ds-table("pads",[Tiny logical signal pads],([Signal],[RTL direction],[Pad kind]), + data.pads.map(p=>(code(p.name),p.direction,p.kind.replace("_"," "))),widths:(2fr,0.8fr,1.2fr)) +#let gpio-mode(mode) = { + let terms=mode.inputs + if mode.do.contains("'") {()} else {(mode.do,)} + if terms.len()==0 {[Not routed]} else {code(terms.join(" / "))} +} +#ds-table("gpio-alternates",[Tiny GPIO alternate-function routes],([GPIO],[ALT0],[ALT1]), + data.gpio.map(g=>(str(g.pin),gpio-mode(g.alt0),gpio-mode(g.alt1))),widths:(0.4fr,1.85fr,1.85fr)) +Disable producers and release output enables before changing a live pad route. I2C and open-drain signals require external +pull-ups and compatible levels. Dedicated UART and XPI pins are not reassigned through the GPIO mux. Verify complete +pin groups, reset drive state and external clock availability before enabling a device. + +== Electrical, Package and Reliability Boundaries +This source-level publication supplies *no numerical production electrical ratings*. TBD means unavailable evidence, +not zero, unlimited range or permission to select a convenient value. Functional clock names are not independent power rails. +#ds-table("physical-gaps",[Evidence required before physical product claims],([Area],[Required evidence],[Current state]),( + ([Supply / absolute maximum],[Pad/core rails, sequencing, injection/ESD limits, approved conditions],[TBD]), + ([AC/DC timing],[PVT, loading, clock reference edge, setup/hold and input/output limits],[TBD]), + ([Package / pinout],[Die pad and package pin mapping, dimensions and bonding],[TBD]), + ([Thermal / power],[Package/board/test conditions, workloads, voltage and measured results],[TBD]), + ([Reliability / ordering],[Qualification records, traceable device revisions and order codes],[TBD])),widths:(1fr,2.5fr,0.5fr)) +No package photograph, fabricated part number, regulatory mark or silicon speed grade is inferred from the digital profile. +The documented STA deficit remains visible in @tiny-evidence; it is not an operating specification. + += Software +== Reset, Boot and Linker Layout +Reset enters the Flash alias at #code(data.reset_address). The Tiny runtime excludes the generic PSRAM delay/setup branches. +With CSR support selected it masks interrupts and installs the direct trap entry, initializes registers/stack, copies code +and data when load/run addresses differ, clears BSS, performs the configured premain work, and enters main. +#flow("boot",( + [Reset / JTAG state established · Fetch from NOR alias], + [Mask interrupts; establish trap entry and register/stack state], + [Tiny skips PSRAM setup · Copy initialized code/data into SRAM], + [Clear SRAM BSS · Perform configured premain initialization], + [Enter Tiny application · Handle terminal result or watchdog restart] +),[Tiny ordinary startup: source order, not a guaranteed boot-time measurement.]) +The `ld2_all_sram` layout places runtime code, data, BSS and stack in SRAM with initialized material loaded from Flash. +Memory-map capacity, load-image bytes, runtime static occupation and stack high-water demand are different quantities. +Inspect the actual ELF/MAP and reserve buffers plus stack/scratch margin before deployment. No matching size/high-water +measurement is supplied by this datasheet build. +#source-note("crt/arch/riscv/startup.S",title:"Tiny conditional startup and relocation") +#source-note("crt/linker/ld2_all_sram.lds",title:"Flash load / SRAM runtime linker layout") + +== SDK, API Completion and Polling +Consume public headers under #code("") and the #code("rs_") namespace. The Tiny build selects product-specific +application composition and generated address/IRQ/capability metadata. This does not generate replacement IP register ABIs. +Unsupported PLL, application-hart or selectable-core APIs return an error before MMIO. + +*A successful API return describes that API's completion boundary*: a start command can be accepted before its operation +finishes. FIFO acceptance is not completed serial transmission. A timeout can leave work active and buffers owned by a +device. Capture state and complete abort/drain before reuse. + +Software timeout arguments are polling budgets, not milliseconds. CPU/compiler work and bus stalls affect elapsed time; +a budget cannot bound a register read that never returns. Hardware counters and device-specific timeouts use their own +documented clock units. Use CLINT or another appropriate timebase when an elapsed-time deadline is required. + +== DMA Descriptors and Buffer Lifetime +#tcd-diagram() +#ds-table("tcd-fields",[Source-derived DMA C descriptor layout],([Byte offset],[Field],[Bytes],[Role]), + data.tcd.map(f=>(code("0x"+upper(str(f.offset,base:16))),code(f.name),str(f.bytes),f.role)),widths:(0.75fr,1.7fr,0.45fr,1.1fr)) +The descriptor is 64 bytes and each descriptor address is 64-byte aligned. Tiny permits only the implemented transfer kind, +request, increment and width combinations. Stride fields remain zero and row count is at most one. A field in the ABI is +not evidence of cyclic, 2D or stream support. HAL result fields do not imply that hardware directly writes every result word. + +#ds-table("tcd-control",[Descriptor control positions and portable Tiny use],([Bits],[Field],[Meaning / restriction]),( + ([0],[VALID],[Must be set for a submitted descriptor.]), + ([1 / 2],[SRC_INC / DST_INC],[Increment the corresponding memory address; use the endpoint's required mode.]), + ([3 / 4],[CRC_ENABLE / CRC_FINAL],[Select the implemented CRC processing/final comparison.]), + ([5 / 6],[INT_DONE / INT_ERROR],[Declared SDK flags; use the channel event-enable/IRQ registers rather than assuming per-descriptor IRQ gating.]), + ([10:8],[KIND],[Tiny admits MM-to-MM value zero only.]), + ([15:12],[REQUEST],[Zero or 3 through 10 in the current Tiny request map.]), + ([17:16],[PRIORITY],[Two-bit software priority value.]), + ([24:20],[BURST],[0 selects the 16-beat default in descriptor submission; 1 through 16 select a bound. Direct configuration requires 1 through 16.]), + ([Other bits],[Reserved / unused],[Use zero for compatibility; a field declaration does not establish an extra operation.])),widths:(0.6fr,1.05fr,2.5fr)) +The current HAL chain helper submits one descriptor at a time, waits, copies result registers into the descriptor and then +follows #code("next_ptr"), bounded by #code("max_tcds"). It is not an autonomous circular-queue API. On a timeout or error, +the helper records observed progress but the caller must still confirm abort/drain before releasing memory. + +Reserve channel, descriptor and payload storage through completion or confirmed recovery. Publish CPU-produced input with +the required fence before starting the non-CPU master. Tiny has no application-hart cache handoff protocol; importing the +Mini HP cache-clean service would describe nonexistent hardware. +#flow("dma-recovery",([Validate channel / request / bounds and reserve storage], + [Publish descriptor/input and configure while idle], [Start and wait for the required completion boundary], + [On failure: capture fault/progress, abort, confirm drain], [Release or reuse storage only after ownership is safe]), + [DMA lifetime and recovery ordering. A polling timeout is not an idle acknowledgement.]) +#source-note("crt/include/retrosoc/hal/dma.h",title:"Handwritten descriptor and public HAL ABI") +#source-note("crt/src/hal/dma_math.c",title:"Descriptor validation and unsupported combinations") + +== Acceptance and Diagnostics +Both #code("bringup") and #code("ci_smoke") select the Tiny acceptance entry point. A controlled first boot with a clear +watchdog reset count performs the tests below, then deliberately requests watchdog reboot. A subsequent boot with a nonzero +retained reset count takes the early successful terminal path. *A pre-existing watchdog reset count is not proof that this +boot executed every test.* Record initial state, image, profile and the final simulator result. +#ds-table("acceptance-codes",[Tiny application failure codes from the reviewed main sequence],([Code],[Stage]),( + ([1],[Primary UART initialization]),([2],[Watchdog status read]),([3],[Tiny build/topology and SRAM discovery]), + ([4],[Compressed execution, A-disabled ISA and exception handler setup]),([5],[Atomic/unmapped probes and first fault]), + ([6],[Memory/UART DMA]),([7],[CLINT progression and timer interrupt]),([8],[RTC, PWM discovery and unsupported-control rejection]), + ([9],[Watchdog configuration/start]),([10],[GPIO, UART1 loopback and I2C NACK checks])),widths:(0.4fr,3.8fr)) +The first valid full-word SYSCTRL TEST_STATUS write is sticky. Bit 31 is valid, bit 0 pass and bits 15:8 the result code. +The testbench must emit #code("SIM_TEST_PASS") and the command must succeed without failure/timeout markers. UART startup +text is diagnostic only. The compact assembly netlist boot test has a narrower scope than the full SDK image. +#source-note("app/apps/ci_smoke/tiny.c",title:"Acceptance order, reset-count branch and terminal codes") +#source-note("app/asm/tiny_boot.S",title:"Separate compact netlist boot test") + += Implementation and Evidence +== Reproducible Development Flow +Start from the committed IHP130 Tiny profile. Use the existing locked dependency setup and doctor flow, then build the +Tiny firmware and selected simulator. The publication pipeline itself does not perform an EDA campaign. +#code-block(raw("make CONFIG=configs/ci/ihp130-tiny.mk setup\nmake CONFIG=configs/ci/ihp130-tiny.mk doctor\nmake CONFIG=configs/ci/ihp130-tiny.mk firmware sim\nmake CONFIG=configs/ci/ihp130-tiny.mk SIMU=IVERILOG firmware sim\nmake CONFIG=configs/ci/ihp130-tiny.mk regress-pr",block:true)) +Tiny source lists exclude Mini product RTL, RIB/RIBP, application-CPU generation and accelerator inputs. Common RTL and +Hazard3 remain revision-locked. Keep generated files in the selected build variant; missing unrelated accelerator corpora +must not become prerequisites for the Tiny publication. + +== Verification Status and Qualification Gaps +Readiness is *prototype*. #data.evidence.boundary +#ds-table("evidence",[Dated repository verification record and publication boundary],([Area],[What the record reports],[Interpretation]), + data.evidence.records.map(r=>(r.at(0),r.at(1),r.at(2))),widths:(0.8fr,1.7fr,1.65fr)) +No matching current-commit raw qualification report is attached. The documented setup WNS of *−455.18 ns* and TNS of +*−13,049,600 ns* describe the dated IHP130 slow-library analysis at a 41.666666667 ns clock constraint, with a reset-distribution deficit. They must not become a positive +24 MHz timing claim. Subsequent source-path migration has its own bounded follow-up record; it does not rerun all earlier stages. + +Publication tests establish document/source consistency and layout, not electrical compliance, full protocol coverage or +silicon operation. Future pass records must identify exact source/profile, tool/model versions, executed stage, raw report +and result. Keep skipped, failed and unfinished work visible. +#source-note("docs/ip/tiny-soc-verification.md",title:"Historical evidence, timing deficit and remaining work") + += Appendix: Global Register Index +Use the instance-qualified address below, then follow the canonical register reference. GPIO common discovery offsets +exist in both views. Repeated groups retain explicit indices; gaps are not additional registers. Addressability does not +override the register's access, alignment, strobe or side-effect rules. +#for entry in data.catalog { + if entry.id=="uart1" {minor-title("UART1 - shared UART register ABI")} else {minor-title(entry.title)} + let ref=data.registers.at(entry.family) + for symbol in entry.regions.filter(s=>s.starts-with("APB4_")) { + let region=data.regions.find(r=>r.symbol==symbol) + let records=() + for group in ref.groups { + let applies=entry.family!="gpio" or group.id=="common" or (group.id=="user" and symbol=="APB4_GPIO") or (group.id=="admin" and symbol=="APB4_GPIO_ADMIN") + if applies { + for instance in range(group.count) { + for reg in ref.registers.filter(r=>r.group==group.id) { + let address=region.base+group.base+instance*group.stride+reg.offset + records.push((code("0x"+upper(str(address,base:16))),link(label("reg-"+entry.family+"-"+reg.key),code(reg.name)), + if group.count>1 {str(instance)} else {[—]},reg.access)) + } + } + } + } + ds-table("index-"+symbol,[#symbol instance addresses],([Absolute address],[Register],[Index],[Access]),records,widths:(1fr,1.9fr,0.4fr,0.85fr)) + } +} + += Document Control +== Revision History +#ds-table("revision",[Document revision history],([Date],[Version],[Change]), + ((doc.date,[v#doc.version #doc.status],[Initial Tiny Gen1 complete reference; independent source extraction and Tiny-qualified integration.]),),widths:(0.8fr,0.85fr,2.5fr)) + +== Sources, License and Contact +Hardware/software snapshot: #code(doc.source_revision). This document's source manifest records the exact technical files, +publication files, managed revisions and fonts/packages used for the build. The PDF digest, chapter review and actual +validation record accompany the output; the document date is not a hardware measurement date. + +The publication uses locked Typst 0.15.1, existing Inter/Fira Code/Noto fonts and the project's managed vector/waveform packages. +The prototype brand is Rill; this identity does not establish an orderable or qualified silicon product. + +The project retains its Mulan PSL v2 license and third-party component/font licenses. Obtain the current source and license +inventory from #link("https://github.com/retroSoC/retroSoC")[the project repository]. +Contact: #link("mailto:"+doc.author_email)[#doc.author (#doc.author_email)]. Maintainer: #doc.maintainer. diff --git a/publications/datasheets/tiny/diagrams.typ b/publications/datasheets/tiny/diagrams.typ new file mode 100644 index 00000000..4365a9ab --- /dev/null +++ b/publications/datasheets/tiny/diagrams.typ @@ -0,0 +1,84 @@ +#import "@preview/cetz:0.5.2" as cetz +#import "@preview/bytefield:0.0.8" as bf +#import "style.typ": * + +#let diagram(id, body, caption) = block(width:100%,breakable:false)[ + #context metadata((kind:"tiny-diagram",id:id,page:here().page())) + #figure(body,caption:caption) +] +#let schematic(nodes, routes, height:90) = { + set text(font:"Inter",size:9pt,weight:"regular",fill:ink) + cetz.canvas(length:1mm,{ + import cetz.draw: rect, line, content + rect((0,0),(172,-height),stroke:none) + for path in routes { + line(..path.map(p=>(p.at(0),-p.at(1))),stroke:0.65pt+ink,mark:(end:"stealth")) + } + for node in nodes { + let (x,y,w,h,label)=node + rect((x,-y),(x+w,-y - h),fill:gray,stroke:0.6pt+ink) + content((x+w/2,-y - h/2),block(width:(w - 4)*1mm)[ + #set text(font:"Inter",size:9pt,weight:"regular") + #set par(leading:2pt,spacing:0pt) + #align(center,label) + ]) + } + }) +} +#let architecture() = diagram("tiny-architecture",schematic(( + (5,4,65,19,[Hazard3 · hart 0 \ RV32IMC · A disabled]), + (104,4,63,19,[JTAG / debug transport \ External TCK domain]), + (5,37,65,15,[AHB-Lite → AXI32 adapter]), + (104,37,63,15,[Four-channel DMA \ AXI32 master]), + (30,69,112,19,[Tiny AXI32 fabric \ One active transaction globally]), + (0,110,40,22,[128 KiB SRAM \ 32 × 4 KiB]), + (44,110,40,22,[XPI read path \ Flash alias / NOR]), + (88,110,40,22,[APB4 bridge \ 16 targets]), + (132,110,40,22,[Error responders \ DECERR / SLVERR]), +),( + ((104,13),(70,13)),((37,23),(37,37)), + ((37,52),(37,61),(60,61),(60,69)),((135,52),(135,61),(112,61),(112,69)), + ((45,88),(45,99),(20,99),(20,110)),((70,88),(70,103),(64,103),(64,110)), + ((103,88),(103,103),(108,103),(108,110)),((127,88),(127,99),(152,99),(152,110)), +),height:134),[Tiny Gen1 integration. System logic runs from the configured 24 MHz clock; JTAG is asynchronous.]) + +#let ip-diagram(entry) = { + let children=entry.nodes.slice(1) + let positions=if children.len()<=3 {((1,40,54,20),(59,40,54,20),(117,40,54,20))} + else {((5,39,68,20),(99,39,68,20),(5,76,68,20),(99,76,68,20))} + let nodes=((50,0,72,20,entry.nodes.first()),) + let routes=() + for (i,name) in children.enumerate() { + let (x,y,w,h)=positions.at(i) + nodes.push((x,y,w,h,name)) + // Control reaches each functional group independently; no invented FIFO-to-FIFO chain. + let branch=if children.len()<=3 or i < 2 {29} else {68} + routes.push(((86,20),(86,branch),(x+w/2,branch),(x+w/2,y))) + } + diagram("ip-"+entry.id,schematic(nodes,routes,height:if children.len()>3 {98} else {62}), + [#entry.title functional groups. Arrows show control reach, not every internal data wire or a cycle schedule.]) +} + +#let flow(id, items, caption) = { + let nodes=items.enumerate().map(((i,item))=>(16,i*23,140,16,item)) + let paths=range(items.len()-1).map(i=>((86,i*23+16),(86,(i+1)*23))) + diagram(id,schematic(nodes,paths,height:items.len()*23-5),caption) +} + +#let tcd-diagram() = { + let names=("next_ptr":"Next","source":"Source","destination":"Destination","byte_count":"Byte count", + "source_stride":"Src stride","destination_stride":"Dst stride","y_count":"Rows","reserved":"Rsvd", + "control":"Control","crc_expected":"CRC expect","crc_seed":"CRC seed","crc_result":"CRC result", + "status":"Status","bytes_done":"Bytes done","error_status":"Error","reserved_tail":"Reserved","reserved_tail2":"Reserved") + let fields=() + for field in data.tcd { + if calc.rem(field.offset,16)==0 {fields.push(bf.note(left)[#("0x"+upper(str(field.offset,base:16)))])} + fields.push(bf.bytes(field.bytes,fill:if field.role=="reserved" {gray} else if field.role=="HAL result" {rgb("#E7EFF6")} else {pale-gold})[#{names.at(field.name)}]) + } + diagram("dma-tcd",{ + set text(font:"Inter",size:9pt) + show: bf.bf-config.with(row-height:27pt,field-font-size:9pt,note-font-size:9pt,header-font-size:9pt,stroke:0.6pt+ink) + bf.bytefield(bpr:128,msb:right,pre:(36pt,),post:(), + bf.bitheader(0,[0],32,[4],64,[8],96,[12],numbers:none,angle:0deg,text-size:9pt),..fields) + },[DMA TCD: four 16-byte rows. Gold: configuration; blue: HAL result fields; gray: reserved.]) +} diff --git a/publications/datasheets/tiny/evidence.json b/publications/datasheets/tiny/evidence.json new file mode 100644 index 00000000..4822f65a --- /dev/null +++ b/publications/datasheets/tiny/evidence.json @@ -0,0 +1,29 @@ +{ + "status": "prototype", + "current_commit_reports": [], + "historical_source": "docs/ip/tiny-soc-verification.md", + "historical_date": "2026-09-25", + "boundary": "Repository-reported local results from an originally uncommitted implementation; raw matching artifacts are not supplied in this publication workspace. Not rerun or promoted to current-commit qualification.", + "records": [ + [ + "RTL and software", + "Repository records directed fabric/SYSCTRL tests and pin-level NOR firmware acceptance in Verilator/Icarus.", + "Reported historical functional evidence, not a new publication-run result." + ], + [ + "Netlist", + "Compact assembly SRAM/pad boot test is recorded; the full C acceptance netlist campaign remains incomplete.", + "Do not substitute the compact netlist test for complete SDK acceptance." + ], + [ + "IHP130 STA", + "Recorded setup WNS -455.18 ns and TNS -13,049,600 ns; dominant reset-distribution path.", + "24 MHz is a functional target, not timing-qualified operation." + ], + [ + "Physical and silicon", + "No matching place/route, PVT/MMMC, CDC/RDC signoff, board characterization or silicon/power report.", + "No numerical electrical, package, thermal or safety qualification claimed." + ] + ] +} diff --git a/publications/datasheets/tiny/ip-reference.typ b/publications/datasheets/tiny/ip-reference.typ new file mode 100644 index 00000000..3ce58a05 --- /dev/null +++ b/publications/datasheets/tiny/ip-reference.typ @@ -0,0 +1,156 @@ +#import "style.typ": * +#import "diagrams.typ": ip-diagram +#import "waveforms.typ": timing +#let inline(value) = { + // A deliberately limited inline grammar: explicit strong spans and raw code. + // Code is opaque, including any literal asterisks it contains. + let bold = false + for (i,part) in value.split("`").enumerate() { + if calc.rem(i,2)==1 { code(part) } else { + for (j,piece) in part.split("**").enumerate() { + if j>0 { bold = not bold } + if bold { strong(piece) } else { piece } + } + } + } +} + +#let subhead(ip, name, depth) = [ + #{ + show heading: it => heading-layout(it,before:rhythm.minor-before,after:rhythm.minor-after) + heading(level:depth+1,numbering:none,outlined:false,bookmarked:true,name) + }#label("detail-"+ip+"-"+lower(name).replace(" ","-")) +] + +#let prose-blocks(ip, section-title, blocks) = { + for (n,item) in blocks.enumerate() { + if item.kind=="heading" { + minor-title(inline(item.text)) + } else if item.kind=="code" { + if item.language not in ("mermaid","dot") { + code-block(raw(item.text,block:true),breakable:true) + } + } else if item.kind=="table" { + ds-table(ip+"-"+str(n),section-title, + item.headers.map(inline),item.rows.map(r=>r.map(inline))) + } else if item.kind=="list" { + let bodies=item.items.enumerate().map(((index,entry))=>{ + let content=prose-blocks(ip+"-"+str(n)+"-"+str(index),section-title,entry.blocks) + if item.ordered {enum.item(entry.number,content)} else {list.item(content)} + }) + if item.ordered {enum(..bodies)} else {list(..bodies)} + } else { par(inline(item.text)) } + } +} + +#let prose-sections(ip, sections, depth) = { + for (index,section) in sections.enumerate() { + if sections.len()>1 { minor-title(section.title) } + prose-blocks(ip+"-"+str(index),section.title,section.blocks) + } +} + +#let bit-layout(register) = { + let fields=register.fields.sorted(key:f=>-f.msb) + set text(size:9pt) + set par(leading:rhythm.small-leading,spacing:0pt) + let cells = () + for high in (31,15) { + cells += range(high,high - 16,step:-1).map(b=>align(center,str(b))) + cells += fields.enumerate().filter(((n,f))=>f.lsb<=high and f.msb>=high - 15).map(((n,f))=>{ + let span=calc.min(f.msb,high)-calc.max(f.lsb,high - 15)+1 + let text=if f.name.len()<=span*4 {f.name} else {"F"+str(n+1)} + table.cell(colspan:span,fill:if f.name=="Reserved" {gray} else {pale-gold},align(center,text)) + }) + } + table(columns:range(16).map(n=>1fr), + stroke:table-stroke,inset:rhythm.bits-inset,..cells) +} + +#let register-section(family, depth) = { + let reference=data.registers.at(family) + subhead(family,"Register Summary",depth) + [Offsets are byte offsets within the named register group. Repeated groups use the base, + stride and instance range below. Access descriptions include register-specific restrictions. + A numeric reset identifies stored or fixed state. Dynamic marks live producer/integration + state; apply the domain, validity and snapshot rules before consuming it. Not retained marks + a command or data port, rather than a persistent configuration word.] + for group in reference.groups { + let registers=reference.registers.filter(r=>r.group==group.id) + if registers.len()==0 { continue } + minor-title(group.title) + if group.count>1 { + par([Instance offset: #code("0x"+str(group.base,base:16)) + n × #code("0x"+str(group.stride,base:16)), + n = 0…#(group.count - 1). Local offsets below are added to this instance offset.]) + } + { + // Register-name links keep their blue color and destination, without decoration. + show underline: omit-link-underline + ds-table(family+"-summary-"+group.id,group.title, + ([Offset],[Register],[Access],[Reset],[Description]), + registers.map(r=>(code("0x"+str(r.offset,base:16)),link(label("reg-"+family+"-"+r.key),code(r.name)),r.access,inline(r.reset),inline(r.description))), + widths:(0.55fr,1.6fr,0.6fr,1.1fr,2.6fr)) + } + } + subhead(family,"Register Description",depth) + [Bit-layout cells refer to the numbered field rows below each diagram. Reserved bits must + be handled as specified by the register; register access checks still apply to the full word.] + for register in reference.registers { + context metadata((kind:"tiny-register",family:family,key:register.key,page:here().page())) + block(above:rhythm.register-before,below:rhythm.metadata-after,breakable:false,sticky:true)[ + #show heading: it => heading-layout(it,before:0pt,after:rhythm.register-after) + #set text(size:9pt) + #set par(leading:rhythm.small-leading,spacing:rhythm.small-spacing) + #heading(level:depth+2,numbering:none,outlined:false,bookmarked:true,register.name) + #label("reg-"+family+"-"+register.key) + #text(9pt,fill:muted)[#register.group · offset #code("0x"+str(register.offset,base:16)) · #register.access · reset #inline(register.reset)] + #linebreak() + #source(register.source,title:"RTL definition",line:register.line) + #if register.c_source!=none { [ · ]; source(register.c_source,title:"C ABI / HAL") } + ] + par(inline(register.description)) + block(breakable:false,above:rhythm.bits-space,below:rhythm.bits-space,bit-layout(register)) + let fields=register.fields.sorted(key:f=>-f.msb) + ds-table("fields-"+family+"-"+register.key,[#register.name field descriptions], + ([\#],[Bits],[Field],[Reset],[Description]), + fields.enumerate().map(((n,f))=>("F"+str(n+1),str(f.msb)+if f.msb!=f.lsb {":"+str(f.lsb)} else {""},code(f.name),inline(f.reset),inline(f.description))), + widths:(0.25fr,0.5fr,1.1fr,0.75fr,2.3fr)) + if register.at("notes",default:"")!="" { par(inline(register.notes)) } + } +} + + +#let reference(entry) = { + pagebreak(weak:true) + context metadata((kind:"ip-start",id:entry.id,page:here().page())) + [#heading(level:3,entry.title)#label(entry.id)] + ip(entry.id) + minor-title("Features and functional organization") + list(..entry.features.map(inline)) + ip-diagram(entry) + minor-title("Functional description and integration boundary") + for paragraph in entry.paragraphs {par(inline(paragraph))} + minor-title("Protocol and representative timing") + [The common AXI/APB rules in @tiny-bus and this instance's access rules both apply. + *Example waveforms show ordering and stable handshakes, not guaranteed cycle latency or electrical timing.*] + timing(if entry.family in data.waveforms {entry.family} else {"apb4"},[#entry.title representative transaction.],instance:entry.id) + if entry.id=="uart1" { + minor-title("Shared register reference") + [Use the @uart0 register definition with the UART1 base and IRQ from this chapter. + *Do not use the UART0 convenience HAL or DMA route as a UART1 binding.*] + } else {register-section(entry.family,3)} + minor-title("Software sequence and recovery") + enum(..entry.steps.map(inline)) + if entry.id!="uart1" { + let api=data.apis.at(entry.family) + if api.len()>0 {ds-table("api-"+entry.id,[#entry.title selected SDK interfaces],([Function],[Declaration]), + api.map(a=>(code(a.name),code(a.signature))),widths:(1fr,3fr))} + if entry.family in data.examples { + code-block(raw(data.examples.at(entry.family),block:true,lang:"c"),breakable:true) + text(9pt,fill:muted)[Syntax-checked API fragment; clocks, pins, memory and arguments must already be valid. + Submission is not necessarily transfer completion.] + } + } + source-note(data.registers.at(entry.family).document,title:"Register and detailed interface contract") + context metadata((kind:"ip-end",id:entry.id,page:here().page())) +} diff --git a/publications/datasheets/tiny/register-annotations.json b/publications/datasheets/tiny/register-annotations.json new file mode 100644 index 00000000..f47d41af --- /dev/null +++ b/publications/datasheets/tiny/register-annotations.json @@ -0,0 +1,2767 @@ +{ + "xpi": { + "main.ID": { + "access": "RO" + }, + "main.VERSION": { + "access": "RO" + }, + "main.CAPABILITY": { + "access": "RO" + }, + "main.CTRL": { + "access": "RW", + "reset": "1", + "description": "Global controller enable. Configure protected slot/LUT state only in the allowed idle/disabled state.", + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "ENABLE", + "description": "Enable the XPI controller.", + "reset": "1", + "expression": "XPI_CTRL_ENABLE" + }, + { + "lsb": 1, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "0", + "expression": "reserved" + } + ] + }, + "main.STATUS": { + "access": "RO" + }, + "main.COMMAND": { + "access": "WO", + "fields": [ + { + "name": "INDIRECT_START", + "lsb": 0, + "msb": 0, + "description": "Start the configured indirect sequence.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "POLL_START", + "lsb": 1, + "msb": 1, + "description": "Start automatic status polling.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "ABORT", + "lsb": 2, + "msb": 2, + "description": "Abort the current command and release chip select safely.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 3, + "msb": 31, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + } + ], + "reset": "Not retained" + }, + "main.ERROR_STATE": { + "access": "RW1C", + "fields": [ + { + "name": "CODE", + "lsb": 0, + "msb": 3, + "description": "First XPI error code.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 4, + "msb": 30, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + }, + { + "name": "VALID", + "lsb": 31, + "msb": 31, + "description": "Sticky first-error valid; write one to clear the snapshot.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + } + ], + "reset": "0" + }, + "main.ERROR_ADDR": { + "access": "RO" + }, + "main.ERROR_INFO": { + "access": "RO", + "fields": [ + { + "name": "CODE", + "lsb": 0, + "msb": 3, + "description": "Captured error code.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "SLOT", + "lsb": 4, + "msb": 5, + "description": "Captured chip-select slot.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "PC", + "lsb": 6, + "msb": 8, + "description": "Captured LUT program counter.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 9, + "msb": 31, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + } + ], + "reset": "0" + }, + "main.INTR_STATE": { + "access": "RW1C" + }, + "main.INTR_ENABLE": { + "access": "RW" + }, + "main.INTR_STATUS": { + "access": "RO" + }, + "main.INTR_TEST": { + "access": "WO", + "fields": [ + { + "name": "INDIRECT_DONE", + "lsb": 0, + "msb": 0, + "description": "Write one to inject indirect done.", + "reset": "Not retained", + "expression": "XPI_INTR_INDIRECT_DONE" + }, + { + "name": "POLL_MATCH", + "lsb": 1, + "msb": 1, + "description": "Write one to inject poll match.", + "reset": "Not retained", + "expression": "XPI_INTR_POLL_MATCH" + }, + { + "name": "TX_WATERMARK", + "lsb": 2, + "msb": 2, + "description": "Write one to inject tx watermark.", + "reset": "Not retained", + "expression": "XPI_INTR_TX_WATERMARK" + }, + { + "name": "RX_WATERMARK", + "lsb": 3, + "msb": 3, + "description": "Write one to inject rx watermark.", + "reset": "Not retained", + "expression": "XPI_INTR_RX_WATERMARK" + }, + { + "name": "AXI_ERROR", + "lsb": 4, + "msb": 4, + "description": "Write one to inject axi error.", + "reset": "Not retained", + "expression": "XPI_INTR_AXI_ERROR" + }, + { + "name": "SEQUENCE_ERROR", + "lsb": 5, + "msb": 5, + "description": "Write one to inject sequence error.", + "reset": "Not retained", + "expression": "XPI_INTR_SEQUENCE_ERROR" + }, + { + "name": "TIMEOUT", + "lsb": 6, + "msb": 6, + "description": "Write one to inject timeout.", + "reset": "Not retained", + "expression": "XPI_INTR_TIMEOUT" + }, + { + "name": "ABORT_DONE", + "lsb": 7, + "msb": 7, + "description": "Write one to inject abort done.", + "reset": "Not retained", + "expression": "XPI_INTR_ABORT_DONE" + }, + { + "name": "Reserved", + "lsb": 8, + "msb": 31, + "description": "Reserved; write zero.", + "reset": "0", + "expression": "reserved" + } + ], + "reset": "Not retained" + }, + "main.DMA_CTRL": { + "access": "RW", + "fields": [ + { + "name": "TX_ENABLE", + "lsb": 0, + "msb": 0, + "description": "Enable TX DMA request pacing.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "RX_ENABLE", + "lsb": 1, + "msb": 1, + "description": "Enable RX DMA request pacing.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 2, + "msb": 31, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + } + ], + "reset": "0" + }, + "main.FIFO_CTRL": { + "access": "RW", + "reset": "0x00001010", + "fields": [ + { + "name": "TX_WATERMARK", + "lsb": 0, + "msb": 7, + "description": "TX low-watermark threshold.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "RX_WATERMARK", + "lsb": 8, + "msb": 15, + "description": "RX high-watermark threshold.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "TX_FLUSH", + "lsb": 16, + "msb": 16, + "description": "Write-one TX FIFO flush pulse; reads as zero.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "RX_FLUSH", + "lsb": 17, + "msb": 17, + "description": "Write-one RX FIFO flush pulse; reads as zero.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 18, + "msb": 31, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + } + ] + }, + "main.FIFO_STATUS": { + "access": "RO" + }, + "main.TXDATA": { + "access": "WO", + "fields": [ + { + "name": "DATA", + "lsb": 0, + "msb": 31, + "description": "Word pushed into the transmit FIFO using the documented PIO packing.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + } + ], + "reset": "Not retained" + }, + "main.RXDATA": { + "access": "RO / pop" + }, + "main.INDIRECT_ADDR": { + "access": "RW" + }, + "main.INDIRECT_COUNT": { + "access": "RW" + }, + "main.INDIRECT_CFG": { + "access": "RW", + "fields": [ + { + "lsb": 0, + "msb": 1, + "name": "INDIRECT_SLOT", + "description": "Indirect slot.", + "reset": "0x0", + "expression": "s_indirect_cfg_q[1:0]" + }, + { + "lsb": 2, + "msb": 3, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0x0", + "expression": "s_indirect_cfg_q" + }, + { + "lsb": 4, + "msb": 7, + "name": "INDIRECT_SEQ", + "description": "Indirect seq.", + "reset": "0x0", + "expression": "s_indirect_cfg_q[7:4]" + }, + { + "lsb": 8, + "msb": 31, + "name": "Reserved", + "description": "Reads zero.", + "reset": "0x0", + "expression": "24'd0" + } + ] + }, + "main.POLL_CFG": { + "access": "RW", + "fields": [ + { + "lsb": 0, + "msb": 1, + "name": "POLL_SLOT", + "description": "Poll slot.", + "reset": "0x0", + "expression": "s_poll_cfg_q[1:0]" + }, + { + "lsb": 2, + "msb": 3, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0x0", + "expression": "s_poll_cfg_q" + }, + { + "lsb": 4, + "msb": 7, + "name": "POLL_SEQ", + "description": "Poll seq.", + "reset": "0x0", + "expression": "s_poll_cfg_q[7:4]" + }, + { + "lsb": 8, + "msb": 31, + "name": "Reserved", + "description": "Reads zero.", + "reset": "0x0", + "expression": "24'd0" + } + ] + }, + "main.POLL_MASK": { + "access": "RW" + }, + "main.POLL_MATCH": { + "access": "RW" + }, + "main.POLL_INTERVAL": { + "access": "RW" + }, + "main.POLL_TIMEOUT": { + "access": "RW" + }, + "main.PERF_CTRL": { + "access": "RW" + }, + "main.PERF_AXI_READ_BYTES": { + "access": "RO" + }, + "main.PERF_AXI_WRITE_BYTES": { + "access": "RO" + }, + "main.PERF_PHY_BYTES": { + "access": "RO" + }, + "main.PERF_COMMANDS": { + "access": "RO" + }, + "main.PERF_STALL_CYCLES": { + "access": "RO" + }, + "main.CONFIG_LOCK": { + "access": "RW", + "fields": [ + { + "name": "GLOBAL", + "lsb": 0, + "msb": 0, + "description": "Lock global configuration until reset.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "SLOTS", + "lsb": 1, + "msb": 4, + "description": "Lock slots 0 through 3 respectively.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "LUT", + "lsb": 5, + "msb": 5, + "description": "Lock LUT contents until reset.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 6, + "msb": 31, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + } + ], + "reset": "0" + }, + "slot.CTRL": { + "access": "RW", + "fields": [ + { + "name": "ENABLE", + "lsb": 0, + "msb": 0, + "description": "Enable this chip-select slot.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "MEMORY_ENABLE", + "lsb": 1, + "msb": 1, + "description": "Permit mapped reads through this slot.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "WRITE_ENABLE", + "lsb": 2, + "msb": 2, + "description": "Permit mapped writes at the controller frontend; product data-plane policy still applies.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "CPOL", + "lsb": 3, + "msb": 3, + "description": "Select SPI mode 3 when set; mode 0 when clear.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 4, + "msb": 31, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + } + ], + "reset": "slot 0: 0x3; slots 1-3: 0", + "description": "Per-chip-select ctrl." + }, + "slot.DEVICE_SIZE": { + "access": "RW", + "fields": [ + { + "name": "BYTES", + "lsb": 0, + "msb": 31, + "description": "Device/addressable span for this slot.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + } + ], + "reset": "slot 0: 0x01000000; slots 1-3: 0x04000000", + "description": "Per-chip-select device size." + }, + "slot.SEQ_CFG": { + "access": "RW", + "fields": [ + { + "name": "READ_SEQUENCE", + "lsb": 0, + "msb": 3, + "description": "Mapped-read LUT sequence index.", + "reset": "0x0", + "expression": "reviewed semantic field" + }, + { + "name": "WRITE_SEQUENCE", + "lsb": 4, + "msb": 7, + "description": "Mapped-write LUT sequence index.", + "reset": "0x0", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 8, + "msb": 31, + "description": "Reserved; preserve zero when writing.", + "reset": "0x0", + "expression": "reserved" + } + ], + "reset": "0", + "description": "Per-chip-select seq cfg." + }, + "slot.TIMING": { + "access": "RW", + "fields": [ + { + "name": "CLK_DIV", + "lsb": 0, + "msb": 7, + "description": "Serial clock divider field.", + "reset": "0x0", + "expression": "reviewed semantic field" + }, + { + "name": "CS_SETUP", + "lsb": 8, + "msb": 15, + "description": "Chip-select setup interval.", + "reset": "0x0", + "expression": "reviewed semantic field" + }, + { + "name": "CS_HOLD", + "lsb": 16, + "msb": 23, + "description": "Chip-select hold interval.", + "reset": "0x0", + "expression": "reviewed semantic field" + }, + { + "name": "CS_HIGH", + "lsb": 24, + "msb": 31, + "description": "Minimum deselected interval.", + "reset": "0x2", + "expression": "reviewed semantic field" + } + ], + "reset": "0x02000000", + "description": "Per-chip-select timing." + }, + "slot.TIMEOUT": { + "access": "RW", + "fields": [ + { + "name": "CYCLES", + "lsb": 0, + "msb": 31, + "description": "Nonzero operation timeout budget.", + "reset": "0x10000", + "expression": "reviewed semantic field" + } + ], + "reset": "0x00010000", + "description": "Per-chip-select timeout." + }, + "slot.BOUNDARY": { + "access": "RW", + "fields": [ + { + "name": "BYTES", + "lsb": 0, + "msb": 31, + "description": "Zero disables device-boundary splitting; otherwise a power of two from 4 bytes to 64 MiB.", + "reset": "0x0", + "expression": "reviewed semantic field" + } + ], + "reset": "0", + "description": "Per-chip-select boundary." + } + }, + "sram": { + "main.CAPABILITY": { + "fields": [ + { + "name": "PRESENT", + "lsb": 0, + "msb": 0, + "description": "SRAM is present.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "NATIVE_AXI4", + "lsb": 1, + "msb": 1, + "description": "Native AXI memory interface.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "BYTE_WRITE", + "lsb": 2, + "msb": 2, + "description": "Byte-write strobes supported.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "FIXED", + "lsb": 3, + "msb": 3, + "description": "Local SRAM supports FIXED; Tiny fabric admits only single-beat FIXED.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "INCR", + "lsb": 4, + "msb": 4, + "description": "Incrementing bursts supported within system limits.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "WRAP", + "lsb": 5, + "msb": 5, + "description": "Local SRAM capability only: Tiny fabric rejects WRAP requests.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "PERFORMANCE", + "lsb": 6, + "msb": 6, + "description": "Performance counters present.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "Reserved", + "lsb": 7, + "msb": 7, + "description": "Reads zero.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "MAX_BEATS", + "lsb": 8, + "msb": 15, + "description": "Local maximum 16 beats.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "DATA_BYTES", + "lsb": 16, + "msb": 23, + "description": "Four data bytes in the Tiny instance.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "Reserved", + "lsb": 24, + "msb": 31, + "description": "Reads zero.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + } + ], + "description": "Local SRAM capabilities, 16 maximum beats and four data bytes. The Tiny fabric imposes the narrower end-to-end transfer subset." + } + }, + "gpio": { + "user.DATA_IN": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Synchronized and filtered pin inputs.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "user.DATA_OUT": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Software output latch.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "user.OUT_SET": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomically set output-latch bits.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "user.OUT_CLEAR": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomically clear output-latch bits.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "user.OUT_TOGGLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomically toggle output-latch bits.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "user.INTR_STATE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Sticky raw interrupt state.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "user.INTR_STATUS": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. INTR_STATE & INTR_ENABLE.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "user.INTR_ENABLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Per-pin interrupt enable.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "user.INTR_ENABLE_SET": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomically set interrupt-enable bits.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "user.INTR_ENABLE_CLEAR": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomically clear interrupt-enable bits.", + "reset": "0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.DATA_IN": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Synchronized and filtered inputs.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.DATA_OUT": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Software output latch.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.OUT_SET": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomic output set.", + "reset": "-", + "expression": "32-pin bitmap" + } + ] + }, + "admin.OUT_CLEAR": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomic output clear.", + "reset": "-", + "expression": "32-pin bitmap" + } + ] + }, + "admin.OUT_TOGGLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomic output toggle.", + "reset": "-", + "expression": "32-pin bitmap" + } + ] + }, + "admin.OUTPUT_ENABLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Software output-enable latch.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.OE_SET": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomic output-enable set.", + "reset": "-", + "expression": "32-pin bitmap" + } + ] + }, + "admin.OE_CLEAR": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomic output-enable clear.", + "reset": "-", + "expression": "32-pin bitmap" + } + ] + }, + "admin.OE_TOGGLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Atomic output-enable toggle.", + "reset": "-", + "expression": "32-pin bitmap" + } + ] + }, + "admin.OPEN_DRAIN": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Drive zero for output low and release for output high.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.INPUT_CMOS": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Select the PDK CMOS input characteristic when supported.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.PULL_UP": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Enable pad pull-up when supported.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.PULL_DOWN": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Enable pad pull-down when supported.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.ALT_ENABLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Select an alternate function instead of software output.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.ALT_SELECT": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Select ALT1 when set and ALT0 when clear.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.USER_SELECT": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Select user-IP pad ownership.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.USER_LOCK": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Permanently lock USER_SELECT bits until reset.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.USER_STATUS": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Active user ownership after the handoff guard cycle.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.USER_ACCESS_MASK": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Permit user-window data and interrupt bits.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.INTR_RISE_ENABLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Rising-edge event selection.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.INTR_FALL_ENABLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Falling-edge event selection.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.INTR_HIGH_ENABLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. High-level event selection.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.INTR_LOW_ENABLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Low-level event selection.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.INTR_ENABLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Per-pin interrupt output enable.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.INTR_STATE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Sticky raw interrupt state. Events win over clear.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.INTR_STATUS": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Enabled interrupt state.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.INTR_TEST": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Write-one software interrupt test.", + "reset": "-", + "expression": "32-pin bitmap" + } + ] + }, + "admin.FILTER_ENABLE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Enable the digital stability filter per pin.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + }, + "admin.CONFIG_LOCK": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "PIN[31:0]", + "description": "Bit n applies to GPIO n. Permanently lock per-pin configuration until reset.", + "reset": "0x0", + "expression": "32-pin bitmap" + } + ] + } + }, + "dma": { + "main.GLOBAL_CTRL": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "RESET", + "description": "Reset.", + "reset": "Register reset applies", + "expression": "`APB4_DMA__GLOBAL_CTRL_RESET" + }, + { + "lsb": 1, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + }, + "ch.CTRL": { + "fields": [ + { + "name": "START", + "lsb": 0, + "msb": 0, + "description": "Write one to request start.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "SUSPEND", + "lsb": 1, + "msb": 1, + "description": "Write one to request suspend.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "RESUME", + "lsb": 2, + "msb": 2, + "description": "Write one to request resume.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "ABORT", + "lsb": 3, + "msb": 3, + "description": "Write one to request abort.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "RESET", + "lsb": 4, + "msb": 4, + "description": "Write one to request reset.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 5, + "msb": 31, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + } + ], + "access": "WO", + "reset": "Not retained" + }, + "main.CAPABILITY": { + "fields": [ + { + "name": "DESCRIPTOR", + "lsb": 0, + "msb": 0, + "description": "Direct and linked-descriptor engine present.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "Reserved", + "lsb": 1, + "msb": 7, + "description": "Reads zero.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "CHANNELS", + "lsb": 8, + "msb": 15, + "description": "Four channel contexts in Tiny.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "DATA_WIDTH", + "lsb": 16, + "msb": 23, + "description": "32-bit transfer data width.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "MAX_BURST_FIELD", + "lsb": 24, + "msb": 27, + "description": "The 4-bit cast of MaxBurstBeats=16 reads zero. This is an encoding limitation, not a zero-beat engine.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "STREAM_COUNT", + "lsb": 28, + "msb": 30, + "description": "Zero: Tiny disables stream endpoints.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "Reserved", + "lsb": 31, + "msb": 31, + "description": "Reads zero.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + } + ], + "description": "Tiny reads 0x00200401. The maximum-burst field truncates 16 to zero; the top-level parameter and SDK limit remain 16 beats. Do not infer the burst limit solely from this field." + } + }, + "timer": { + "main.INTR_TEST": { + "fields": [ + { + "name": "MASK", + "lsb": 0, + "msb": 2, + "description": "Write-one mask using the corresponding event/interrupt bit assignments.", + "reset": "Register reset applies", + "expression": "reviewed field" + }, + { + "name": "Reserved", + "lsb": 3, + "msb": 31, + "description": "Reserved; write zero.", + "reset": "0", + "expression": "reserved" + } + ], + "access": "WO", + "reset": "Not retained" + }, + "main.CTRL": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "ENABLE", + "description": "Enable.", + "reset": "0x0", + "expression": "s_ctrl_q[`TIMER_CTRL_ENABLE]" + }, + { + "lsb": 1, + "msb": 2, + "name": "MODE", + "description": "Mode.", + "reset": "0x0", + "expression": "s_ctrl_q[2:1]" + }, + { + "lsb": 3, + "msb": 3, + "name": "DIRECTION", + "description": "Direction.", + "reset": "0x0", + "expression": "s_ctrl_q[`TIMER_CTRL_DIRECTION]" + }, + { + "lsb": 4, + "msb": 4, + "name": "DEBUG_FREEZE_ENABLE", + "description": "Debug freeze enable.", + "reset": "0x0", + "expression": "s_ctrl_q[`TIMER_CTRL_DEBUG_FREEZE]" + }, + { + "lsb": 5, + "msb": 5, + "name": "COMPARE0_ENABLE", + "description": "Compare0 enable.", + "reset": "0x0", + "expression": "s_ctrl_q[`TIMER_CTRL_COMPARE0_ENABLE]" + }, + { + "lsb": 6, + "msb": 6, + "name": "COMPARE1_ENABLE", + "description": "Compare1 enable.", + "reset": "0x0", + "expression": "s_ctrl_q[`TIMER_CTRL_COMPARE1_ENABLE]" + }, + { + "lsb": 7, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0x0", + "expression": "s_ctrl_q" + } + ] + } + }, + "pwm": { + "main.COMMAND": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "UPDATE", + "description": "Update.", + "reset": "Register reset applies", + "expression": "`PWM_COMMAND_UPDATE_MASK" + }, + { + "lsb": 1, + "msb": 1, + "name": "SYNC", + "description": "Sync.", + "reset": "Register reset applies", + "expression": "`PWM_COMMAND_SYNC_MASK" + }, + { + "lsb": 2, + "msb": 2, + "name": "FAULT_TEST", + "description": "Fault test.", + "reset": "Register reset applies", + "expression": "`PWM_COMMAND_FAULT_TEST_MASK" + }, + { + "lsb": 3, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + }, + "main.INTR_TEST": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "TIMER0_ZERO", + "description": "Timer0 zero.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_TIMER0_ZERO_MASK" + }, + { + "lsb": 1, + "msb": 1, + "name": "TIMER1_ZERO", + "description": "Timer1 zero.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_TIMER1_ZERO_MASK" + }, + { + "lsb": 2, + "msb": 2, + "name": "TIMER0_PERIOD", + "description": "Timer0 period.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_TIMER0_PERIOD_MASK" + }, + { + "lsb": 3, + "msb": 3, + "name": "TIMER1_PERIOD", + "description": "Timer1 period.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_TIMER1_PERIOD_MASK" + }, + { + "lsb": 4, + "msb": 4, + "name": "TIMER0_UPDATE", + "description": "Timer0 update.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_TIMER0_UPDATE_MASK" + }, + { + "lsb": 5, + "msb": 5, + "name": "TIMER1_UPDATE", + "description": "Timer1 update.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_TIMER1_UPDATE_MASK" + }, + { + "lsb": 6, + "msb": 6, + "name": "FADE0_DONE", + "description": "Fade0 done.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_FADE0_DONE_MASK" + }, + { + "lsb": 7, + "msb": 7, + "name": "FADE1_DONE", + "description": "Fade1 done.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_FADE1_DONE_MASK" + }, + { + "lsb": 8, + "msb": 8, + "name": "FADE2_DONE", + "description": "Fade2 done.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_FADE2_DONE_MASK" + }, + { + "lsb": 9, + "msb": 9, + "name": "FADE3_DONE", + "description": "Fade3 done.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_FADE3_DONE_MASK" + }, + { + "lsb": 10, + "msb": 10, + "name": "FAULT", + "description": "Fault.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_FAULT_MASK" + }, + { + "lsb": 11, + "msb": 11, + "name": "CAPTURE0", + "description": "Capture0.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_CAPTURE0_MASK" + }, + { + "lsb": 12, + "msb": 12, + "name": "CAPTURE1", + "description": "Capture1.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_CAPTURE1_MASK" + }, + { + "lsb": 13, + "msb": 13, + "name": "CAPTURE0_OVERFLOW", + "description": "Capture0 overflow.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_CAPTURE0_OVERFLOW_MASK" + }, + { + "lsb": 14, + "msb": 14, + "name": "CAPTURE1_OVERFLOW", + "description": "Capture1 overflow.", + "reset": "Register reset applies", + "expression": "`PWM_INTR_CAPTURE1_OVERFLOW_MASK" + }, + { + "lsb": 15, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + }, + "main.FAULT_CLEAR": { + "fields": [ + { + "name": "CLEAR", + "lsb": 0, + "msb": 0, + "description": "Write one to clear the one-shot fault latch when permitted by fault policy.", + "reset": "Register reset applies", + "expression": "reviewed field" + }, + { + "name": "Reserved", + "lsb": 1, + "msb": 31, + "description": "Reserved; write zero.", + "reset": "0", + "expression": "reserved" + } + ], + "access": "WO", + "reset": "Not retained" + }, + "main.CTRL": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "ENABLE", + "description": "Enable.", + "reset": "0x0", + "expression": "`PWM_CTRL_ENABLE_MASK" + }, + { + "lsb": 1, + "msb": 1, + "name": "DEBUG_FREEZE", + "description": "Debug freeze.", + "reset": "0x0", + "expression": "`PWM_CTRL_DEBUG_FREEZE_MASK" + }, + { + "lsb": 2, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0x0", + "expression": "s_ctrl_q" + } + ] + }, + "main.FAULT_STATUS": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "RAW", + "description": "Raw fault input.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 1, + "msb": 1, + "name": "SYNCHRONIZED", + "description": "Synchronized active-polarity fault.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 2, + "msb": 2, + "name": "FILTERED", + "description": "Fault after digital filtering.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 3, + "msb": 3, + "name": "LATCHED", + "description": "One-shot fault latch.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 4, + "msb": 4, + "name": "KILL", + "description": "Fault currently forces safe output values.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 5, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + } + ], + "review_source": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "review_notes": "Reviewed against the pinned implementation: explicit slices, write masks and consumer use; 2026-09-06." + }, + "main.OUTPUT_STATUS": { + "fields": [ + { + "lsb": 0, + "msb": 3, + "name": "OUTPUT", + "description": "Four driven PWM values.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 4, + "msb": 7, + "name": "OUTPUT_ENABLE", + "description": "Four output-enable values.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 8, + "msb": 11, + "name": "RAW_CHANNEL", + "description": "Raw channel waveform values.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 12, + "msb": 15, + "name": "DEADTIME_OUTPUT", + "description": "Complementary/dead-time output values.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 16, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + } + ], + "review_source": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "review_notes": "Reviewed against the pinned implementation: explicit slices, write masks and consumer use; 2026-09-06." + }, + "main.CAPTURE_STATUS": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "ENABLE", + "description": "Capture timebase enabled.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 1, + "msb": 2, + "name": "EMPTY", + "description": "One empty bit per capture FIFO.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 3, + "msb": 4, + "name": "FULL", + "description": "One full bit per capture FIFO.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 5, + "msb": 6, + "name": "WATERMARK", + "description": "One watermark indication per capture FIFO.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 7, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + } + ], + "review_source": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "review_notes": "Reviewed against the pinned implementation: explicit slices, write masks and consumer use; 2026-09-06." + }, + "main.CAPTURE0_CTRL": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "ENABLE", + "description": "Enable this capture channel.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 1, + "msb": 1, + "name": "RISE", + "description": "Capture rising edges.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 2, + "msb": 2, + "name": "FALL", + "description": "Capture falling edges.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 3, + "msb": 3, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 4, + "msb": 7, + "name": "FILTER", + "description": "Required stable input count.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 8, + "msb": 10, + "name": "WATERMARK", + "description": "FIFO interrupt threshold; zero is interpreted as one. FIFO depth is four.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 11, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + } + ], + "review_source": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv", + "review_notes": "Reviewed against the pinned implementation: explicit slices, write masks and consumer use; 2026-09-06.", + "reset": "0" + }, + "main.CAPTURE0_STATUS": { + "fields": [ + { + "lsb": 0, + "msb": 2, + "name": "LEVEL", + "description": "Number of timestamps held in the FIFO.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 3, + "msb": 3, + "name": "EMPTY", + "description": "FIFO contains no timestamp.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 4, + "msb": 4, + "name": "FULL", + "description": "FIFO is full.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 5, + "msb": 5, + "name": "WATERMARK", + "description": "Enabled channel has reached its watermark.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 6, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + } + ], + "review_source": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "review_notes": "Reviewed against the pinned implementation: explicit slices, write masks and consumer use; 2026-09-06." + }, + "main.CAPTURE1_CTRL": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "ENABLE", + "description": "Enable this capture channel.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 1, + "msb": 1, + "name": "RISE", + "description": "Capture rising edges.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 2, + "msb": 2, + "name": "FALL", + "description": "Capture falling edges.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 3, + "msb": 3, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 4, + "msb": 7, + "name": "FILTER", + "description": "Required stable input count.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 8, + "msb": 10, + "name": "WATERMARK", + "description": "FIFO interrupt threshold; zero is interpreted as one. FIFO depth is four.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + }, + { + "lsb": 11, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv" + } + ], + "review_source": "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv", + "review_notes": "Reviewed against the pinned implementation: explicit slices, write masks and consumer use; 2026-09-06.", + "reset": "0" + }, + "main.CAPTURE1_STATUS": { + "fields": [ + { + "lsb": 0, + "msb": 2, + "name": "LEVEL", + "description": "Number of timestamps held in the FIFO.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 3, + "msb": 3, + "name": "EMPTY", + "description": "FIFO contains no timestamp.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 4, + "msb": 4, + "name": "FULL", + "description": "FIFO is full.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 5, + "msb": 5, + "name": "WATERMARK", + "description": "Enabled channel has reached its watermark.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + }, + { + "lsb": 6, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv" + } + ], + "review_source": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "review_notes": "Reviewed against the pinned implementation: explicit slices, write masks and consumer use; 2026-09-06." + }, + "channel.ACTION": { + "fields": [ + { + "lsb": 0, + "msb": 1, + "name": "ZERO", + "description": "0: hold; 1: low; 2: high; 3: toggle on this event.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv" + }, + { + "lsb": 2, + "msb": 3, + "name": "PERIOD", + "description": "0: hold; 1: low; 2: high; 3: toggle on this event.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv" + }, + { + "lsb": 4, + "msb": 5, + "name": "PHASE_UP", + "description": "0: hold; 1: low; 2: high; 3: toggle on this event.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv" + }, + { + "lsb": 6, + "msb": 7, + "name": "DUTY_UP", + "description": "0: hold; 1: low; 2: high; 3: toggle on this event.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv" + }, + { + "lsb": 8, + "msb": 9, + "name": "PHASE_DOWN", + "description": "0: hold; 1: low; 2: high; 3: toggle on this event.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv" + }, + { + "lsb": 10, + "msb": 11, + "name": "DUTY_DOWN", + "description": "0: hold; 1: low; 2: high; 3: toggle on this event.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv" + }, + { + "lsb": 12, + "msb": 13, + "name": "SYNC", + "description": "0: hold; 1: low; 2: high; 3: toggle on this event.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv" + }, + { + "lsb": 14, + "msb": 15, + "name": "FADE_DONE", + "description": "0: hold; 1: low; 2: high; 3: toggle on this event.", + "reset": "Register reset applies", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv" + }, + { + "lsb": 16, + "msb": 31, + "name": "Reserved", + "description": "No defined software function. Preserve zero when writing.", + "reset": "0", + "expression": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv" + } + ], + "review_source": "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv", + "review_notes": "Reviewed against the pinned implementation: explicit slices, write masks and consumer use; 2026-09-06.", + "reset": "0" + } + }, + "rtc": { + "main.COMMAND": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + }, + { + "lsb": 1, + "msb": 1, + "name": "STATUS_DONE", + "description": "Status done.", + "reset": "Register reset applies", + "expression": "`RTC_COMMAND_STATUS_DONE_MASK" + }, + { + "lsb": 2, + "msb": 2, + "name": "STATUS_ERROR", + "description": "Status error.", + "reset": "Register reset applies", + "expression": "`RTC_COMMAND_STATUS_ERROR_MASK" + }, + { + "lsb": 3, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + }, + "main.EVENT_CLEAR": { + "fields": [ + { + "name": "MASK", + "lsb": 0, + "msb": 4, + "description": "Write-one mask using the corresponding event/interrupt bit assignments.", + "reset": "Register reset applies", + "expression": "reviewed field" + }, + { + "name": "Reserved", + "lsb": 5, + "msb": 31, + "description": "Reserved; write zero.", + "reset": "0", + "expression": "reserved" + } + ], + "access": "WO", + "reset": "Not retained" + }, + "main.EVENT_TEST": { + "fields": [ + { + "name": "MASK", + "lsb": 0, + "msb": 4, + "description": "Write-one mask using the corresponding event/interrupt bit assignments.", + "reset": "Register reset applies", + "expression": "reviewed field" + }, + { + "name": "Reserved", + "lsb": 5, + "msb": 31, + "description": "Reserved; write zero.", + "reset": "0", + "expression": "reserved" + } + ], + "access": "WO", + "reset": "Not retained" + }, + "main.CALIB_PPM": { + "fields": [ + { + "name": "PPM", + "lsb": 0, + "msb": 15, + "description": "Signed two-complement calibration in parts per million; supported interval -488 to +488.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "SIGN", + "lsb": 16, + "msb": 31, + "description": "Sign extension of bit 15 on read.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + } + ], + "access": "RW", + "reset": "0" + }, + "main.CTRL": { + "reset": "0" + }, + "main.TIME_LOAD_LO": { + "reset": "0" + }, + "main.TIME_LOAD_HI": { + "reset": "0" + }, + "main.TIME_LOAD_SUBSEC": { + "reset": "0" + }, + "main.ALARM0_TIME_LO": { + "reset": "0" + }, + "main.ALARM0_TIME_HI": { + "reset": "0" + }, + "main.ALARM0_SUBSEC": { + "reset": "0" + }, + "main.ALARM1_TIME_LO": { + "reset": "0" + }, + "main.ALARM1_TIME_HI": { + "reset": "0" + }, + "main.ALARM1_SUBSEC": { + "reset": "0" + }, + "main.ALARM_ENABLE": { + "reset": "0" + }, + "main.PERIOD_RELOAD": { + "reset": "0" + }, + "main.PERIOD_CTRL": { + "reset": "0" + }, + "main.INTR_ENABLE": { + "reset": "0" + }, + "main.WAKE_ENABLE": { + "reset": "0" + }, + "main.SECOND_CYCLES": { + "reset": "18432000", + "notes": "Reset comes from the RTC_CLOCK_HZ integration parameter; it is not a 32.768 kHz oscillator assumption." + }, + "main.INTR_STATE": { + "access": "RO" + }, + "main.WAKE_STATE": { + "access": "RO" + } + }, + "wdg": { + "main.CTRL": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "START", + "description": "Start.", + "reset": "Register reset applies", + "expression": "`WDG_CTRL_START_MASK" + }, + { + "lsb": 1, + "msb": 1, + "name": "SNAPSHOT", + "description": "Snapshot.", + "reset": "Register reset applies", + "expression": "`WDG_CTRL_SNAPSHOT_MASK" + }, + { + "lsb": 2, + "msb": 2, + "name": "CLEAR_CAUSE", + "description": "Clear cause.", + "reset": "Register reset applies", + "expression": "`WDG_CTRL_CLEAR_CAUSE_MASK" + }, + { + "lsb": 3, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + }, + "main.SERVICE": { + "fields": [ + { + "lsb": 0, + "msb": 31, + "name": "KEY", + "description": "Two-key watchdog service port.", + "reset": "Not retained", + "expression": "write data" + } + ], + "reset": "Not retained (command/data port)" + }, + "main.INTR_TEST": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "WARNING", + "description": "Warning.", + "reset": "Register reset applies", + "expression": "`WDG_INTR_WARNING_MASK" + }, + { + "lsb": 1, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + } + }, + "uart": { + "main.TXDATA": { + "fields": [ + { + "lsb": 0, + "msb": 7, + "name": "DATA", + "description": "Push one character from bits 7:0.", + "reset": "Not retained", + "expression": "write data" + }, + { + "lsb": 8, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "zero" + } + ], + "reset": "Not retained (command/data port)" + }, + "main.FIFO_CTRL": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "TX_FLUSH", + "description": "Tx flush.", + "reset": "Register reset applies", + "expression": "`UART_FIFO_CTRL_TX_FLUSH" + }, + { + "lsb": 1, + "msb": 1, + "name": "RX_FLUSH", + "description": "Rx flush.", + "reset": "Register reset applies", + "expression": "`UART_FIFO_CTRL_RX_FLUSH" + }, + { + "lsb": 2, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + }, + "main.INTR_TEST": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "RX_WATERMARK", + "description": "Rx watermark.", + "reset": "Register reset applies", + "expression": "`UART_INTR_RX_WATERMARK" + }, + { + "lsb": 1, + "msb": 1, + "name": "RX_TIMEOUT", + "description": "Rx timeout.", + "reset": "Register reset applies", + "expression": "`UART_INTR_RX_TIMEOUT" + }, + { + "lsb": 2, + "msb": 2, + "name": "TX_WATERMARK", + "description": "Tx watermark.", + "reset": "Register reset applies", + "expression": "`UART_INTR_TX_WATERMARK" + }, + { + "lsb": 3, + "msb": 3, + "name": "TX_DONE", + "description": "Tx done.", + "reset": "Register reset applies", + "expression": "`UART_INTR_TX_DONE" + }, + { + "lsb": 4, + "msb": 4, + "name": "RX_ERROR", + "description": "Rx error.", + "reset": "Register reset applies", + "expression": "`UART_INTR_RX_ERROR" + }, + { + "lsb": 5, + "msb": 5, + "name": "BREAK", + "description": "Break.", + "reset": "Register reset applies", + "expression": "`UART_INTR_BREAK" + }, + { + "lsb": 6, + "msb": 6, + "name": "CTS_CHANGE", + "description": "Cts change.", + "reset": "Register reset applies", + "expression": "`UART_INTR_CTS_CHANGE" + }, + { + "lsb": 7, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + } + }, + "i2c": { + "main.COMMAND": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "ABORT", + "description": "Abort.", + "reset": "Register reset applies", + "expression": "`I2C_COMMAND_ABORT" + }, + { + "lsb": 1, + "msb": 1, + "name": "RECOVER", + "description": "Recover.", + "reset": "Register reset applies", + "expression": "`I2C_COMMAND_RECOVER" + }, + { + "lsb": 2, + "msb": 2, + "name": "CMD_FLUSH", + "description": "Cmd flush.", + "reset": "Register reset applies", + "expression": "`I2C_COMMAND_CMD_FLUSH" + }, + { + "lsb": 3, + "msb": 3, + "name": "RX_FLUSH", + "description": "Rx flush.", + "reset": "Register reset applies", + "expression": "`I2C_COMMAND_RX_FLUSH" + }, + { + "lsb": 4, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + }, + "main.INTR_TEST": { + "fields": [ + { + "lsb": 0, + "msb": 0, + "name": "DONE", + "description": "Done.", + "reset": "Register reset applies", + "expression": "`I2C_INTR_DONE" + }, + { + "lsb": 1, + "msb": 1, + "name": "CMD_WATERMARK", + "description": "Cmd watermark.", + "reset": "Register reset applies", + "expression": "`I2C_INTR_CMD_WATERMARK" + }, + { + "lsb": 2, + "msb": 2, + "name": "RX_WATERMARK", + "description": "Rx watermark.", + "reset": "Register reset applies", + "expression": "`I2C_INTR_RX_WATERMARK" + }, + { + "lsb": 3, + "msb": 3, + "name": "NACK", + "description": "Nack.", + "reset": "Register reset applies", + "expression": "`I2C_INTR_NACK" + }, + { + "lsb": 4, + "msb": 4, + "name": "ARB_LOST", + "description": "Arb lost.", + "reset": "Register reset applies", + "expression": "`I2C_INTR_ARB_LOST" + }, + { + "lsb": 5, + "msb": 5, + "name": "TIMEOUT", + "description": "Timeout.", + "reset": "Register reset applies", + "expression": "`I2C_INTR_TIMEOUT" + }, + { + "lsb": 6, + "msb": 6, + "name": "ERROR", + "description": "Error.", + "reset": "Register reset applies", + "expression": "`I2C_INTR_ERROR" + }, + { + "lsb": 7, + "msb": 7, + "name": "RECOVERY_DONE", + "description": "Recovery done.", + "reset": "Register reset applies", + "expression": "`I2C_INTR_RECOVERY_DONE" + }, + { + "lsb": 8, + "msb": 31, + "name": "Reserved", + "description": "Reserved; write zero.", + "reset": "Not retained", + "expression": "32'd0" + } + ], + "reset": "Not retained (command/data port)" + }, + "main.DATA_CMD": { + "fields": [ + { + "name": "DATA", + "lsb": 0, + "msb": 7, + "description": "Byte to transmit; ignored for a read command.", + "reset": "Register reset applies", + "expression": "reviewed field" + }, + { + "name": "READ", + "lsb": 8, + "msb": 8, + "description": "Read one byte instead of transmitting DATA.", + "reset": "Register reset applies", + "expression": "reviewed field" + }, + { + "name": "RESTART", + "lsb": 9, + "msb": 9, + "description": "Issue START/repeated START before this byte.", + "reset": "Register reset applies", + "expression": "reviewed field" + }, + { + "name": "STOP", + "lsb": 10, + "msb": 10, + "description": "Issue STOP after this command.", + "reset": "Register reset applies", + "expression": "reviewed field" + }, + { + "name": "NACK_LAST", + "lsb": 11, + "msb": 11, + "description": "Return NACK for the final received byte.", + "reset": "Register reset applies", + "expression": "reviewed field" + }, + { + "name": "Reserved", + "lsb": 12, + "msb": 31, + "description": "Reserved; write zero.", + "reset": "0", + "expression": "reserved" + } + ], + "access": "WO", + "reset": "Not retained" + }, + "main.CMD_WATERMARK": { + "reset": "4" + }, + "main.RX_WATERMARK": { + "reset": "8" + } + }, + "clint": { + "msip.MSIP": { + "fields": [ + { + "name": "PENDING", + "lsb": 0, + "msb": 0, + "description": "Machine software-interrupt request for this hart.", + "reset": "0x0", + "expression": "reviewed field" + }, + { + "name": "Reserved", + "lsb": 1, + "msb": 31, + "description": "Reserved; write zero.", + "reset": "0x0", + "expression": "reserved" + } + ], + "access": "RW", + "reset": "0", + "description": "Per-hart software interrupt pending bit." + }, + "compare.MTIMECMP": { + "fields": [ + { + "name": "VALUE", + "lsb": 0, + "msb": 31, + "description": "Comparator bits 31:0.", + "reset": "0xffffffff", + "expression": "reviewed field" + } + ], + "access": "RW", + "reset": "0xFFFFFFFF", + "description": "Comparator bits 31:0." + }, + "main.MTIME": { + "fields": [ + { + "name": "VALUE", + "lsb": 0, + "msb": 31, + "description": "Machine time bits 31:0.", + "reset": "0x0", + "expression": "reviewed field" + } + ], + "access": "RW", + "reset": "0", + "description": "Machine time bits 31:0." + }, + "main.MTIMEH": { + "fields": [ + { + "name": "VALUE", + "lsb": 0, + "msb": 31, + "description": "Machine time bits 63:32.", + "reset": "0x0", + "expression": "reviewed field" + } + ], + "access": "RW", + "reset": "0", + "description": "Machine time bits 63:32." + } + }, + "archinfo": { + "main.TOPOLOGY": { + "fields": [ + { + "name": "MCU_HARTS", + "lsb": 0, + "msb": 7, + "description": "One management MCU hart.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "USER_CORE_SLOTS", + "lsb": 8, + "msb": 15, + "description": "Zero selectable user-core slots.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "GPIO_COUNT", + "lsb": 16, + "msb": 23, + "description": "32 GPIOs.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "IRQ_VECTOR_WIDTH", + "lsb": 24, + "msb": 31, + "description": "32 core interrupt positions.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + } + ] + }, + "main.TECHNOLOGY": { + "fields": [ + { + "name": "PROCESS_NM", + "lsb": 0, + "msb": 15, + "description": "130 nm technology identifier; not a measured manufacturing result.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "PDK_ID", + "lsb": 16, + "msb": 23, + "description": "1: IHP130.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + }, + { + "name": "TARGET_CLASS", + "lsb": 24, + "msb": 31, + "description": "2: ASIC target class; not silicon qualification.", + "reset": "Register reset applies", + "expression": "source-bound Tiny capability field" + } + ] + } + } +} diff --git a/publications/datasheets/tiny/register-contract.json b/publications/datasheets/tiny/register-contract.json new file mode 100644 index 00000000..4edab63d --- /dev/null +++ b/publications/datasheets/tiny/register-contract.json @@ -0,0 +1,365 @@ +{ + "xpi": { + "main.ID": 0, + "main.VERSION": 4, + "main.CAPABILITY": 8, + "main.CTRL": 12, + "main.STATUS": 16, + "main.COMMAND": 20, + "main.ERROR_STATE": 24, + "main.ERROR_ADDR": 28, + "main.ERROR_INFO": 32, + "main.INTR_STATE": 36, + "main.INTR_ENABLE": 40, + "main.INTR_STATUS": 44, + "main.INTR_TEST": 48, + "main.DMA_CTRL": 52, + "main.FIFO_CTRL": 56, + "main.FIFO_STATUS": 60, + "main.TXDATA": 64, + "main.RXDATA": 68, + "main.INDIRECT_ADDR": 72, + "main.INDIRECT_COUNT": 76, + "main.INDIRECT_CFG": 80, + "main.POLL_CFG": 84, + "main.POLL_MASK": 88, + "main.POLL_MATCH": 92, + "main.POLL_INTERVAL": 96, + "main.POLL_TIMEOUT": 100, + "main.PERF_CTRL": 104, + "main.PERF_AXI_READ_BYTES": 108, + "main.PERF_AXI_WRITE_BYTES": 112, + "main.PERF_PHY_BYTES": 116, + "main.PERF_COMMANDS": 120, + "main.PERF_STALL_CYCLES": 124, + "main.CONFIG_LOCK": 128, + "slot.CTRL": 0, + "slot.DEVICE_SIZE": 4, + "slot.SEQ_CFG": 8, + "slot.TIMING": 12, + "slot.TIMEOUT": 16, + "slot.BOUNDARY": 20, + "lut.LUT_WORD": 0 + }, + "sram": { + "main.IP_ID": 0, + "main.IP_VERSION": 4, + "main.CAPABILITY": 8, + "main.MEMORY_BYTES": 12, + "main.BANK_COUNT": 16, + "main.BANK_BYTES": 20, + "main.PERF_READ_REQUESTS": 32, + "main.PERF_WRITE_REQUESTS": 36, + "main.PERF_READ_BEATS": 40, + "main.PERF_WRITE_BEATS": 44, + "main.PERF_STALL_CYCLES": 48, + "main.PERF_ERROR_RESPONSES": 52 + }, + "gpio": { + "user.DATA_IN": 0, + "user.DATA_OUT": 4, + "user.OUT_SET": 8, + "user.OUT_CLEAR": 12, + "user.OUT_TOGGLE": 16, + "user.INTR_STATE": 20, + "user.INTR_STATUS": 24, + "user.INTR_ENABLE": 28, + "user.INTR_ENABLE_SET": 32, + "user.INTR_ENABLE_CLEAR": 36, + "admin.DATA_IN": 0, + "admin.DATA_OUT": 4, + "admin.OUT_SET": 8, + "admin.OUT_CLEAR": 12, + "admin.OUT_TOGGLE": 16, + "admin.OUTPUT_ENABLE": 20, + "admin.OE_SET": 24, + "admin.OE_CLEAR": 28, + "admin.OE_TOGGLE": 32, + "admin.OPEN_DRAIN": 36, + "admin.INPUT_CMOS": 40, + "admin.PULL_UP": 44, + "admin.PULL_DOWN": 48, + "admin.ALT_ENABLE": 52, + "admin.ALT_SELECT": 56, + "admin.USER_SELECT": 60, + "admin.USER_LOCK": 64, + "admin.USER_STATUS": 68, + "admin.USER_ACCESS_MASK": 72, + "admin.INTR_RISE_ENABLE": 76, + "admin.INTR_FALL_ENABLE": 80, + "admin.INTR_HIGH_ENABLE": 84, + "admin.INTR_LOW_ENABLE": 88, + "admin.INTR_ENABLE": 92, + "admin.INTR_STATE": 96, + "admin.INTR_STATUS": 100, + "admin.INTR_TEST": 104, + "admin.FILTER_ENABLE": 108, + "admin.FILTER_DIV": 112, + "admin.FILTER_COUNT": 116, + "admin.CONFIG_LOCK": 120, + "common.PAD_CAPABILITY": 244, + "common.IP_VERSION": 248, + "common.CAPABILITY": 252 + }, + "dma": { + "main.IP_ID": 0, + "main.IP_VERSION": 4, + "main.CAPABILITY": 8, + "main.GLOBAL_CTRL": 12, + "main.GLOBAL_STATUS": 16, + "main.IRQ_STATE": 20, + "main.IRQ_ENABLE": 24, + "main.IRQ_TEST": 28, + "main.ERROR_SUMMARY": 32, + "main.REQUEST_STATUS": 36, + "ch.CTRL": 0, + "ch.CFG": 4, + "ch.SRC_ADDR": 8, + "ch.DST_ADDR": 12, + "ch.BYTE_COUNT": 16, + "ch.REQUEST_SEL": 20, + "ch.BURST_CFG": 24, + "ch.EVENT_ENABLE": 28, + "ch.STATUS": 32, + "ch.EVENT_STATUS": 36, + "ch.ERROR_STATUS": 40, + "ch.ERROR_ADDR": 44, + "ch.CURRENT_SRC": 48, + "ch.CURRENT_DST": 52, + "ch.REMAINING": 56, + "ch.BYTES_DONE": 60, + "ch.STALL_CYCLES_LO": 64, + "ch.STALL_CYCLES_HI": 68, + "ch.TCD_HEAD": 72, + "ch.TCD_COUNT": 76, + "ch.CRC_EXPECTED": 80, + "ch.CRC_RESULT": 84 + }, + "timer": { + "main.CTRL": 0, + "main.LOAD": 4, + "main.VALUE": 8, + "main.BGLOAD": 12, + "main.PRESCALE": 16, + "main.COMPARE0": 20, + "main.COMPARE1": 24, + "main.STATUS": 28, + "main.INTR_STATE": 32, + "main.INTR_ENABLE": 36, + "main.INTR_STATUS": 40, + "main.INTR_TEST": 44, + "main.IP_VERSION": 248, + "main.CAPABILITY": 252 + }, + "pwm": { + "main.CTRL": 0, + "main.STATUS": 4, + "main.COMMAND": 8, + "main.SAFETY_LOCK": 12, + "main.FAULT_CTRL": 16, + "main.FAULT_SAFE": 20, + "main.FAULT_STATUS": 24, + "main.FAULT_CLEAR": 28, + "main.INTR_STATE": 32, + "main.INTR_ENABLE": 36, + "main.INTR_TEST": 40, + "main.OUTPUT_STATUS": 44, + "main.CLOCK_HZ": 48, + "main.IP_ID": 244, + "main.IP_VERSION": 248, + "main.CAPABILITY": 252, + "main.CAPTURE_CTRL": 1024, + "main.CAPTURE_DIVIDER": 1028, + "main.CAPTURE_COUNTER": 1032, + "main.CAPTURE_STATUS": 1036, + "main.CAPTURE0_CTRL": 1040, + "main.CAPTURE0_STATUS": 1044, + "main.CAPTURE0_DATA": 1048, + "main.CAPTURE1_CTRL": 1056, + "main.CAPTURE1_STATUS": 1060, + "main.CAPTURE1_DATA": 1064, + "timer.CTRL": 0, + "timer.DIVIDER": 4, + "timer.PERIOD": 8, + "timer.PHASE": 12, + "timer.COUNTER": 16, + "timer.ACTIVE_DIVIDER": 20, + "timer.ACTIVE_PERIOD": 24, + "timer.STATUS": 28, + "channel.CTRL": 0, + "channel.PHASE": 4, + "channel.DUTY": 8, + "channel.ACTION": 12, + "channel.FORCE": 16, + "channel.FADE_CTRL": 20, + "channel.FADE_TARGET": 24, + "channel.FADE_STEP": 28, + "channel.FADE_INTERVAL": 32, + "channel.FADE_STATUS": 36, + "channel.ACTIVE_PHASE": 40, + "channel.ACTIVE_DUTY": 44, + "channel.GAMMA_INDEX": 48, + "channel.GAMMA_TARGET": 52, + "channel.GAMMA_STEP": 56, + "channel.GAMMA_INTERVAL": 60, + "operator.CTRL": 0, + "operator.DEADTIME": 4, + "operator.CARRIER": 8, + "operator.STATUS": 12 + }, + "rtc": { + "main.CTRL": 0, + "main.STATUS": 4, + "main.COMMAND": 8, + "main.COMMAND_STATUS": 12, + "main.TIME_LOAD_LO": 16, + "main.TIME_LOAD_HI": 20, + "main.TIME_LOAD_SUBSEC": 24, + "main.SNAPSHOT_TIME_LO": 28, + "main.SNAPSHOT_TIME_HI": 32, + "main.SNAPSHOT_SUBSEC": 36, + "main.SECOND_CYCLES": 40, + "main.CALIB_PPM": 44, + "main.ALARM0_TIME_LO": 48, + "main.ALARM0_TIME_HI": 52, + "main.ALARM0_SUBSEC": 56, + "main.ALARM1_TIME_LO": 60, + "main.ALARM1_TIME_HI": 64, + "main.ALARM1_SUBSEC": 68, + "main.ALARM_ENABLE": 72, + "main.PERIOD_RELOAD": 76, + "main.PERIOD_CTRL": 80, + "main.EVENT_RAW": 84, + "main.EVENT_CLEAR": 88, + "main.EVENT_TEST": 92, + "main.INTR_ENABLE": 96, + "main.INTR_STATE": 100, + "main.WAKE_ENABLE": 104, + "main.WAKE_STATE": 108, + "main.CLOCK_HZ": 240, + "main.IP_ID": 244, + "main.IP_VERSION": 248, + "main.CAPABILITY": 252 + }, + "wdg": { + "main.CTRL": 0, + "main.STATUS": 4, + "main.PRESCALE": 8, + "main.TIMEOUT": 12, + "main.WINDOW_MIN": 16, + "main.EARLY_WARNING": 20, + "main.CONFIG": 24, + "main.CONFIG_LOCK": 28, + "main.SERVICE": 32, + "main.COMMAND_STATUS": 36, + "main.COUNT_SNAPSHOT": 40, + "main.EVENT_RAW": 44, + "main.INTR_STATE": 48, + "main.INTR_ENABLE": 52, + "main.INTR_TEST": 56, + "main.RESET_CAUSE": 60, + "main.RESET_COUNT_SNAPSHOT": 64, + "main.CLOCK_HZ": 68, + "main.IP_ID": 244, + "main.IP_VERSION": 248, + "main.CAPABILITY": 252 + }, + "uart": { + "main.BAUD_INT": 0, + "main.BAUD_FRAC": 4, + "main.LINE_CTRL": 8, + "main.CTRL": 12, + "main.TXDATA": 16, + "main.RXDATA": 20, + "main.STATUS": 24, + "main.FIFO_LEVEL": 28, + "main.FIFO_CTRL": 32, + "main.TX_WATERMARK": 36, + "main.RX_WATERMARK": 40, + "main.RX_TIMEOUT_BITS": 44, + "main.ERROR_STATUS": 48, + "main.INTR_STATE": 52, + "main.INTR_ENABLE": 56, + "main.INTR_STATUS": 60, + "main.INTR_TEST": 64, + "main.DMA_CTRL": 68, + "main.FLOW_CTRL": 72, + "main.RTS_WATERMARK": 76, + "main.IP_VERSION": 248, + "main.CAPABILITY": 252 + }, + "i2c": { + "main.CTRL": 0, + "main.SCL_TIMING": 4, + "main.START_TIMING": 8, + "main.DATA_TIMING": 12, + "main.STOP_TIMING": 16, + "main.FILTER": 20, + "main.STRETCH_TIMEOUT": 24, + "main.BUS_IDLE_TIMEOUT": 28, + "main.COMMAND_TIMEOUT": 32, + "main.TARGET_ADDR": 36, + "main.DATA_CMD": 40, + "main.RXDATA": 44, + "main.STATUS": 48, + "main.FIFO_LEVEL": 52, + "main.COMMAND": 56, + "main.CMD_WATERMARK": 60, + "main.RX_WATERMARK": 64, + "main.ERROR_STATUS": 68, + "main.INTR_STATE": 72, + "main.INTR_ENABLE": 76, + "main.INTR_STATUS": 80, + "main.INTR_TEST": 84, + "main.LINE_STATE": 88, + "main.IP_VERSION": 248, + "main.CAPABILITY": 252 + }, + "clint": { + "msip.MSIP": 0, + "compare.MTIMECMP": 16384, + "compare.MTIMECMP_HI": 16388, + "main.MTIME": 49144, + "main.MTIMEH": 49148 + }, + "archinfo": { + "main.COMPONENT_ID": 0, + "main.VENDOR_ID": 4, + "main.SOC_ID": 8, + "main.SOC_REVISION": 12, + "main.BUILD_ID_LO": 16, + "main.BUILD_ID_HI": 20, + "main.CONFIG_ID": 24, + "main.BUILD_STATUS": 28, + "main.REFERENCE_CLOCK": 32, + "main.SRAM_BYTES": 36, + "main.TOPOLOGY": 40, + "main.FEATURES0": 44, + "main.TECHNOLOGY": 48, + "main.DEVICE_ID_STATUS": 52, + "main.DEVICE_ID0": 56, + "main.DEVICE_ID1": 60, + "main.DEVICE_ID2": 64, + "main.DEVICE_ID3": 68, + "main.IP_VERSION": 248, + "main.CAPABILITY": 252 + }, + "sysctrl": { + "main.CORESEL": 0, + "main.IPSEL": 4, + "main.FAULT_STATUS": 16, + "main.FAULT_ADDR": 20, + "main.FAULT_COUNT": 24, + "main.USER_CORE_RESET": 32, + "main.USER_CORE_STATUS": 36, + "main.FAULT_MASTER": 40, + "main.FAULT_DETAIL": 44, + "main.PERF_CTRL": 64, + "main.PERF_MGMT_WAIT_LO": 68, + "main.PERF_MGMT_WAIT_HI": 72, + "main.PERF_DMA_WAIT_LO": 84, + "main.PERF_DMA_WAIT_HI": 88, + "main.TEST_STATUS": 132, + "main.RTC_WAKE_STATUS": 136 + } +} diff --git a/publications/datasheets/tiny/register-profiles.json b/publications/datasheets/tiny/register-profiles.json new file mode 100644 index 00000000..60a4176a --- /dev/null +++ b/publications/datasheets/tiny/register-profiles.json @@ -0,0 +1,746 @@ +{ + "xpi": { + "document": "docs/ip/xpi.md", + "defines": [ + "rtl/ip/storage/xpi_define.svh" + ], + "rtl": [ + "rtl/ip/storage/xpi_reg.sv", + "rtl/ip/storage/xpi_pkg.sv" + ], + "parameters": {}, + "groups": [ + { + "id": "main", + "title": "Global XPI registers", + "pattern": "APB4_XPI__(?!SLOT_|LUT_).+", + "strip": "^APB4_XPI__", + "base": 0, + "stride": 0, + "count": 1 + }, + { + "id": "slot", + "title": "Chip-select slots", + "pattern": "APB4_XPI__SLOT_.+", + "strip": "^APB4_XPI__SLOT_", + "base": 256, + "stride": 32, + "count": 4, + "exclude": [ + "APB4_XPI__SLOT_BASE", + "APB4_XPI__SLOT_STRIDE" + ] + }, + { + "id": "lut", + "title": "LUT words", + "pattern": "(?!)", + "strip": "^", + "base": 512, + "stride": 4, + "count": 64 + } + ], + "field_aliases": { + "IRQ_STATE": [ + "APB4_XPI__IRQ_" + ], + "IRQ_ENABLE": [ + "APB4_XPI__IRQ_" + ], + "IRQ_TEST": [ + "APB4_XPI__IRQ_" + ], + "INTR_STATE": [ + "XPI_INTR_" + ], + "INTR_ENABLE": [ + "XPI_INTR_" + ], + "INTR_STATUS": [ + "XPI_INTR_" + ] + }, + "extra": [ + { + "group": "lut", + "name": "LUT_WORD", + "offset": 0, + "access": "RW / locked", + "reset": "Boot LUT; other sequences STOP", + "description": "Two 16-bit instructions. Sequence n begins at word 4*n; PC7 must terminate or jump on CS. Bits 9:8 of each halfword are reserved.", + "fields": [ + { + "name": "OPERAND0", + "lsb": 0, + "msb": 7, + "description": "Instruction operand.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 8, + "msb": 9, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + }, + { + "name": "PADS0", + "lsb": 10, + "msb": 11, + "description": "0 = one pad, 1 = two pads, 2 = four pads; 3 is invalid.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "OPCODE0", + "lsb": 12, + "msb": 15, + "description": "0 STOP, 1 CMD, 2 ADDR, 3 MODE, 4 DUMMY, 5 TX, 6 RX, 7 JUMP_ON_CS.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "OPERAND1", + "lsb": 16, + "msb": 23, + "description": "Instruction operand.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "Reserved", + "lsb": 24, + "msb": 25, + "description": "Reserved; preserve zero when writing.", + "reset": "0", + "expression": "reserved" + }, + { + "name": "PADS1", + "lsb": 26, + "msb": 27, + "description": "0 = one pad, 1 = two pads, 2 = four pads; 3 is invalid.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + }, + { + "name": "OPCODE1", + "lsb": 28, + "msb": 31, + "description": "0 STOP, 1 CMD, 2 ADDR, 3 MODE, 4 DUMMY, 5 TX, 6 RX, 7 JUMP_ON_CS.", + "reset": "Register reset applies", + "expression": "reviewed semantic field" + } + ] + } + ], + "support": [ + "rtl/ip/storage/apb4_xpi.sv", + "rtl/ip/storage/xpi_clkgen.sv", + "rtl/ip/storage/xpi_core.sv", + "rtl/ip/storage/xpi_if.sv", + "rtl/ip/storage/xpi_indirect.sv", + "rtl/ip/storage/xpi_mm.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "sram": { + "document": "docs/ip/onchip-sram.md", + "defines": [ + "rtl/ip/memory/onchip_ram_define.svh" + ], + "rtl": [ + "rtl/ip/memory/onchip_ram_reg.sv" + ], + "parameters": { + "Present": 1, + "CapacityKiB": 128, + "BankCount": 32, + "BankBytes": 4096, + "DataBytes": 4 + }, + "groups": [ + { + "id": "main", + "title": "SRAM management", + "pattern": "APB4_ONCHIP_RAM__.+", + "strip": "^APB4_ONCHIP_RAM__", + "base": 0, + "stride": 0, + "count": 1 + } + ], + "default_access": "RO", + "support": [], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "gpio": { + "document": "docs/ip/gpio.md", + "defines": [ + "rtl/ip/peripheral/gpio_define.svh" + ], + "rtl": [ + "rtl/ip/peripheral/gpio_reg.sv" + ], + "parameters": { + "PinNum": 32, + "NumPins": 32, + "GPIO_NUM": 32 + }, + "groups": [ + { + "id": "user", + "title": "User window", + "pattern": "APB4_GPIO_USER_.+", + "strip": "^APB4_GPIO_USER_", + "base": 0, + "stride": 0, + "count": 1, + "section": "User window" + }, + { + "id": "admin", + "title": "Management window", + "pattern": "APB4_GPIO_ADMIN_.+", + "strip": "^APB4_GPIO_ADMIN_", + "base": 0, + "stride": 0, + "count": 1, + "section": "Management window" + }, + { + "id": "common", + "title": "Common discovery registers", + "pattern": "APB4_GPIO_(PAD_CAPABILITY|IP_VERSION|CAPABILITY)", + "strip": "^APB4_GPIO_", + "base": 0, + "stride": 0, + "count": 1 + } + ], + "support": [ + "rtl/ip/peripheral/apb4_gpio.sv", + "rtl/ip/peripheral/gpio_core.sv", + "rtl/ip/peripheral/gpio_if.sv", + "rtl/ip/peripheral/user_gpio_if.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "dma": { + "document": "docs/ip/dma.md", + "defines": [ + "rtl/ip/peripheral/dma_define.svh" + ], + "rtl": [ + "rtl/ip/peripheral/dma_reg.sv", + "rtl/ip/peripheral/dma_pkg.sv" + ], + "parameters": { + "NumChannels": 4, + "ChannelIndexWidth": 2, + "EnableStreams": 0, + "DataWidth": 32, + "MaxBurstBeats": 16 + }, + "groups": [ + { + "id": "main", + "title": "Register bank", + "pattern": "APB4_DMA__(?!CH_).+", + "strip": "^APB4_DMA__", + "base": 0, + "stride": 0, + "count": 1 + }, + { + "id": "ch", + "title": "DMA channel registers", + "pattern": "APB4_DMA__CH_.+", + "strip": "^APB4_DMA__CH_", + "base": 256, + "stride": 128, + "count": 4, + "exclude": [ + "APB4_DMA__CH_BASE", + "APB4_DMA__CH_STRIDE", + "APB4_DMA__CH_BASE_OFFSET" + ], + "doc_name_prefix": "CH_" + } + ], + "field_aliases": { + "EVENT_ENABLE": [ + "APB4_DMA__EVENT_" + ], + "EVENT_STATUS": [ + "APB4_DMA__EVENT_" + ], + "STATUS": [ + "APB4_DMA__STATUS_" + ] + }, + "support": [ + "rtl/ip/peripheral/apb4_dma.sv", + "rtl/ip/peripheral/dma_axi4_master.sv", + "rtl/ip/peripheral/dma_core.sv", + "rtl/ip/peripheral/dma_req_if.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "timer": { + "document": "docs/ip/timer.md", + "defines": [ + "rtl/ip/peripheral/timer_define.svh" + ], + "rtl": [ + "rtl/ip/peripheral/timer_reg.sv" + ], + "parameters": {}, + "groups": [ + { + "id": "main", + "title": "Register bank", + "pattern": "APB4_TIMER_.+", + "strip": "^APB4_TIMER_", + "base": 0, + "stride": 0, + "count": 1 + } + ], + "field_aliases": { + "INTR_STATE": [ + "TIMER_INTR_" + ], + "INTR_ENABLE": [ + "TIMER_INTR_" + ], + "INTR_STATUS": [ + "TIMER_INTR_" + ], + "INTR_TEST": [ + "TIMER_INTR_" + ], + "ERROR_STATUS": [ + "TIMER_ERROR_" + ] + }, + "support": [ + "rtl/ip/peripheral/apb4_timer.sv", + "rtl/ip/peripheral/timer_core.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "pwm": { + "document": "rtl/managed/clusterip/pwm/doc/datasheet.md", + "defines": [ + "rtl/managed/clusterip/pwm/rtl/pwm_define.svh" + ], + "rtl": [ + "rtl/managed/clusterip/pwm/rtl/pwm_reg.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_pkg.sv" + ], + "parameters": { + "PCLK_HZ": 24000000, + "RTC_CLOCK_HZ": 24000000, + "WDG_CLOCK_HZ": 24000000, + "FIFO_DEPTH": 8 + }, + "groups": [ + { + "id": "main", + "title": "Register bank", + "pattern": "PWM_(?!TIMER_)(?!CHANNEL_)(?!OPERATOR_).+_OFFSET", + "strip": "^PWM_", + "base": 0, + "stride": 0, + "count": 1 + }, + { + "id": "timer", + "title": "TIMER registers", + "pattern": "PWM_TIMER_.+", + "strip": "^PWM_TIMER_", + "base": 256, + "stride": 64, + "count": 2, + "exclude": [ + "PWM_TIMER_BASE", + "PWM_TIMER_STRIDE", + "PWM_TIMER_BASE_OFFSET" + ], + "section": "Timer Blocks" + }, + { + "id": "channel", + "title": "CHANNEL registers", + "pattern": "PWM_CHANNEL_.+", + "strip": "^PWM_CHANNEL_", + "base": 512, + "stride": 64, + "count": 4, + "exclude": [ + "PWM_CHANNEL_BASE", + "PWM_CHANNEL_STRIDE", + "PWM_CHANNEL_BASE_OFFSET" + ], + "section": "Channel Blocks" + }, + { + "id": "operator", + "title": "OPERATOR registers", + "pattern": "PWM_OPERATOR_.+", + "strip": "^PWM_OPERATOR_", + "base": 768, + "stride": 64, + "count": 2, + "exclude": [ + "PWM_OPERATOR_BASE", + "PWM_OPERATOR_STRIDE", + "PWM_OPERATOR_BASE_OFFSET" + ], + "section": "Operator Blocks" + } + ], + "field_aliases": { + "INTR_STATE": [ + "PWM_INTR_" + ], + "INTR_ENABLE": [ + "PWM_INTR_" + ], + "INTR_TEST": [ + "PWM_INTR_" + ], + "CAPTURE0_CTRL": [ + "PWM_CAPTURE_CH_" + ], + "CAPTURE1_CTRL": [ + "PWM_CAPTURE_CH_" + ] + }, + "support": [ + "rtl/managed/clusterip/pwm/rtl/apb4_pwm.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_capture.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_carrier.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_channel.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_deadtime.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_if.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_tickgen.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_timer.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "rtc": { + "document": "rtl/managed/clusterip/rtc/doc/datasheet.md", + "defines": [ + "rtl/managed/clusterip/rtc/rtl/rtc_define.svh" + ], + "rtl": [ + "rtl/managed/clusterip/rtc/rtl/rtc_reg.sv", + "rtl/managed/clusterip/rtc/rtl/rtc_pkg.sv" + ], + "parameters": { + "PCLK_HZ": 24000000, + "RTC_CLOCK_HZ": 24000000, + "WDG_CLOCK_HZ": 24000000, + "FIFO_DEPTH": 8 + }, + "groups": [ + { + "id": "main", + "title": "Register bank", + "pattern": "RTC_.+_OFFSET", + "strip": "^RTC_", + "base": 0, + "stride": 0, + "count": 1 + } + ], + "field_aliases": { + "INTR_STATE": [ + "RTC_INTR_" + ], + "INTR_ENABLE": [ + "RTC_INTR_" + ], + "INTR_TEST": [ + "RTC_INTR_" + ] + }, + "support": [ + "rtl/managed/clusterip/rtc/rtl/apb4_rtc.sv", + "rtl/managed/clusterip/rtc/rtl/rtc_core.sv", + "rtl/managed/clusterip/rtc/rtl/rtc_if.sv", + "rtl/managed/clusterip/rtc/rtl/rtc_tickgen.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "wdg": { + "document": "rtl/managed/clusterip/wdg/doc/datasheet.md", + "defines": [ + "rtl/managed/clusterip/wdg/rtl/wdg_define.svh" + ], + "rtl": [ + "rtl/managed/clusterip/wdg/rtl/wdg_reg.sv", + "rtl/managed/clusterip/wdg/rtl/wdg_pkg.sv" + ], + "parameters": { + "PCLK_HZ": 24000000, + "RTC_CLOCK_HZ": 24000000, + "WDG_CLOCK_HZ": 24000000, + "FIFO_DEPTH": 8 + }, + "groups": [ + { + "id": "main", + "title": "Register bank", + "pattern": "WDG_.+_OFFSET", + "strip": "^WDG_", + "base": 0, + "stride": 0, + "count": 1 + } + ], + "field_aliases": { + "INTR_STATE": [ + "WDG_INTR_" + ], + "INTR_ENABLE": [ + "WDG_INTR_" + ], + "INTR_TEST": [ + "WDG_INTR_" + ] + }, + "support": [ + "rtl/managed/clusterip/wdg/rtl/apb4_wdg.sv", + "rtl/managed/clusterip/wdg/rtl/wdg_core.sv", + "rtl/managed/clusterip/wdg/rtl/wdg_if.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "uart": { + "document": "docs/ip/uart.md", + "defines": [ + "rtl/ip/serial/apb4_uart_define.svh" + ], + "rtl": [ + "rtl/ip/serial/uart_reg.sv" + ], + "parameters": { + "TxFifoDepth": 64, + "RxFifoDepth": 64, + "TxFifoLogDepth": 6, + "RxFifoLogDepth": 6 + }, + "groups": [ + { + "id": "main", + "title": "Register bank", + "pattern": "APB4_UART_.+", + "strip": "^APB4_UART_", + "base": 0, + "stride": 0, + "count": 1 + } + ], + "field_aliases": { + "LINE_CTRL": [ + "UART_LINE_" + ], + "CTRL": [ + "UART_CTRL_" + ], + "STATUS": [ + "UART_STATUS_" + ], + "FIFO_CTRL": [ + "UART_FIFO_CTRL_" + ], + "RXDATA": [ + "UART_RXDATA_" + ], + "ERROR_STATUS": [ + "UART_ERROR_" + ], + "INTR_STATE": [ + "UART_INTR_" + ], + "INTR_ENABLE": [ + "UART_INTR_" + ], + "INTR_STATUS": [ + "UART_INTR_" + ], + "INTR_TEST": [ + "UART_INTR_" + ], + "DMA_CTRL": [ + "UART_DMA_" + ], + "FLOW_CTRL": [ + "UART_FLOW_" + ] + }, + "support": [ + "rtl/ip/serial/apb4_uart.sv", + "rtl/ip/serial/apb4_uart_rx.sv", + "rtl/ip/serial/apb4_uart_tx.sv", + "rtl/ip/serial/uart_baudgen.sv", + "rtl/ip/serial/uart_core.sv", + "rtl/ip/serial/uart_flow_ctrl.sv", + "rtl/ip/serial/uart_if.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "i2c": { + "document": "docs/ip/i2c.md", + "defines": [ + "rtl/ip/serial/apb4_i2c_define.svh" + ], + "rtl": [ + "rtl/ip/serial/i2c_reg.sv" + ], + "parameters": {}, + "groups": [ + { + "id": "main", + "title": "Register bank", + "pattern": "APB4_I2C_.+", + "strip": "^APB4_I2C_", + "base": 0, + "stride": 0, + "count": 1 + } + ], + "field_aliases": { + "INTR_STATE": [ + "I2C_INTR_" + ], + "INTR_ENABLE": [ + "I2C_INTR_" + ], + "INTR_STATUS": [ + "I2C_INTR_" + ], + "INTR_TEST": [ + "I2C_INTR_" + ], + "ERROR_STATUS": [ + "I2C_ERROR_" + ] + }, + "support": [ + "rtl/ip/serial/apb4_i2c.sv", + "rtl/ip/serial/i2c_core.sv", + "rtl/ip/serial/i2c_filter.sv", + "rtl/ip/serial/i2c_if.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "clint": { + "document": "docs/ip/clint.md", + "defines": [ + "rtl/ip/peripheral/clint_define.svh" + ], + "rtl": [ + "rtl/ip/peripheral/clint_reg.sv" + ], + "parameters": { + "HartNum": 1 + }, + "groups": [ + { + "id": "msip", + "title": "Per-hart software interrupt", + "pattern": "APB4_CLINT_MSIP", + "strip": "^APB4_CLINT_", + "base": 0, + "stride": 4, + "count": 1 + }, + { + "id": "compare", + "title": "Per-hart timer comparator", + "pattern": "APB4_CLINT_MTIMECMP", + "strip": "^APB4_CLINT_", + "base": 0, + "stride": 8, + "count": 1 + }, + { + "id": "main", + "title": "Shared 64-bit time", + "pattern": "APB4_CLINT_MTIMEH?", + "strip": "^APB4_CLINT_", + "base": 0, + "stride": 0, + "count": 1 + } + ], + "extra": [ + { + "group": "compare", + "name": "MTIMECMP_HI", + "offset": 16388, + "access": "RW", + "reset": "0xFFFFFFFF", + "description": "High word of the per-hart 64-bit machine timer comparator.", + "fields": [ + { + "name": "VALUE", + "lsb": 0, + "msb": 31, + "description": "Comparator bits 63:32.", + "reset": "Register reset applies", + "expression": "reviewed field" + } + ] + } + ], + "support": [ + "rtl/ip/peripheral/apb4_clint.sv", + "rtl/ip/peripheral/clint_core.sv", + "rtl/ip/peripheral/clint_if.sv", + "rtl/ip/peripheral/clint_timebase.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + }, + "archinfo": { + "document": "rtl/managed/clusterip/archinfo/doc/datasheet.md", + "defines": [ + "rtl/managed/clusterip/archinfo/rtl/archinfo_define.svh" + ], + "rtl": [ + "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv" + ], + "parameters": { + "REFERENCE_CLOCK_HZ": 24000000, + "SRAM_BYTES": 131072, + "TOPOLOGY": 538968065, + "FEATURES0": 32766, + "TECHNOLOGY": 33620098 + }, + "groups": [ + { + "id": "main", + "title": "Register bank", + "pattern": "ARCHINFO_.+_OFFSET", + "strip": "^ARCHINFO_", + "base": 0, + "stride": 0, + "count": 1 + } + ], + "default_access": "RO", + "support": [ + "rtl/managed/clusterip/archinfo/rtl/apb4_archinfo.sv" + ], + "memory_map": "rtl/tiny/address_map/memory_map.json" + } +} diff --git a/publications/datasheets/tiny/source-contract.json b/publications/datasheets/tiny/source-contract.json new file mode 100644 index 00000000..d2346185 --- /dev/null +++ b/publications/datasheets/tiny/source-contract.json @@ -0,0 +1,182 @@ +{ + "regions": { + "FLASH": [ + 0, + 16777216 + ], + "APB4_GPIO": [ + 268435456, + 4096 + ], + "APB4_UART0": [ + 268439552, + 4096 + ], + "APB4_TIM0": [ + 268443648, + 4096 + ], + "APB4_TIM1": [ + 268447744, + 4096 + ], + "APB4_I2C0": [ + 268460032, + 4096 + ], + "APB4_XPI": [ + 268472320, + 4096 + ], + "APB4_DMA": [ + 268476416, + 4096 + ], + "APB4_SYSCTRL": [ + 268480512, + 4096 + ], + "APB4_CLINT": [ + 268566528, + 65536 + ], + "APB4_I2C1": [ + 268505088, + 4096 + ], + "APB4_GPIO_ADMIN": [ + 268517376, + 4096 + ], + "APB4_SRAM": [ + 268529664, + 4096 + ], + "APB4_UART1": [ + 268533760, + 4096 + ], + "APB4_ARCHINFO": [ + 536870912, + 4096 + ], + "APB4_PWM": [ + 536879104, + 4096 + ], + "APB4_RTC": [ + 536887296, + 4096 + ], + "APB4_WDG": [ + 536891392, + 4096 + ], + "SRAM": [ + 805306368, + 131072 + ], + "XPI": [ + 1342177280, + 268435456 + ] + }, + "interrupts": { + "clint_software": 0, + "clint_timer": 1, + "uart0": 2, + "timer0": 3, + "timer1": 4, + "i2c0": 7, + "xpi": 9, + "pwm": 11, + "rtc": 13, + "watchdog_early_warning": 14, + "gpio": 18, + "i2c1": 19, + "dma": 20, + "uart1": 26 + }, + "sources": [ + "rtl/ip/core/mgmt_core_wrapper.sv", + "rtl/ip/core/mgmt_debug_wrapper.sv", + "rtl/ip/core/mgmt_debug_reset.sv", + "rtl/ip/interconnect/ahbl2axi4.sv", + "crt/arch/riscv/startup.S", + "crt/linker/ld2_all_sram.lds", + "crt/src/hal/dma_math.c", + "crt/src/hal/sysctrl.c", + "crt/src/core/archinfo.c", + "app/apps/ci_smoke/tiny.c", + "app/apps/ci_smoke/mcu_acceptance.S", + "app/apps/bringup/tiny.mk", + "app/apps/ci_smoke/tiny.mk", + "scripts/generate_tiny.py", + "tests/test_tiny.py" + ], + "bindings": [ + { + "file": "rtl/tiny/top/tiny_axi4_fabric.sv", + "text": [ + "(s_selected_addr.len <= 8'd15)", + "(s_last_addr[31:12] == s_selected_addr.addr[31:12])", + "s_accept = (s_state_q == Idle) && s_selected_valid;", + "Response: if (s_terminal) s_state_d = Idle;", + "s_tgt_d = s_protocol_legal ? s_decoded_target : 3'd4;", + "assign s_protocol_legal = !s_selected_addr.lock && (s_selected_addr.size <= 3'd2) &&\n ((s_selected_addr.addr & ((32'd1 << s_selected_addr.size) - 32'd1)) == 32'd0) &&\n ((s_selected_addr.burst == 2'b01) ||\n ((s_selected_addr.burst == 2'b00) && (s_selected_addr.len == 8'd0))) &&\n (s_selected_addr.len <= 8'd15) && !s_last_addr[32] &&\n (s_last_addr[31:12] == s_selected_addr.addr[31:12]) &&\n (decode_target(\n s_last_addr[31:0]\n ) == s_decoded_target) && ((s_decoded_target != 3'd2) || (s_selected_addr.len == 8'd0));", + "assign s_terminal = (s_state_q == Response) &&\n (s_write_q ? (s_target_bvalid[s_tgt_q] && s_bready[s_owner_q]) :\n (s_target_rvalid[s_tgt_q] && s_rready[s_owner_q] && s_target_rlast[s_tgt_q]));" + ] + }, + { + "file": "crt/src/hal/dma_math.c", + "text": [ + "#ifdef RS_SOC_TINY\n if (config->kind != RS_DMA_KIND_MM_TO_MM) {\n return false;\n }\n#endif" + ] + }, + { + "file": "crt/arch/riscv/startup.S", + "text": [ + "#ifndef RS_SOC_TINY" + ] + }, + { + "file": "rtl/tiny/top/retrosoc_tiny.sv", + "text": [ + ".RTC_CLOCK_HZ(24_000_000)", + ".WDG_CLOCK_HZ(24_000_000)", + ".RESET_PULSE_CYCLES(8)", + "assign u_uart1_if.cts_n_i = 1'b0;" + ] + }, + { + "file": "rtl/ip/peripheral/dma_reg.sv", + "text": [ + "`APB4_DMA__CAPABILITY:\n s_read_data = {\n 1'b0,\n (EnableStreams ? 3'd3 : 3'd0),\n 4'(MaxBurstBeats),\n 8'(DataWidth),\n 8'(NumChannels),\n 7'd0,\n 1'b1\n };" + ] + }, + { + "file": "crt/include/retrosoc/hal/dma.h", + "text": [ + "#define RS_DMA_TCD_VALID UINT32_C(0x00000001)", + "#define RS_DMA_TCD_SRC_INC UINT32_C(0x00000002)", + "#define RS_DMA_TCD_DST_INC UINT32_C(0x00000004)", + "#define RS_DMA_TCD_CRC_ENABLE UINT32_C(0x00000008)", + "#define RS_DMA_TCD_CRC_FINAL UINT32_C(0x00000010)", + "#define RS_DMA_TCD_INT_DONE UINT32_C(0x00000020)", + "#define RS_DMA_TCD_INT_ERROR UINT32_C(0x00000040)", + "#define RS_DMA_TCD_KIND_SHIFT 8U", + "#define RS_DMA_TCD_REQUEST_SHIFT 12U", + "#define RS_DMA_TCD_PRIORITY_SHIFT 16U", + "#define RS_DMA_TCD_BURST_SHIFT 20U" + ] + }, + { + "file": "crt/src/hal/dma.c", + "text": [ + "if (burst == UINT32_C(0)) {\n burst = RS_DMA_MAX_BURST_BEATS;\n }", + "RS_DMA_CH_REG(channel, RS_DMA_CH_REG_TCD_COUNT) = UINT32_C(1);", + "current = (rs_dma_tcd_t *)(uintptr_t)current->next_ptr;" + ] + } + ] +} diff --git a/publications/datasheets/tiny/structure-contract.json b/publications/datasheets/tiny/structure-contract.json new file mode 100644 index 00000000..6dac12f9 --- /dev/null +++ b/publications/datasheets/tiny/structure-contract.json @@ -0,0 +1,217 @@ +{ + "schema_version": 1, + "state": "frozen", + "ip_ids": [ + "xpi", + "sram", + "gpio", + "dma", + "timer", + "pwm", + "rtc", + "wdg", + "uart0", + "uart1", + "i2c", + "sysctrl", + "clint", + "archinfo" + ], + "entries": [ + { + "level": 1, + "title": "Product Brief", + "anchor": null + }, + { + "level": 2, + "title": "Features", + "anchor": null + }, + { + "level": 2, + "title": "Configuration and Scope", + "anchor": "tiny-configuration" + }, + { + "level": 2, + "title": "Reading and Evidence Conventions", + "anchor": null + }, + { + "level": 1, + "title": "System Architecture", + "anchor": null + }, + { + "level": 2, + "title": "Processor and Integration", + "anchor": "tiny-core" + }, + { + "level": 2, + "title": "Clock, Reset and Operating State", + "anchor": "tiny-clock" + }, + { + "level": 2, + "title": "Bus Transactions, Arbitration and Errors", + "anchor": "tiny-bus" + }, + { + "level": 2, + "title": "Memory Map and Access Conventions", + "anchor": "tiny-addresses" + }, + { + "level": 2, + "title": "Interrupt and DMA Request Routing", + "anchor": "tiny-irq" + }, + { + "level": 2, + "title": "Peripherals", + "anchor": null + }, + { + "level": 3, + "title": "XPI Universal Controller", + "anchor": "xpi" + }, + { + "level": 3, + "title": "On-Chip SRAM", + "anchor": "sram" + }, + { + "level": 3, + "title": "General-Purpose Input/Output (GPIO)", + "anchor": "gpio" + }, + { + "level": 3, + "title": "Direct Memory Access (DMA)", + "anchor": "dma" + }, + { + "level": 3, + "title": "General-Purpose Timers (TIM0, TIM1)", + "anchor": "timer" + }, + { + "level": 3, + "title": "Pulse Width Modulation (PWM)", + "anchor": "pwm" + }, + { + "level": 3, + "title": "Real-Time Clock (RTC)", + "anchor": "rtc" + }, + { + "level": 3, + "title": "Watchdog (WDG)", + "anchor": "wdg" + }, + { + "level": 3, + "title": "Management UART (UART0)", + "anchor": "uart0" + }, + { + "level": 3, + "title": "Second UART (UART1)", + "anchor": "uart1" + }, + { + "level": 3, + "title": "Inter-Integrated Circuit (I2C0, I2C1)", + "anchor": "i2c" + }, + { + "level": 3, + "title": "System Controller (SYSCTRL)", + "anchor": "sysctrl" + }, + { + "level": 3, + "title": "Local Interrupt Controller (CLINT)", + "anchor": "clint" + }, + { + "level": 3, + "title": "Architecture Information (ARCHINFO)", + "anchor": "archinfo" + }, + { + "level": 2, + "title": "Pins and Board Connections", + "anchor": "tiny-pins" + }, + { + "level": 2, + "title": "Electrical, Package and Reliability Boundaries", + "anchor": null + }, + { + "level": 1, + "title": "Software", + "anchor": null + }, + { + "level": 2, + "title": "Reset, Boot and Linker Layout", + "anchor": "tiny-boot" + }, + { + "level": 2, + "title": "SDK, API Completion and Polling", + "anchor": null + }, + { + "level": 2, + "title": "DMA Descriptors and Buffer Lifetime", + "anchor": "tiny-dma-format" + }, + { + "level": 2, + "title": "Acceptance and Diagnostics", + "anchor": "tiny-diagnostics" + }, + { + "level": 1, + "title": "Implementation and Evidence", + "anchor": null + }, + { + "level": 2, + "title": "Reproducible Development Flow", + "anchor": null + }, + { + "level": 2, + "title": "Verification Status and Qualification Gaps", + "anchor": "tiny-evidence" + }, + { + "level": 1, + "title": "Appendix: Global Register Index", + "anchor": "tiny-register-index" + }, + { + "level": 1, + "title": "Document Control", + "anchor": null + }, + { + "level": 2, + "title": "Revision History", + "anchor": null + }, + { + "level": 2, + "title": "Sources, License and Contact", + "anchor": "publication-provenance" + } + ] +} diff --git a/publications/datasheets/tiny/style.md b/publications/datasheets/tiny/style.md new file mode 100644 index 00000000..160b0e9a --- /dev/null +++ b/publications/datasheets/tiny/style.md @@ -0,0 +1,40 @@ +# Tiny datasheet layout supplement + +Tiny follows the reviewed [Mini visual language](../style.md), but owns an +independent [style implementation](style.typ). This addition does not edit, +import or reflow Mini's template. Changes to Tiny must preserve the publication +isolation boundary rather than inserting fake Mini/HP data into its model. + +Use A4 portrait, 19 mm horizontal margins, a 172 mm body, 10.5 pt Inter body, +9 pt tables/source links and Fira Code identifiers, and the existing gold/gray +palette. Headings, table continuation notices, Contents hierarchy, figure/table +directories and underlined links follow the approved layout. Short critical +phrases use true Inter Bold, not an extra font-weight increment. Code remains +regular. Continuation notices retain the existing 8.5 pt exception. + +The cover title is `retroSoC Tiny` (30 pt) / `Gen1` (23 pt). The 13 pt positioning +line is `An Open-Source, Single-Core RISC-V MCU`. The Rill bilingual metadata, +version/date, author email and maintainer retain the established two-line grid. +Keep the right-hand title area empty for a logo. The Chinese label uses the +locked Noto CJK Bold and the same cap-edge compensation as the approved cover. + +Available is full pale gold; Functional uses a vertical left-half fill; +Reproduced/Tapedout are empty. Marks remain manually controlled prototype status, +not a score derived from a document build or historical test count. + +Every IP starts on a new page. Shared UART layouts have one canonical reference +with instance-specific address, IRQ and software qualifications. GPIO views and +DMA/PWM repeated groups preserve exact base/stride/index formulas. A constant +zero capability field must not be mislabeled reserved when it has defined +semantics, such as Tiny's truncated DMA maximum-burst discovery field. + +Use native Typst/CeTZ vector structure diagrams and the existing locked waveform +renderer. Keep labels at least 9 pt; Tiny has no need to invent compact bus CDC +boxes. Explain diagram abstraction: functional control reach is not a complete +netlist, and representative waveforms are not measured cycle timings. Register +bit layouts and the source-derived 64-byte DMA diagram must match their tables. + +Keep implementation, configuration, available tests, executed results and +physical qualification separate. In particular, preserve the negative timing +record and external-device qualification gaps. Record full source/asset hashes, +font/package revisions, PDF digest, page map and actual verification results. diff --git a/publications/datasheets/tiny/style.typ b/publications/datasheets/tiny/style.typ new file mode 100644 index 00000000..37b41c07 --- /dev/null +++ b/publications/datasheets/tiny/style.typ @@ -0,0 +1,372 @@ +// Tiny-owned layout snapshot of the approved Mini style; Mini is not imported or modified. +#let ink = rgb("#292C31") +#let gold = rgb("#A38442") +#let pale-gold = rgb("#F4EFE4") +#let gray = rgb("#F1F2F3") +#let rule = rgb("#D5D6D8") +#let muted = rgb("#62666C") +#let link-color = rgb("#245A81") +#let inline-code-color = rgb("#B12146") +#let table-stroke = 0.6pt + black +#let mono = "FiraCode Nerd Font" +#let data = json(sys.inputs.at("data")) +#let doc = data.document +#let ip-chapters = json("chapter-index.json") +// RM0486-inspired spacing, adapted to the retained Inter sizes. Inter's +// cap-height-to-baseline box is 7.639 pt at 10.5 pt and 6.548 pt at 9 pt. +// Thus these leading values yield 12.6 / 10.8 pt baseline pitches, rather +// than treating Typst's `leading` as the whole distance between baselines. +#let rhythm = ( + body-leading: 4.96pt, body-spacing: 11.26pt, + small-leading: 4.25pt, small-spacing: 8.25pt, + heading-before: (28pt,24pt,18pt,12pt,10pt), + heading-after: (18pt,10pt,8pt,6pt,5pt), + heading-gap: 8pt, minor-before: 12pt, minor-after: 6pt, + register-before: 12pt, register-after: 4pt, + list-spacing: 7.96pt, list-indent: 0pt, list-body-indent: 8pt, + figure-space: 12pt, figure-caption: 6pt, table-caption: 4pt, + table-inset: (x:6pt,y:5pt), table-notes: 6pt, + continuation-size: 8.5pt, continuation-gap: 2pt, + code-space: 8pt, code-inset: 8pt, + note-space: 12pt, note-inset: 10pt, + metadata-before: 4pt, metadata-after: 6pt, + bits-space: 6pt, bits-inset: (x:3pt,y:5pt), + toc-leading: 9.09pt, toc-indent: 14pt, toc-group-before: 12pt, toc-group-after: 4pt, + header-gap: 4pt, + cover-leading: 4.96pt, cover-spacing: 3.675pt, cover-list-spacing: 7.96pt, + cover-heading-before: (12pt,12pt), cover-heading-after: 6pt, + cover-gap: 3pt, cover-meta-gap: 4pt, cover-rule-gap: 2pt, + cover-gutter: 7mm, cover-list-indent: 0.5em, + diagram-leading: 0.4em, inventory-leading: 0.35em, +) + +#let heading-layout(it, before: none, after: none) = { + if it.outlined and it.numbering != none and it.level <= 2 { + context { + let preceding = query(selector(heading).before(it.location(),inclusive:false)).filter(h=>h.outlined and h.numbering!=none) + let chapters = preceding.filter(h=>h.level==1) + let product-brief = if it.level==1 {it.body==[Product Brief]} + else {chapters.len()>0 and chapters.last().body==[Product Brief]} + // Chapter openers and their first section form one heading group. + // Subsequent sections break independently, even when their text is short. + let chapter-opener = it.level==2 and preceding.len()>0 and preceding.last().level==1 + if not product-brief and not chapter-opener {pagebreak(weak:true)} + } + } + let index = calc.min(it.level - 1,4) + let sizes = (21pt,16pt,13pt,11pt,10.5pt) + block(above: if before == none {rhythm.heading-before.at(index)} else {before}, + below: if after == none {rhythm.heading-after.at(index)} else {after}, sticky:true)[ + #set text(size:sizes.at(index),weight:"semibold") + #set par(leading:rhythm.body-leading,spacing:0pt) + #if it.numbering == none { it.body } else { + grid(columns:(auto,1fr),column-gutter:rhythm.heading-gap, + text(fill:gold,counter(heading).display(it.numbering)),it.body) + } + ] +} + +#let minor-title(body) = block(above:rhythm.minor-before,below:rhythm.minor-after,sticky:true,strong(body)) +// Only this editing round emits active ranges; earlier markers remain historical. +#let current-change(id) = id.starts-with(doc.change_prefix) or id in ( + "contents","table-directory","figure-directory") +#let change-start(id, title, category:"modified") = context { + if current-change(id) {metadata(( + kind:"publication-change-start",id:id,title:title,category:category,page:here().page()))} +} +#let change-end(id) = context { + if current-change(id) {metadata((kind:"publication-change-end",id:id,page:here().page()))} +} +#let code-block(body, breakable:false) = block(above:rhythm.code-space,below:rhythm.code-space, + width:100%,inset:rhythm.code-inset,fill:gray,breakable:breakable)[ + #set par(leading:rhythm.small-leading,spacing:rhythm.small-spacing) + #body +] +#let artifact-mark(state) = { + assert(state in ("empty", "left-half", "full"), message:"Unknown artifact mark") + box(width:3mm,height:3mm)[ + #place(top + left,circle(radius:1.5mm,fill:white,stroke:none)) + #if state=="left-half" { + place(top + left,box(width:1.5mm,height:3mm,clip:true)[ + #circle(radius:1.5mm,fill:pale-gold,stroke:none) + ]) + } else if state=="full" { + place(top + left,circle(radius:1.5mm,fill:pale-gold,stroke:none)) + } + #place(top + left,circle(radius:1.5mm,fill:none, + stroke:0.6pt + if state=="empty" {ink} else {gold})) + ] +} +#let artifact-evaluation(states) = rect(width:92mm,height:10mm,radius:1.5mm, + fill:white,stroke:0.6pt + ink,inset:(x:2mm,y:1mm))[ + #set text(size:9pt,weight:"regular",fill:ink) + #set par(leading:rhythm.small-leading,spacing:0pt) + #align(center + horizon)[ + #grid(columns:(1fr,1fr,1fr,1fr),row-gutter:2pt,align:center, + ..states.map(state=>state.name), + ..states.map(state=>artifact-mark(state.fill)), + ) + ] +] +#let cover(body, evaluation:none) = { + show heading: it => { + if it.level==1 and it.body==[Product Brief] and evaluation!=none { + block(width:100%,above:rhythm.cover-heading-before.first(), + below:rhythm.cover-heading-after,sticky:true)[ + #grid(columns:(1fr,92mm),column-gutter:4mm,row-gutter:2pt, + align(horizon,heading-layout(it,before:0pt,after:0pt)), + artifact-evaluation(evaluation), + [], align(center,text(9pt,weight:"regular",fill:black)[Artifact Evaluation]), + ) + ] + } else { + heading-layout(it, + before:rhythm.cover-heading-before.at(calc.min(it.level - 1,1)), + after:rhythm.cover-heading-after) + } + } + body +} + +#let omit-link-underline(it) = it.body +#let repository-footer-link() = context { + show underline: omit-link-underline + show link: set text(fill:link-color,weight:"regular") + let body=text(font:"Inter",size:9pt,weight:"regular",fill:link-color)[https://github.com/retroSoC/retroSoC] + link("https://github.com/retroSoC/retroSoC",body) +} + +#let contents(depth:5) = { + set text(size:9.5pt,fill:ink) + show link: set text(fill:ink) + show underline: omit-link-underline + set par(leading:rhythm.toc-leading,spacing:rhythm.toc-leading) + set outline(indent:rhythm.toc-indent) + show outline.entry: it => context { + let peers = query(heading).filter(h=>h.outlined and h.level==it.level and h.numbering!=none) + let widths = peers.map(h=>measure(text(weight:if it.level==1 {"bold"} else {"regular"}, + numbering(h.numbering,..counter(heading).at(h.location())))).width) + let prefix-width = calc.max(0pt,..widths) + let prefix = if it.prefix()==none {none} else if it.level==1 {strong(it.prefix())} else {it.prefix()} + // Scope emphasis by the section ancestor, not by a hard-coded chapter number. + let ancestors = query(selector(heading).before(it.element.location(),inclusive:true)).filter(h=>h.level<=2) + let peripheral = ancestors.len()>0 and ancestors.last().body==[Peripherals] + let inner = if it.level==1 { + [#strong(it.body())#h(0.5em)#box(width:1fr,it.fill)#h(0.5em)#it.page()] + } else if peripheral { + // Keep parentheses, separators and qualifiers such as "partial" regular. + show regex("\\([^()]*\\)"): group => { + show regex("\\b[A-Z][A-Z0-9]*(?:-[A-Z0-9]+)*\\b"): strong + group + } + it.inner() + } else {it.inner()} + block(above:rhythm.toc-leading + if it.level==1 {rhythm.toc-group-before} else {0pt}, + below:rhythm.toc-leading + if it.level==1 {rhythm.toc-group-after} else {0pt},breakable:false)[ + #link(it.element.location(),it.indented( + if prefix==none {none} else {box(width:prefix-width,prefix)},inner,gap:rhythm.heading-gap)) + ] + } + outline(title:[Contents],depth:depth) +} +#let figure-directory(tables:false) = context { + set text(font:"Inter",size:9.5pt,fill:ink,weight:"regular") + show link: set text(fill:ink) + show underline: omit-link-underline + set par(leading:rhythm.toc-leading,spacing:rhythm.toc-leading) + set outline(indent:0pt) + show outline: set heading(bookmarked:true) + // Include every numbered non-table figure, including native vector diagrams. + // Continuation notices and unnumbered register layouts are not figure entries. + let included(f) = (f.kind==table)==tables and f.numbering!=none and f.caption!=none + let prefix(entry) = [#(entry.prefix()).] + let peers = query(figure).filter(included) + let widths = peers.map(f=>measure(prefix(outline.entry(1,f))).width) + let prefix-width = calc.max(0pt,..widths) + show outline.entry: it => { + if included(it.element) { + block(above:rhythm.toc-leading,below:rhythm.toc-leading,breakable:false)[ + #link(it.element.location(),it.indented( + box(width:prefix-width,prefix(it)),it.inner(),gap:rhythm.heading-gap)) + ] + } + } + outline(title:if tables {[List of tables]} else {[List of figures]},target:figure) +} +#let inline-code(body) = context { + // Link scopes already select link-color; keep that semantic cue and underline. + set text(fill:if text.fill==link-color {link-color} else {inline-code-color}) + body +} +#let code(value) = inline-code(text(font: mono, size: 9pt, weight:"regular", + value.replace("_", "_\u{200b}").replace(".", ".\u{200b}"))) +#let source(path, title: "Interface and implementation reference", line:none) = { + // Publication metadata can postdate the frozen hardware commit. Route readers + // to the delivered manifest instead of constructing a nonexistent old blob. + if path.starts-with("publications/") { + return link(,text(size:9pt,title)) + } + let managed = data.managed_sources.find(s=>path.starts-with(s.destination + "/")) + let url = if managed == none { + "https://github.com/retroSoC/retroSoC/blob/" + doc.source_revision + "/" + path + } else { + managed.url.trim(".git", at:end) + "/blob/" + managed.revision + "/" + path.slice(managed.destination.len()+1) + } + if line!=none { url += "#L"+str(line) } + link(url, text(size: 9pt, title)) +} +#let source-note(path, title:"Interface and implementation reference", line:none) = block( + above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[ + #set par(leading:rhythm.small-leading,spacing:rhythm.small-spacing) + #source(path,title:title,line:line) +] +#let note(body, title: "Integration note", below: rhythm.note-space) = block( + width: 100%, inset: rhythm.note-inset, fill: pale-gold, stroke: (left: 2pt + gold), + above: rhythm.note-space, below: below, breakable: false, +)[#text(weight: "semibold", title) #linebreak() #body] +#let tbd(body) = note(body, title: "TBD - specification not available") +#let placeholder(title, height: 35mm) = block( + width: 100%, height: height, stroke: 0.7pt + rule, fill: gray, + inset: rhythm.note-inset, above: rhythm.note-space, below: rhythm.note-space, breakable: false, +)[#align(center + horizon)[#text(weight: "semibold", title) \ + #text(9pt, fill: muted)[TBD - awaiting reviewed engineering data]]] + +// Frame each row at its outer edges without adding internal vertical rules. +// Repeated header rows supply the top edge on every continued table segment. +#let table-rules(columns, header-row:0) = (x,y) => ( + top: if y==header-row {table-stroke} else {none}, + bottom: table-stroke, + left: if x==0 {table-stroke} else {none}, + right: if x==columns - 1 {table-stroke} else {none}, +) + +#let continuation-notice() = layout(size => { + let body = block(width:100%,above:0pt,below:0pt)[ + #set text(size:rhythm.continuation-size,weight:"regular",fill:black, + top-edge:"ascender",bottom-edge:"descender") + #set par(leading:4pt,spacing:0pt) + (continued) + ] + let extent = measure(body,width:size.width) + block(width:100%,above:rhythm.table-caption,below:0pt, + inset:(bottom:rhythm.continuation-gap))[ + #block(width:extent.width,height:extent.height,above:0pt,below:0pt,body) + ] +}) + +#let ds-table(key, caption, headers, rows, widths: auto, notes: none) = { + let anchor = label("start-" + key) + figure( + kind: table, supplement: [Table], caption: caption, + block(breakable: rows.len() > 8, width: 100%)[ + #metadata(none)#anchor + #set text(size: 9pt) + #set par(leading: rhythm.small-leading, spacing: rhythm.small-spacing) + #table( + columns: if widths == auto { headers.len() } else { widths }, + inset: rhythm.table-inset, + stroke: table-rules(headers.len(),header-row:1), + fill: (x, y) => if y == 1 { gray } else { none }, + align: left + horizon, + table.header(repeat: true, + table.cell(colspan: headers.len(), inset: 0pt, + stroke:(top:none,bottom:table-stroke,left:none,right:none),fill: white)[ + #context if here().page() > query(anchor).first().location().page() { + continuation-notice() + } + ], + ..headers.map(h => table.cell(fill: gray, text(weight: "semibold", h))), + ), + ..rows.map(row => row.map(v => table.cell(breakable: false, v))).flatten(), + ) + #if notes != none { block(above: rhythm.table-notes, breakable: false, text(9pt, fill: muted, notes)) } + ], + ) +} + +#let ip(id) = { + let entry = data.catalog.find(e => e.id == id) + let windows = data.regions.filter(r => r.symbol in entry.regions) + let irqs = data.interrupts.filter(i => i.name in entry.irqs) + block(above: rhythm.metadata-before, below: rhythm.metadata-after, breakable: false, sticky: true)[ + #entry.summary + #set text(size: 9pt) + #set par(leading: rhythm.small-leading, spacing: rhythm.small-spacing) + #table(columns: (1.3fr, 1fr, 0.7fr), inset: rhythm.table-inset, + stroke: table-rules(3), + table.header(..([Address window],[Base address],[Size]).map(h=> + table.cell(fill:gray,text(weight:"semibold",h)))), + ..windows.map(r => (code(r.symbol), code(r.base_hex), r.size_label)).flatten(), + ) + #block(above: rhythm.metadata-before)[ + *Core IRQ bit:* #if irqs.len() == 0 { [No dedicated source.] } else { + irqs.map(i => str(i.core_bit) + " (" + i.name.replace("_", " ") + ")").join("; ") + } + ] + #for (n, p) in entry.sources.enumerate() { + source(p, title: if n == 0 { "Detailed contract / source" } else { "Additional source" }) + if n < entry.sources.len() - 1 { [ · ] } + } + ] +} + +#let template(body) = { + set document(title: doc.title, author: doc.author, + keywords: ("retroSoC", "Tiny", "Gen1", "datasheet", doc.document_id, "v"+doc.version, doc.status)) + set text(font: "Inter", size: 10.5pt, fill: ink, lang: "en", weight: "regular") + show strong: it => text(weight:"bold",it.body) + set par(justify: false, leading: rhythm.body-leading, spacing: rhythm.body-spacing,first-line-indent:0pt) + set list(indent:rhythm.list-indent,body-indent:rhythm.list-body-indent,spacing:rhythm.list-spacing) + set enum(indent:rhythm.list-indent,body-indent:rhythm.list-body-indent,spacing:rhythm.list-spacing) + set page(paper: "a4", margin: (x: 19mm, top: 21mm, bottom: 20mm), + header: context { + let hs = query(heading.where(level: 1)).filter(h => h.location().page() <= here().page()) + // Heading locations avoid the extra layout pass needed by page-valued metadata. + // A later chapter/section heading closes the preceding IP's header scope. + let navigation=query(selector(heading.where(level:1)).or(heading.where(level:2), + ..ip-chapters.map(chapter=>label(chapter.id)))) + .filter(h=>h.location().page()<=here().page()) + let active=if navigation.len()==0 {none} else { + ip-chapters.find(chapter=>label(chapter.id)==navigation.last().fields().at("label",default:none)) + } + set text(size: 9pt, fill: muted) + grid(columns: (1fr, 1fr), [#doc.brand_name · #doc.title], align(right)[ + #if active!=none { upper(active.id) } else if hs.len() > 0 { hs.last().body } else { [Product datasheet] } + ]) + v(rhythm.header-gap) + line(length: 100%, stroke: 0.6pt + gold) + }, + footer: context { + set text(size: 9pt, fill: muted) + set par(leading:0pt,spacing:0pt) + line(length: 100%, stroke: 0.35pt + rule) + v(rhythm.header-gap) + grid(columns: (1fr, auto, 1fr), + repository-footer-link(), + [#counter(page).display() / #counter(page).final().first()], + align(right)[#doc.date], + ) + }, + ) + set heading(numbering: "1.1.1.1.1", outlined: true) + show heading: heading-layout + show raw: set text(font: mono, size: 9pt, weight:"regular") + show raw.where(block:false): inline-code + show link: set text(fill:link-color) + show link: it => underline(stroke:0.4pt + link-color,offset:2pt,it) + show ref: it => { + if it.element!=none and it.element.func()==heading and it.form=="normal" { + set text(fill:link-color) + show underline: omit-link-underline + it + } else {it} + } + set figure(gap: rhythm.figure-caption) + show figure: set block(above:rhythm.figure-space,below:rhythm.figure-space,breakable:false) + set figure.caption(position:top) + show figure.where(kind: table): set figure(gap:rhythm.table-caption) + show figure.where(kind: table): set block(breakable: true) + show figure.caption: set text(size: 9pt, fill: black) + show figure.caption: it => block(above:0pt,below:0pt,sticky:it.position==top,it) + body +} diff --git a/publications/datasheets/tiny/tiny.json b/publications/datasheets/tiny/tiny.json new file mode 100644 index 00000000..aff43a0c --- /dev/null +++ b/publications/datasheets/tiny/tiny.json @@ -0,0 +1,17 @@ +{ + "title": "retroSoC Tiny Gen1", + "document_id": "RS-TINY-DS", + "brand_name": "Rill", + "brand_name_zh": "清溪", + "version": "0.1", + "status": "DRAFT", + "date": "2026-09-25", + "author": "Yuchi Miao", + "author_email": "miaoyuchi@ict.ac.cn", + "maintainer": "ECOS Team, ICT, CAS", + "source_revision": "9c706ba0ff1da1028c299cfff573010a86dfd7ce", + "profile": "configs/ci/ihp130-tiny.mk", + "change_prefix": "tiny-v01-", + "entrypoint": "publications/datasheets/tiny/datasheet.typ", + "filename": "retrosoc-tiny-gen1-datasheet.pdf" +} diff --git a/publications/datasheets/tiny/waveforms.json b/publications/datasheets/tiny/waveforms.json new file mode 100644 index 00000000..a2b8a7ea --- /dev/null +++ b/publications/datasheets/tiny/waveforms.json @@ -0,0 +1,1126 @@ +{ + "apb4": { + "source": { + "signal": [ + { + "name": "pclk", + "wave": "p......." + }, + { + "name": "psel", + "wave": "01...0.." + }, + { + "name": "penable", + "wave": "0.1..0.." + }, + { + "name": "pready", + "wave": "0...10.." + }, + { + "name": "pwrite", + "wave": "1......." + }, + { + "name": "paddr", + "wave": "x=...x..", + "data": [ + "address" + ] + }, + { + "name": "pwdata", + "wave": "x=...x..", + "data": [ + "write data" + ] + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: apb4_if. Clock: pclk. Write with wait states; address and write data are distinct stable buses. Transfer completes when psel, penable and pready are high. Example cycles only. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "pclk": { + "file": "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv", + "scope": "apb4_if", + "symbol": "pclk", + "meaning": "APB sampling clock.", + "polarity": "rising-edge" + }, + "psel": { + "file": "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv", + "scope": "apb4_if", + "symbol": "psel", + "meaning": "Select stays asserted through the wait states.", + "polarity": "active-high" + }, + "penable": { + "file": "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv", + "scope": "apb4_if", + "symbol": "penable", + "meaning": "Access phase follows the setup phase.", + "polarity": "active-high" + }, + "pready": { + "file": "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv", + "scope": "apb4_if", + "symbol": "pready", + "meaning": "High with select and enable completes this transfer.", + "polarity": "active-high" + }, + "pwrite": { + "file": "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv", + "scope": "apb4_if", + "symbol": "pwrite", + "meaning": "Write direction for the illustrated transfer.", + "polarity": "active-high" + }, + "paddr": { + "file": "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv", + "scope": "apb4_if", + "symbol": "paddr", + "meaning": "Stable byte address across setup and access.", + "polarity": "data" + }, + "pwdata": { + "file": "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv", + "scope": "apb4_if", + "symbol": "pwdata", + "meaning": "Stable write payload until completion.", + "polarity": "data" + } + }, + "review_sources": [ + "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Split the former ADDR / DATA lane; retained the valid APB wait-state ordering.", + "parameters": { + "APB_ADDR_WIDTH": 32, + "APB_DATA_WIDTH": 32 + }, + "parameter_note": "The PRODUCT APB interface uses 32-bit address and data." + }, + "axi4": { + "source": { + "signal": [ + { + "name": "aclk", + "wave": "p......." + }, + { + "name": "arvalid", + "wave": "01.0...." + }, + { + "name": "arready", + "wave": "0.10...." + }, + { + "name": "rvalid", + "wave": "0...1..0" + }, + { + "name": "rready", + "wave": "0....1.." + }, + { + "name": "rlast", + "wave": "0.....10" + }, + { + "name": "rdata", + "wave": "x...=.=x", + "data": [ + "D0", + "D1" + ] + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: axi4_if. Clock: aclk. Independent address and response channels. D0 is held while rready is low, then D1 completes with rlast. Example cycles only. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "aclk": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "aclk", + "meaning": "AXI sampling clock.", + "polarity": "rising-edge" + }, + "arvalid": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "arvalid", + "meaning": "Read-address valid held until accepted.", + "polarity": "active-high" + }, + "arready": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "arready", + "meaning": "Address acceptance.", + "polarity": "active-high" + }, + "rvalid": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "rvalid", + "meaning": "Read data valid across the stall.", + "polarity": "active-high" + }, + "rready": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "rready", + "meaning": "Read response acceptance.", + "polarity": "active-high" + }, + "rlast": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "rlast", + "meaning": "Final data beat indication.", + "polarity": "active-high" + }, + "rdata": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "rdata", + "meaning": "First beat held during backpressure, then final beat.", + "polarity": "data" + } + }, + "review_sources": [ + "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Preserved the original two-beat read handshakes; declarations use the native data-fabric interface.", + "parameters": { + "ADDR_WIDTH": 32, + "DATA_WIDTH": 32, + "ID_WIDTH": 1, + "USER_WIDTH": 1 + }, + "parameter_note": "Tiny integration: AXI data/address 32 bits, ID 1 bit, USER 1 bit." + }, + "xpi": { + "source": { + "signal": [ + { + "name": "nss_o[0]", + "wave": "10......1" + }, + { + "name": "sck_o", + "wave": "0p..|..0." + }, + { + "name": "io_oe_o", + "wave": "=...=....", + "data": [ + "0xf", + "0x0" + ] + }, + { + "name": "io_do_o", + "wave": "x=..x....", + "data": [ + "cmd/addr" + ] + }, + { + "name": "io_di_i", + "wave": "x....=..x", + "data": [ + "read data" + ] + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: xpi_if. Clock: xpi_core.clk_i; sck_o is the serial clock. Quad mode-0 command/address, turnaround and read excerpt. Serial phases are compressed; io_do_o is not a tri-state pad. io_oe_o defines when outputs drive and io_di_i carries received data. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "nss_o[0]": { + "file": "rtl/ip/storage/xpi_if.sv", + "scope": "xpi_if", + "symbol": "nss_o", + "meaning": "Selected chip-select, active low.", + "polarity": "active-low" + }, + "sck_o": { + "file": "rtl/ip/storage/xpi_if.sv", + "scope": "xpi_if", + "symbol": "sck_o", + "meaning": "Representative mode-0 serial clocks.", + "polarity": "rising-edge" + }, + "io_oe_o": { + "file": "rtl/ip/storage/xpi_if.sv", + "scope": "xpi_if", + "symbol": "io_oe_o", + "meaning": "Output enable changes from transmit to receive.", + "polarity": "data" + }, + "io_do_o": { + "file": "rtl/ip/storage/xpi_if.sv", + "scope": "xpi_if", + "symbol": "io_do_o", + "meaning": "Driven command/address nibbles; value immaterial when OE is zero.", + "polarity": "data" + }, + "io_di_i": { + "file": "rtl/ip/storage/xpi_if.sv", + "scope": "xpi_if", + "symbol": "io_di_i", + "meaning": "Sampled receive nibbles after turnaround.", + "polarity": "data" + } + }, + "review_sources": [ + "rtl/ip/storage/xpi_core.sv", + "rtl/ip/storage/xpi_define.svh", + "rtl/ip/storage/xpi_if.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Removed synthetic phase/IO lanes and separated input, output and output-enable signals. Reviewed XPI core pad assignments.", + "parameters": { + "XPI_NSS_NUM": 4 + }, + "parameter_note": "xpi_define.svh fixes four chip selects." + }, + "sram": { + "source": { + "signal": [ + { + "name": "aclk", + "wave": "p......." + }, + { + "name": "arvalid", + "wave": "01.0...." + }, + { + "name": "arready", + "wave": "0.10...." + }, + { + "name": "rvalid", + "wave": "0...1..0" + }, + { + "name": "rready", + "wave": "0....1.." + }, + { + "name": "rdata", + "wave": "x...=..x", + "data": [ + "read data" + ] + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: axi4_if. Clock: aclk at the native SRAM AXI boundary. Native SRAM AXI read with response backpressure. The diagram illustrates the interface contract, not a guaranteed memory latency; read data remains stable while stalled. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "aclk": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "aclk", + "meaning": "AXI sampling clock.", + "polarity": "rising-edge" + }, + "arvalid": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "arvalid", + "meaning": "Read address request.", + "polarity": "active-high" + }, + "arready": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "arready", + "meaning": "Read address accepted.", + "polarity": "active-high" + }, + "rvalid": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "rvalid", + "meaning": "Response held valid during a sink stall.", + "polarity": "active-high" + }, + "rready": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "rready", + "meaning": "Read response sink readiness.", + "polarity": "active-high" + }, + "rdata": { + "file": "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "scope": "axi4_if", + "symbol": "rdata", + "meaning": "Read data remains stable until consumed.", + "polarity": "data" + } + }, + "review_sources": [ + "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Split the synthetic AR-handshake into actual ARVALID/ARREADY members; retained response wait behavior.", + "parameters": { + "ADDR_WIDTH": 32, + "DATA_WIDTH": 32, + "ID_WIDTH": 1, + "USER_WIDTH": 1 + }, + "parameter_note": "Tiny integration: AXI data/address 32 bits, ID 1 bit, USER 1 bit." + }, + "gpio": { + "source": { + "signal": [ + { + "name": "user_select_i[0]", + "wave": "0...1..." + }, + { + "name": "user_handoff_i[0]", + "wave": "0.1..0.." + }, + { + "name": "s_selected_oe[0]", + "wave": "1......." + }, + { + "name": "s_selected_data[0]", + "wave": "0...1..." + }, + { + "name": "open_drain_i[0]", + "wave": "0......." + }, + { + "name": "oe_o[0]", + "wave": "1.0..1.." + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: gpio_core, gpio_if. Clock: clk_i; ownership handoff observation. Pin 0 push-pull ownership handoff. The actual pad OE equation is !user_handoff_i[0] && s_selected_oe[0] when open drain is disabled; the guard suppresses drive while selection changes. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "user_select_i[0]": { + "file": "rtl/ip/peripheral/gpio_core.sv", + "scope": "gpio_core", + "symbol": "user_select_i", + "meaning": "Pin 0 switches from native to user selection.", + "polarity": "active-high" + }, + "user_handoff_i[0]": { + "file": "rtl/ip/peripheral/gpio_core.sv", + "scope": "gpio_core", + "symbol": "user_handoff_i", + "meaning": "Handoff guard disables pin drive.", + "polarity": "active-high" + }, + "s_selected_oe[0]": { + "file": "rtl/ip/peripheral/gpio_core.sv", + "scope": "gpio_core", + "symbol": "s_selected_oe", + "meaning": "Both selected owners request output enable in this example.", + "polarity": "active-high" + }, + "s_selected_data[0]": { + "file": "rtl/ip/peripheral/gpio_core.sv", + "scope": "gpio_core", + "symbol": "s_selected_data", + "meaning": "Selected data changes with the owner.", + "polarity": "data" + }, + "open_drain_i[0]": { + "file": "rtl/ip/peripheral/gpio_core.sv", + "scope": "gpio_core", + "symbol": "open_drain_i", + "meaning": "Push-pull mode selected.", + "polarity": "active-high" + }, + "oe_o[0]": { + "file": "rtl/ip/peripheral/gpio_if.sv", + "scope": "gpio_if", + "symbol": "oe_o", + "meaning": "Actual pad output enable is suppressed by the handoff guard.", + "polarity": "active-high" + } + }, + "review_sources": [ + "rtl/ip/peripheral/gpio_core.sv", + "rtl/ip/peripheral/gpio_if.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Removed old-owner/new-owner pseudo-signals and used actual owner, guard and selected-data/enable signals. Pad behavior follows the reviewed output-enable equation.", + "parameters": { + "PinNum": 32, + "DataWidth": 32 + }, + "parameter_note": "PRODUCT has one 32-pin GPIO controller and matching gpio_if." + }, + "dma": { + "source": { + "signal": [ + { + "name": "start_i[0]", + "wave": "010......" + }, + { + "name": "busy_o[0]", + "wave": "0.1....0." + }, + { + "name": "remaining_o[31:0]", + "wave": "=.=..=.=.", + "data": [ + "16", + "16", + "8", + "0" + ] + }, + { + "name": "done_o[0]", + "wave": "0......1." + }, + { + "name": "error_o[0]", + "wave": "0........" + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: dma_core. Clock: clk_i; descriptor/data work and response latency omitted. Channel 0 successful transfer after a valid configuration or linked descriptor. Remaining bytes reach zero before completion is consumed. Descriptor fetches, bus handshakes and variable stalls are omitted; interrupt routing remains a register-bank function. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "start_i[0]": { + "file": "rtl/ip/peripheral/dma_core.sv", + "scope": "dma_core", + "symbol": "start_i", + "meaning": "Channel 0 software-start pulse.", + "polarity": "active-high" + }, + "busy_o[0]": { + "file": "rtl/ip/peripheral/dma_core.sv", + "scope": "dma_core", + "symbol": "busy_o", + "meaning": "Channel 0 executes a valid memory transfer.", + "polarity": "active-high" + }, + "remaining_o[31:0]": { + "file": "rtl/ip/peripheral/dma_core.sv", + "scope": "dma_core", + "symbol": "remaining_o", + "meaning": "Remaining bytes for channel 0.", + "polarity": "data" + }, + "done_o[0]": { + "file": "rtl/ip/peripheral/dma_core.sv", + "scope": "dma_core", + "symbol": "done_o", + "meaning": "Channel completion state after all work finishes.", + "polarity": "active-high" + }, + "error_o[0]": { + "file": "rtl/ip/peripheral/dma_core.sv", + "scope": "dma_core", + "symbol": "error_o", + "meaning": "No channel error in this successful example.", + "polarity": "active-high" + } + }, + "review_sources": [ + "rtl/ip/peripheral/dma_core.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Replaced descriptor-ready, AXI/stream-work and completion-IRQ pseudo-signals with actual channel start/status/progress ports.", + "parameters": { + "NumChannels": 4, + "DataWidth": 32, + "AddrWidth": 32 + }, + "parameter_note": "Tiny selects four channels, 32-bit transfers and no stream endpoints." + }, + "timer": { + "source": { + "signal": [ + { + "name": "s_tick", + "wave": "010101010" + }, + { + "name": "value_o", + "wave": "=.=.=.=.=", + "data": [ + "0", + "1", + "2", + "3", + "0" + ] + }, + { + "name": "compare0_event_o", + "wave": "0....10.." + }, + { + "name": "timeout_event_o", + "wave": "0......10" + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: timer_core. Clock: clk_i; qualified prescaler ticks shown. Periodic up-count example with load_i = 3 and compare0_i = 2. The event tests the current value on s_tick; the counter then advances or reloads. Prescale clocks are omitted. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "s_tick": { + "file": "rtl/ip/peripheral/timer_core.sv", + "scope": "timer_core", + "symbol": "s_tick", + "meaning": "Prescaler-qualified count enable.", + "polarity": "active-high" + }, + "value_o": { + "file": "rtl/ip/peripheral/timer_core.sv", + "scope": "timer_core", + "symbol": "value_o", + "meaning": "Periodic up-counter value between ticks.", + "polarity": "data" + }, + "compare0_event_o": { + "file": "rtl/ip/peripheral/timer_core.sv", + "scope": "timer_core", + "symbol": "compare0_event_o", + "meaning": "Compare event when the current value equals two on a tick.", + "polarity": "active-high" + }, + "timeout_event_o": { + "file": "rtl/ip/peripheral/timer_core.sv", + "scope": "timer_core", + "symbol": "timeout_event_o", + "meaning": "Terminal event at value three.", + "polarity": "active-high" + } + }, + "review_sources": [ + "rtl/ip/peripheral/timer_core.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Replaced a fictitious core IRQ-state lane with compare0_event_o and timeout_event_o; reviewed compare-before-update behavior.", + "parameters": { + "CounterWidth": 32, + "PrescaleWidth": 16 + }, + "parameter_note": "Reference TIM0/TIM1 use 32-bit counters and 16-bit prescalers." + }, + "pwm": { + "source": { + "signal": [ + { + "name": "timer_counter_o[0]", + "wave": "=.=.=.=.=", + "data": [ + "0", + "1", + "2", + "3", + "0" + ] + }, + { + "name": "channel_duty_i[0]", + "wave": "=..=.....", + "data": [ + "1", + "2" + ] + }, + { + "name": "update_i", + "wave": "0...10..." + }, + { + "name": "channel_active_duty_o[0]", + "wave": "=....=...", + "data": [ + "1", + "2" + ] + }, + { + "name": "pwm_o[0]", + "wave": "10......1" + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: pwm_core. Clock: clk_i; timer/update boundaries shown. Timer/channel 0 example with a shadow duty update. Actual application timing depends on the configured update mode; counter wrap and update intervals are illustrative, not an electrical timing guarantee. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "timer_counter_o[0]": { + "file": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "scope": "pwm_core", + "symbol": "timer_counter_o", + "meaning": "Timer 0 counter excerpt.", + "polarity": "data" + }, + "channel_duty_i[0]": { + "file": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "scope": "pwm_core", + "symbol": "channel_duty_i", + "meaning": "Software changes the shadow duty input.", + "polarity": "data" + }, + "update_i": { + "file": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "scope": "pwm_core", + "symbol": "update_i", + "meaning": "Explicit update request.", + "polarity": "active-high" + }, + "channel_active_duty_o[0]": { + "file": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "scope": "pwm_core", + "symbol": "channel_active_duty_o", + "meaning": "Active duty reflects the accepted update.", + "polarity": "data" + }, + "pwm_o[0]": { + "file": "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "scope": "pwm_core", + "symbol": "pwm_o", + "meaning": "Channel 0 output for the shown counter/duty example.", + "polarity": "active-high" + } + }, + "review_sources": [ + "rtl/managed/clusterip/pwm/rtl/pwm_core.sv", + "rtl/managed/clusterip/pwm/rtl/pwm_define.svh", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Mapped counter, shadow input, update command, active duty and output ports. Replaced synthetic shadow-update/active-update signals.", + "parameters": { + "PWM_TIMER_COUNT": 2, + "PWM_CHANNEL_COUNT": 4 + }, + "parameter_note": "pwm_define.svh declares two timers and four PWM channels." + }, + "rtc": { + "source": { + "signal": [ + { + "name": "command_valid_i", + "wave": "01..0..." + }, + { + "name": "command_ready_o", + "wave": "0..10..." + }, + { + "name": "response_valid_o", + "wave": "01..0..." + }, + { + "name": "response_ready_i", + "wave": "0..10..." + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: rtc_core. Clock: clk_i (RTC core domain). Core command/response handshake: response_valid_o equals command_valid_i and command_ready_o equals response_ready_i. The APB-to-RTC CDC and software snapshot reads are outside this interface sketch. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "command_valid_i": { + "file": "rtl/managed/clusterip/rtc/rtl/rtc_core.sv", + "scope": "rtc_core", + "symbol": "command_valid_i", + "meaning": "Command remains valid through backpressure.", + "polarity": "active-high" + }, + "command_ready_o": { + "file": "rtl/managed/clusterip/rtc/rtl/rtc_core.sv", + "scope": "rtc_core", + "symbol": "command_ready_o", + "meaning": "Command ready mirrors response_ready_i.", + "polarity": "active-high" + }, + "response_valid_o": { + "file": "rtl/managed/clusterip/rtc/rtl/rtc_core.sv", + "scope": "rtc_core", + "symbol": "response_valid_o", + "meaning": "Response valid directly mirrors command_valid_i.", + "polarity": "active-high" + }, + "response_ready_i": { + "file": "rtl/managed/clusterip/rtc/rtl/rtc_core.sv", + "scope": "rtc_core", + "symbol": "response_ready_i", + "meaning": "Response sink eventually accepts the transaction.", + "polarity": "active-high" + } + }, + "review_sources": [ + "rtl/managed/clusterip/rtc/rtl/rtc_core.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Corrected the old artificial command-busy/response delay; reviewed the direct ready/valid assignments in rtc_core." + }, + "wdg": { + "source": { + "signal": [ + { + "name": "active_o", + "wave": "1.......0" + }, + { + "name": "window_open_o", + "wave": "0.10.1..0" + }, + { + "name": "s_service_command", + "wave": "0.10....." + }, + { + "name": "warning_active_o", + "wave": "0.....1.0" + }, + { + "name": "reset_req_o", + "wave": "0.......1" + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: wdg_core. Clock: clk_i (watchdog reference domain); elapsed count intervals omitted. A legal service occurs while the window is open; a later unserviced interval reaches early warning and timeout. Programmed timeouts, prescale clocks and reset-pulse duration are not drawn to scale. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "active_o": { + "file": "rtl/managed/clusterip/wdg/rtl/wdg_core.sv", + "scope": "wdg_core", + "symbol": "active_o", + "meaning": "Watchdog active through service and later timeout.", + "polarity": "active-high" + }, + "window_open_o": { + "file": "rtl/managed/clusterip/wdg/rtl/wdg_core.sv", + "scope": "wdg_core", + "symbol": "window_open_o", + "meaning": "Service window opens, closes on reload, then opens again.", + "polarity": "active-high" + }, + "s_service_command": { + "file": "rtl/managed/clusterip/wdg/rtl/wdg_core.sv", + "scope": "wdg_core", + "symbol": "s_service_command", + "meaning": "Accepted legal service command during the first open window.", + "polarity": "active-high" + }, + "warning_active_o": { + "file": "rtl/managed/clusterip/wdg/rtl/wdg_core.sv", + "scope": "wdg_core", + "symbol": "warning_active_o", + "meaning": "Early warning before the later unserviced timeout.", + "polarity": "active-high" + }, + "reset_req_o": { + "file": "rtl/managed/clusterip/wdg/rtl/wdg_core.sv", + "scope": "wdg_core", + "symbol": "reset_req_o", + "meaning": "Reset request asserted on terminal timeout.", + "polarity": "active-high" + } + }, + "review_sources": [ + "rtl/managed/clusterip/wdg/rtl/wdg_core.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Mapped actual window, accepted-service predicate, warning and reset outputs; removed abstract count-phase and valid-service names." + }, + "uart": { + "source": { + "signal": [ + { + "name": "tx_o", + "wave": "101010.101.." + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: uart_core. Clock: clk_i; displayed intervals are programmed serial bit periods. 8N1 transmission of 0xA5, least-significant bit first: idle, start, eight data bits and stop. Oversampling clocks are omitted. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "tx_o": { + "file": "rtl/ip/serial/uart_core.sv", + "scope": "uart_core", + "symbol": "tx_o", + "meaning": "Transmitted serial output, idle and stop high.", + "polarity": "data" + } + }, + "review_sources": [ + "rtl/ip/serial/apb4_uart_tx.sv", + "rtl/ip/serial/uart_core.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Removed synthetic bit-slot clock and moved payload/configuration into the note; retained the valid TX bit sequence." + }, + "i2c": { + "source": { + "signal": [ + { + "name": "scl_i", + "wave": "1.0.1.0.1.0.1.." + }, + { + "name": "sda_i", + "wave": "10.1...0.....1." + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: i2c_core. Clock: clk_i; observed serial SCL/SDA intervals. Representative data and acknowledge bit intervals, not a complete byte: START/STOP change SDA while SCL is high; other changes occur while SCL is low. Full address/data bytes are omitted. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "scl_i": { + "file": "rtl/ip/serial/i2c_core.sv", + "scope": "i2c_core", + "symbol": "scl_i", + "meaning": "Observed SCL after input filtering.", + "polarity": "rising-edge" + }, + "sda_i": { + "file": "rtl/ip/serial/i2c_core.sv", + "scope": "i2c_core", + "symbol": "sda_i", + "meaning": "Observed SDA, including START and STOP.", + "polarity": "data" + } + }, + "review_sources": [ + "rtl/ip/serial/i2c_core.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Removed phase labels and invalid multi-bit data notation on scalar SDA. Reviewed open-drain inputs and protocol transitions." + }, + "clint": { + "source": { + "signal": [ + { + "name": "tick_i", + "wave": "0101010." + }, + { + "name": "mtime_o", + "wave": "=.=.=.==", + "data": [ + "N-1", + "N", + "N+1", + "N+2", + "N+2" + ] + }, + { + "name": "mtimecmp_i[0]", + "wave": "=.....=.", + "data": [ + "N", + "N+8" + ] + }, + { + "name": "timer_irq_o[0]", + "wave": "0..1...0" + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: clint_core. Clock: clk_i; mtime tick and comparator update. Hart 0: the timer IRQ is a registered comparison of mtime_o against mtimecmp_i[0]. Updating compare above the current time deasserts the IRQ on a subsequent core edge; timebase tick spacing is illustrative. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "tick_i": { + "file": "rtl/ip/peripheral/clint_core.sv", + "scope": "clint_core", + "symbol": "tick_i", + "meaning": "Qualified timebase increments.", + "polarity": "active-high" + }, + "mtime_o": { + "file": "rtl/ip/peripheral/clint_core.sv", + "scope": "clint_core", + "symbol": "mtime_o", + "meaning": "MTIME advances through the programmed compare value.", + "polarity": "data" + }, + "mtimecmp_i[0]": { + "file": "rtl/ip/peripheral/clint_core.sv", + "scope": "clint_core", + "symbol": "mtimecmp_i", + "meaning": "Hart 0 compare is moved beyond the current time.", + "polarity": "data" + }, + "timer_irq_o[0]": { + "file": "rtl/ip/peripheral/clint_core.sv", + "scope": "clint_core", + "symbol": "timer_irq_o", + "meaning": "Registered timer interrupt follows comparison.", + "polarity": "active-high" + } + }, + "review_sources": [ + "rtl/ip/peripheral/clint_core.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Mapped mtime/mtimecmp aliases to ports and retained the registered comparator delay.", + "parameters": { + "HartNum": 1 + }, + "parameter_note": "Each LP or HP local interrupt block in this example has one hart." + }, + "archinfo": { + "source": { + "signal": [ + { + "name": "paddr_i", + "wave": "x=...x..", + "data": [ + "offset" + ] + }, + { + "name": "psel_i", + "wave": "01...0.." + }, + { + "name": "penable_i", + "wave": "0.1..0.." + }, + { + "name": "pwrite_i", + "wave": "0......." + }, + { + "name": "pready_o", + "wave": "1......." + }, + { + "name": "prdata_o", + "wave": "x=...x..", + "data": [ + "value" + ] + } + ], + "config": { + "hscale": 1, + "skin": "lowkey" + } + }, + "note": "Scope: archinfo_reg. Clock: APB combinational read boundary; sampled in its wrapper PCLK domain. Read-only identification register selection. pready_o is asserted combinationally; no invented internal PCLK port or multi-cycle read-result pipeline is implied. Tiny binds this interface/core to the system clock; illustrative order only, not measured timing.", + "clock_domain": "Tiny system clock, 24 MHz configured target", + "signals": { + "paddr_i": { + "file": "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv", + "scope": "archinfo_reg", + "symbol": "paddr_i", + "meaning": "Read register offset.", + "polarity": "data" + }, + "psel_i": { + "file": "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv", + "scope": "archinfo_reg", + "symbol": "psel_i", + "meaning": "APB select.", + "polarity": "active-high" + }, + "penable_i": { + "file": "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv", + "scope": "archinfo_reg", + "symbol": "penable_i", + "meaning": "APB access enable.", + "polarity": "active-high" + }, + "pwrite_i": { + "file": "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv", + "scope": "archinfo_reg", + "symbol": "pwrite_i", + "meaning": "Read transaction.", + "polarity": "active-high" + }, + "pready_o": { + "file": "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv", + "scope": "archinfo_reg", + "symbol": "pready_o", + "meaning": "Always-ready register interface.", + "polarity": "active-high" + }, + "prdata_o": { + "file": "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv", + "scope": "archinfo_reg", + "symbol": "prdata_o", + "meaning": "Read value selected by address.", + "polarity": "data" + } + }, + "review_sources": [ + "rtl/managed/clusterip/archinfo/rtl/archinfo_reg.sv", + "rtl/tiny/top/retrosoc_tiny.sv" + ], + "review_note": "Used the actual combinational archinfo_reg ports; corrected the fictitious PCLK/APB-read signal labels." + } +} diff --git a/publications/datasheets/tiny/waveforms.typ b/publications/datasheets/tiny/waveforms.typ new file mode 100644 index 00000000..36f33c5f --- /dev/null +++ b/publications/datasheets/tiny/waveforms.typ @@ -0,0 +1,56 @@ +#import "@preview/jogs:0.2.4": compile-js, call-js-function +#import "style.typ": ink, gold, muted, data, rhythm +#let wave-bytecode=compile-js(read(data.wave_renderer)) + +// Thread the palette index through nested WaveDrom groups without mutating +// the source dictionary. Codes 2-9 and '=' differ only in bus fill color. +#let color-signals(signals, start: 0) = { + let next = start + let colored = () + for signal in signals { + if type(signal) == array { + let (group, index) = color-signals(signal, start: next) + colored.push(group) + next = index + } else if type(signal) == dictionary and signal.at("wave", default: "").contains(regex("[=2-9]")) { + let row = signal + row.wave = row.wave.replace(regex("[=2-9]"), str(3 + calc.rem(next, 4))) + colored.push(row) + next += 1 + } else { + colored.push(signal) + } + } + (colored, next) +} + +#let color-wave-source(source) = { + let colored = source + if "signal" in source { colored.signal = color-signals(source.signal).first() } + colored +} + +// Keep the pinned SVG renderer and its geometry; override only valid bus fills. +// Signal names and edges remain readable independently of color. +#let wave-svg(key) = { + let entry = data.waveforms.at(key) + let svg = call-js-function(wave-bytecode,"wavy",json.encode(color-wave-source(entry.source))) + svg = svg.replace(regex("font-family:[^;]+;"), "font-family:Inter;") + svg = svg.replace(regex("font-family=\"[^\"]+\""), "font-family=\"Inter\"") + svg = svg.replace(regex("(?i)#(?:0041c4|0000ff|00f)\\b"), "#292C31") + svg = svg.replace("fill:blue", "fill:#292C31") + svg.replace("", "text{font-weight:400}.info{font-weight:400;font-style:normal}.s8{fill:#F4EFE4}.s9{fill:#E7EFF6}.s10{fill:#E8F1EA}.s11{fill:#EEEAF5}") +} + +#let timing(key, caption, instance:none) = { + let entry = data.waveforms.at(key) + block(width:100%,above:rhythm.figure-space,below:rhythm.figure-space,breakable:false)[ + #context metadata((kind:"tiny-diagram",id:"wave-"+if instance==none {key} else {instance},page:here().page())) + #show figure: set block(above:0pt,below:0pt) + #figure(image(bytes(wave-svg(key))), caption: caption) + #block(width:100%,above:rhythm.metadata-before,below:0pt)[ + #set par(leading:rhythm.small-leading,spacing:rhythm.small-spacing) + #align(center,text(9pt,fill:muted,entry.note)) + ] + ] +} diff --git a/publications/examples/tiny/archinfo.c b/publications/examples/tiny/archinfo.c new file mode 100644 index 00000000..514e0942 --- /dev/null +++ b/publications/examples/tiny/archinfo.c @@ -0,0 +1,10 @@ +#include + +rs_status_t example_archinfo(rs_archinfo_t *info) +{ + rs_status_t result = rs_archinfo_read(info); + if (result != RS_OK) { + return result; + } + return rs_archinfo_validate_build(info); +} diff --git a/publications/examples/tiny/clint.c b/publications/examples/tiny/clint.c new file mode 100644 index 00000000..413dd82a --- /dev/null +++ b/publications/examples/tiny/clint.c @@ -0,0 +1,6 @@ +#include + +rs_status_t example_clint(uint64_t *time) +{ + return rs_clint_get_time(time); +} diff --git a/publications/examples/tiny/dma.c b/publications/examples/tiny/dma.c new file mode 100644 index 00000000..dd3652f0 --- /dev/null +++ b/publications/examples/tiny/dma.c @@ -0,0 +1,10 @@ +#include + +rs_status_t example_dma(uint32_t channel, const rs_dma_config_t *config) +{ + rs_status_t result = rs_dma_configure(channel, config); + if (result != RS_OK) { + return result; + } + return rs_dma_start(channel); +} diff --git a/publications/examples/tiny/gpio.c b/publications/examples/tiny/gpio.c new file mode 100644 index 00000000..c78e000b --- /dev/null +++ b/publications/examples/tiny/gpio.c @@ -0,0 +1,6 @@ +#include + +rs_status_t example_gpio(uint32_t pin, const rs_gpio_config_t *config) +{ + return rs_gpio_configure(pin, config); +} diff --git a/publications/examples/tiny/i2c.c b/publications/examples/tiny/i2c.c new file mode 100644 index 00000000..a00710fe --- /dev/null +++ b/publications/examples/tiny/i2c.c @@ -0,0 +1,6 @@ +#include + +rs_status_t example_i2c(rs_i2c_bus_t bus, uint32_t source_clock_hz, uint32_t bus_hz) +{ + return rs_i2c_init(bus, source_clock_hz, bus_hz); +} diff --git a/publications/examples/tiny/pwm.c b/publications/examples/tiny/pwm.c new file mode 100644 index 00000000..126cb9ef --- /dev/null +++ b/publications/examples/tiny/pwm.c @@ -0,0 +1,6 @@ +#include + +rs_status_t example_pwm(void) +{ + return rs_pwm_probe(); +} diff --git a/publications/examples/tiny/rtc.c b/publications/examples/tiny/rtc.c new file mode 100644 index 00000000..8d45804b --- /dev/null +++ b/publications/examples/tiny/rtc.c @@ -0,0 +1,6 @@ +#include + +rs_status_t example_rtc(void) +{ + return rs_rtc_probe(); +} diff --git a/publications/examples/tiny/sram.c b/publications/examples/tiny/sram.c new file mode 100644 index 00000000..edebc889 --- /dev/null +++ b/publications/examples/tiny/sram.c @@ -0,0 +1,6 @@ +#include + +rs_status_t example_sram(rs_onchip_sram_info_t *info) +{ + return rs_onchip_sram_probe(info); +} diff --git a/publications/examples/tiny/sysctrl.c b/publications/examples/tiny/sysctrl.c new file mode 100644 index 00000000..763b2db8 --- /dev/null +++ b/publications/examples/tiny/sysctrl.c @@ -0,0 +1,4 @@ +#include +rs_status_t tiny_fault(rs_sysctrl_fault_status_t *status) { + return rs_sysctrl_get_fault_status(status); +} diff --git a/publications/examples/tiny/timer.c b/publications/examples/tiny/timer.c new file mode 100644 index 00000000..2dcba232 --- /dev/null +++ b/publications/examples/tiny/timer.c @@ -0,0 +1,10 @@ +#include + +rs_status_t example_timer(rs_timer_id_t timer, const rs_timer_config_t *config) +{ + rs_status_t result = rs_timer_configure(timer, config); + if (result != RS_OK) { + return result; + } + return rs_timer_start(timer); +} diff --git a/publications/examples/tiny/uart.c b/publications/examples/tiny/uart.c new file mode 100644 index 00000000..1f6f7903 --- /dev/null +++ b/publications/examples/tiny/uart.c @@ -0,0 +1,6 @@ +#include + +rs_status_t example_uart(uint32_t source_clock_hz, uint32_t baud_rate) +{ + return rs_uart_init(source_clock_hz, baud_rate); +} diff --git a/publications/examples/tiny/wdg.c b/publications/examples/tiny/wdg.c new file mode 100644 index 00000000..ccfa6a18 --- /dev/null +++ b/publications/examples/tiny/wdg.c @@ -0,0 +1,5 @@ +#include +rs_status_t tiny_watchdog_status(rs_watchdog_status_t *status) +{ + return rs_watchdog_get_status(status, RS_TIMEOUT_DEFAULT); +} diff --git a/publications/examples/tiny/xpi.c b/publications/examples/tiny/xpi.c new file mode 100644 index 00000000..555703fc --- /dev/null +++ b/publications/examples/tiny/xpi.c @@ -0,0 +1,6 @@ +#include + +rs_status_t example_xpi(void) +{ + return rs_xpi_probe(); +} diff --git a/publications/implementation_reference.py b/publications/implementation_reference.py index c1c1c099..0fe8bc43 100644 --- a/publications/implementation_reference.py +++ b/publications/implementation_reference.py @@ -34,7 +34,12 @@ def lp_parameters(text: str) -> dict[str, str]: matches = re.findall(r"\bhazard3_cpu_1port\s*#\s*\((.*?)\)\s+u_hazard3_cpu_1port\s*\(", without_comments(text), re.S) if len(matches) != 1: raise ValueError("LP instance missing or ambiguous") - return unique_pairs(re.findall(r"\.([A-Z][A-Z0-9_]*)\s*\(([^()]*)\)", matches[0]), "LP") + parameters = unique_pairs(re.findall(r"\.([A-Z][A-Z0-9_]*)\s*\(([^()]*)\)", matches[0]), "LP") + # The fixed Mini integration uses the shared wrapper's Boolean feature + # defaults. Keep configurable integer expressions (notably IRQ count) intact. + defaults = dict(re.findall(r"parameter\s+bit\s+(\w+)\s*=\s*1'b([01])", without_comments(text))) + return {name: defaults.get(value, value) if name.startswith("EXTENSION_") else value + for name, value in parameters.items()} def hp_parameters(text: str) -> tuple[dict[str, str], list[str]]: @@ -109,7 +114,7 @@ def validate_details(spec: dict, ids: set[str], root: Path, active_limits: set[s def collect_details(root: Path, spec: dict, ids: set[str], active_limits: set[str]) -> dict: validate_details(spec, ids, root, active_limits) - lp = lp_parameters((root / "rtl/mini/top/mgmt_core_wrapper.sv").read_text(encoding="utf-8")) + lp = lp_parameters((root / "rtl/ip/core/mgmt_core_wrapper.sv").read_text(encoding="utf-8")) hp_source = (root / "scripts/vexiiriscv/GenerateRetroSocHp.scala").read_text(encoding="utf-8") hp, hp_isa = hp_parameters(hp_source) for required, actual, name in ((spec["cpu"]["lp_fields"], lp, "LP"), (spec["cpu"]["hp_fields"], hp, "HP")): diff --git a/publications/programming_reference.py b/publications/programming_reference.py index 00c9e991..ca4de1e9 100644 --- a/publications/programming_reference.py +++ b/publications/programming_reference.py @@ -111,11 +111,11 @@ def buffer_budget(kind: str, *, width=0, height=0, rate=0, bits=0, milliseconds= "total_bytes": stride * count, "dma_supported": supported} -def constants(text: str, prefix: str, rtl=False) -> dict[str, int]: +def constants(text: str, prefix: str, rtl=False, *, exclude: frozenset[str] = frozenset()) -> dict[str, int]: text = re.sub(r"/\*.*?\*/|//[^\n]*", "", text, flags=re.S) pattern = (rf"\b({prefix}\w+)\s*=\s*\d+'d(\d+)\s*;" if rtl else rf"\b({prefix}\w+)\s*(?:=\s*|\s+)(\d+)(?:U)?(?=\s*[,;\n])") - pairs = re.findall(pattern, text) + pairs = [(name, value) for name, value in re.findall(pattern, text) if name not in exclude] if len({name for name, _ in pairs}) != len(pairs): raise ValueError(f"duplicate constant: {prefix}") return {name: int(value) for name, value in pairs} @@ -194,8 +194,10 @@ def collect_programming(root: Path, spec: dict, ids: set[str], revision: str) -> sdk_text = (root / "crt/include/retrosoc/hal/dma.h").read_text() sdk = constants(sdk_text, "RS_DMA_REQUEST_") channels = constants(sdk_text, "RS_DMA_CHANNEL_") - channels.update(constants((root / "crt/include/retrosoc/hal/dma_regs.h").read_text(), "RS_DMA_CHANNEL_")) - channels.pop("RS_DMA_CHANNEL_COUNT") + # Capacity is selected by product; it is not a named channel allocation. + # Keep the Mini publication's role inventory independent of Tiny's count. + channels.update(constants((root / "crt/include/retrosoc/hal/dma_regs.h").read_text(), + "RS_DMA_CHANNEL_", exclude=frozenset({"RS_DMA_CHANNEL_COUNT"}))) if {r["symbol"] for r in spec["channels"]} != set(channels): raise ValueError("DMA channel allocation coverage mismatch") for row in result["dma_routes"]: diff --git a/publications/register_reference.py b/publications/register_reference.py index b82ea471..436712c9 100644 --- a/publications/register_reference.py +++ b/publications/register_reference.py @@ -21,6 +21,22 @@ LITERAL = re.compile(r"(?P\d+)?'[sS]?(?P[hHbBdDoO])(?P[0-9a-fA- def number(expression: str, constants: dict[str, int] | None = None) -> int: constants = constants or {} expression = " ".join(expression.split()).replace("`", "") + # Preserve sized-cast truncation and unwrap a complete parenthesized + # expression before looking for an SV conditional at its top level. + while expression.startswith("(") and expression.endswith(")"): + depth = 0 + enclosed = True + for index, character in enumerate(expression): + depth += (character == "(") - (character == ")") + if depth == 0 and index != len(expression) - 1: + enclosed = False + break + if not enclosed or depth != 0: + break + expression = expression[1:-1].strip() + sized_cast = re.fullmatch(r"(\d+)'\(([^()]*)\)", expression) + if sized_cast: + return number(sized_cast[2], constants) & ((1 << int(sized_cast[1])) - 1) expression = LITERAL.sub( lambda m: str( int(m["digits"].replace("_", ""), {"h": 16, "b": 2, "d": 10, "o": 8}[m["base"].lower()]) @@ -125,10 +141,11 @@ def named_argument(text: str, name: str) -> str | None: raise ValueError(f"unclosed {name} argument") -def parse_definitions(paths: list[str], extra: dict[str, int]) -> tuple[dict, dict]: +def parse_definitions(paths: list[str], extra: dict[str, int], + memory_map: str = "rtl/mini/address_map/memory_map.json") -> tuple[dict, dict]: definitions = {} constants = dict(extra) - memory = json.loads((ROOT / "rtl/mini/address_map/memory_map.json").read_text()) + memory = json.loads((ROOT / memory_map).read_text(encoding="utf-8")) constants.update( { f"SOC_SYSCTRL_{r['symbol']}_OFFSET": int(r["offset"], 0) @@ -139,7 +156,7 @@ def parse_definitions(paths: list[str], extra: dict[str, int]) -> tuple[dict, di key = f"SOC_SYSCTRL_{register['symbol']}_OFFSET" definitions[key] = { "expression": f"16'h{int(register['offset'], 0):04x}", - "source": "rtl/mini/address_map/memory_map.json", + "source": memory_map, "line": 1, } for path in paths: @@ -151,7 +168,7 @@ def parse_definitions(paths: list[str], extra: dict[str, int]) -> tuple[dict, di "line": text.count("\n", 0, match.start()) + 1, } for match in re.finditer( - r"\b(?:localparam|parameter)\s+(?:(?:int(?:\s+unsigned)?|logic(?:\s*\[[^]]+\])?|\w+_t)\s+)?" + r"\b(?:localparam|parameter)\s+(?:(?:int(?:\s+unsigned)?|bit|logic(?:\s*\[[^]]+\])?|\w+_t)\s+)?" r"(\w+)\s*=\s*([^;\n]+)", text, ): @@ -165,7 +182,7 @@ def parse_definitions(paths: list[str], extra: dict[str, int]) -> tuple[dict, di }, ) for match in re.finditer( - r"\blocalparam\s+(?:int(?:\s+unsigned)?|logic(?:\s*\[[^]]+\])?|\w+_t)\s+(\w+)\s*=\s*([^;]+);", + r"\blocalparam\s+(?:int(?:\s+unsigned)?|bit|logic(?:\s*\[[^]]+\])?|\w+_t)\s+(\w+)\s*=\s*([^;]+);", text, ): definitions[match[1]] = { @@ -694,7 +711,8 @@ def refine_fields(record: dict, spec: dict, definitions: dict, model: dict) -> l def extract_profile(ip: str, spec: dict, annotations: dict) -> dict: paths = list(dict.fromkeys(spec.get("defines", []) + spec["rtl"])) - definitions, constants = parse_definitions(paths, spec.get("parameters", {})) + memory_map = spec.get("memory_map", "rtl/mini/address_map/memory_map.json") + definitions, constants = parse_definitions(paths, spec.get("parameters", {}), memory_map) text = "\n".join(strip_comments((ROOT / p).read_text(encoding="utf-8")) for p in spec["rtl"]) model = source_model(text, constants) model["definitions"] = definitions @@ -712,7 +730,7 @@ def extract_profile(ip: str, spec: dict, annotations: dict) -> dict: if support_module is None: continue _, support_constants = parse_definitions( - spec.get("defines", []) + [source], spec.get("parameters", {}) + spec.get("defines", []) + [source], spec.get("parameters", {}), memory_map ) support_model = source_model(support_text, support_constants) support_model["module"] = support_module[1] diff --git a/publications/tiny_reference.py b/publications/tiny_reference.py new file mode 100644 index 00000000..294f4514 --- /dev/null +++ b/publications/tiny_reference.py @@ -0,0 +1,278 @@ +"""Tiny-only publication assembly; no Mini product collector or data is loaded.""" +from __future__ import annotations + +import copy +import ctypes +import dataclasses +import json +import re +import subprocess +from pathlib import Path + +from publications import register_reference as registers +from publications.waveform_reference import source_paths as wave_sources, validate_waveforms +from scripts.check_clock_reset_domains import validate as validate_clocks +from scripts.generate_tiny import read_topology +from scripts.rtl.generate_memory_map import read_map as read_memory +from scripts.rtl.generate_pin_map import read_map as read_pins + +ROOT = Path(__file__).resolve().parents[1] +BOOK = Path("publications/datasheets/tiny") +MAP = "rtl/tiny/address_map/memory_map.json" +TOPOLOGY = "rtl/tiny/integration/soc_topology.json" +PINS = "rtl/tiny/pin_map/pin_map.json" +CLOCKS = "rtl/tiny/integration/clock_reset_domains.json" +TOP = "rtl/tiny/top/retrosoc_tiny.sv" +SYSCTRL = "rtl/tiny/top/tiny_sysctrl.sv" +ARCHINFO = "rtl/tiny/top/tiny_archinfo.sv" +FAMILIES = {"xpi", "sram", "gpio", "dma", "timer", "pwm", "rtc", "wdg", "uart", "i2c", "clint", "archinfo"} +MANAGED = {"publication_media", "hazard3", "cluster_common", "cluster_archinfo", "cluster_pwm", "cluster_rtc", "cluster_wdg"} +SUPPORTED_SYSCTRL = { + "CORESEL", "IPSEL", "USER_CORE_RESET", "USER_CORE_STATUS", "FAULT_STATUS", "FAULT_ADDR", + "FAULT_COUNT", "FAULT_MASTER", "FAULT_DETAIL", "PERF_CTRL", "PERF_MGMT_WAIT_LO", + "PERF_MGMT_WAIT_HI", "PERF_DMA_WAIT_LO", "PERF_DMA_WAIT_HI", "TEST_STATUS", "RTC_WAKE_STATUS", +} + + +def read(path: Path): + return json.loads(path.read_text(encoding="utf-8")) + + +def profile_values(path: Path) -> dict[str, str]: + return dict(re.findall(r"^\s*(\w+)\s*:?=\s*([^\s#]+)", path.read_text(encoding="utf-8"), re.M)) + + +def instance_parameters(text: str, module: str, instance: str) -> dict[str, int]: + found = re.findall(rf"\b{module}\s*#\s*\((.*?)\)\s+{instance}\s*\(", text, re.S) + if len(found) != 1: + raise ValueError(f"missing or ambiguous Tiny instance: {instance}") + return {name: registers.number(value) for name, value in re.findall(r"\.(\w+)\s*\(([^()]*)\)", found[0])} + + +def require_snippets(root: Path, path: str, snippets: list[str]) -> None: + text = re.sub(r"\s+", "", registers.strip_comments((root / path).read_text(encoding="utf-8"))) + for snippet in snippets: + if re.sub(r"\s+", "", snippet) not in text: + raise ValueError(f"Tiny behavior binding changed: {path}: {snippet}") + + +def facts(root: Path = ROOT) -> dict: + profile = profile_values(root / "configs/ci/ihp130-tiny.mk") + required = {"SOC": "TINY", "PDK": "IHP130", "HAVE_HP": "NO", "HAVE_PLL": "NO", + "SRAM_SIZE_KIB": "128", "EXT_CLK_HZ": "24000000", "ISA": "RV32IM", + "HAVE_CSR": "YES", "LINK_TYPE": "ld2_all_sram"} + if any(profile.get(key) != value for key, value in required.items()): + raise ValueError("Tiny publication profile changed; review configuration and ISA boundary") + top = (root / TOP).read_text(encoding="utf-8") + ram = instance_parameters(top, "onchip_ram", "u_sram") + dma = instance_parameters(top, "apb4_dma", "u_dma") + cpu = instance_parameters(top, "mgmt_core_wrapper", "u_cpu") + if ram != {"CapacityKiB": 128, "DataWidth": 32, "IdWidth": 1}: + raise ValueError("Tiny SRAM parameters changed") + if dma != {"NumChannels": 4, "MaxBurstBeats": 16, "FifoDepth": 32, "RequestMask": 0x7F9, "EnableStreams": 0}: + raise ValueError("Tiny DMA parameters changed") + if cpu != {"ExternalIrqCount": 30, "EnableAtomics": 0, "TwoCycleBusErrors": 1}: + raise ValueError("Tiny CPU integration changed") + require_snippets(root, "rtl/ip/core/mgmt_core_wrapper.sv", [".EXTENSION_C(1)", ".EXTENSION_A(EnableAtomics)"]) + require_snippets(root, TOP, ["u_masters_axi4_if[2]", ".axi4(u_masters_axi4_if[0])", + ".axi4(u_masters_axi4_if[1])", ".cfg_apb4(u_sram_apb4_if)", + "assign s_tick = s_tick_count_q == 5'd23;"]) + require_snippets(root, SYSCTRL, ["(apb4.paddr[1:0] != 2'd0)", "(apb4.pstrb != 4'hf)", + "if (!s_test_q[31] && apb4.pwdata[31]) s_test_d = apb4.pwdata & 32'h8000_ff01;", + "if (!s_fault_stat_d[0])", "if (rtc_wake_i) s_wake_d = 1'b1;"]) + arch = instance_parameters((root / ARCHINFO).read_text(encoding="utf-8").split(".BUILD_ID")[0] + ") u_archinfo (", "apb4_archinfo", "u_archinfo") + if arch != {"REFERENCE_CLOCK_HZ": 24000000, "SRAM_BYTES": 131072, "TOPOLOGY": 0x20200001, + "FEATURES0": 0x7FFE, "TECHNOLOGY": 0x02010082}: + raise ValueError("Tiny discovery parameters changed") + require_snippets(root, ARCHINFO, ["32'h5449_4e59 : u_info_apb4_if.prdata", ".device_id_valid_i(1'b0)", ".device_id_read_enable_i(1'b0)"]) + return {"profile": profile, "sram": ram, "dma": dma, "cpu": cpu, "archinfo": arch, + "hardware_isa": "RV32IMC", "firmware_isa": profile["ISA"], "soc_id": 0x54494E59, + "system_hz": int(profile["EXT_CLK_HZ"]), "timebase_hz": int(profile["CLINT_TIMEBASE_HZ"])} + + +def field_rows(parts: list[tuple[str, int, int, str]]) -> list[dict]: + rows, used = [], set() + for name, low, high, description in parts: + rows.append(dict(name=name, lsb=low, msb=high, description=description, reset="0", expression="Tiny source-bound field")) + if used.intersection(range(low, high + 1)): + raise ValueError("overlapping Tiny SYSCTRL field") + used.update(range(low, high + 1)) + for low in range(32): + if low in used: + continue + high = low + while high + 1 < 32 and high + 1 not in used: + high += 1 + used.update(range(low, high + 1)) + rows.append(dict(name="Reserved", lsb=low, msb=high, description="Reads zero; use zero when writing. No stored state.", reset="0", expression="zero")) + return sorted(rows, key=lambda row: row["lsb"]) + + +def sysctrl_registers(root: Path) -> dict: + text = (root / SYSCTRL).read_text(encoding="utf-8") + read_case = text.split("unique case (s_offset)")[1].split("endcase")[0] + active = set(re.findall(r"`APB4_SYSCTRL__(\w+)", read_case)) + if active != SUPPORTED_SYSCTRL: + raise ValueError("Tiny SYSCTRL decode coverage changed") + offsets = {r["symbol"]: int(r["offset"], 0) for r in read(root / MAP)["sysctrl_registers"]} + definitions = { + "FAULT_STATUS": ("RW1C", "Sticky first fault. Bit 0 clears pending; a new fault can win after clear.", [("PENDING", 0, 0, "A fault record is pending."), ("WRITE", 1, 1, "Faulting transaction was a write."), ("CLASS", 2, 4, "1: decode error; 2: protocol/target error.")]), + "FAULT_MASTER": ("RO", "Master of the captured first fault.", [("MASTER", 0, 0, "0 CPU, 1 DMA.")]), + "FAULT_DETAIL": ("RO", "Captured AXI response code.", [("RESPONSE", 0, 1, "AXI RRESP/BRESP encoding.")]), + "PERF_CTRL": ("RW / command", "Enable counters, clear counters/snapshots or capture a coherent pair. Clear takes precedence over snapshot.", [("ENABLE", 0, 0, "Counter enable state."), ("CLEAR", 1, 1, "Write-one pulse; reads zero."), ("SNAPSHOT", 2, 2, "Write-one pulse; reads zero.")]), + "TEST_STATUS": ("RW sticky", "First full-word valid result is sticky until system reset; write mask 0x8000FF01.", [("PASS", 0, 0, "Pass when valid is set."), ("CODE", 8, 15, "Application-defined result code."), ("VALID", 31, 31, "The first valid write locks the result.")]), + "RTC_WAKE_STATUS": ("RO / W1C", "Live wake and sticky observation; hardware set wins over clear.", [("LIVE", 0, 0, "Live RTC wake input."), ("SEEN", 1, 1, "Sticky seen flag; write one to clear.")]), + } + rows = [] + for name in sorted(active, key=offsets.get): + default = "Read-only compatibility value; no selectable core or IP." if name in {"CORESEL", "IPSEL", "USER_CORE_RESET", "USER_CORE_STATUS"} else ( + "Saturating count of fault events; clearing pending does not clear this count." if name == "FAULT_COUNT" else + "Captured first-fault address." if name == "FAULT_ADDR" else "Word of the CPU/DMA wait-counter snapshot; capture through PERF_CTRL before combining halves.") + access, description, parts = definitions.get(name, ("RO", default, [("VALUE", 0, 31, default)])) + reset = 0xFFFFFFFF if name == "USER_CORE_RESET" else 0x200 if name == "USER_CORE_STATUS" else 0 + fields = field_rows(parts) + for f in fields: + f["reset"] = hex((reset >> f["lsb"]) & ((1 << (f["msb"] - f["lsb"] + 1)) - 1)) + rows.append(dict(key="main." + name, name=name, symbol="APB4_SYSCTRL__" + name, offset=offsets[name], group="main", + width=32, access=access, reset=f"0x{reset:08X}", rtl_reset=f"0x{reset:08X}", description=description, + fields=fields, source=SYSCTRL, line=text[:text.index("`APB4_SYSCTRL__" + name)].count("\n") + 1, + c_source="crt/include/retrosoc/hal/sysctrl.h", review=None, readback=[])) + return dict(id="sysctrl", groups=[dict(id="main", title="Tiny control and diagnostics", base=0, stride=0, count=1)], + registers=rows, document="docs/ip/tiny-soc.md", sources=[SYSCTRL, MAP, "rtl/ip/peripheral/sysctrl_define.svh", "crt/include/retrosoc/hal/sysctrl.h", "crt/src/hal/sysctrl.c"]) + + +def collect_registers(fact: dict, root: Path = ROOT) -> dict: + profiles = read(root / BOOK / "register-profiles.json") + annotations = read(root / BOOK / "register-annotations.json") + if set(profiles) != FAMILIES or any(s.get("memory_map") != MAP for s in profiles.values()): + raise ValueError("Tiny register families must be independent of Mini") + profiles["sram"]["parameters"].update(CapacityKiB=fact["sram"]["CapacityKiB"], BankCount=32, DataBytes=4) + profiles["dma"]["parameters"].update(NumChannels=fact["dma"]["NumChannels"], EnableStreams=0, ChannelIndexWidth=2) + profiles["dma"]["groups"][1]["count"] = fact["dma"]["NumChannels"] + profiles["archinfo"]["parameters"].update(fact["archinfo"]) + result = {name: registers.extract_profile(name, spec, annotations.get(name, {})) for name, spec in profiles.items()} + info = result["archinfo"] + info["sources"].append(ARCHINFO) + for reg in info["registers"]: + if reg["name"] == "SOC_ID": + value = fact["soc_id"] + reg.update(reset=f"0x{value:08X}", rtl_reset=f"0x{value:08X}", readback=["Tiny adapter constant 0x54494E59"], description="Tiny SoC identity supplied by the owned adapter.", source=ARCHINFO, line=28, + fields=[dict(name="SOC_ID", lsb=0, msb=31, description="ASCII TINY; validate before using product-specific controls.", reset=hex(value), expression="Tiny adapter constant")]) + if reg["name"] in {"BUILD_ID_LO", "BUILD_ID_HI", "CONFIG_ID", "BUILD_STATUS"}: + reg.pop("rtl_reset", None) + reg["reset"] = "Build-dependent" + for f in reg["fields"]: + f["reset"] = "Build-dependent" + result["sysctrl"] = sysctrl_registers(root) + registers.validate_reference(result) + validate_register_inventory(result, read(root / BOOK / "register-contract.json")) + return result + + +def validate_register_inventory(reference: dict, expected: dict) -> None: + actual = {family: {r["key"]: r["offset"] for r in value["registers"]} for family, value in reference.items()} + if actual != expected: + raise ValueError("Tiny frozen register inventory has missing, extra or changed entries") + + +def validate_evidence(value: dict) -> None: + if value.get("status") != "prototype" or value.get("current_commit_reports") != []: + raise ValueError("Tiny qualification requires matching independently reviewed reports") + if value.get("historical_source") != "docs/ip/tiny-soc-verification.md" or not value.get("boundary"): + raise ValueError("Tiny historical evidence needs its source and scope") + + +def validate_configuration(config: dict) -> None: + expected = {"title": "retroSoC Tiny Gen1", "document_id": "RS-TINY-DS", "status": "DRAFT", + "profile": "configs/ci/ihp130-tiny.mk", "entrypoint": "publications/datasheets/tiny/datasheet.typ", + "filename": "retrosoc-tiny-gen1-datasheet.pdf"} + if any(config.get(key) != value for key, value in expected.items()): + raise ValueError("Tiny publication configuration cannot select another product or claim release") + + +def validate_maps(root: Path, fact: dict) -> tuple: + topology = read_topology(root / TOPOLOGY, root / MAP) + reset, regions, _ = read_memory(root / MAP, fact["sram"]["CapacityKiB"]) + contract = read(root / BOOK / "source-contract.json") + if {r["symbol"]: (r["base"], r["size"]) for r in regions} != {k: tuple(v) for k, v in contract["regions"].items()}: + raise ValueError("Tiny address coverage changed") + if {r["name"]: r["core_bit"] for r in topology["interrupts"]} != contract["interrupts"]: + raise ValueError("Tiny interrupt coverage changed") + return reset, regions, topology + + +def collect(config: dict, *, check_snapshot: bool = True) -> dict: + validate_configuration(config) + fact = facts() + reset, regions, topology = validate_maps(ROOT, fact) + pads, _ = read_pins(ROOT / PINS) + validate_clocks(ROOT / CLOCKS, ROOT) + contract = read(ROOT / BOOK / "source-contract.json") + for binding in contract["bindings"]: + require_snippets(ROOT, binding["file"], binding["text"]) + refs = collect_registers(fact) + catalog = read(ROOT / BOOK / "catalog.json") + index = read(ROOT / BOOK / "chapter-index.json") + frozen_ids = read(ROOT / BOOK / "structure-contract.json")["ip_ids"] + if ([r["id"] for r in catalog] != [r["id"] for r in index] or [r["id"] for r in index] != frozen_ids + or len(catalog) != 14 or any(r["family"] not in refs for r in catalog)): + raise ValueError("Tiny IP inventory must contain the fourteen reviewed chapters") + assigned = {r for row in catalog for r in row["regions"]} + if assigned != {r["symbol"] for r in regions} or sum(len(r["regions"]) for r in catalog) != len(assigned): + raise ValueError("Tiny catalog misses an address region") + waves = read(ROOT / BOOK / "waveforms.json") + audit = validate_waveforms(waves, ROOT) + evidence = read(ROOT / BOOK / "evidence.json") + validate_evidence(evidence) + lock = read(ROOT / "dependencies/dependencies.lock.json") + paths = {MAP, TOPOLOGY, PINS, CLOCKS, TOP, SYSCTRL, ARCHINFO, config["profile"], + "docs/ip/tiny-soc.md", "docs/ip/tiny-soc-verification.md", "dependencies/dependencies.lock.json", "LICENSE"} + paths.update(contract["sources"]) + paths.update(b["file"] for b in contract["bindings"]) + paths.update(wave_sources(waves)) + for item in refs.values(): + paths.update(item["sources"]) + paths.add(item["document"]) + for row in catalog: + paths.update(row["sources"]) + for template in (ROOT / BOOK).glob("*.typ"): + paths.update(re.findall(r'source(?:-note)?\(\s*"([^"]+)"', template.read_text(encoding="utf-8"))) + examples, apis = {}, {} + for family in refs: + alias = {"sram": "onchip_sram", "wdg": "watchdog"}.get(family, family) + header = "crt/include/retrosoc/" + ("core/archinfo.h" if family == "archinfo" else f"hal/{alias}.h") + paths.add(header) + declarations = re.findall(r"\b((?:rs_status_t|void|bool|uint\d+_t)\s+(rs_\w+)\s*\([^;{}]*\));", (ROOT / header).read_text(encoding="utf-8")) + apis[family] = [dict(name=name, signature=" ".join(signature.split()) + ";") for signature, name in declarations + if family != "sysctrl" or any(term in name for term in ("fault", "perf", "test_status", "rtc_wake"))] + path = ROOT / "publications/examples/tiny" / f"{family}.c" + if path.is_file(): + paths.add(path.relative_to(ROOT).as_posix()) + examples[family] = path.read_text(encoding="utf-8") + header_text = (ROOT / "crt/include/retrosoc/hal/dma.h").read_text(encoding="utf-8") + tcd_text = re.search(r"typedef struct\s*\{([^}]+)\}\s*rs_dma_tcd_t;", header_text) + members = re.findall(r"(uint32_t|int32_t|uint16_t)\s+(\w+)\s*;", tcd_text[1]) + types = {"uint32_t": ctypes.c_uint32, "int32_t": ctypes.c_int32, "uint16_t": ctypes.c_uint16} + layout = type("TinyTcd", (ctypes.Structure,), {"_fields_": [(name, types[kind]) for kind, name in members]}) + if ctypes.sizeof(layout) != 64 or len(members) != 17: + raise ValueError("Tiny TCD layout changed") + tcd = [dict(name=name, offset=getattr(layout, name).offset, bytes=ctypes.sizeof(types[kind]), + role="reserved" if "reserved" in name else "HAL result" if name in {"crc_result", "status", "bytes_done", "error_status"} else "configuration") for kind, name in members] + for relative in paths: + if relative.startswith("rtl/mini/") or not (ROOT / relative).is_file(): + raise ValueError(f"Tiny source missing or product leak: {relative}") + if check_snapshot: + if not re.fullmatch(r"[a-f0-9]{40}", config["source_revision"]): + raise ValueError("Tiny requires a complete reviewed SHA") + technical = sorted(p for p in paths if not p.startswith("publications/") and p != "dependencies/dependencies.lock.json") + changed = subprocess.check_output(["git", "diff", "--name-only", config["source_revision"], "--", *technical], cwd=ROOT, text=True).strip() + if changed: + raise ValueError("Tiny technical sources differ from reviewed snapshot:\n" + changed) + for r in regions: + r.update(base_hex=f"0x{r['base']:08X}", end_hex=f"0x{r['end']:08X}", size_label=f"{r['size'] // 1024} KiB") + return dict(document=config, facts=fact, reset_address=f"0x{reset:08X}", regions=regions, interrupts=topology["interrupts"], gpio=topology["gpio_alt_functions"], + pads=[dataclasses.asdict(p) for p in pads], clocks=read(ROOT / CLOCKS)["domains"], registers=refs, catalog=catalog, + chapter_index=index, waveforms=waves, waveform_audit=audit, source_paths=sorted(paths), + managed_sources=[v for k, v in lock["sources"].items() if k in MANAGED], + wave_renderer="/" + lock["archives"]["typst_wavy"]["destination"] + "/wavy.js", + evidence=copy.deepcopy(evidence), examples=examples, apis=apis, tcd=tcd) diff --git a/rtl/README.md b/rtl/README.md index 0eac5fd4..418c2b2d 100644 --- a/rtl/README.md +++ b/rtl/README.md @@ -1,10 +1,11 @@ # RTL Design and Simulation This directory contains retroSoC SystemVerilog RTL, CPU/IP integration, -peripheral and technology wrappers, filelists, testbench support, and the Mini +peripheral and technology wrappers, filelists, testbench support, and the Mini/Tiny SoC build entry points. -`mini/` is the active SoC integration flow. `managed/` contains locked or +`mini/` and `tiny/` own independent product integrations. Tiny is the single-hart +AXI32/APB4 wired MCU described in [its contract](../docs/ip/tiny-soc.md). `managed/` contains locked or vendored integration inputs, `ip/` contains self-owned IP and experiments, and `model/` contains committed device simulation models with preserved upstream notices. `filelist/` selects PDK-specific RTL sources; `tech/` contains diff --git a/rtl/ip/README.md b/rtl/ip/README.md index c6a9a238..d9b4ae76 100644 --- a/rtl/ip/README.md +++ b/rtl/ip/README.md @@ -1,11 +1,14 @@ -# RIB and Experimental IP +# Shared RTL IP This directory owns project RTL IP. Self-owned IP is grouped by function: interconnect, util, memory, storage, -serial, USB, multimedia, and peripheral. The Mini SoC selects active sources -explicitly in rtl/mini/filelist/ip.fl, whose source order is part of -the build contract. +serial, USB, multimedia, and peripheral. Mini and Tiny select active sources +explicitly in their product filelists. +Source order is part of the build contract. Shared Hazard3/debug wrappers are +in `core`, AXI adapters in `interconnect`, and native AXI SRAM in `memory`. +Both products reference these shared files directly in their own filelists. +Tiny does not select any RIB/RIBP module. experimental contains retained inactive RTL. It is not included by any active filelist and must not become a build dependency without an explicit integration diff --git a/rtl/mini/top/mgmt_core_wrapper.sv b/rtl/ip/core/mgmt_core_wrapper.sv similarity index 97% rename from rtl/mini/top/mgmt_core_wrapper.sv rename to rtl/ip/core/mgmt_core_wrapper.sv index 502fcd29..e0c7cfa2 100644 --- a/rtl/mini/top/mgmt_core_wrapper.sv +++ b/rtl/ip/core/mgmt_core_wrapper.sv @@ -11,7 +11,9 @@ `include "mmap_define.svh" module mgmt_core_wrapper #( - parameter int ExternalIrqCount = 30 + parameter int ExternalIrqCount = 30, + parameter bit EnableAtomics = 1'b1, + parameter bit TwoCycleBusErrors = 1'b0 ) ( // verilog_format: off -- preserve reviewed column alignment input logic clk_i, @@ -58,7 +60,7 @@ module mgmt_core_wrapper #( .hclk(clk_i), .hresetn(s_core_rst_n) ); - ahbl2axi4 u_ahbl2axi4 ( + ahbl2axi4 #(.TwoCycleErrors(TwoCycleBusErrors)) u_ahbl2axi4 ( .ahbl (u_ahbl_if), .axi4 (axi4), .idle_o(s_ahbl_idle) @@ -103,7 +105,7 @@ module mgmt_core_wrapper #( hazard3_cpu_1port #( .RESET_VECTOR (`SOC_CPU_RESET_ADDR), .MTVEC_INIT (32'h0000_0000), - .EXTENSION_A (1), + .EXTENSION_A (EnableAtomics), .EXTENSION_C (1), .EXTENSION_E (0), .EXTENSION_M (1), diff --git a/rtl/mini/top/mgmt_debug_reset.sv b/rtl/ip/core/mgmt_debug_reset.sv similarity index 100% rename from rtl/mini/top/mgmt_debug_reset.sv rename to rtl/ip/core/mgmt_debug_reset.sv diff --git a/rtl/mini/top/mgmt_debug_wrapper.sv b/rtl/ip/core/mgmt_debug_wrapper.sv similarity index 100% rename from rtl/mini/top/mgmt_debug_wrapper.sv rename to rtl/ip/core/mgmt_debug_wrapper.sv diff --git a/rtl/mini/top/ahbl2axi4.sv b/rtl/ip/interconnect/ahbl2axi4.sv similarity index 85% rename from rtl/mini/top/ahbl2axi4.sv rename to rtl/ip/interconnect/ahbl2axi4.sv index e8d3391b..330ca1bd 100644 --- a/rtl/mini/top/ahbl2axi4.sv +++ b/rtl/ip/interconnect/ahbl2axi4.sv @@ -11,7 +11,9 @@ `include "axi4_define.svh" -module ahbl2axi4 ( +module ahbl2axi4 #( + parameter bit TwoCycleErrors = 1'b0 +) ( ahbl_if.slave ahbl, axi4_if.master axi4, output logic idle_o @@ -27,6 +29,7 @@ module ahbl2axi4 ( localparam logic [2:0] FSM_WRITE_RESP = 3'd2; localparam logic [2:0] FSM_READ = 3'd3; localparam logic [2:0] FSM_READ_RESP = 3'd4; + localparam logic [2:0] FSM_ERROR_RESP = 3'd5; logic [2:0] s_fsm_d, s_fsm_q; logic [31:0] s_addr_d, s_addr_q; @@ -37,15 +40,22 @@ module ahbl2axi4 ( logic [ 3:0] s_wstrb; logic [31:0] s_wdata; logic s_terminal; + logic s_axi_err; + logic s_resp_valid; assign idle_o = s_fsm_q == FSM_IDLE; - assign s_terminal = ((s_fsm_q == FSM_WRITE_RESP) && axi4.bvalid) || - ((s_fsm_q == FSM_READ_RESP) && axi4.rvalid); + assign s_resp_valid = ((s_fsm_q == FSM_WRITE_RESP) && axi4.bvalid) || + ((s_fsm_q == FSM_READ_RESP) && axi4.rvalid); + assign s_axi_err = s_resp_valid && + (((s_fsm_q == FSM_WRITE_RESP) && (axi4.bresp != `AXI4_RESP_OKAY)) || + ((s_fsm_q == FSM_READ_RESP) && (axi4.rresp != `AXI4_RESP_OKAY))); + // In compliant mode, the AXI terminal error is consumed during the first + // AHB ERROR cycle (HREADY=0). The saved state supplies the final ERROR cycle + // (HREADY=1), allowing Hazard3 to squash a following pipelined access. + assign s_terminal = (s_resp_valid && !(TwoCycleErrors && s_axi_err)) || + (s_fsm_q == FSM_ERROR_RESP); assign ahbl.hready = (s_fsm_q == FSM_IDLE) || s_terminal; - assign ahbl.hresp = s_terminal && - (((s_fsm_q == FSM_WRITE_RESP) && (axi4.bresp != `AXI4_RESP_OKAY)) || - ((s_fsm_q == FSM_READ_RESP) && (axi4.rresp != `AXI4_RESP_OKAY))) ? - AHBL_RESP_ERROR : AHBL_RESP_OKAY; + assign ahbl.hresp = (s_axi_err || (s_fsm_q == FSM_ERROR_RESP)) ? AHBL_RESP_ERROR : AHBL_RESP_OKAY; assign ahbl.hrdata = axi4.rdata; always_comb begin @@ -155,6 +165,9 @@ module ahbl2axi4 ( FSM_READ: begin if (axi4.arvalid && axi4.arready) s_fsm_d = FSM_READ_RESP; end + FSM_WRITE_RESP, FSM_READ_RESP: begin + if (TwoCycleErrors && s_axi_err) s_fsm_d = FSM_ERROR_RESP; + end default: begin end endcase diff --git a/rtl/mini/top/apb4_if_bridge.sv b/rtl/ip/interconnect/apb4_if_bridge.sv similarity index 100% rename from rtl/mini/top/apb4_if_bridge.sv rename to rtl/ip/interconnect/apb4_if_bridge.sv diff --git a/rtl/mini/top/axi4_connector.sv b/rtl/ip/interconnect/axi4_connector.sv similarity index 100% rename from rtl/mini/top/axi4_connector.sv rename to rtl/ip/interconnect/axi4_connector.sv diff --git a/rtl/mini/top/axi4_error_slave.sv b/rtl/ip/interconnect/axi4_error_slave.sv similarity index 100% rename from rtl/mini/top/axi4_error_slave.sv rename to rtl/ip/interconnect/axi4_error_slave.sv diff --git a/rtl/mini/top/onchip_ram.sv b/rtl/ip/memory/onchip_ram.sv similarity index 100% rename from rtl/mini/top/onchip_ram.sv rename to rtl/ip/memory/onchip_ram.sv diff --git a/rtl/mini/top/onchip_ram_define.svh b/rtl/ip/memory/onchip_ram_define.svh similarity index 100% rename from rtl/mini/top/onchip_ram_define.svh rename to rtl/ip/memory/onchip_ram_define.svh diff --git a/rtl/mini/top/onchip_ram_reg.sv b/rtl/ip/memory/onchip_ram_reg.sv similarity index 100% rename from rtl/mini/top/onchip_ram_reg.sv rename to rtl/ip/memory/onchip_ram_reg.sv diff --git a/rtl/ip/peripheral/apb4_dma.sv b/rtl/ip/peripheral/apb4_dma.sv index 053038d0..9cc49bdd 100644 --- a/rtl/ip/peripheral/apb4_dma.sv +++ b/rtl/ip/peripheral/apb4_dma.sv @@ -9,11 +9,13 @@ // See the Mulan PSL v2 for more details. module apb4_dma #( - parameter int AddrWidth = 32, - parameter int DataWidth = 32, - parameter int NumChannels = 4, - parameter int MaxBurstBeats = 16, - parameter int FifoDepth = 16 + parameter int AddrWidth = 32, + parameter int DataWidth = 32, + parameter int NumChannels = 4, + parameter int MaxBurstBeats = 16, + parameter int FifoDepth = 16, + parameter logic [15:0] RequestMask = 16'h3fff, + parameter bit EnableStreams = 1'b1 ) ( // verilog_format: off -- integration ports retain established peripheral endpoint names. input logic clk_i, @@ -72,7 +74,8 @@ module apb4_dma #( dma_reg #( .NumChannels (NumChannels), .DataWidth (DataWidth), - .MaxBurstBeats(MaxBurstBeats) + .MaxBurstBeats(MaxBurstBeats), + .EnableStreams(EnableStreams) ) u_dma_reg ( .clk_i (clk_i), .rst_n_i (rst_n_i), @@ -119,6 +122,8 @@ module apb4_dma #( ); dma_core #( + .RequestMask (RequestMask), + .EnableStreams(EnableStreams), .AddrWidth (AddrWidth), .DataWidth (DataWidth), .NumChannels (NumChannels), diff --git a/rtl/ip/peripheral/dma_core.sv b/rtl/ip/peripheral/dma_core.sv index b7c28ae5..ea373cce 100644 --- a/rtl/ip/peripheral/dma_core.sv +++ b/rtl/ip/peripheral/dma_core.sv @@ -12,13 +12,15 @@ `include "axi4_define.svh" module dma_core #( - parameter int AddrWidth = 32, - parameter int DataWidth = 32, - parameter int NumChannels = 4, - parameter int ChannelIndexWidth = (NumChannels > 1) ? $clog2(NumChannels) : 1, - parameter int MaxBurstBeats = 16, - parameter int FifoDepth = 16, - parameter bit EnableCrc = 1'b1 + parameter int AddrWidth = 32, + parameter int DataWidth = 32, + parameter int NumChannels = 4, + parameter int ChannelIndexWidth = (NumChannels > 1) ? $clog2(NumChannels) : 1, + parameter int MaxBurstBeats = 16, + parameter int FifoDepth = 16, + parameter bit EnableCrc = 1'b1, + parameter logic [15:0] RequestMask = 16'h3fff, + parameter bit EnableStreams = 1'b1 ) ( // verilog_format: off -- channel vectors are kept aligned with the register-bank ABI. input logic clk_i, @@ -447,7 +449,9 @@ module dma_core #( s_start_valid[channel] = 1'b1; s_start_err_code[channel] = DMA_ERROR_CONFIG; - if ((s_cfg_width[channel] != DMA_WIDTH_32) || (s_cfg_byte_count[channel] == 32'd0) || + if (!RequestMask[s_cfg_request[channel]] || + (!EnableStreams && (s_cfg_kind[channel] != DMA_KIND_MM_TO_MM)) || + (s_cfg_width[channel] != DMA_WIDTH_32) || (s_cfg_byte_count[channel] == 32'd0) || (s_cfg_burst[channel] == 5'd0) || (s_cfg_burst[channel] > 5'(MaxBurstBeats))) begin s_start_valid[channel] = 1'b0; @@ -1268,7 +1272,9 @@ module dma_core #( if (s_tcd_parse_q) begin s_tcd_parse_q <= 1'b0; - if (s_err_q[s_tcd_read_owner_q] || + if (!RequestMask[s_tcd_word7_q[s_tcd_read_owner_q][15:12]] || + (!EnableStreams && (s_tcd_word7_q[s_tcd_read_owner_q][10:8] != DMA_KIND_MM_TO_MM)) || + s_err_q[s_tcd_read_owner_q] || (s_tcd_word7_q[s_tcd_read_owner_q][0] == 1'b0) || (s_tcd_word3_q[s_tcd_read_owner_q] == 32'd0) || (s_tcd_word1_q[s_tcd_read_owner_q][1:0] != 2'b00) || diff --git a/rtl/ip/peripheral/dma_reg.sv b/rtl/ip/peripheral/dma_reg.sv index e691d29e..da3b3860 100644 --- a/rtl/ip/peripheral/dma_reg.sv +++ b/rtl/ip/peripheral/dma_reg.sv @@ -12,6 +12,7 @@ module dma_reg #( parameter int NumChannels = 4, + parameter bit EnableStreams = 1'b1, parameter int ChannelIndexWidth = (NumChannels > 1) ? $clog2(NumChannels) : 1, parameter int DataWidth = 32, parameter int MaxBurstBeats = 16 @@ -350,7 +351,15 @@ module dma_reg #( `APB4_DMA__IP_ID: s_read_data = IpId; `APB4_DMA__IP_VERSION: s_read_data = IpVersion; `APB4_DMA__CAPABILITY: - s_read_data = {1'b0, 3'd3, 4'(MaxBurstBeats), 8'(DataWidth), 8'(NumChannels), 7'd0, 1'b1}; + s_read_data = { + 1'b0, + (EnableStreams ? 3'd3 : 3'd0), + 4'(MaxBurstBeats), + 8'(DataWidth), + 8'(NumChannels), + 7'd0, + 1'b1 + }; `APB4_DMA__GLOBAL_CTRL: s_read_data = 32'd0; `APB4_DMA__GLOBAL_STATUS: s_read_data = {31'd0, |busy_i}; `APB4_DMA__IRQ_STATE: s_read_data = {{(32 - NumChannels) {1'b0}}, s_irq_state}; diff --git a/rtl/mini/top/gpio_pad_bridge.sv b/rtl/ip/peripheral/gpio_pad_bridge.sv similarity index 100% rename from rtl/mini/top/gpio_pad_bridge.sv rename to rtl/ip/peripheral/gpio_pad_bridge.sv diff --git a/rtl/ip/storage/apb4_xpi.sv b/rtl/ip/storage/apb4_xpi.sv index 8205879a..b07e4d01 100644 --- a/rtl/ip/storage/apb4_xpi.sv +++ b/rtl/ip/storage/apb4_xpi.sv @@ -10,7 +10,9 @@ `include "xpi_define.svh" -`ifdef SIMU_VERILATOR +`ifdef RETROSOC_SOC__TINY +`define APB4_XPI_CORE_MODULE xpi_core +`elsif SIMU_VERILATOR `define APB4_XPI_CORE_MODULE xpi_core_verilator `else `define APB4_XPI_CORE_MODULE xpi_core diff --git a/rtl/mini/top/soc_common_cdc.sv b/rtl/ip/util/soc_common_cdc.sv similarity index 100% rename from rtl/mini/top/soc_common_cdc.sv rename to rtl/ip/util/soc_common_cdc.sv diff --git a/rtl/mini/top/soc_common_fifo.sv b/rtl/ip/util/soc_common_fifo.sv similarity index 100% rename from rtl/mini/top/soc_common_fifo.sv rename to rtl/ip/util/soc_common_fifo.sv diff --git a/rtl/mini/Makefile b/rtl/mini/Makefile index 15a95b63..017020b6 100644 --- a/rtl/mini/Makefile +++ b/rtl/mini/Makefile @@ -1,6 +1,6 @@ GENERATED_FL_DIR := $(FLOW_FILELIST_DIR) MEMORY_MAP_SOURCE := $(RTL_PATH)/address_map/memory_map.json -MEMORY_MAP_SCRIPT := $(RTL_PATH)/address_map/generate_memory_map.py +MEMORY_MAP_SCRIPT := $(ROOT_PATH)/scripts/rtl/generate_memory_map.py MEMORY_MAP_DIR := $(VARIANT_ROOT)/generated/memory_map MEMORY_MAP_STAMP := $(MEMORY_MAP_DIR)/.stamp MEMORY_MAP_RTL_DIR := $(MEMORY_MAP_DIR)/rtl @@ -8,7 +8,7 @@ MEMORY_MAP_C_DIR := $(MEMORY_MAP_DIR)/include MEMORY_MAP_LINKER_DIR := $(MEMORY_MAP_DIR)/linker MEMORY_MAP_FILELIST := $(MEMORY_MAP_DIR)/memory_map.fl PIN_MAP_SOURCE := $(RTL_PATH)/pin_map/pin_map.json -PIN_MAP_SCRIPT := $(RTL_PATH)/pin_map/generate_pin_map.py +PIN_MAP_SCRIPT := $(ROOT_PATH)/scripts/rtl/generate_pin_map.py PIN_MAP_DIR := $(VARIANT_ROOT)/generated/pin_map PIN_MAP_STAMP := $(PIN_MAP_DIR)/.stamp PIN_MAP_FILELIST := $(PIN_MAP_DIR)/pin_map.fl @@ -132,7 +132,7 @@ check-clock-reset-domains: $(FLOW_PYTHON) $(CLOCK_RESET_DOMAINS_SCRIPT) --map $(CLOCK_RESET_DOMAINS_SOURCE) --root $(ROOT_PATH) $(FILELIST_STAMP): $(FILELIST_TEMPLATES) $(RTL_PATH)/script/generate_filelist.py $(LOCAL_RTL_FILES) \ - $(RTL_PATH)/script/filelist.py $(MEMORY_MAP_STAMP) $(PIN_MAP_STAMP) $(SOC_TOPOLOGY_STAMP) \ + $(ROOT_PATH)/scripts/rtl/filelist.py $(MEMORY_MAP_STAMP) $(PIN_MAP_STAMP) $(SOC_TOPOLOGY_STAMP) \ $(USER_EXTENSIONS_STAMP) $(ARCHINFO_METADATA_STAMP) \ $(if $(filter MPW,$(MINI_MODE)),$(MPW_VARIANT_STAMP)) \ $(if $(filter YES,$(HAVE_HP)),$(HP_GENERATED_STAMP)) @@ -146,7 +146,7 @@ $(FILELIST_STAMP): $(FILELIST_TEMPLATES) $(RTL_PATH)/script/generate_filelist.py generate_filelist: $(FILELIST_STAMP) # software -include $(RTL_PATH)/mk/software.mk +include $(ROOT_PATH)/rtl/mk/software.mk #====================== filelist ====================== ifeq ($(PDK), IHP130) diff --git a/rtl/mini/README.md b/rtl/mini/README.md index a51b4d2d..04689708 100644 --- a/rtl/mini/README.md +++ b/rtl/mini/README.md @@ -1,8 +1,12 @@ # Mini SoC Integration -This directory is the active Mini SoC integration boundary. +This directory is the Mini SoC integration boundary. Tiny owns a separate +[MCU integration](../tiny/README.md). Shared CPU/debug, memory, bus helpers and +software build logic are owned outside Mini. Filelists, build rules and tests +reference their canonical shared paths directly. -- address_map contains the canonical address-map input and generator. +- address_map contains the canonical Mini address-map input. Its generator + lives in `scripts/rtl/generate_memory_map.py`. - core contains self-owned Mini core wrappers. - dv contains behavioural testbench, device models, and Verilator harness sources. @@ -10,8 +14,10 @@ This directory is the active Mini SoC integration boundary. behavioral/synthesis Common source set; `netlist_support.fl` is the explicit allowlist of testbench dependencies not already present in a synthesized netlist. -- mk contains simulator and software make fragments. -- script contains filelist, address-map, conversion, and setup helpers. +- mk contains Mini simulator and formal make fragments; shared firmware rules + live in `rtl/mk/software.mk`. +- script contains Mini filelist generation and simulator-binding helpers. + Shared parsing/conversion helpers live in `scripts/rtl`. - top contains SoC integration RTL, including `apb4_system` for the APB4 platform block and `apb4_periph` for the APB4 peripheral container. diff --git a/rtl/mini/address_map/README.md b/rtl/mini/address_map/README.md index 02178dea..cc7de341 100644 --- a/rtl/mini/address_map/README.md +++ b/rtl/mini/address_map/README.md @@ -1,6 +1,7 @@ # Canonical Address Map -memory_map.json is the sole source for Mini SoC address ranges. Its generator +`memory_map.json` is the sole source for Mini SoC address ranges. The shared +[generator](../../../scripts/rtl/generate_memory_map.py) emits RTL include definitions, SDK headers, linker memory regions, and the filelist include path into the selected build variant. diff --git a/rtl/mini/filelist/commonip.fl b/rtl/mini/filelist/commonip.fl index f5da1514..68a45917 100644 --- a/rtl/mini/filelist/commonip.fl +++ b/rtl/mini/filelist/commonip.fl @@ -9,7 +9,7 @@ /clusterip/common/rtl/interface/ram_if.sv /top/rib_if.sv /clusterip/common/rtl/utils/register.sv -/top/soc_common_fifo.sv +/ip/util/soc_common_fifo.sv /clusterip/common/rtl/utils/spill_register.sv /clusterip/common/rtl/stream/round_robin_arbiter.sv /clusterip/common/rtl/utils/lfsr.sv @@ -20,7 +20,7 @@ /clusterip/common/rtl/cdc/cdc_sync.sv /clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv /clusterip/common/rtl/cdc/cdc_2phase.sv -/top/soc_common_cdc.sv +/ip/util/soc_common_cdc.sv /clusterip/common/rtl/clkrst/clk_int_div.sv /clusterip/common/rtl/clock/safe_clock_mux.sv /clusterip/common/rtl/clkrst/rst_sync.sv diff --git a/rtl/mini/filelist/inc.fl b/rtl/mini/filelist/inc.fl index 2f1af8e9..3f625127 100644 --- a/rtl/mini/filelist/inc.fl +++ b/rtl/mini/filelist/inc.fl @@ -13,6 +13,7 @@ +incdir+/clusterip/rtc/rtl +incdir+/clusterip/wdg/rtl +incdir+/clusterip/crc/rtl ++incdir+/ip/core +incdir+/ip/interconnect +incdir+/ip/util +incdir+/ip/memory diff --git a/rtl/mini/filelist/top.fl b/rtl/mini/filelist/top.fl index 61e1e8af..b481e6d5 100644 --- a/rtl/mini/filelist/top.fl +++ b/rtl/mini/filelist/top.fl @@ -1,11 +1,11 @@ -/top/apb4_if_bridge.sv +/ip/interconnect/apb4_if_bridge.sv /top/apb4_async_bridge.sv -/top/gpio_pad_bridge.sv +/ip/peripheral/gpio_pad_bridge.sv /top/memory_pad_mux.sv /top/ribp2rib.sv /top/rib2ribp.sv /top/rib2apb.sv -/top/axi4_connector.sv +/ip/interconnect/axi4_connector.sv /top/axi4_master_idle.sv /top/axi4_mgmt_router.sv /top/axi4_async_bridge.sv @@ -18,9 +18,9 @@ /top/fabric_monitor.sv /top/soc_data_plane.sv /top/data_plane_fault_cdc.sv -/top/axi4_error_slave.sv +/ip/interconnect/axi4_error_slave.sv /top/rib2axi4.sv -/top/ahbl2axi4.sv +/ip/interconnect/ahbl2axi4.sv /top/axi42apb4_system.sv /top/axi42apb4_periph.sv /top/axi4_word_bridge.sv @@ -33,8 +33,8 @@ /top/retrosoc.sv /top/retrosoc_asic.sv /top/retrosoc_core.sv -/top/onchip_ram_reg.sv -/top/onchip_ram.sv +/ip/memory/onchip_ram_reg.sv +/ip/memory/onchip_ram.sv /top/resource_controller.sv /top/apb4_periph.sv /top/apb4_system.sv @@ -46,10 +46,10 @@ /top/clock_frequency_monitor.sv /top/soc_clock_gate.sv /top/soc_clock_reset_subsystem.sv -/top/mgmt_debug_reset.sv +/ip/core/mgmt_debug_reset.sv /top/hp_lifecycle_controller.sv -/top/mgmt_debug_wrapper.sv -/top/mgmt_core_wrapper.sv +/ip/core/mgmt_debug_wrapper.sv +/ip/core/mgmt_core_wrapper.sv /top/hp_core_wrapper.sv /top/hp_subsystem.sv /top/user_core_design.sv diff --git a/rtl/mini/formal/generate_formal_filelist.py b/rtl/mini/formal/generate_formal_filelist.py index d40c176e..fb7c8a4a 100644 --- a/rtl/mini/formal/generate_formal_filelist.py +++ b/rtl/mini/formal/generate_formal_filelist.py @@ -10,10 +10,9 @@ from pathlib import Path SCRIPT_DIR = Path(__file__).resolve().parent ROOT = SCRIPT_DIR.parents[2] -FILELIST_DIR = ROOT / "rtl/mini/script" -sys.path.insert(0, str(FILELIST_DIR)) +sys.path.insert(0, str(ROOT)) -from filelist import FileList, write_filelist # noqa: E402 +from scripts.rtl.filelist import FileList, write_filelist # noqa: E402 COMMON_RTL = ROOT / "rtl/managed/clusterip/common/rtl" @@ -249,8 +248,8 @@ def source_files(target: str) -> list[Path]: COMMON_RTL / "utils/register.sv", COMMON_RTL / "utils/xchecker.sv", ROOT / "rtl/tech/tc_sram.sv", - TOP / "onchip_ram_reg.sv", - TOP / "onchip_ram.sv", + ROOT / "rtl/ip/memory/onchip_ram_reg.sv", + ROOT / "rtl/ip/memory/onchip_ram.sv", SCRIPT_DIR / "onchip_ram_formal.sv", ] if target == "opipsram": diff --git a/rtl/mini/integration/clock_reset_domains.json b/rtl/mini/integration/clock_reset_domains.json index 43ee342f..ca2b5763 100644 --- a/rtl/mini/integration/clock_reset_domains.json +++ b/rtl/mini/integration/clock_reset_domains.json @@ -68,7 +68,7 @@ "reset": "s_jtag_trst_n_sync", "reset_source": "jtag_trst_n_i", "reset_primitive": "rst_sync", - "path": "rtl/mini/top/mgmt_debug_wrapper.sv", + "path": "rtl/ip/core/mgmt_debug_wrapper.sv", "instance": "u_jtag_rst_sync", "sta": {"source_port": "jtag_tck_i_pad", "object_type": "port", "period_ns": 100.0, "async_group": "jtag"} }, diff --git a/rtl/mini/mk/formal.mk b/rtl/mini/mk/formal.mk index a44689b3..e773d1f6 100644 --- a/rtl/mini/mk/formal.mk +++ b/rtl/mini/mk/formal.mk @@ -178,8 +178,8 @@ FORMAL_SOURCE_FILES := $(RTL_PATH)/formal/bus_formal.sv \ $(ROOT_PATH)/rtl/ip/memory/psram_pkg.sv \ $(ROOT_PATH)/rtl/ip/memory/psram_axi4.sv \ $(ROOT_PATH)/rtl/ip/memory/psram_phy.sv \ - $(RTL_PATH)/top/onchip_ram_reg.sv \ - $(RTL_PATH)/top/onchip_ram.sv \ + $(ROOT_PATH)/rtl/ip/memory/onchip_ram_reg.sv \ + $(ROOT_PATH)/rtl/ip/memory/onchip_ram.sv \ $(ROOT_PATH)/rtl/tech/tc_sram.sv \ $(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/register.sv \ $(ROOT_PATH)/rtl/managed/clusterip/common/rtl/utils/xchecker.sv \ @@ -242,11 +242,11 @@ $(FORMAL_DIR)/%/formal.fl: $(FORMAL_FILELIST_GENERATOR) $(FORMAL_SOURCE_FILES) \ --memory-map-dir $(MEMORY_MAP_DIR) --soc-topology-dir $(SOC_TOPOLOGY_DIR) \ --user-extensions-dir $(USER_EXTENSIONS_DIR) -$(FORMAL_DIR)/%/design.v: $(FORMAL_DIR)/%/formal.fl $(RTL_PATH)/script/convt_sv2v.py \ - $(RTL_PATH)/script/filelist.py $(FORMAL_SOURCE_FILES) +$(FORMAL_DIR)/%/design.v: $(FORMAL_DIR)/%/formal.fl $(ROOT_PATH)/scripts/rtl/convt_sv2v.py \ + $(ROOT_PATH)/scripts/rtl/filelist.py $(FORMAL_SOURCE_FILES) python3 $(ROOT_PATH)/scripts/run_flow.py --tool formal-sv2v \ --log $(@D)/sv2v.log --result $(@D)/result-sv2v.json \ - -- python3 $(RTL_PATH)/script/convt_sv2v.py -f $< --output $@ + -- python3 $(ROOT_PATH)/scripts/rtl/convt_sv2v.py -f $< --output $@ $(FORMAL_DIR)/%/prove.sby: $(FORMAL_DIR)/%/design.v \ $(FORMAL_SBY_GENERATOR) diff --git a/rtl/mini/mk/iverilog.mk b/rtl/mini/mk/iverilog.mk index e87c970e..ae1ce74a 100644 --- a/rtl/mini/mk/iverilog.mk +++ b/rtl/mini/mk/iverilog.mk @@ -36,8 +36,8 @@ IVERILOG_SIM_OPTS := +sim_timeout=$(RTL_SIM_TIMEOUT) +wave_$(WAVE) $(CONVERTED_SOC): $(if $(filter MPW,$(MINI_MODE)),$(MPW_VARIANT_STAMP)) $(FILELIST_STAMP) @mkdir -p $(@D) - python3 $(RTL_PATH)/script/convt_sv2v.py $(RTL_FLIST) --output $@ - python3 $(RTL_PATH)/script/filelist_deps.py $(RTL_FLIST) --target $@ \ + python3 $(ROOT_PATH)/scripts/rtl/convt_sv2v.py $(RTL_FLIST) --output $@ + python3 $(ROOT_PATH)/scripts/rtl/filelist_deps.py $(RTL_FLIST) --target $@ \ --output $(CONVERTED_DEPFILE) $(IVERILOG_BEHV_FLIST): $(FILELIST_STAMP) $(CONVERTED_SOC) $(IVERILOG_FILELIST_GEN) @@ -88,7 +88,7 @@ $(IVERILOG_BEHV_SIMV): $(IVERILOG_BEHV_FLIST) --log $(IVERILOG_BEHV_DIR)/compile.log --result $(IVERILOG_BEHV_DIR)/result-compile.json \ --cwd $(IVERILOG_BEHV_DIR) -- $(IVERILOG) $(IVERILOG_COMMON_OPTS) \ $(IVERILOG_TIME_OPTS) -f $< -o simv -s $(RTL_TOP) - python3 $(RTL_PATH)/script/filelist_deps.py -f $(IVERILOG_BEHV_FLIST) \ + python3 $(ROOT_PATH)/scripts/rtl/filelist_deps.py -f $(IVERILOG_BEHV_FLIST) \ --target $@ --output $(IVERILOG_BEHV_DEPFILE) $(IVERILOG_NETL_SIMV): $(IVERILOG_NETL_FLIST) @@ -97,7 +97,7 @@ $(IVERILOG_NETL_SIMV): $(IVERILOG_NETL_FLIST) --log $(IVERILOG_NETL_DIR)/compile.log --result $(IVERILOG_NETL_DIR)/result-compile.json \ --cwd $(IVERILOG_NETL_DIR) -- $(IVERILOG) $(IVERILOG_COMMON_OPTS) \ $(IVERILOG_TIME_OPTS) -f $< -o simv -s $(RTL_TOP) - python3 $(RTL_PATH)/script/filelist_deps.py -f $(IVERILOG_NETL_FLIST) \ + python3 $(ROOT_PATH)/scripts/rtl/filelist_deps.py -f $(IVERILOG_NETL_FLIST) \ --target $@ --output $(IVERILOG_NETL_DEPFILE) $(IVERILOG_POST_SIMV): $(IVERILOG_POST_FLIST) @@ -106,7 +106,7 @@ $(IVERILOG_POST_SIMV): $(IVERILOG_POST_FLIST) --log $(IVERILOG_POST_DIR)/compile.log --result $(IVERILOG_POST_DIR)/result-compile.json \ --cwd $(IVERILOG_POST_DIR) -- $(IVERILOG) $(IVERILOG_COMMON_OPTS) \ $(IVERILOG_POST_OPTS) -f $< -o simv -s $(RTL_TOP) -s retrosoc_sdf_annotator - python3 $(RTL_PATH)/script/filelist_deps.py -f $(IVERILOG_POST_FLIST) \ + python3 $(ROOT_PATH)/scripts/rtl/filelist_deps.py -f $(IVERILOG_POST_FLIST) \ --target $@ --output $(IVERILOG_POST_DEPFILE) comp: $(IVERILOG_BEHV_SIMV) @@ -114,7 +114,7 @@ netcomp: $(IVERILOG_NETL_SIMV) postcomp: $(IVERILOG_POST_SIMV) sim: comp - python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(IVERILOG_BEHV_DIR) \ + python3 $(ROOT_PATH)/scripts/rtl/prepare_norflash.py --sim-dir $(IVERILOG_BEHV_DIR) \ --firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog-sim \ --log $(IVERILOG_BEHV_DIR)/sim.log --result $(IVERILOG_BEHV_DIR)/result-sim.json \ @@ -123,7 +123,7 @@ sim: comp --result $(IVERILOG_BEHV_DIR)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)' netsim: netcomp - python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(IVERILOG_NETL_DIR) \ + python3 $(ROOT_PATH)/scripts/rtl/prepare_norflash.py --sim-dir $(IVERILOG_NETL_DIR) \ --firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog-sim \ --log $(IVERILOG_NETL_DIR)/sim.log --result $(IVERILOG_NETL_DIR)/result-sim.json \ @@ -132,7 +132,7 @@ netsim: netcomp --result $(IVERILOG_NETL_DIR)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)' netsim-boot: netcomp - python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(IVERILOG_NETL_DIR) \ + python3 $(ROOT_PATH)/scripts/rtl/prepare_norflash.py --sim-dir $(IVERILOG_NETL_DIR) \ --firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog-sim \ --log $(IVERILOG_NETL_DIR)/sim.log --result $(IVERILOG_NETL_DIR)/result-sim.json \ @@ -142,7 +142,7 @@ netsim-boot: netcomp --result $(IVERILOG_NETL_DIR)/result-sim-check.json --require 'Hello retroSoC!' postsim: postcomp - python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(IVERILOG_POST_DIR) \ + python3 $(ROOT_PATH)/scripts/rtl/prepare_norflash.py --sim-dir $(IVERILOG_POST_DIR) \ --firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog-sim \ --log $(IVERILOG_POST_DIR)/sim.log --result $(IVERILOG_POST_DIR)/result-sim.json \ diff --git a/rtl/mini/mk/vcs.mk b/rtl/mini/mk/vcs.mk index b39292d8..d08fd0dd 100644 --- a/rtl/mini/mk/vcs.mk +++ b/rtl/mini/mk/vcs.mk @@ -99,13 +99,13 @@ $(VCS_BEHV_SIMV) $(VCS_NETL_SIMV) $(VCS_POST_SIMV): $(MPW_VARIANT_DEP) $(FILELIS $(FLOW_PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool vcs --log $(DIR)/driver-compile.log \ --result $(DIR)/result-compile.json --cwd $(DIR) -- \ $(SIM_TOOL) $(COMMON_OPTS) $(OPTS) $(FLIST) -top $(RTL_TOP) $(COMP_LOG) - $(FLOW_PYTHON) $(RTL_PATH)/script/filelist_deps.py $(DEPS_ARGS) --target $@ --output $(DEPFILE) + $(FLOW_PYTHON) $(ROOT_PATH)/scripts/rtl/filelist_deps.py $(DEPS_ARGS) --target $@ --output $(DEPFILE) $(VCS_NETL_SIMV): $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v $(VCS_POST_SIMV): $(ROOT_PATH)/physical/sdf/retrosoc_asic.v $(ROOT_PATH)/physical/sdf/retrosoc_asic_CTS_MIN.sdf.gz sim netsim postsim: - $(FLOW_PYTHON) $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(DIR) \ + $(FLOW_PYTHON) $(ROOT_PATH)/scripts/rtl/prepare_norflash.py --sim-dir $(DIR) \ --firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex $(FLOW_PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool vcs-sim --stream-bytes \ --log $(DIR)/driver-sim.log \ diff --git a/rtl/mini/mk/verilator.mk b/rtl/mini/mk/verilator.mk index 01fa65c8..1c654349 100644 --- a/rtl/mini/mk/verilator.mk +++ b/rtl/mini/mk/verilator.mk @@ -74,7 +74,7 @@ $(VERILATOR_STAMP): $(MPW_VARIANT_DEP) $(FILELIST_STAMP) $(VERILATOR_EXTRA_SOURC python3 $(ROOT_PATH)/scripts/run_flow.py --tool verilator \ --log $(BUILD_DIR)/verilating.log --result $(BUILD_DIR)/result-verilate.json \ -- $(VERILATOR) $(VERILATOR_FLAGS) - python3 $(RTL_PATH)/script/filelist_deps.py $(RTL_FLIST) \ + python3 $(ROOT_PATH)/scripts/rtl/filelist_deps.py $(RTL_FLIST) \ $(foreach source,$(VERILATOR_EXTRA_SOURCES),--extra $(source)) \ --target $@ --output $(VERILATOR_DEPFILE) @touch $@ @@ -90,7 +90,7 @@ $(RTL_LINT_STAMP): $(MPW_VARIANT_DEP) $(FILELIST_STAMP) $(VERILATOR_EXTRA_SOURCE python3 $(ROOT_PATH)/scripts/run_flow.py --tool rtl-lint \ --log $(RTL_LINT_DIR)/lint.log --result $(RTL_LINT_DIR)/result-rtl-lint.json \ -- $(VERILATOR) $(RTL_LINT_FLAGS) - python3 $(RTL_PATH)/script/filelist_deps.py $(RTL_FLIST) \ + python3 $(ROOT_PATH)/scripts/rtl/filelist_deps.py $(RTL_FLIST) \ $(foreach source,$(VERILATOR_EXTRA_SOURCES),--extra $(source)) \ --target $@ --output $(RTL_LINT_DEPFILE) @touch $@ diff --git a/rtl/mini/pin_map/README.md b/rtl/mini/pin_map/README.md index b11e1b97..b307a18a 100644 --- a/rtl/mini/pin_map/README.md +++ b/rtl/mini/pin_map/README.md @@ -1,7 +1,8 @@ # Canonical SoC Pin Map `pin_map.json` is the single source for the Mini SoC logical pad ABI and its -ASIC, FPGA, Verilator, and RTL-testbench bindings. The generator emits +ASIC, FPGA, Verilator, and RTL-testbench bindings. The shared +[generator](../../../scripts/rtl/generate_pin_map.py) emits temporary SystemVerilog include files below the selected build variant; do not edit generated files. diff --git a/rtl/mini/script/gen_iverilog_filelist.py b/rtl/mini/script/gen_iverilog_filelist.py index 973bc120..cad21a1c 100644 --- a/rtl/mini/script/gen_iverilog_filelist.py +++ b/rtl/mini/script/gen_iverilog_filelist.py @@ -5,9 +5,12 @@ from __future__ import annotations import argparse import gzip import re +import sys from pathlib import Path -from filelist import atomic_write, parse_filelists, write_filelist +REPO_ROOT = Path(__file__).resolve().parents[3] +sys.path.insert(0, str(REPO_ROOT)) +from scripts.rtl.filelist import atomic_write, parse_filelists, write_filelist # noqa: E402 SCRIPT_DIR = Path(__file__).resolve().parent diff --git a/rtl/mini/script/generate_filelist.py b/rtl/mini/script/generate_filelist.py index 54234e77..bddf461c 100644 --- a/rtl/mini/script/generate_filelist.py +++ b/rtl/mini/script/generate_filelist.py @@ -4,9 +4,12 @@ from __future__ import annotations import argparse import re +import sys from pathlib import Path -from filelist import atomic_write +REPO_ROOT = Path(__file__).resolve().parents[3] +sys.path.insert(0, str(REPO_ROOT)) +from scripts.rtl.filelist import atomic_write # noqa: E402 SCRIPT_DIR = Path(__file__).resolve().parent diff --git a/rtl/mk/README.md b/rtl/mk/README.md new file mode 100644 index 00000000..f7eb1952 --- /dev/null +++ b/rtl/mk/README.md @@ -0,0 +1,6 @@ +# Shared RTL/SDK Build Rules + +`software.mk` owns common compiler, linker and firmware artifact rules for Mini +and Tiny. Product configuration and application source selection remain explicit. +Both products include this canonical file directly. Changes require both +product configuration tests, affected firmware builds, and SDK gates. diff --git a/rtl/mini/mk/software.mk b/rtl/mk/software.mk similarity index 90% rename from rtl/mini/mk/software.mk rename to rtl/mk/software.mk index 6e5becd9..60b1e0ce 100644 --- a/rtl/mini/mk/software.mk +++ b/rtl/mk/software.mk @@ -143,6 +143,17 @@ CRT_SRCS := $(ROOT_PATH)/crt/arch/riscv/startup.S \ $(ROOT_PATH)/crt/src/hal/user_ip.c \ $(ROOT_PATH)/crt/src/hal/user_core.c +ifeq ($(SOC),TINY) +DEF_VAL += -DRS_SOC_TINY +CFLAGS += -DRS_SOC_TINY +TINY_CRT_NAMES := startup.S clzsi2.c divdi3.c ffssi2.c udivdi3.c umoddi3.c \ + stdlib.c string.c console.c printf.c archinfo.c clint.c uart_math.c uart.c \ + gpio_math.c gpio.c timer_math.c timer.c pwm.c rtc.c wdg.c watchdog.c i2c_math.c i2c.c \ + dma_math.c dma.c onchip_sram.c xpi.c +CRT_SRCS := $(foreach source,$(CRT_SRCS),$(if $(filter $(notdir $(source)),$(TINY_CRT_NAMES)),$(source))) +CRT_SRCS += $(ROOT_PATH)/crt/src/hal/sysctrl.c +endif + ifeq ($(HAVE_CSR),YES) CRT_SRCS += $(ROOT_PATH)/crt/arch/riscv/system_irq.S CRT_SRCS += $(ROOT_PATH)/crt/src/core/system_irq_handler.c @@ -155,7 +166,7 @@ APP_SRCS := APP_INC_DIRS := APP_CFLAGS := APP_CRT_SRCS := -APP_MK := $(ROOT_PATH)/app/apps/$(APP)/app.mk +APP_MK := $(ROOT_PATH)/app/apps/$(APP)/$(if $(filter TINY,$(SOC)),tiny.mk,app.mk) ifeq ($(wildcard $(APP_MK)),) $(error Application profile not found: $(APP_MK)) @@ -221,6 +232,11 @@ FORCE_VERSION: upd_ver_info: $(VERSION_HEADER) +ifeq ($(SOC),TINY) +asm: tiny-boot-image + cp $(SW_BUILD_DIR)/tiny_boot.hex $(SW_BUILD_DIR)/$(ASM_FIRMWARE_NAME).hex + cp $(SW_BUILD_DIR)/tiny_boot.bin $(SW_BUILD_DIR)/$(ASM_FIRMWARE_NAME).bin +else asm: $(MPW_VARIANT_DEP) $(MEMORY_MAP_STAMP) @mkdir -p $(SW_BUILD_DIR)/asm $(MAKE) -C $(ROOT_PATH)/app/asm OUT_DIR=$(SW_BUILD_DIR)/asm \ @@ -232,8 +248,12 @@ asm: $(MPW_VARIANT_DEP) $(MEMORY_MAP_STAMP) $(CRYPTO_CONSTANTS_HEADER): $(ROOT_PATH)/scripts/crypto_constants.py $(ROOT_PATH)/scripts/data/crypto_constants.json $(PYTHON) $(ROOT_PATH)/scripts/crypto_constants.py --root $(ROOT_PATH) --output $(SW_BUILD_DIR)/include -$(FIRMWARE_ELF): $(MPW_VARIANT_DEP) $(MEMORY_MAP_STAMP) $(SOC_TOPOLOGY_STAMP) $(SOC_IRQ_METADATA) $(USER_EXTENSIONS_STAMP) $(ARCHINFO_METADATA_STAMP) $(VERSION_HEADER) $(CRYPTO_CONSTANTS_HEADER) $(SRC_PATH) $(SW_HEADERS) $(LDS_PATH) \ - $(ROOT_PATH)/rtl/mini/mk/software.mk +endif + +CRYPTO_CONSTANTS_DEP := $(if $(filter TINY,$(SOC)),,$(CRYPTO_CONSTANTS_HEADER)) + +$(FIRMWARE_ELF): $(MPW_VARIANT_DEP) $(MEMORY_MAP_STAMP) $(SOC_TOPOLOGY_STAMP) $(SOC_IRQ_METADATA) $(USER_EXTENSIONS_STAMP) $(ARCHINFO_METADATA_STAMP) $(VERSION_HEADER) $(CRYPTO_CONSTANTS_DEP) $(SRC_PATH) $(SW_HEADERS) $(LDS_PATH) \ + $(ROOT_PATH)/rtl/mk/software.mk $(APP_MK) @mkdir -p $(SW_BUILD_DIR) cd $(SW_BUILD_DIR) && $(CP) -P -o $(LINK_TYPE).lds $(LDS_PATH) cp $(MEMORY_REGIONS_LD) $(SW_BUILD_DIR)/memory_regions.ld diff --git a/rtl/rtl_readiness.json b/rtl/rtl_readiness.json index 4339f9f1..616992fc 100644 --- a/rtl/rtl_readiness.json +++ b/rtl/rtl_readiness.json @@ -5,7 +5,8 @@ "name": "owned-rtl", "paths": [ "rtl/ip", - "rtl/mini/top" + "rtl/mini/top", + "rtl/tiny/top" ], "status": "prototype", "baseline_revision": null, diff --git a/rtl/rtl_style_audit.json b/rtl/rtl_style_audit.json index 179552b1..771d6a71 100644 --- a/rtl/rtl_style_audit.json +++ b/rtl/rtl_style_audit.json @@ -96,12 +96,21 @@ } ], "inventory": { + "rtl/ip/core": [ + "mgmt_core_wrapper.sv", + "mgmt_debug_reset.sv", + "mgmt_debug_wrapper.sv" + ], "rtl/ip/experimental": [ "apb4_gpu.sv", "axi4f2ribp.sv", "wb2ribp.sv" ], "rtl/ip/interconnect": [ + "ahbl2axi4.sv", + "apb4_if_bridge.sv", + "axi4_connector.sv", + "axi4_error_slave.sv", "axi4l2ribp.sv", "ribp2ribp.sv", "ribp_regslice.sv" @@ -110,6 +119,9 @@ "apb4_opipsram.sv", "apb4_psram.sv", "axi4_sdram.sv", + "onchip_ram.sv", + "onchip_ram_define.svh", + "onchip_ram_reg.sv", "opipsram_axi4.sv", "opipsram_core.sv", "opipsram_define.svh", @@ -125,11 +137,11 @@ "psram_phy.sv", "psram_pkg.sv", "psram_reg.sv", + "sdram_axi4.sv", "sdram_clkgen.sv", "sdram_core.sv", "sdram_define.svh", "sdram_pkg.sv", - "sdram_axi4.sv", "sdram_reg.sv" ], "rtl/ip/multimedia": [ @@ -142,8 +154,8 @@ "apu_codec_sequencer.sv", "apu_codec_transport.sv", "apu_control_store.sv", - "apu_dma.sv", "apu_define.svh", + "apu_dma.sv", "apu_entropy_engine.sv", "apu_kernel_engine.sv", "apu_kws_apum_profile.svh", @@ -159,9 +171,9 @@ "apu_primitive_dispatcher.sv", "apu_proof_memo.sv", "apu_reconstruction_engine.sv", + "apu_reg.sv", "apu_resampler.sv", "apu_ring_scheduler.sv", - "apu_reg.sv", "apu_stream_router.sv", "apu_transform_engine.sv", "axi4s_dvp.sv", @@ -171,8 +183,8 @@ "ga2d_addr_gen.sv", "ga2d_axi4_master.sv", "ga2d_core.sv", - "ga2d_dma.sv", "ga2d_define.svh", + "ga2d_dma.sv", "ga2d_pixel.sv", "ga2d_pkg.sv", "ga2d_reg.sv", @@ -217,7 +229,6 @@ ], "rtl/ip/peripheral": [ "apb4_clint.sv", - "clock_ctrl_if.sv", "apb4_dma.sv", "apb4_gpio.sv", "apb4_hp_mailbox.sv", @@ -229,6 +240,7 @@ "clint_if.sv", "clint_reg.sv", "clint_timebase.sv", + "clock_ctrl_if.sv", "dma_axi4_master.sv", "dma_core.sv", "dma_define.svh", @@ -238,6 +250,7 @@ "gpio_core.sv", "gpio_define.svh", "gpio_if.sv", + "gpio_pad_bridge.sv", "gpio_reg.sv", "hp_mailbox_define.svh", "pll_ctrl_if.sv", @@ -328,9 +341,6 @@ "xpi_pkg.sv", "xpi_reg.sv" ], - "rtl/ip/util": [ - "async_fifo.sv" - ], "rtl/ip/usb": [ "apb4_usb2.sv", "usb2_define.svh", @@ -349,53 +359,49 @@ "usb2_ulpi_if.sv", "usb2_ulpi_link.sv" ], + "rtl/ip/util": [ + "async_fifo.sv", + "soc_common_cdc.sv", + "soc_common_fifo.sv" + ], "rtl/mini/top": [ - "ahbl2axi4.sv", "ahbl2ribp.sv", - "apb4_if_bridge.sv", "apb4_async_bridge.sv", "apb4_periph.sv", "apb4_system.sv", - "axi42apb4_system.sv", + "axi42apb4.svh", "axi42apb4_periph.sv", + "axi42apb4_state.svh", + "axi42apb4_system.sv", "axi42ram.sv", "axi42ribp.sv", "axi42ribp_burst.sv", - "axi4_bus.sv", "axi4_address_gate.sv", "axi4_async_bridge.sv", - "axi4_connector.sv", + "axi4_bus.sv", "axi4_data_crossbar.sv", - "axi4_target_guard.sv", "axi4_downsizer_64to32.sv", - "axi4_error_slave.sv", "axi4_id_prefix.sv", "axi4_interconnect.sv", "axi4_master_idle.sv", "axi4_mgmt_router.sv", + "axi4_target_guard.sv", "axi4_upsizer_32to64.sv", "axi4_word_bridge.sv", - "core_wrapper.sv", "clock_config_controller.sv", "clock_frequency_monitor.sv", + "core_wrapper.sv", "data_plane_fault_cdc.sv", "extension_compat.sv", "extension_dma_master.sv", "extension_slot.sv", "extension_subsystem.sv", "fabric_monitor.sv", - "gpio_pad_bridge.sv", "hp_axi4_mux3.sv", "hp_core_wrapper.sv", - "hp_subsystem.sv", "hp_lifecycle_controller.sv", - "mgmt_core_wrapper.sv", - "mgmt_debug_reset.sv", - "mgmt_debug_wrapper.sv", + "hp_subsystem.sv", "memory_pad_mux.sv", - "onchip_ram_define.svh", - "onchip_ram_reg.sv", - "onchip_ram.sv", "pll_rcu_controller.sv", "rcu.sv", "resource_controller.sv", @@ -416,24 +422,28 @@ "soc_clock_config.svh", "soc_clock_gate.sv", "soc_clock_reset_subsystem.sv", - "soc_common_cdc.sv", - "soc_common_fifo.sv", "soc_data_plane.sv", "user_core_design.sv", "user_core_top.sv", "user_extensions.svh", "user_ip_design_template.sv", "user_ip_top.sv", - "user_ip_wrapper.sv", - "axi42apb4.svh", - "axi42apb4_state.svh" + "user_ip_wrapper.sv" + ], + "rtl/tiny/top": [ + "retrosoc_tiny.sv", + "retrosoc_tiny_asic.sv", + "tiny_archinfo.sv", + "tiny_axi42apb4.sv", + "tiny_axi4_fabric.sv", + "tiny_sysctrl.sv" ] }, "reviewed_boundaries": [ { "paths": [ - "rtl/ip/experimental/axi4f2ribp.sv", "rtl/ip/experimental/apb4_gpu.sv", + "rtl/ip/experimental/axi4f2ribp.sv", "rtl/ip/experimental/wb2ribp.sv" ], "result": "inactive experimental source", @@ -475,16 +485,16 @@ }, { "paths": [ - "rtl/mini/top/onchip_ram.sv", - "rtl/mini/top/onchip_ram_reg.sv" + "rtl/ip/memory/onchip_ram.sv", + "rtl/ip/memory/onchip_ram_reg.sv" ], "result": "reviewed AXI and technology-memory boundary", "rationale": "AXI and APB state uses Common registers; the synchronous bank array retains the stable technology wrapper and PDK SRAM pin boundary." }, { "paths": [ - "rtl/mini/top/soc_common_cdc.sv", - "rtl/mini/top/soc_common_fifo.sv" + "rtl/ip/util/soc_common_cdc.sv", + "rtl/ip/util/soc_common_fifo.sv" ], "result": "managed compatibility wrapper retained", "rationale": "The narrow self-owned wrappers preserve required Verilator filename behavior while including managed Common source." diff --git a/rtl/rtl_style_manifest.json b/rtl/rtl_style_manifest.json index ffaf3c01..6a5f3141 100644 --- a/rtl/rtl_style_manifest.json +++ b/rtl/rtl_style_manifest.json @@ -4,7 +4,8 @@ "owned": { "roots": [ "rtl/ip", - "rtl/mini/top" + "rtl/mini/top", + "rtl/tiny/top" ], "suffixes": [ ".sv", @@ -18,7 +19,8 @@ "verification": { "roots": [ "rtl/mini/formal", - "rtl/mini/dv" + "rtl/mini/dv", + "rtl/tiny/dv" ], "suffixes": [ ".sv", diff --git a/rtl/tiny/Makefile b/rtl/tiny/Makefile new file mode 100644 index 00000000..faaaa48b --- /dev/null +++ b/rtl/tiny/Makefile @@ -0,0 +1,151 @@ +export CCACHE_DIR := $(CACHE_ROOT)/ccache/verilator +export CCACHE_TEMPDIR := $(CACHE_ROOT)/ccache/verilator/tmp + +TINY_GENERATED_DIR := $(VARIANT_ROOT)/generated/tiny +GENERATED_FL_DIR := $(FLOW_FILELIST_DIR) +FILELIST_STAMP := $(GENERATED_FL_DIR)/.stamp +MEMORY_MAP_DIR := $(TINY_GENERATED_DIR)/memory_map +MEMORY_MAP_C_DIR := $(MEMORY_MAP_DIR)/include +MEMORY_MAP_LINKER_DIR := $(MEMORY_MAP_DIR)/linker +MEMORY_MAP_STAMP := $(FILELIST_STAMP) +PIN_MAP_DIR := $(TINY_GENERATED_DIR)/pin_map +SOC_TOPOLOGY_INCLUDE_DIR := $(TINY_GENERATED_DIR)/include +SOC_TOPOLOGY_STAMP := $(FILELIST_STAMP) +SOC_IRQ_METADATA := $(SOC_TOPOLOGY_INCLUDE_DIR)/retrosoc/generated/irq_metadata.h +USER_EXTENSIONS_DIR := $(TINY_GENERATED_DIR) +USER_EXTENSIONS_STAMP := $(FILELIST_STAMP) +ARCHINFO_METADATA_DIR := $(TINY_GENERATED_DIR)/archinfo +ARCHINFO_METADATA_SCRIPT := $(ROOT_PATH)/rtl/managed/clusterip/archinfo/scripts/generate_metadata.py +ARCHINFO_METADATA_STAMP := $(ARCHINFO_METADATA_DIR)/.stamp +TINY_MAPS := $(wildcard $(RTL_PATH)/address_map/*.json $(RTL_PATH)/pin_map/*.json $(RTL_PATH)/integration/*.json) +TINY_TEMPLATES := $(wildcard $(RTL_PATH)/filelist/*.fl) +TINY_TOOLS := $(ROOT_PATH)/scripts/generate_tiny.py $(wildcard $(ROOT_PATH)/scripts/rtl/*.py) + +$(ARCHINFO_METADATA_STAMP): $(LOCK_FILE) $(wildcard $(ARCHINFO_METADATA_SCRIPT)) + @test -f $(ARCHINFO_METADATA_SCRIPT) || { echo "Run Tiny setup first" >&2; exit 1; } + $(PYTHON) $(ARCHINFO_METADATA_SCRIPT) --repo-root $(ROOT_PATH) --lock $(LOCK_FILE) \ + --config-digest $(CONFIG_DIGEST) $(if $(filter YES,$(BUILD_RELEASE)),--release) \ + --output-sv $(ARCHINFO_METADATA_DIR)/archinfo_integration_metadata.svh \ + --output-c $(ARCHINFO_METADATA_DIR)/archinfo_integration_metadata.h + @touch $@ + +$(FILELIST_STAMP): $(ROOT_PATH)/Makefile $(RTL_PATH)/Makefile $(TINY_MAPS) $(TINY_TEMPLATES) $(TINY_TOOLS) $(ARCHINFO_METADATA_STAMP) + $(PYTHON) $(ROOT_PATH)/scripts/generate_tiny.py --output $(TINY_GENERATED_DIR) \ + --filelists $(GENERATED_FL_DIR) $(foreach define,$(DEF_LIST),--define $(define)) + @touch $@ + +$(SOC_IRQ_METADATA): $(FILELIST_STAMP) + @test -f $@ + +generate_filelist memory-map pin-map soc-topology user-extensions: $(FILELIST_STAMP) +archinfo-metadata: $(ARCHINFO_METADATA_STAMP) +check-memory-map: + $(PYTHON) $(ROOT_PATH)/scripts/rtl/generate_memory_map.py --map $(RTL_PATH)/address_map/memory_map.json --check +check-pin-map: + $(PYTHON) $(ROOT_PATH)/scripts/rtl/generate_pin_map.py --map $(RTL_PATH)/pin_map/pin_map.json --check +check-soc-topology: + $(PYTHON) $(ROOT_PATH)/scripts/generate_tiny.py --check +check-clock-reset-domains: + $(PYTHON) $(ROOT_PATH)/scripts/check_clock_reset_domains.py --map $(RTL_PATH)/integration/clock_reset_domains.json --root $(ROOT_PATH) + +RTL_FILELISTS := $(addprefix $(GENERATED_FL_DIR)/,def.fl inc.fl commonip.fl clusterip.fl ip.fl tech.fl core_hazard3.fl top.fl) +RTL_FLIST := $(foreach filelist,$(RTL_FILELISTS),-f $(filelist)) +PDK_FILELIST := $(GENERATED_FL_DIR)/pdk_ihp130.fl +TINY_TB_FLIST := -f $(GENERATED_FL_DIR)/tb.fl +TOP_DESIGN := retrosoc_tiny_asic +RTL_NAME := retrosoc_tiny_asic +OPENSTA_NETLIST := $(SYN_BUILD_ROOT)/out/$(RTL_NAME)_yosys.v +OPENSTA_CONFIG := $(SYN_BUILD_ROOT)/out/$(RTL_NAME)_yosys.config +NETLIST_PATH := $(OPENSTA_NETLIST) +TINY_CONVERTED := $(SIM_BUILD_ROOT)/converted_soc.v +TINY_DEPFILE := $(SIM_BUILD_ROOT)/sources.d +TINY_LINT_LOG := $(VARIANT_ROOT)/lint/verilator/lint.log +SOC_SIM_TIME ?= 1800 +TINY_SIM_TIMEOUT ?= 20000000 +VERILATOR ?= verilator +IVERILOG ?= iverilog +VVP ?= vvp + +include $(ROOT_PATH)/rtl/mk/software.mk +-include $(TINY_DEPFILE) + +$(TINY_CONVERTED): $(FILELIST_STAMP) + @mkdir -p $(@D) + $(PYTHON) $(ROOT_PATH)/scripts/rtl/convt_sv2v.py $(RTL_FLIST) --output $@ + $(PYTHON) $(ROOT_PATH)/scripts/rtl/filelist_deps.py $(RTL_FLIST) \ + --target $@ --output $(TINY_DEPFILE) + +ifeq ($(SIMU),VERILATOR) +$(SIM_BUILD_ROOT)/emu: $(FILELIST_STAMP) $(wildcard $(RTL_PATH)/dv/*.sv) + @mkdir -p $(SIM_BUILD_ROOT) $(CCACHE_TEMPDIR) + $(PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool verilator \ + --log $(SIM_BUILD_ROOT)/compile.log --result $(SIM_BUILD_ROOT)/result-compile.json -- \ + $(VERILATOR) --binary --timing --assert -j $(JOBS) --top-module $(RTL_TOP) \ + -Wno-fatal --timescale 1ns/1ps --Mdir $(SIM_BUILD_ROOT)/obj_dir -o $(SIM_BUILD_ROOT)/emu \ + $(RTL_FLIST) -f $(PDK_FILELIST) $(TINY_TB_FLIST) + $(PYTHON) $(ROOT_PATH)/scripts/rtl/filelist_deps.py $(RTL_FLIST) $(TINY_TB_FLIST) \ + --target $@ --output $(TINY_DEPFILE) +comp: $(SIM_BUILD_ROOT)/emu +TINY_RUN := timeout --foreground $(SOC_SIM_TIME)s $(SIM_BUILD_ROOT)/emu +else +$(SIM_BUILD_ROOT)/simv: $(TINY_CONVERTED) $(wildcard $(RTL_PATH)/dv/*.sv) + $(PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool iverilog \ + --log $(SIM_BUILD_ROOT)/compile.log --result $(SIM_BUILD_ROOT)/result-compile.json -- \ + $(IVERILOG) -g2012 -gno-specify -s $(RTL_TOP) -o $@ -f $(GENERATED_FL_DIR)/def.fl \ + -f $(GENERATED_FL_DIR)/inc.fl -f $(PDK_FILELIST) $(TINY_TB_FLIST) $(TINY_CONVERTED) +comp: $(SIM_BUILD_ROOT)/simv +TINY_RUN := $(VVP) $(SIM_BUILD_ROOT)/simv +endif + +rtl-lint: $(FILELIST_STAMP) | manifest + $(PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool rtl-lint \ + --log $(TINY_LINT_LOG) --result $(VARIANT_ROOT)/lint/verilator/result-rtl-lint.json -- \ + $(VERILATOR) --lint-only --timing --assert --timescale 1ns/1ps --Wall -Wno-fatal \ + --top-module retrosoc_tiny_asic $(RTL_FLIST) -f $(PDK_FILELIST) +check-rtl-lint: rtl-lint + $(PYTHON) $(ROOT_PATH)/scripts/analyze_warnings.py check --root $(ROOT_PATH) \ + --profile $(PROFILE_NAME) --variant-root $(VARIANT_ROOT) --tool rtl-lint \ + --output $(META_DIR)/rtl-lint-warnings.json + +sim: comp firmware | manifest + $(PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool $(SIM_TOOL_NAME)-sim \ + --log $(SIM_BUILD_ROOT)/sim.log --result $(SIM_BUILD_ROOT)/result-sim.json -- \ + $(TINY_RUN) +firmware=$(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex +max_cycles=$(TINY_SIM_TIMEOUT) + $(PYTHON) $(ROOT_PATH)/scripts/check_simulation.py --log $(SIM_BUILD_ROOT)/sim.log \ + --result $(SIM_BUILD_ROOT)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)' + +netcomp: $(FILELIST_STAMP) + @mkdir -p $(NETLIST_SIM_ROOT) + $(PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool iverilog \ + --log $(NETLIST_SIM_ROOT)/compile.log --result $(NETLIST_SIM_ROOT)/result-compile.json -- \ + $(IVERILOG) -g2012 -gno-specify -DRETROSOC_SOC__TINY_NETLIST -s $(RTL_TOP) -o $(NETLIST_SIM_ROOT)/simv \ + -f $(GENERATED_FL_DIR)/def.fl -f $(GENERATED_FL_DIR)/inc.fl -f $(PDK_FILELIST) \ + $(TINY_TB_FLIST) $(NETLIST_PATH) +netsim: netcomp firmware | manifest + $(PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool iverilog-sim \ + --log $(NETLIST_SIM_ROOT)/sim.log --result $(NETLIST_SIM_ROOT)/result-sim.json -- \ + $(VVP) $(NETLIST_SIM_ROOT)/simv +firmware=$(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex +max_cycles=$(TINY_SIM_TIMEOUT) + $(PYTHON) $(ROOT_PATH)/scripts/check_simulation.py --log $(NETLIST_SIM_ROOT)/sim.log \ + --result $(NETLIST_SIM_ROOT)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)' + +.PHONY: generate_filelist memory-map pin-map soc-topology user-extensions archinfo-metadata \ + check-memory-map check-pin-map check-soc-topology check-clock-reset-domains comp sim \ + rtl-lint check-rtl-lint netcomp netsim netsim-boot + +TINY_BOOT_ELF := $(SW_BUILD_DIR)/tiny_boot.elf +$(TINY_BOOT_ELF): $(ROOT_PATH)/app/asm/tiny_boot.S $(FILELIST_STAMP) + @mkdir -p $(SW_BUILD_DIR) + $(CC) -march=rv32im_zicsr -mabi=ilp32 -nostdlib -I$(MEMORY_MAP_C_DIR) -I$(SOC_TOPOLOGY_INCLUDE_DIR) \ + -Wl,-Ttext=0x0,--entry=_start,--build-id=none -o $@ $< + $(OBJC) -O verilog $@ $(SW_BUILD_DIR)/tiny_boot.hex + $(OBJC) -O binary $@ $(SW_BUILD_DIR)/tiny_boot.bin + +tiny-boot-image: $(TINY_BOOT_ELF) +netsim-boot: netcomp tiny-boot-image | manifest + $(PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool iverilog-sim \ + --log $(NETLIST_SIM_ROOT)/sim.log --result $(NETLIST_SIM_ROOT)/result-sim.json -- \ + $(VVP) $(NETLIST_SIM_ROOT)/simv +firmware=$(SW_BUILD_DIR)/tiny_boot.hex +max_cycles=100000 + $(PYTHON) $(ROOT_PATH)/scripts/check_simulation.py --log $(NETLIST_SIM_ROOT)/sim.log \ + --result $(NETLIST_SIM_ROOT)/result-sim-check.json --require 'SIM_TEST_PASS' + +.PHONY: tiny-boot-image \ No newline at end of file diff --git a/rtl/tiny/README.md b/rtl/tiny/README.md new file mode 100644 index 00000000..0db50f25 --- /dev/null +++ b/rtl/tiny/README.md @@ -0,0 +1,32 @@ +# Tiny MCU Integration + +Tiny is the independent single-Hazard3 wired MCU product. Its frozen contract +is [Tiny MCU](../../docs/ip/tiny-soc.md). Use +`make CONFIG=configs/ci/ihp130-tiny.mk setup` followed by +`make CONFIG=configs/ci/ihp130-tiny.mk firmware sim`. + +`top` owns product integration, `address_map`, `pin_map` and `integration` own +canonical address, pad, IRQ and clock/reset inputs, `filelist` selects sources, +`dv` owns product verification, and `mk` owns product configuration. Reusable +RTL lives in `rtl/ip`; Common and Hazard3 remain locked managed inputs. +No Tiny source list includes RIB/RIBP or Mini product RTL. Build rules invoke +shared helpers in `scripts/rtl` directly; generated files belong only under +the selected build variant. + +The initial IHP130 profile has 128 KiB SRAM, 24 MHz AXI32/APB4, four DMA channels, +and RV32IMC without atomics. Wireless, external RAM, HP cores and accelerators +are outside this release. Run both Icarus and Verilator, the Tiny directed +tests, and the IHP130 regression before claiming qualification. Synthesis and +STA use the Tiny top and clock inventory, not Mini constraints. + +`make CONFIG=configs/ci/ihp130-tiny.mk regress-pr` runs only Tiny's IHP130 +matrix. The regression runner also accepts `--soc TINY`; leaving it unset +retains the combined Mini/Tiny IHP130 matrix. `netsim-boot` uses the compact +assembly SRAM/pad test, while `netsim` uses the full SDK acceptance image. +See the [verification record](../../docs/ip/tiny-soc-verification.md) for +qualification boundaries and the observed reset-distribution timing deficit. + +The [Tiny Gen1 datasheet](../../publications/datasheets/tiny/README.md) provides +the source-bound product/register/software reference. Its publication build is +separate from RTL acceptance and does not promote historical test or timing +records into new qualification results. diff --git a/rtl/tiny/address_map/memory_map.json b/rtl/tiny/address_map/memory_map.json new file mode 100644 index 00000000..0036f910 --- /dev/null +++ b/rtl/tiny/address_map/memory_map.json @@ -0,0 +1,406 @@ +{ + "schema_version": 2, + "cpu_reset": "0x00000000", + "sysctrl_registers": [ + { + "symbol": "CORESEL", + "offset": "0x00" + }, + { + "symbol": "IPSEL", + "offset": "0x04" + }, + { + "symbol": "PLL_CFG", + "offset": "0x08" + }, + { + "symbol": "PLL_CMD", + "offset": "0x0C" + }, + { + "symbol": "FAULT_STATUS", + "offset": "0x10" + }, + { + "symbol": "FAULT_ADDR", + "offset": "0x14" + }, + { + "symbol": "FAULT_COUNT", + "offset": "0x18" + }, + { + "symbol": "PLL_STATUS", + "offset": "0x1C" + }, + { + "symbol": "USER_CORE_RESET", + "offset": "0x20" + }, + { + "symbol": "USER_CORE_STATUS", + "offset": "0x24" + }, + { + "symbol": "FAULT_MASTER", + "offset": "0x28" + }, + { + "symbol": "FAULT_DETAIL", + "offset": "0x2C" + }, + { + "symbol": "PERF_CTRL", + "offset": "0x40" + }, + { + "symbol": "PERF_MGMT_WAIT_LO", + "offset": "0x44" + }, + { + "symbol": "PERF_MGMT_WAIT_HI", + "offset": "0x48" + }, + { + "symbol": "PERF_USER_WAIT_LO", + "offset": "0x4C" + }, + { + "symbol": "PERF_USER_WAIT_HI", + "offset": "0x50" + }, + { + "symbol": "PERF_DMA_WAIT_LO", + "offset": "0x54" + }, + { + "symbol": "PERF_DMA_WAIT_HI", + "offset": "0x58" + }, + { + "symbol": "PERF_APB4_PERIPH_WAIT_LO", + "offset": "0x5C" + }, + { + "symbol": "PERF_APB4_PERIPH_WAIT_HI", + "offset": "0x60" + }, + { + "symbol": "PERF_APB4_SYSTEM_WAIT_LO", + "offset": "0x64" + }, + { + "symbol": "PERF_APB4_SYSTEM_WAIT_HI", + "offset": "0x68" + }, + { + "symbol": "PERF_SDRAM_WAIT_LO", + "offset": "0x6C" + }, + { + "symbol": "PERF_SDRAM_WAIT_HI", + "offset": "0x70" + }, + { + "symbol": "PERF_PSRAM_WAIT_LO", + "offset": "0x74" + }, + { + "symbol": "PERF_PSRAM_WAIT_HI", + "offset": "0x78" + }, + { + "symbol": "PERF_FLASH_WAIT_LO", + "offset": "0x7C" + }, + { + "symbol": "PERF_FLASH_WAIT_HI", + "offset": "0x80" + }, + { + "symbol": "TEST_STATUS", + "offset": "0x84" + }, + { + "symbol": "RTC_WAKE_STATUS", + "offset": "0x88" + }, + { + "symbol": "PERF_SDIO0_WAIT_LO", + "offset": "0x8C" + }, + { + "symbol": "PERF_SDIO0_WAIT_HI", + "offset": "0x90" + }, + { + "symbol": "PERF_SDIO1_WAIT_LO", + "offset": "0x94" + }, + { + "symbol": "PERF_SDIO1_WAIT_HI", + "offset": "0x98" + }, + { + "symbol": "PERF_USB2_WAIT_LO", + "offset": "0x9C" + }, + { + "symbol": "PERF_USB2_WAIT_HI", + "offset": "0xA0" + }, + { + "symbol": "HP_CTRL", + "offset": "0xA4" + }, + { + "symbol": "HP_STATUS", + "offset": "0xA8" + }, + { + "symbol": "DEBUG_SELECT", + "offset": "0xAC" + }, + { + "symbol": "CLK_HP_REQ", + "offset": "0xB0" + }, + { + "symbol": "CLK_HP_CURRENT", + "offset": "0xB4" + }, + { + "symbol": "CLK_LP_CFG", + "offset": "0xB8" + }, + { + "symbol": "CLK_PCLK_CFG", + "offset": "0xBC" + }, + { + "symbol": "CLK_STATUS", + "offset": "0xC0" + }, + { + "symbol": "CLK_FAULT", + "offset": "0xC4" + }, + { + "symbol": "CLK_TIMEOUT", + "offset": "0xC8" + }, + { + "symbol": "CLK_GATE", + "offset": "0xCC" + }, + { + "symbol": "MEM_PAD_CTRL", + "offset": "0xD0" + }, + { + "symbol": "MEM_PAD_STATUS", + "offset": "0xD4" + }, + { + "symbol": "MEM_PAD_FAULT", + "offset": "0xD8" + } + ], + "regions": [ + { + "symbol": "FLASH", + "base": "0x00000000", + "size": "0x01000000", + "route": "axi4", + "kind": "active", + "public": true, + "linker": "FLASH", + "user_access": "ro", + "burst": "incr16" + }, + { + "symbol": "APB4_GPIO", + "base": "0x10000000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "rw" + }, + { + "symbol": "APB4_UART0", + "base": "0x10001000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "rw" + }, + { + "symbol": "APB4_TIM0", + "base": "0x10002000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "rw" + }, + { + "symbol": "APB4_TIM1", + "base": "0x10003000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "rw" + }, + { + "symbol": "APB4_I2C0", + "base": "0x10006000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "rw" + }, + { + "symbol": "APB4_XPI", + "base": "0x10009000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "none" + }, + { + "symbol": "APB4_DMA", + "base": "0x1000A000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "none" + }, + { + "symbol": "APB4_SYSCTRL", + "base": "0x1000B000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "none" + }, + { + "symbol": "APB4_CLINT", + "base": "0x10020000", + "size": "0x00010000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "none" + }, + { + "symbol": "APB4_I2C1", + "base": "0x10011000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "rw" + }, + { + "symbol": "APB4_GPIO_ADMIN", + "base": "0x10014000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "none" + }, + { + "symbol": "APB4_SRAM", + "base": "0x10017000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "none" + }, + { + "symbol": "APB4_UART1", + "base": "0x10018000", + "size": "0x00001000", + "route": "apb4_periph", + "kind": "active", + "public": true, + "user_access": "rw" + }, + { + "symbol": "APB4_ARCHINFO", + "base": "0x20000000", + "size": "0x00001000", + "route": "apb4_system", + "kind": "active", + "public": true, + "user_access": "ro" + }, + { + "symbol": "APB4_PWM", + "base": "0x20002000", + "size": "0x00001000", + "route": "apb4_system", + "kind": "active", + "public": true, + "user_access": "rw" + }, + { + "symbol": "APB4_RTC", + "base": "0x20004000", + "size": "0x00001000", + "route": "apb4_system", + "kind": "active", + "public": true, + "user_access": "rw" + }, + { + "symbol": "APB4_WDG", + "base": "0x20005000", + "size": "0x00001000", + "route": "apb4_system", + "kind": "active", + "public": true, + "user_access": "none" + }, + { + "symbol": "SRAM", + "base": "0x30000000", + "size": "0x00020000", + "size_options": [ + "0x00001000", + "0x00004000", + "0x00008000", + "0x00010000", + "0x00020000" + ], + "route": "ram", + "kind": "active", + "public": true, + "linker": "SRAM", + "user_access": "rw", + "burst": "incr16" + }, + { + "symbol": "XPI", + "base": "0x50000000", + "size": "0x10000000", + "route": "axi4", + "kind": "active", + "public": true, + "user_access": "rw", + "burst": "incr16" + } + ], + "legacy_rib": false, + "capability_header": "retrosoc/generated/soc_features.h" +} diff --git a/rtl/tiny/dv/retrosoc_tiny_tb.sv b/rtl/tiny/dv/retrosoc_tiny_tb.sv new file mode 100644 index 00000000..d29f15c6 --- /dev/null +++ b/rtl/tiny/dv/retrosoc_tiny_tb.sv @@ -0,0 +1,86 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 +`timescale 1ns / 1ps + +module retrosoc_tiny_tb; + logic s_clk_driver = 1'b0; + wire s_clk = s_clk_driver; + logic s_reset_driver = 1'b0; + wire s_rst_n = s_reset_driver; + wire s_uart0_tx, s_uart1_tx; + wire s_uart0_rx = 1'b1; + wire s_uart1_rx = 1'b1; + wire s_jtag_tck = 1'b0; + wire s_jtag_tms = 1'b1; + wire s_jtag_tdi = 1'b0; + wire s_jtag_trst_n = s_rst_n; + wire s_jtag_tdo; + tri1 [31:0] s_gpio; + wire s_xpi_sck; + wire [ 3:0] s_xpi_nss; + tri [ 3:0] s_xpi_data; + integer s_cycles; + integer s_max_cycles = 20000000; + integer s_done_cycles = 0; + logic [ 7:0] s_uart_byte; + +`ifdef RETROSOC_SOC__TINY_NETLIST + wire [7:0] s_test_code = { + u_dut.s_test_code_7_, + u_dut.s_test_code_6_, + u_dut.s_test_code_5_, + u_dut.s_test_code_4_, + u_dut.s_test_code_3_, + u_dut.s_test_code_2_, + u_dut.s_test_code_1_, + u_dut.s_test_code_0_ + }; +`else + wire [7:0] s_test_code = u_dut.s_test_code; +`endif + + always #20.833333 s_clk_driver = !s_clk_driver; + initial begin + if ($value$plusargs("max_cycles=%d", s_max_cycles)) begin + end + repeat (20) @(posedge s_clk); + @(negedge s_clk); + s_reset_driver = 1'b1; + for (s_cycles = 0; s_cycles < s_max_cycles; s_cycles = s_cycles + 1) begin + @(posedge s_clk); + if (u_dut.s_test_done) begin + if (!u_dut.s_test_pass) $fatal(1, "SIM_TEST_FAIL code=%0d", s_test_code); + s_done_cycles = s_done_cycles + 1; + if (s_done_cycles == 128) begin + $display("SIM_TEST_PASS Tiny cycles=%0d", s_cycles); + $finish; + end + end + end + if (s_done_cycles != 128) $fatal(1, "SIM_TEST_TIMEOUT Tiny cycles=%0d", s_cycles); + end + +`ifdef RETROSOC_SOC__TINY_NETLIST + // UART0 diagnostic output; SYSCTRL remains the authoritative test verdict. + initial + forever begin + @(negedge s_uart0_tx); + #1627.604; + for (int bit_index = 0; bit_index < 8; bit_index++) begin + s_uart_byte[bit_index] = s_uart0_tx; + #1085.069; + end + $write("%c", s_uart_byte); + end + +`endif + + retrosoc_tiny_asic u_dut ( + `include "retrosoc_asic_tb_bindings.svh" + ); + tiny_qspi_nor u_flash ( + .sck_i (s_xpi_sck), + .cs_n_i (s_xpi_nss[0]), + .data_io(s_xpi_data) + ); +endmodule diff --git a/rtl/tiny/dv/tiny_qspi_nor.sv b/rtl/tiny/dv/tiny_qspi_nor.sv new file mode 100644 index 00000000..9f2afc1b --- /dev/null +++ b/rtl/tiny/dv/tiny_qspi_nor.sv @@ -0,0 +1,91 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 +`timescale 1ns / 1ps + +// Pin-level 0xEB NOR model: 8 command bits, 24 quad address bits, 8 mode +// bits and four dummy clocks. Unsupported commands fail closed. This model +// verifies reset-read transport; program/erase and analog NOR timing are not +// represented. Both simulators use exactly this same serial model. +module tiny_qspi_nor ( + input logic sck_i, + input logic cs_n_i, + inout wire [3:0] data_io +); + typedef enum logic [2:0] { + Command, + Address, + Mode, + Dummy, + Data + } state_e; + state_e s_state; + logic [ 7:0] s_memory [0:16777215]; + logic [ 7:0] s_command; + logic [23:0] s_address; + logic [ 3:0] s_output; + integer s_count; + integer s_nibble; + string s_firmware; + + assign data_io = (!cs_n_i && (s_state == Data)) ? s_output : 4'bzzzz; + initial begin + s_state = Command; + s_count = 0; + s_command = '0; + s_address = '0; + if (!$value$plusargs("firmware=%s", s_firmware)) $fatal(1, "Missing +firmware hex image"); + $readmemh(s_firmware, s_memory); + end + always @(posedge sck_i or posedge cs_n_i) begin + if (cs_n_i) begin + s_state = Command; + s_count = 0; + s_command = '0; + s_address = '0; + end else begin + case (s_state) + Command: begin + s_command = {s_command[6:0], data_io[0]}; + if (s_count == 7) begin + if (s_command != 8'heb) $fatal(1, "Unsupported NOR command %02x", s_command); + s_state = Address; + s_count = 0; + end else s_count = s_count + 1; + end + Address: begin + s_address = {s_address[19:0], data_io}; + if (s_count == 5) begin + s_state = Mode; + s_count = 0; + end else s_count = s_count + 1; + end + Mode: begin + if (s_count == 1) begin + s_state = Dummy; + s_count = 0; + end else s_count = s_count + 1; + end + Dummy: begin + if (s_count == 3) s_state = Data; + else s_count = s_count + 1; + end + Data: begin + end + default: $fatal(1, "Invalid NOR state"); + endcase + end + end + always @(negedge sck_i or posedge cs_n_i) begin + if (cs_n_i) begin + s_nibble = 0; + s_output = '0; + end else if (s_state == Data) begin + if ((s_nibble & 1) == 0) s_output = s_memory[s_address+(s_nibble/2)][7:4]; + else s_output = s_memory[s_address+(s_nibble/2)][3:0]; + s_nibble = s_nibble + 1; + end else begin + s_nibble = 0; + s_output = '0; + end + end +endmodule diff --git a/rtl/tiny/filelist/clusterip.fl b/rtl/tiny/filelist/clusterip.fl new file mode 100644 index 00000000..33e91aeb --- /dev/null +++ b/rtl/tiny/filelist/clusterip.fl @@ -0,0 +1,24 @@ +/clusterip/archinfo/rtl/archinfo_reg.sv +/clusterip/archinfo/rtl/apb4_archinfo.sv +/clusterip/pwm/rtl/pwm_pkg.sv +/clusterip/pwm/rtl/pwm_tickgen.sv +/clusterip/pwm/rtl/pwm_timer.sv +/clusterip/pwm/rtl/pwm_channel.sv +/clusterip/pwm/rtl/pwm_deadtime.sv +/clusterip/pwm/rtl/pwm_carrier.sv +/clusterip/pwm/rtl/pwm_capture.sv +/clusterip/pwm/rtl/pwm_core.sv +/clusterip/pwm/rtl/pwm_reg.sv +/clusterip/pwm/rtl/pwm_if.sv +/clusterip/pwm/rtl/apb4_pwm.sv +/clusterip/rtc/rtl/rtc_pkg.sv +/clusterip/rtc/rtl/rtc_if.sv +/clusterip/rtc/rtl/rtc_tickgen.sv +/clusterip/rtc/rtl/rtc_core.sv +/clusterip/rtc/rtl/rtc_reg.sv +/clusterip/rtc/rtl/apb4_rtc.sv +/clusterip/wdg/rtl/wdg_pkg.sv +/clusterip/wdg/rtl/wdg_if.sv +/clusterip/wdg/rtl/wdg_core.sv +/clusterip/wdg/rtl/wdg_reg.sv +/clusterip/wdg/rtl/apb4_wdg.sv diff --git a/rtl/tiny/filelist/commonip.fl b/rtl/tiny/filelist/commonip.fl new file mode 100644 index 00000000..d603e2c4 --- /dev/null +++ b/rtl/tiny/filelist/commonip.fl @@ -0,0 +1,22 @@ +/clusterip/common/rtl/interface/apb4_if.sv +/clusterip/common/rtl/interface/apb4_pure_if.sv +/clusterip/common/rtl/interface/ahbl_if.sv +/clusterip/common/rtl/interface/axi4_if.sv +/clusterip/common/rtl/interface/axi4_addr_gen.sv +/clusterip/common/rtl/interface/axi4_stream_if.sv +/clusterip/common/rtl/interface/ram_if.sv +/clusterip/common/rtl/utils/register.sv +/clusterip/common/rtl/utils/spill_register.sv +/clusterip/common/rtl/stream/round_robin_arbiter.sv +/clusterip/common/rtl/utils/lfsr.sv +/clusterip/common/rtl/utils/bin2gray.sv +/clusterip/common/rtl/utils/gray2bin.sv +/clusterip/common/rtl/base/ecc_secded.sv +/clusterip/common/rtl/utils/edge_det.sv +/clusterip/common/rtl/cdc/cdc_sync.sv +/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv +/clusterip/common/rtl/cdc/cdc_2phase.sv +/clusterip/common/rtl/clkrst/rst_sync.sv +/clusterip/common/rtl/clkrst/counter.sv +/ip/util/soc_common_fifo.sv +/ip/util/soc_common_cdc.sv diff --git a/rtl/tiny/filelist/core_hazard3.fl b/rtl/tiny/filelist/core_hazard3.fl new file mode 100644 index 00000000..19f4138a --- /dev/null +++ b/rtl/tiny/filelist/core_hazard3.fl @@ -0,0 +1,28 @@ +/hazard3/hazard3_core.v +/hazard3/hazard3_cpu_1port.v +/hazard3/hazard3_cpu_2port.v +/hazard3/arith/hazard3_alu.v +/hazard3/arith/hazard3_branchcmp.v +/hazard3/arith/hazard3_mul_fast.v +/hazard3/arith/hazard3_muldiv_seq.v +/hazard3/arith/hazard3_onehot_encode.v +/hazard3/arith/hazard3_onehot_priority.v +/hazard3/arith/hazard3_onehot_priority_dynamic.v +/hazard3/arith/hazard3_priority_encode.v +/hazard3/arith/hazard3_shift_barrel.v +/hazard3/hazard3_csr.v +/hazard3/hazard3_decode.v +/hazard3/hazard3_frontend.v +/hazard3/hazard3_instr_decompress.v +/hazard3/hazard3_irq_ctrl.v +/hazard3/hazard3_pmp.v +/hazard3/hazard3_power_ctrl.v +/hazard3/hazard3_regfile_1w2r.v +/hazard3/hazard3_triggers.v +/hazard3/debug/cdc/hazard3_apb_async_bridge.v +/hazard3/debug/cdc/hazard3_reset_sync.v +/hazard3/debug/cdc/hazard3_sync_1bit.v +/hazard3/debug/dtm/hazard3_jtag_dtm_core.v +/hazard3/debug/dtm/hazard3_jtag_dtm.v +/hazard3/debug/dm/hazard3_dm.v ++incdir+/hazard3/ diff --git a/rtl/tiny/filelist/inc.fl b/rtl/tiny/filelist/inc.fl new file mode 100644 index 00000000..6bfcb184 --- /dev/null +++ b/rtl/tiny/filelist/inc.fl @@ -0,0 +1,19 @@ ++incdir+/top ++incdir+/clusterip/common/rtl ++incdir+/clusterip/common/rtl/cdc ++incdir+/clusterip/common/rtl/clkrst ++incdir+/clusterip/common/rtl/clock ++incdir+/clusterip/common/rtl/interface ++incdir+/clusterip/common/rtl/tech ++incdir+/clusterip/common/rtl/utils ++incdir+/clusterip/archinfo/rtl ++incdir+/clusterip/pwm/rtl ++incdir+/clusterip/rtc/rtl ++incdir+/clusterip/wdg/rtl ++incdir+/ip/interconnect ++incdir+/ip/util ++incdir+/ip/memory ++incdir+/ip/storage ++incdir+/ip/serial ++incdir+/ip/peripheral ++incdir+/ip/core diff --git a/rtl/tiny/filelist/ip.fl b/rtl/tiny/filelist/ip.fl new file mode 100644 index 00000000..097d03f2 --- /dev/null +++ b/rtl/tiny/filelist/ip.fl @@ -0,0 +1,48 @@ +/ip/serial/i2c_if.sv +/ip/serial/i2c_filter.sv +/ip/serial/i2c_core.sv +/ip/serial/i2c_reg.sv +/ip/serial/apb4_i2c.sv +/ip/serial/uart_if.sv +/ip/serial/uart_baudgen.sv +/ip/serial/apb4_uart_tx.sv +/ip/serial/apb4_uart_rx.sv +/ip/serial/uart_flow_ctrl.sv +/ip/serial/uart_core.sv +/ip/serial/uart_reg.sv +/ip/serial/apb4_uart.sv +/ip/storage/xpi_pkg.sv +/ip/storage/xpi_if.sv +/ip/storage/xpi_reg.sv +/ip/storage/xpi_mm.sv +/ip/storage/xpi_indirect.sv +/ip/storage/xpi_clkgen.sv +/ip/storage/xpi_core.sv +/ip/storage/apb4_xpi.sv +/ip/peripheral/dma_pkg.sv +/ip/peripheral/dma_req_if.sv +/ip/peripheral/dma_axi4_master.sv +/ip/peripheral/dma_reg.sv +/ip/peripheral/dma_core.sv +/ip/peripheral/apb4_dma.sv +/ip/peripheral/clint_if.sv +/ip/peripheral/clint_reg.sv +/ip/peripheral/clint_core.sv +/ip/peripheral/apb4_clint.sv +/ip/peripheral/timer_core.sv +/ip/peripheral/timer_reg.sv +/ip/peripheral/apb4_timer.sv +/ip/peripheral/gpio_if.sv +/ip/peripheral/user_gpio_if.sv +/ip/peripheral/gpio_core.sv +/ip/peripheral/gpio_reg.sv +/ip/peripheral/apb4_gpio.sv +/ip/memory/onchip_ram_reg.sv +/ip/memory/onchip_ram.sv +/ip/interconnect/ahbl2axi4.sv +/ip/interconnect/axi4_connector.sv +/ip/interconnect/axi4_error_slave.sv +/ip/core/mgmt_debug_reset.sv +/ip/core/mgmt_debug_wrapper.sv +/ip/core/mgmt_core_wrapper.sv +/ip/peripheral/gpio_pad_bridge.sv diff --git a/rtl/tiny/filelist/netlist_support.fl b/rtl/tiny/filelist/netlist_support.fl new file mode 100644 index 00000000..71a99538 --- /dev/null +++ b/rtl/tiny/filelist/netlist_support.fl @@ -0,0 +1 @@ +// The Tiny testbench uses only scalar pad ports. diff --git a/rtl/tiny/filelist/sys_def.fl b/rtl/tiny/filelist/sys_def.fl new file mode 100644 index 00000000..58b038bd --- /dev/null +++ b/rtl/tiny/filelist/sys_def.fl @@ -0,0 +1 @@ +// Tiny uses no external DRAM model definitions. diff --git a/rtl/tiny/filelist/tb.fl b/rtl/tiny/filelist/tb.fl new file mode 100644 index 00000000..106d6b51 --- /dev/null +++ b/rtl/tiny/filelist/tb.fl @@ -0,0 +1,2 @@ +/dv/tiny_qspi_nor.sv +/dv/retrosoc_tiny_tb.sv diff --git a/rtl/tiny/filelist/tech.fl b/rtl/tiny/filelist/tech.fl new file mode 100644 index 00000000..e82b3a91 --- /dev/null +++ b/rtl/tiny/filelist/tech.fl @@ -0,0 +1,3 @@ +/tech/tc_io.sv +/tech/tc_clk.sv +/tech/tc_sram.sv diff --git a/rtl/tiny/filelist/top.fl b/rtl/tiny/filelist/top.fl new file mode 100644 index 00000000..fbea0eac --- /dev/null +++ b/rtl/tiny/filelist/top.fl @@ -0,0 +1,6 @@ +/top/tiny_axi4_fabric.sv +/top/tiny_axi42apb4.sv +/top/tiny_sysctrl.sv +/top/tiny_archinfo.sv +/top/retrosoc_tiny.sv +/top/retrosoc_tiny_asic.sv diff --git a/rtl/tiny/integration/clock_reset_domains.json b/rtl/tiny/integration/clock_reset_domains.json new file mode 100644 index 00000000..718581e9 --- /dev/null +++ b/rtl/tiny/integration/clock_reset_domains.json @@ -0,0 +1,57 @@ +{ + "schema_version": 2, + "reset_ports": [ + "ext_rst_n_i_pad", + "jtag_trst_n_i_pad" + ], + "domains": [ + { + "name": "system", + "clock": "clk_i", + "reset": "s_rst_n", + "reset_source": "rst_n_i", + "reset_primitive": "rst_sync", + "path": "rtl/tiny/top/retrosoc_tiny.sv", + "instance": "u_system_rst_sync", + "sta": { + "source_port": "extclk_i_pad", + "pin": "u_clock_buffer/clk_o", + "period_ns": 41.666666667, + "async_group": "system" + } + }, + { + "name": "jtag", + "clock": "s_jtag_tck_buf", + "reset": "s_jtag_trst_n_sync", + "reset_source": "jtag_trst_n_i", + "reset_primitive": "rst_sync", + "path": "rtl/ip/core/mgmt_debug_wrapper.sv", + "instance": "u_jtag_rst_sync", + "sta": { + "source_port": "jtag_tck_i_pad", + "object_type": "port", + "period_ns": 100.0, + "async_group": "jtag" + } + } + ], + "crossings": [ + { + "name": "debug_dmi", + "source": "jtag", + "destination": "system", + "primitive": "hazard3_apb_async_bridge", + "path": "rtl/managed/hazard3/hdl/debug/dtm/hazard3_jtag_dtm_core.v", + "instance": "inst_hazard3_apb_async_bridge" + }, + { + "name": "debug_hard_reset", + "source": "jtag", + "destination": "system", + "primitive": "cdc_sync", + "path": "rtl/ip/core/mgmt_debug_wrapper.sv", + "instance": "u_dmihardreset_cdc_sync" + } + ] +} diff --git a/rtl/tiny/integration/soc_topology.json b/rtl/tiny/integration/soc_topology.json new file mode 100644 index 00000000..004795d2 --- /dev/null +++ b/rtl/tiny/integration/soc_topology.json @@ -0,0 +1,614 @@ +{ + "schema_version": 1, + "gpio_pins": 32, + "irq_vector_width": 32, + "external_irq_count": 30, + "dma_channels": 4, + "apb_targets": [ + { + "name": "gpio", + "regions": [ + "APB4_GPIO", + "APB4_GPIO_ADMIN" + ] + }, + { + "name": "uart0", + "regions": [ + "APB4_UART0" + ] + }, + { + "name": "uart1", + "regions": [ + "APB4_UART1" + ] + }, + { + "name": "timer0", + "regions": [ + "APB4_TIM0" + ] + }, + { + "name": "timer1", + "regions": [ + "APB4_TIM1" + ] + }, + { + "name": "i2c0", + "regions": [ + "APB4_I2C0" + ] + }, + { + "name": "i2c1", + "regions": [ + "APB4_I2C1" + ] + }, + { + "name": "xpi", + "regions": [ + "APB4_XPI" + ] + }, + { + "name": "dma", + "regions": [ + "APB4_DMA" + ] + }, + { + "name": "sysctrl", + "regions": [ + "APB4_SYSCTRL" + ] + }, + { + "name": "clint", + "regions": [ + "APB4_CLINT" + ] + }, + { + "name": "sram", + "regions": [ + "APB4_SRAM" + ] + }, + { + "name": "archinfo", + "regions": [ + "APB4_ARCHINFO" + ] + }, + { + "name": "pwm", + "regions": [ + "APB4_PWM" + ] + }, + { + "name": "rtc", + "regions": [ + "APB4_RTC" + ] + }, + { + "name": "wdg", + "regions": [ + "APB4_WDG" + ] + } + ], + "interrupts": [ + { + "name": "clint_software", + "core_bit": 0, + "signal": "u_clint_if.software_irq_o[0]" + }, + { + "name": "clint_timer", + "core_bit": 1, + "signal": "u_clint_if.timer_irq_o[0]" + }, + { + "name": "uart0", + "core_bit": 2, + "signal": "u_uart0_if.irq_o" + }, + { + "name": "timer0", + "core_bit": 3, + "signal": "s_timer0_irq" + }, + { + "name": "timer1", + "core_bit": 4, + "signal": "s_timer1_irq" + }, + { + "name": "i2c0", + "core_bit": 7, + "signal": "u_i2c0_if.irq_o" + }, + { + "name": "xpi", + "core_bit": 9, + "signal": "s_xpi_irq" + }, + { + "name": "pwm", + "core_bit": 11, + "signal": "u_pwm_if.irq_o" + }, + { + "name": "rtc", + "core_bit": 13, + "signal": "u_rtc_if.irq_o" + }, + { + "name": "watchdog_early_warning", + "core_bit": 14, + "signal": "u_wdg_if.irq_o" + }, + { + "name": "gpio", + "core_bit": 18, + "signal": "u_gpio_if.irq_o" + }, + { + "name": "i2c1", + "core_bit": 19, + "signal": "u_i2c1_if.irq_o" + }, + { + "name": "dma", + "core_bit": 20, + "signal": "s_dma_irq" + }, + { + "name": "uart1", + "core_bit": 26, + "signal": "u_uart1_if.irq_o" + } + ], + "gpio_alt_functions": [ + { + "pin": 0, + "alt0": { + "inputs": [ + "u_uart0_if.cts_n_i" + ], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 1, + "alt0": { + "inputs": [], + "do": "u_uart0_if.rts_n_o", + "oe": "1'b1" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 2, + "alt0": { + "inputs": [ + "u_pwm_if.sync_i" + ], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 3, + "alt0": { + "inputs": [], + "do": "u_pwm_if.pwm_o[0]", + "oe": "u_pwm_if.oe_o[0]" + }, + "alt1": { + "inputs": [ + "u_i2c1_if.scl_i" + ], + "do": "u_i2c1_if.scl_o", + "oe": "u_i2c1_if.scl_oe_o" + } + }, + { + "pin": 4, + "alt0": { + "inputs": [], + "do": "u_pwm_if.pwm_o[1]", + "oe": "u_pwm_if.oe_o[1]" + }, + "alt1": { + "inputs": [ + "u_i2c1_if.sda_i" + ], + "do": "u_i2c1_if.sda_o", + "oe": "u_i2c1_if.sda_oe_o" + } + }, + { + "pin": 5, + "alt0": { + "inputs": [], + "do": "u_pwm_if.pwm_o[2]", + "oe": "u_pwm_if.oe_o[2]" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 6, + "alt0": { + "inputs": [], + "do": "u_pwm_if.pwm_o[3]", + "oe": "u_pwm_if.oe_o[3]" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 7, + "alt0": { + "inputs": [ + "u_i2c0_if.scl_i" + ], + "do": "u_i2c0_if.scl_o", + "oe": "u_i2c0_if.scl_oe_o" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 8, + "alt0": { + "inputs": [ + "u_i2c0_if.sda_i" + ], + "do": "u_i2c0_if.sda_o", + "oe": "u_i2c0_if.sda_oe_o" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 9, + "alt0": { + "inputs": [ + "u_pwm_if.fault_i" + ], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 10, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 11, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 12, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 13, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 14, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 15, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 16, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 17, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 18, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 19, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 20, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 21, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 22, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 23, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 24, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 25, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 26, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 27, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 28, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 29, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 30, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [ + "u_pwm_if.capture_i[0]" + ], + "do": "1'b0", + "oe": "1'b0" + } + }, + { + "pin": 31, + "alt0": { + "inputs": [], + "do": "1'b0", + "oe": "1'b0" + }, + "alt1": { + "inputs": [ + "u_pwm_if.capture_i[1]" + ], + "do": "1'b0", + "oe": "1'b0" + } + } + ] +} diff --git a/rtl/tiny/mk/config.mk b/rtl/tiny/mk/config.mk new file mode 100644 index 00000000..59e65aef --- /dev/null +++ b/rtl/tiny/mk/config.mk @@ -0,0 +1,49 @@ +# Tiny's first qualified integration is deliberately a fixed MCU profile. +ifneq ($(MINI_MODE),NONE) +$(error SOC=TINY requires MINI_MODE=NONE) +endif +ifneq ($(PDK),IHP130) +$(error SOC=TINY currently supports only PDK=IHP130) +endif +ifneq ($(HAVE_HP),NO) +$(error SOC=TINY requires HAVE_HP=NO) +endif +ifneq ($(HAVE_PLL),NO) +$(error SOC=TINY requires HAVE_PLL=NO) +endif +ifneq ($(HAVE_SRAM_IF),YES) +$(error SOC=TINY requires HAVE_SRAM_IF=YES) +endif +ifneq ($(HAVE_SRAM_MACRO),YES) +$(error SOC=TINY requires HAVE_SRAM_MACRO=YES) +endif +ifneq ($(SRAM_SIZE_KIB),128) +$(error SOC=TINY first release requires SRAM_SIZE_KIB=128) +endif +ifneq ($(EXT_CLK_HZ),24000000) +$(error SOC=TINY first release requires EXT_CLK_HZ=24000000) +endif +ifneq ($(AUD_CLK_HZ),$(EXT_CLK_HZ)) +$(error SOC=TINY uses the system clock for RTC and watchdog) +endif +ifneq ($(CLINT_TIMEBASE_HZ),1000000) +$(error SOC=TINY requires CLINT_TIMEBASE_HZ=1000000) +endif +ifeq ($(filter $(SIMU),IVERILOG VERILATOR),) +$(error SOC=TINY supports SIMU=IVERILOG or VERILATOR) +endif +ifeq ($(filter $(APP),bringup ci_smoke),) +$(error SOC=TINY supports APP=bringup or ci_smoke) +endif +ifneq ($(LINK_TYPE),ld2_all_sram) +$(error SOC=TINY requires LINK_TYPE=ld2_all_sram) +endif +ifneq ($(HAVE_CSR),YES) +$(error SOC=TINY requires HAVE_CSR=YES) +endif +ifneq ($(ISA),RV32IM) +$(error SOC=TINY firmware uses ISA=RV32IM) +endif +ifneq ($(filter YES,$(APU_ENABLE_P7) $(NPU_P5_ACCEPTANCE) $(NPU_P6_ACCEPTANCE)),) +$(error SOC=TINY does not include multimedia accelerators) +endif \ No newline at end of file diff --git a/rtl/tiny/pin_map/pin_map.json b/rtl/tiny/pin_map/pin_map.json new file mode 100644 index 00000000..be65c3cb --- /dev/null +++ b/rtl/tiny/pin_map/pin_map.json @@ -0,0 +1,312 @@ +{ + "schema_version": 1, + "power_pads": { + "vdd": 8, + "vss": 8, + "iovdd": 8, + "iovss": 8 + }, + "pads": [ + { + "kind": "tri_input", + "direction": "inout", + "ports": [ + { + "name": "extclk_i_pad", + "signal": "s_ext_clk" + } + ] + }, + { + "kind": "schmitt_input", + "direction": "inout", + "ports": [ + { + "name": "ext_rst_n_i_pad", + "signal": "s_ext_rst_n" + } + ] + }, + { + "kind": "tri_input", + "direction": "inout", + "ports": [ + { + "name": "jtag_tck_i_pad", + "signal": "s_jtag_tck" + }, + { + "name": "jtag_tms_i_pad", + "signal": "s_jtag_tms" + }, + { + "name": "jtag_tdi_i_pad", + "signal": "s_jtag_tdi" + } + ] + }, + { + "kind": "schmitt_input", + "direction": "inout", + "ports": [ + { + "name": "jtag_trst_n_i_pad", + "signal": "s_jtag_trst_n" + } + ] + }, + { + "kind": "tri_output", + "direction": "output", + "ports": [ + { + "name": "jtag_tdo_o_pad", + "signal": "s_jtag_tdo" + } + ] + }, + { + "kind": "full", + "direction": "inout", + "prefix": "gpio_", + "suffix": "_io_pad", + "count": 32, + "interface": "u_gpio_if" + }, + { + "kind": "tri_output", + "direction": "output", + "ports": [ + { + "name": "uart0_tx_o_pad", + "signal": "s_uart0_tx" + } + ] + }, + { + "kind": "tri_input", + "direction": "inout", + "ports": [ + { + "name": "uart0_rx_i_pad", + "signal": "s_uart0_rx" + } + ] + }, + { + "kind": "tri_output", + "direction": "output", + "ports": [ + { + "name": "uart1_tx_o_pad", + "signal": "s_uart1_tx" + } + ] + }, + { + "kind": "tri_input", + "direction": "inout", + "ports": [ + { + "name": "uart1_rx_i_pad", + "signal": "s_uart1_rx" + } + ] + }, + { + "kind": "tri_output", + "direction": "output", + "ports": [ + { + "name": "xpi_sck_o_pad", + "signal": "u_xpi_if.sck_o" + } + ] + }, + { + "kind": "tri_output", + "direction": "output", + "prefix": "xpi_nss", + "suffix": "_o_pad", + "count": 4, + "signal": "u_xpi_if.nss_o[{index}]" + }, + { + "kind": "xpi_data", + "direction": "inout", + "prefix": "xpi_dat", + "suffix": "_io_pad", + "count": 4 + } + ], + "profiles": { + "fpga_mini": { + "bindings": { + "extclk_i_pad": "s_clk", + "ext_rst_n_i_pad": "s_rst_n", + "jtag_tck_i_pad": "s_jtag_tck", + "jtag_tms_i_pad": "s_jtag_tms", + "jtag_tdi_i_pad": "s_jtag_tdi", + "jtag_trst_n_i_pad": "s_jtag_trst_n", + "jtag_tdo_o_pad": "s_jtag_tdo", + "gpio_0_io_pad": "s_gpio[0]", + "gpio_1_io_pad": "s_gpio[1]", + "gpio_2_io_pad": "s_gpio[2]", + "gpio_3_io_pad": "s_gpio[3]", + "gpio_4_io_pad": "s_gpio[4]", + "gpio_5_io_pad": "s_gpio[5]", + "gpio_6_io_pad": "s_gpio[6]", + "gpio_7_io_pad": "s_gpio[7]", + "gpio_8_io_pad": "s_gpio[8]", + "gpio_9_io_pad": "s_gpio[9]", + "gpio_10_io_pad": "s_gpio[10]", + "gpio_11_io_pad": "s_gpio[11]", + "gpio_12_io_pad": "s_gpio[12]", + "gpio_13_io_pad": "s_gpio[13]", + "gpio_14_io_pad": "s_gpio[14]", + "gpio_15_io_pad": "s_gpio[15]", + "gpio_16_io_pad": "s_gpio[16]", + "gpio_17_io_pad": "s_gpio[17]", + "gpio_18_io_pad": "s_gpio[18]", + "gpio_19_io_pad": "s_gpio[19]", + "gpio_20_io_pad": "s_gpio[20]", + "gpio_21_io_pad": "s_gpio[21]", + "gpio_22_io_pad": "s_gpio[22]", + "gpio_23_io_pad": "s_gpio[23]", + "gpio_24_io_pad": "s_gpio[24]", + "gpio_25_io_pad": "s_gpio[25]", + "gpio_26_io_pad": "s_gpio[26]", + "gpio_27_io_pad": "s_gpio[27]", + "gpio_28_io_pad": "s_gpio[28]", + "gpio_29_io_pad": "s_gpio[29]", + "gpio_30_io_pad": "s_gpio[30]", + "gpio_31_io_pad": "s_gpio[31]", + "uart0_tx_o_pad": "s_uart0_tx", + "uart0_rx_i_pad": "s_uart0_rx", + "uart1_tx_o_pad": "s_uart1_tx", + "uart1_rx_i_pad": "s_uart1_rx", + "xpi_sck_o_pad": "s_xpi_sck", + "xpi_nss0_o_pad": "s_xpi_nss[0]", + "xpi_nss1_o_pad": "s_xpi_nss[1]", + "xpi_nss2_o_pad": "s_xpi_nss[2]", + "xpi_nss3_o_pad": "s_xpi_nss[3]", + "xpi_dat0_io_pad": "s_xpi_data[0]", + "xpi_dat1_io_pad": "s_xpi_data[1]", + "xpi_dat2_io_pad": "s_xpi_data[2]", + "xpi_dat3_io_pad": "s_xpi_data[3]" + } + }, + "verilator": { + "bindings": { + "extclk_i_pad": "s_clk", + "ext_rst_n_i_pad": "s_rst_n", + "jtag_tck_i_pad": "s_jtag_tck", + "jtag_tms_i_pad": "s_jtag_tms", + "jtag_tdi_i_pad": "s_jtag_tdi", + "jtag_trst_n_i_pad": "s_jtag_trst_n", + "jtag_tdo_o_pad": "s_jtag_tdo", + "gpio_0_io_pad": "s_gpio[0]", + "gpio_1_io_pad": "s_gpio[1]", + "gpio_2_io_pad": "s_gpio[2]", + "gpio_3_io_pad": "s_gpio[3]", + "gpio_4_io_pad": "s_gpio[4]", + "gpio_5_io_pad": "s_gpio[5]", + "gpio_6_io_pad": "s_gpio[6]", + "gpio_7_io_pad": "s_gpio[7]", + "gpio_8_io_pad": "s_gpio[8]", + "gpio_9_io_pad": "s_gpio[9]", + "gpio_10_io_pad": "s_gpio[10]", + "gpio_11_io_pad": "s_gpio[11]", + "gpio_12_io_pad": "s_gpio[12]", + "gpio_13_io_pad": "s_gpio[13]", + "gpio_14_io_pad": "s_gpio[14]", + "gpio_15_io_pad": "s_gpio[15]", + "gpio_16_io_pad": "s_gpio[16]", + "gpio_17_io_pad": "s_gpio[17]", + "gpio_18_io_pad": "s_gpio[18]", + "gpio_19_io_pad": "s_gpio[19]", + "gpio_20_io_pad": "s_gpio[20]", + "gpio_21_io_pad": "s_gpio[21]", + "gpio_22_io_pad": "s_gpio[22]", + "gpio_23_io_pad": "s_gpio[23]", + "gpio_24_io_pad": "s_gpio[24]", + "gpio_25_io_pad": "s_gpio[25]", + "gpio_26_io_pad": "s_gpio[26]", + "gpio_27_io_pad": "s_gpio[27]", + "gpio_28_io_pad": "s_gpio[28]", + "gpio_29_io_pad": "s_gpio[29]", + "gpio_30_io_pad": "s_gpio[30]", + "gpio_31_io_pad": "s_gpio[31]", + "uart0_tx_o_pad": "s_uart0_tx", + "uart0_rx_i_pad": "s_uart0_rx", + "uart1_tx_o_pad": "s_uart1_tx", + "uart1_rx_i_pad": "s_uart1_rx", + "xpi_sck_o_pad": "s_xpi_sck", + "xpi_nss0_o_pad": "s_xpi_nss[0]", + "xpi_nss1_o_pad": "s_xpi_nss[1]", + "xpi_nss2_o_pad": "s_xpi_nss[2]", + "xpi_nss3_o_pad": "s_xpi_nss[3]", + "xpi_dat0_io_pad": "s_xpi_data[0]", + "xpi_dat1_io_pad": "s_xpi_data[1]", + "xpi_dat2_io_pad": "s_xpi_data[2]", + "xpi_dat3_io_pad": "s_xpi_data[3]" + } + }, + "tb": { + "bindings": { + "extclk_i_pad": "s_clk", + "ext_rst_n_i_pad": "s_rst_n", + "jtag_tck_i_pad": "s_jtag_tck", + "jtag_tms_i_pad": "s_jtag_tms", + "jtag_tdi_i_pad": "s_jtag_tdi", + "jtag_trst_n_i_pad": "s_jtag_trst_n", + "jtag_tdo_o_pad": "s_jtag_tdo", + "gpio_0_io_pad": "s_gpio[0]", + "gpio_1_io_pad": "s_gpio[1]", + "gpio_2_io_pad": "s_gpio[2]", + "gpio_3_io_pad": "s_gpio[3]", + "gpio_4_io_pad": "s_gpio[4]", + "gpio_5_io_pad": "s_gpio[5]", + "gpio_6_io_pad": "s_gpio[6]", + "gpio_7_io_pad": "s_gpio[7]", + "gpio_8_io_pad": "s_gpio[8]", + "gpio_9_io_pad": "s_gpio[9]", + "gpio_10_io_pad": "s_gpio[10]", + "gpio_11_io_pad": "s_gpio[11]", + "gpio_12_io_pad": "s_gpio[12]", + "gpio_13_io_pad": "s_gpio[13]", + "gpio_14_io_pad": "s_gpio[14]", + "gpio_15_io_pad": "s_gpio[15]", + "gpio_16_io_pad": "s_gpio[16]", + "gpio_17_io_pad": "s_gpio[17]", + "gpio_18_io_pad": "s_gpio[18]", + "gpio_19_io_pad": "s_gpio[19]", + "gpio_20_io_pad": "s_gpio[20]", + "gpio_21_io_pad": "s_gpio[21]", + "gpio_22_io_pad": "s_gpio[22]", + "gpio_23_io_pad": "s_gpio[23]", + "gpio_24_io_pad": "s_gpio[24]", + "gpio_25_io_pad": "s_gpio[25]", + "gpio_26_io_pad": "s_gpio[26]", + "gpio_27_io_pad": "s_gpio[27]", + "gpio_28_io_pad": "s_gpio[28]", + "gpio_29_io_pad": "s_gpio[29]", + "gpio_30_io_pad": "s_gpio[30]", + "gpio_31_io_pad": "s_gpio[31]", + "uart0_tx_o_pad": "s_uart0_tx", + "uart0_rx_i_pad": "s_uart0_rx", + "uart1_tx_o_pad": "s_uart1_tx", + "uart1_rx_i_pad": "s_uart1_rx", + "xpi_sck_o_pad": "s_xpi_sck", + "xpi_nss0_o_pad": "s_xpi_nss[0]", + "xpi_nss1_o_pad": "s_xpi_nss[1]", + "xpi_nss2_o_pad": "s_xpi_nss[2]", + "xpi_nss3_o_pad": "s_xpi_nss[3]", + "xpi_dat0_io_pad": "s_xpi_data[0]", + "xpi_dat1_io_pad": "s_xpi_data[1]", + "xpi_dat2_io_pad": "s_xpi_data[2]", + "xpi_dat3_io_pad": "s_xpi_data[3]" + } + } + } +} diff --git a/rtl/tiny/top/retrosoc_tiny.sv b/rtl/tiny/top/retrosoc_tiny.sv new file mode 100644 index 00000000..f8938bd4 --- /dev/null +++ b/rtl/tiny/top/retrosoc_tiny.sv @@ -0,0 +1,375 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 +`include "mmap_define.svh" + +module retrosoc_tiny ( + input logic clk_i, + input logic rst_n_i, + input logic jtag_tck_i, + input logic jtag_tms_i, + input logic jtag_tdi_i, + input logic jtag_trst_n_i, + output logic jtag_tdo_o, + input logic uart0_rx_i, + output logic uart0_tx_o, + input logic uart1_rx_i, + output logic uart1_tx_o, + gpio_if.soc_pad gpio, + xpi_if.dut xpi, + output logic test_done_o, + output logic test_pass_o, + output logic [7:0] test_code_o +); + logic s_por_rst_n, s_rst_n; + logic s_debug_halted; + logic [31:0] s_irq; + logic s_fault_valid, s_fault_master, s_fault_write; + logic [31:0] s_fault_addr; + logic [ 1:0] s_fault_resp; + logic s_perf_enable, s_perf_clear; + logic [63:0] s_cpu_wait, s_dma_wait; + logic s_timer0_irq, s_timer1_irq, s_xpi_irq, s_dma_irq; + logic s_dma_done; + logic [7:0] s_dma_stall; + logic [4:0] s_tick_count_d, s_tick_count_q; + logic s_tick; + logic s_unused_uart1_tx_stall, s_unused_uart1_rx_stall; + uart_if u_uart0_if (); + uart_if u_uart1_if (); + i2c_if u_i2c0_if (); + i2c_if u_i2c1_if (); + pwm_if u_pwm_if (); + clint_if u_clint_if (); + gpio_if u_gpio_if (); + user_gpio_if u_user_gpio_if (); + dma_req_if u_dma_req_if (); + rtc_if u_rtc_if ( + .rtc_clk_i (clk_i), + .rtc_rst_n_i(s_rst_n) + ); + // The watchdog reset pulse must survive resetting the bus/CPU. Its timer + // uses POR reset while its APB register domain uses the system reset. + wdg_if u_wdg_if ( + .wdg_clk_i (clk_i), + .wdg_rst_n_i(s_por_rst_n) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_masters_axi4_if[2] ( + .aclk (clk_i), + .aresetn(s_rst_n) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) u_targets_axi4_if[5] ( + .aclk (clk_i), + .aresetn(s_rst_n) + ); + axi4_stream_if #( + .DATA_WIDTH(32) + ) u_i2s_tx_axis_if ( + .aclk (clk_i), + .aresetn(s_rst_n) + ); + axi4_stream_if #( + .DATA_WIDTH(32) + ) u_i2s_rx_axis_if ( + .aclk (clk_i), + .aresetn(s_rst_n) + ); + axi4_stream_if #( + .DATA_WIDTH(32) + ) u_dvp_rx_axis_if ( + .aclk (clk_i), + .aresetn(s_rst_n) + ); + axi4_stream_if #( + .DATA_WIDTH(32) + ) u_crypto_tx_axis_if ( + .aclk (clk_i), + .aresetn(s_rst_n) + ); + axi4_stream_if #( + .DATA_WIDTH(32) + ) u_crypto_rx_axis_if ( + .aclk (clk_i), + .aresetn(s_rst_n) + ); + `include "tiny_apb_interfaces.svh" + +rst_sync u_por_rst_sync ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .rst_n_o(s_por_rst_n) + ); + rst_sync u_system_rst_sync ( + .clk_i (clk_i), + .rst_n_i(s_por_rst_n && !u_wdg_if.reset_req_o), + .rst_n_o(s_rst_n) + ); + assign s_tick = s_tick_count_q == 5'd23; + assign s_tick_count_d = s_tick ? 5'd0 : (s_tick_count_q + 5'd1); + dffr #( + .DATA_WIDTH(5) + ) u_tick_reg ( + .clk_i (clk_i), + .rst_n_i(s_rst_n), + .dat_i (s_tick_count_d), + .dat_o (s_tick_count_q) + ); + mgmt_core_wrapper #( + .ExternalIrqCount (30), + .EnableAtomics (1'b0), + .TwoCycleBusErrors(1'b1) + ) u_cpu ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .irq_i (s_irq), + .jtag_tck_i (jtag_tck_i), + .jtag_tms_i (jtag_tms_i), + .jtag_tdi_i (jtag_tdi_i), + .jtag_trst_n_i (jtag_trst_n_i), + .jtag_tdo_o (jtag_tdo_o), + .debug_halted_o(s_debug_halted), + .axi4 (u_masters_axi4_if[0]) + ); + tiny_axi4_fabric u_fabric ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .masters (u_masters_axi4_if), + .targets (u_targets_axi4_if), + .perf_enable_i (s_perf_enable), + .perf_clear_i (s_perf_clear), + .fault_valid_o (s_fault_valid), + .fault_addr_o (s_fault_addr), + .fault_master_o(s_fault_master), + .fault_write_o (s_fault_write), + .fault_resp_o (s_fault_resp), + .cpu_wait_o (s_cpu_wait), + .dma_wait_o (s_dma_wait) + ); + onchip_ram #( + .CapacityKiB(128), + .DataWidth (32), + .IdWidth (1) + ) u_sram ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .mem_axi4 (u_targets_axi4_if[0]), + .cfg_apb4 (u_sram_apb4_if), + .perf_enable_i(s_perf_enable), + .perf_clear_i (s_perf_clear) + ); + apb4_xpi u_xpi ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .mem_axi4 (u_targets_axi4_if[1]), + .apb4 (u_xpi_apb4_if), + .xpi (xpi), + .dma_xfer_done_i(s_dma_done), + .dma_tx_stall_o (s_dma_stall[0]), + .dma_rx_stall_o (s_dma_stall[1]), + .irq_o (s_xpi_irq) + ); + tiny_axi42apb4 u_apb_bridge ( + .clk_i (clk_i), + .rst_n_i(s_rst_n), + .axi4 (u_targets_axi4_if[2]), + `include "tiny_apb_connections.svh" + ); + axi4_error_slave #( + .Response(2'b11) + ) u_decode_error ( + .clk_i (clk_i), + .rst_n_i(s_rst_n), + .axi4 (u_targets_axi4_if[3]) + ); + axi4_error_slave #( + .Response(2'b10) + ) u_protocol_error ( + .clk_i (clk_i), + .rst_n_i(s_rst_n), + .axi4 (u_targets_axi4_if[4]) + ); + tiny_sysctrl u_sysctrl ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .apb4 (u_sysctrl_apb4_if), + .fault_valid_i (s_fault_valid), + .fault_addr_i (s_fault_addr), + .fault_write_i (s_fault_write), + .fault_master_i(s_fault_master), + .fault_resp_i (s_fault_resp), + .cpu_wait_i (s_cpu_wait), + .dma_wait_i (s_dma_wait), + .rtc_wake_i (u_rtc_if.wake_o), + .perf_enable_o (s_perf_enable), + .perf_clear_o (s_perf_clear), + .test_done_o (test_done_o), + .test_pass_o (test_pass_o), + .test_code_o (test_code_o) + ); + tiny_archinfo u_archinfo ( + .clk_i (clk_i), + .rst_n_i(s_rst_n), + .apb4 (u_archinfo_apb4_if) + ); + apb4_gpio u_gpio ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .apb4 (u_gpio_apb4_if), + .gpio (u_gpio_if), + .user_gpio(u_user_gpio_if) + ); + gpio_pad_bridge u_gpio_pads ( + .inner(u_gpio_if), + .outer(gpio) + ); + assign u_user_gpio_if.do_o = '0; + assign u_user_gpio_if.oe_o = '0; + assign u_uart0_if.rx_i = uart0_rx_i; + assign uart0_tx_o = u_uart0_if.tx_o; + assign u_uart1_if.rx_i = uart1_rx_i; + assign u_uart1_if.cts_n_i = 1'b0; + assign uart1_tx_o = u_uart1_if.tx_o; + assign u_wdg_if.debug_halted_i = s_debug_halted; + `include "tiny_gpio.svh" + `include "tiny_irq.svh" +apb4_uart u_uart0 ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .apb4 (u_uart0_apb4_if), + .uart (u_uart0_if), + .dma_tx_stall_o(s_dma_stall[2]), + .dma_rx_stall_o(s_dma_stall[3]) + ); + apb4_i2c u_i2c0 ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .apb4 (u_i2c0_apb4_if), + .i2c (u_i2c0_if), + .dma_tx_stall_o(s_dma_stall[4]), + .dma_rx_stall_o(s_dma_stall[5]) + ); + apb4_timer u_timer0 ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .debug_halted_i(s_debug_halted), + .apb4 (u_timer0_apb4_if), + .irq_o (s_timer0_irq) + ); + apb4_uart u_uart1 ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .apb4 (u_uart1_apb4_if), + .uart (u_uart1_if), + .dma_tx_stall_o(s_unused_uart1_tx_stall), + .dma_rx_stall_o(s_unused_uart1_rx_stall) + ); + apb4_i2c u_i2c1 ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .apb4 (u_i2c1_apb4_if), + .i2c (u_i2c1_if), + .dma_tx_stall_o(s_dma_stall[6]), + .dma_rx_stall_o(s_dma_stall[7]) + ); + apb4_timer u_timer1 ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .debug_halted_i(s_debug_halted), + .apb4 (u_timer1_apb4_if), + .irq_o (s_timer1_irq) + ); + apb4_clint u_clint ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .timebase_tick_i(s_tick), + .apb4 (u_clint_apb4_if), + .clint (u_clint_if) + ); + apb4_pwm #( + .PCLK_HZ(24_000_000) + ) u_pwm ( + .debug_halted_i(s_debug_halted), + .apb4 (u_pwm_apb4_if), + .pwm (u_pwm_if) + ); + apb4_rtc #( + .RTC_CLOCK_HZ(24_000_000) + ) u_rtc ( + .apb4(u_rtc_apb4_if), + .rtc (u_rtc_if) + ); + apb4_wdg #( + .WDG_CLOCK_HZ (24_000_000), + .RESET_PULSE_CYCLES(8) + ) u_watchdog ( + .apb4(u_wdg_apb4_if), + .wdg (u_wdg_if) + ); + apb4_dma #( + .NumChannels (4), + .MaxBurstBeats(16), + .FifoDepth (32), + .RequestMask (16'h07f9), + .EnableStreams(1'b0) + ) u_dma ( + .clk_i (clk_i), + .rst_n_i (s_rst_n), + .dma_xfer_done_o(s_dma_done), + .irq_o (s_dma_irq), + .hw_trg (u_dma_req_if), + .apb4 (u_dma_apb4_if), + .axi4 (u_masters_axi4_if[1]), + .i2s_tx_axis (u_i2s_tx_axis_if), + .i2s_rx_axis (u_i2s_rx_axis_if), + .dvp_rx_axis (u_dvp_rx_axis_if), + .crypto_in_axis (u_crypto_tx_axis_if), + .crypto_out_axis(u_crypto_rx_axis_if) + ); + assign u_dma_req_if.i2s_tx_proc = 1'b0; + assign u_dma_req_if.i2s_rx_proc = 1'b0; + assign u_dma_req_if.crypto_in_proc = 1'b0; + assign u_dma_req_if.crypto_out_proc = 1'b0; + assign u_dma_req_if.qspi_tx_proc = !s_dma_stall[0]; + assign u_dma_req_if.qspi_rx_proc = !s_dma_stall[1]; + assign u_dma_req_if.uart_tx_proc = !s_dma_stall[2]; + assign u_dma_req_if.uart_rx_proc = !s_dma_stall[3]; + assign u_dma_req_if.i2c0_tx_proc = !s_dma_stall[4]; + assign u_dma_req_if.i2c0_rx_proc = !s_dma_stall[5]; + assign u_dma_req_if.i2c1_tx_proc = !s_dma_stall[6]; + assign u_dma_req_if.i2c1_rx_proc = !s_dma_stall[7]; + assign u_i2s_rx_axis_if.tvalid = '0; + assign u_i2s_rx_axis_if.tdata = '0; + assign u_i2s_rx_axis_if.tstrb = '0; + assign u_i2s_rx_axis_if.tkeep = '0; + assign u_i2s_rx_axis_if.tlast = '0; + assign u_i2s_rx_axis_if.tid = '0; + assign u_i2s_rx_axis_if.tdest = '0; + assign u_i2s_rx_axis_if.tuser = '0; + assign u_dvp_rx_axis_if.tvalid = '0; + assign u_dvp_rx_axis_if.tdata = '0; + assign u_dvp_rx_axis_if.tstrb = '0; + assign u_dvp_rx_axis_if.tkeep = '0; + assign u_dvp_rx_axis_if.tlast = '0; + assign u_dvp_rx_axis_if.tid = '0; + assign u_dvp_rx_axis_if.tdest = '0; + assign u_dvp_rx_axis_if.tuser = '0; + assign u_crypto_rx_axis_if.tvalid = '0; + assign u_crypto_rx_axis_if.tdata = '0; + assign u_crypto_rx_axis_if.tstrb = '0; + assign u_crypto_rx_axis_if.tkeep = '0; + assign u_crypto_rx_axis_if.tlast = '0; + assign u_crypto_rx_axis_if.tid = '0; + assign u_crypto_rx_axis_if.tdest = '0; + assign u_crypto_rx_axis_if.tuser = '0; + assign u_i2s_tx_axis_if.tready = 1'b0; + assign u_crypto_tx_axis_if.tready = 1'b0; +endmodule diff --git a/rtl/tiny/top/retrosoc_tiny_asic.sv b/rtl/tiny/top/retrosoc_tiny_asic.sv new file mode 100644 index 00000000..0c89657b --- /dev/null +++ b/rtl/tiny/top/retrosoc_tiny_asic.sv @@ -0,0 +1,40 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 +module retrosoc_tiny_asic ( + `include "retrosoc_asic_ports.svh" +); + logic s_ext_clk, s_clk, s_ext_rst_n; + logic s_jtag_tck, s_jtag_tms, s_jtag_tdi, s_jtag_trst_n, s_jtag_tdo; + logic s_uart0_rx, s_uart0_tx, s_uart1_rx, s_uart1_tx; + // Stable simulator/netlist observation points; no package test pins. + /* verilator lint_off UNUSEDSIGNAL */ + (* keep = "true" *)logic s_test_done; + (* keep = "true" *)logic s_test_pass; + (* keep = "true" *)logic [7:0] s_test_code; + /* verilator lint_on UNUSEDSIGNAL */ + gpio_if u_gpio_if (); + xpi_if u_xpi_if (); + `include "retrosoc_asic_pad_bindings.svh" +tc_clk_buf u_clock_buffer ( + .clk_i(s_ext_clk), + .clk_o(s_clk) + ); + retrosoc_tiny u_soc ( + .clk_i (s_clk), + .rst_n_i (s_ext_rst_n), + .jtag_tck_i (s_jtag_tck), + .jtag_tms_i (s_jtag_tms), + .jtag_tdi_i (s_jtag_tdi), + .jtag_trst_n_i(s_jtag_trst_n), + .jtag_tdo_o (s_jtag_tdo), + .uart0_rx_i (s_uart0_rx), + .uart0_tx_o (s_uart0_tx), + .uart1_rx_i (s_uart1_rx), + .uart1_tx_o (s_uart1_tx), + .gpio (u_gpio_if), + .xpi (u_xpi_if), + .test_done_o (s_test_done), + .test_pass_o (s_test_pass), + .test_code_o (s_test_code) + ); +endmodule diff --git a/rtl/tiny/top/tiny_archinfo.sv b/rtl/tiny/top/tiny_archinfo.sv new file mode 100644 index 00000000..40f0ad62 --- /dev/null +++ b/rtl/tiny/top/tiny_archinfo.sv @@ -0,0 +1,43 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 +`include "archinfo_integration_metadata.svh" +`include "archinfo_define.svh" + +// The locked ArchInfo V2 has a fixed Mini SOC_ID. This owned adapter changes +// only that read-only identity, retaining the managed ABI and build metadata. +module tiny_archinfo ( + input logic clk_i, + input logic rst_n_i, + apb4_if.slave apb4 +); + apb4_if u_info_apb4_if ( + .pclk (clk_i), + .presetn(rst_n_i) + ); + assign u_info_apb4_if.paddr = apb4.paddr; + assign u_info_apb4_if.psel = apb4.psel; + assign u_info_apb4_if.penable = apb4.penable; + assign u_info_apb4_if.pwrite = apb4.pwrite; + assign u_info_apb4_if.pwdata = apb4.pwdata; + assign u_info_apb4_if.pstrb = apb4.pstrb; + assign u_info_apb4_if.pprot = apb4.pprot; + assign apb4.pready = u_info_apb4_if.pready; + assign apb4.pslverr = u_info_apb4_if.pslverr; + assign apb4.prdata = (apb4.paddr[11:0] == `ARCHINFO_SOC_ID_OFFSET) ? + 32'h5449_4e59 : u_info_apb4_if.prdata; + apb4_archinfo #( + .REFERENCE_CLOCK_HZ(24_000_000), + .SRAM_BYTES (131072), + .TOPOLOGY (32'h2020_0001), + .FEATURES0 (32'h0000_7ffe), + .TECHNOLOGY (32'h0201_0082), + .BUILD_ID (`ARCHINFO_INTEGRATION_BUILD_ID), + .CONFIG_ID (`ARCHINFO_INTEGRATION_CONFIG_ID), + .BUILD_STATUS (`ARCHINFO_INTEGRATION_BUILD_STATUS) + ) u_archinfo ( + .device_id_i (128'd0), + .device_id_valid_i (1'b0), + .device_id_read_enable_i(1'b0), + .apb4 (u_info_apb4_if) + ); +endmodule diff --git a/rtl/tiny/top/tiny_axi42apb4.sv b/rtl/tiny/top/tiny_axi42apb4.sv new file mode 100644 index 00000000..4cd6fdc3 --- /dev/null +++ b/rtl/tiny/top/tiny_axi42apb4.sv @@ -0,0 +1,220 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 +`include "mmap_define.svh" + +// APB setup/access are separate cycles; rejected bursts never assert PSEL. +module tiny_axi42apb4 ( + input logic clk_i, + input logic rst_n_i, + axi4_if.slave axi4, + `include "tiny_apb_ports.svh" +); + typedef enum logic [2:0] { + Idle, + WriteData, + Setup, + Access, + ReadResponse, + WriteResponse, + ReadError, + WriteError + } state_e; + state_e s_state_d, s_state_q; + logic [2:0] s_state_bits_q; + logic [31:0] s_addr_d, s_addr_q; + logic [31:0] s_wdata_d, s_wdata_q; + logic [31:0] s_data_d, s_data_q; + logic [3:0] s_wstrb_d, s_wstrb_q; + logic s_id_d, s_id_q; + logic s_write_d, s_write_q; + logic [1:0] s_resp_d, s_resp_q; + logic [7:0] s_len_d, s_len_q; + logic [7:0] s_beat_d, s_beat_q; + logic [15:0] s_select, s_ready, s_error; + logic [15:0][31:0] s_rdata; + logic s_access, s_enable, s_done, s_err; + logic [31:0] s_read_data; + + assign s_state_q = state_e'(s_state_bits_q); + assign axi4.arready = s_state_q == Idle; + assign axi4.awready = (s_state_q == Idle) && !axi4.arvalid; + assign axi4.wready = (s_state_q == WriteData) || (s_state_q == WriteError); + assign axi4.bid = s_id_q; + assign axi4.bresp = s_resp_q; + assign axi4.buser = '0; + assign axi4.bvalid = s_state_q == WriteResponse; + assign axi4.rid = s_id_q; + assign axi4.rdata = s_data_q; + assign axi4.rresp = s_resp_q; + assign axi4.ruser = '0; + assign axi4.rlast = s_beat_q == s_len_q; + assign axi4.rvalid = (s_state_q == ReadResponse) || (s_state_q == ReadError); + assign s_access = (s_state_q == Setup) || (s_state_q == Access); + assign s_enable = s_state_q == Access; + assign s_done = |(s_select & s_ready); + assign s_err = |(s_select & s_error); + + always_comb begin + s_select = '0; + `include "tiny_apb_decode.svh" +s_read_data = '0; + for (int unsigned target = 0; target < 16; target++) begin + if (s_select[target]) s_read_data = s_rdata[target]; + end + end + `include "tiny_apb_wiring.svh" + + always_comb begin + s_state_d = s_state_q; + s_addr_d = s_addr_q; + s_wdata_d = s_wdata_q; + s_wstrb_d = s_wstrb_q; + s_id_d = s_id_q; + s_write_d = s_write_q; + s_resp_d = s_resp_q; + s_data_d = s_data_q; + s_len_d = s_len_q; + s_beat_d = s_beat_q; + unique case (s_state_q) + Idle: begin + s_beat_d = '0; + s_data_d = '0; + s_resp_d = 2'b00; + if (axi4.arvalid) begin + s_addr_d = axi4.araddr; + s_id_d = axi4.arid; + s_write_d = 1'b0; + s_len_d = axi4.arlen; + if ((axi4.arlen != 8'd0) || (axi4.arburst[1]) || axi4.arlock || + (axi4.arsize > 3'd2) || (axi4.araddr[1:0] != 2'd0)) begin + s_resp_d = 2'b10; + s_state_d = ReadError; + end else s_state_d = Setup; + end else if (axi4.awvalid) begin + s_addr_d = axi4.awaddr; + s_id_d = axi4.awid; + s_write_d = 1'b1; + s_len_d = axi4.awlen; + if ((axi4.awlen != 8'd0) || (axi4.awburst[1]) || axi4.awlock || + (axi4.awsize > 3'd2) || (axi4.awaddr[1:0] != 2'd0)) begin + s_resp_d = 2'b10; + s_state_d = WriteError; + end else s_state_d = WriteData; + end + end + WriteData: + if (axi4.wvalid) begin + s_wdata_d = axi4.wdata; + s_wstrb_d = axi4.wstrb; + if (!axi4.wlast) begin + s_resp_d = 2'b10; + s_state_d = WriteResponse; + end else s_state_d = Setup; + end + Setup: begin + if (s_select == 16'd0) begin + s_resp_d = 2'b11; + s_state_d = s_write_q ? WriteResponse : ReadResponse; + end else s_state_d = Access; + end + Access: + if (s_done) begin + s_resp_d = s_err ? 2'b10 : 2'b00; + s_data_d = s_read_data; + s_state_d = s_write_q ? WriteResponse : ReadResponse; + end + ReadResponse, ReadError: + if (axi4.rready) begin + if (s_beat_q == s_len_q) s_state_d = Idle; + else s_beat_d = s_beat_q + 8'd1; + end + WriteResponse: if (axi4.bready) s_state_d = Idle; + WriteError: + if (axi4.wvalid) begin + if (s_beat_q == s_len_q) s_state_d = WriteResponse; + else s_beat_d = s_beat_q + 8'd1; + end + default: s_state_d = Idle; + endcase + end + dffr #( + .DATA_WIDTH(3) + ) u_state_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_state_d), + .dat_o (s_state_bits_q) + ); + dffr #( + .DATA_WIDTH(32) + ) u_addr_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_addr_d), + .dat_o (s_addr_q) + ); + dffr #( + .DATA_WIDTH(32) + ) u_wdata_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_wdata_d), + .dat_o (s_wdata_q) + ); + dffr #( + .DATA_WIDTH(32) + ) u_data_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_data_d), + .dat_o (s_data_q) + ); + dffr #( + .DATA_WIDTH(4) + ) u_wstrb_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_wstrb_d), + .dat_o (s_wstrb_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_id_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_id_d), + .dat_o (s_id_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_write_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_write_d), + .dat_o (s_write_q) + ); + dffr #( + .DATA_WIDTH(2) + ) u_resp_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_resp_d), + .dat_o (s_resp_q) + ); + dffr #( + .DATA_WIDTH(8) + ) u_len_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_len_d), + .dat_o (s_len_q) + ); + dffr #( + .DATA_WIDTH(8) + ) u_beat_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_beat_d), + .dat_o (s_beat_q) + ); +endmodule diff --git a/rtl/tiny/top/tiny_axi4_fabric.sv b/rtl/tiny/top/tiny_axi4_fabric.sv new file mode 100644 index 00000000..a4473d48 --- /dev/null +++ b/rtl/tiny/top/tiny_axi4_fabric.sv @@ -0,0 +1,297 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 + +`include "mmap_define.svh" + +// One accepted transaction globally. AW and W remain independent: W is +// backpressured until the saved AW has reached its target. The owner and all +// address attributes remain registered until the terminal response handshake. +module tiny_axi4_fabric ( + input logic clk_i, + input logic rst_n_i, + input logic perf_enable_i, + input logic perf_clear_i, + axi4_if.slave masters [2], + axi4_if.master targets [5], + output logic fault_valid_o, + output logic [31:0] fault_addr_o, + output logic fault_master_o, + output logic fault_write_o, + output logic [ 1:0] fault_resp_o, + output logic [63:0] cpu_wait_o, + output logic [63:0] dma_wait_o +); + typedef enum logic [1:0] { + Idle, + Addr, + Response + } state_e; + typedef struct packed { + logic [31:0] addr; + logic [7:0] len; + logic [2:0] size; + logic [1:0] burst; + logic lock; + logic [3:0] cache; + logic [2:0] prot; + logic [3:0] qos; + logic [3:0] region; + logic id; + logic user; + } addr_t; + state_e s_state_d, s_state_q; + logic [1:0] s_state_bits_q; + addr_t s_addr_d, s_addr_q; + addr_t s_read_addr [2]; + addr_t s_write_addr [2]; + addr_t s_selected_addr; + logic s_owner_d, s_owner_q; + logic s_write_d, s_write_q; + logic [2:0] s_tgt_d, s_tgt_q; + logic [3:0] s_request, s_unused_grant; + logic [ 1:0] s_selected; + logic s_selected_valid; + logic s_accept; + logic s_terminal; + logic [32:0] s_last_addr; + logic [ 2:0] s_decoded_target; + logic s_protocol_legal; + logic [1:0] s_awvalid, s_arvalid, s_wvalid, s_wlast, s_bready, s_rready; + logic [1:0][31:0] s_wdata; + logic [1:0][ 3:0] s_wstrb; + logic [1:0] s_wuser; + logic [4:0] s_target_awready, s_target_arready, s_target_wready; + logic [4:0] s_target_bvalid, s_target_rvalid, s_target_rlast; + logic [4:0] s_target_bid, s_target_rid, s_target_buser, s_target_ruser; + logic [4:0][1:0] s_target_bresp, s_target_rresp; + logic [4:0][31:0] s_target_rdata; + logic [1:0][63:0] s_wait_d, s_wait_q; + + function automatic logic [2:0] decode_target(input logic [31:0] addr_i); + if (`SOC_ADDR_IS_SRAM(addr_i)) return 3'd0; + if (`SOC_ADDR_IS_FLASH(addr_i) || `SOC_ADDR_IS_XPI(addr_i)) return 3'd1; + if (`SOC_ADDR_IS_APB4_PERIPH(addr_i) || `SOC_ADDR_IS_APB4_SYSTEM(addr_i)) return 3'd2; + return 3'd3; + endfunction + + assign s_state_q = state_e'(s_state_bits_q); + assign s_request = {s_awvalid[1], s_arvalid[1], s_awvalid[0], s_arvalid[0]}; + assign s_selected_addr = s_selected[0] ? s_write_addr[s_selected[1]] : s_read_addr[s_selected[1]]; + assign s_decoded_target = decode_target(s_selected_addr.addr); + assign s_last_addr = {1'b0, s_selected_addr.addr} + + (({25'd0, s_selected_addr.len} + 33'd1) << s_selected_addr.size) - 33'd1; + assign s_protocol_legal = !s_selected_addr.lock && (s_selected_addr.size <= 3'd2) && + ((s_selected_addr.addr & ((32'd1 << s_selected_addr.size) - 32'd1)) == 32'd0) && + ((s_selected_addr.burst == 2'b01) || + ((s_selected_addr.burst == 2'b00) && (s_selected_addr.len == 8'd0))) && + (s_selected_addr.len <= 8'd15) && !s_last_addr[32] && + (s_last_addr[31:12] == s_selected_addr.addr[31:12]) && + (decode_target( + s_last_addr[31:0] + ) == s_decoded_target) && ((s_decoded_target != 3'd2) || (s_selected_addr.len == 8'd0)); + assign s_accept = (s_state_q == Idle) && s_selected_valid; + assign s_terminal = (s_state_q == Response) && + (s_write_q ? (s_target_bvalid[s_tgt_q] && s_bready[s_owner_q]) : + (s_target_rvalid[s_tgt_q] && s_rready[s_owner_q] && s_target_rlast[s_tgt_q])); + assign fault_resp_o = s_write_q ? s_target_bresp[s_tgt_q] : s_target_rresp[s_tgt_q]; + assign fault_valid_o = s_terminal && (fault_resp_o != 2'b00); + assign fault_addr_o = s_addr_q.addr; + assign fault_master_o = s_owner_q; + assign fault_write_o = s_write_q; + assign cpu_wait_o = s_wait_q[0]; + assign dma_wait_o = s_wait_q[1]; + + // Advance on acceptance: the chosen owner is saved until completion, so the + // next grant after completion starts after this source/direction. + round_robin_arbiter #( + .CLIENTS(4) + ) u_arbiter ( + .clk_i (clk_i), + .rst_n_i (rst_n_i), + .advance_i (s_accept), + .request_i (s_request), + .grant_o (s_unused_grant), + .selected_o(s_selected), + .valid_o (s_selected_valid) + ); + + always_comb begin + s_state_d = s_state_q; + s_owner_d = s_owner_q; + s_write_d = s_write_q; + s_addr_d = s_addr_q; + s_tgt_d = s_tgt_q; + unique case (s_state_q) + Idle: + if (s_accept) begin + s_owner_d = s_selected[1]; + s_write_d = s_selected[0]; + s_addr_d = s_selected_addr; + s_tgt_d = s_protocol_legal ? s_decoded_target : 3'd4; + s_state_d = Addr; + end + Addr: + if (s_write_q ? s_target_awready[s_tgt_q] : s_target_arready[s_tgt_q]) s_state_d = Response; + Response: if (s_terminal) s_state_d = Idle; + default: s_state_d = Idle; + endcase + s_wait_d = s_wait_q; + for (int unsigned master = 0; master < 2; master++) begin + if (perf_clear_i) s_wait_d[master] = '0; + else if (perf_enable_i && (s_awvalid[master] || s_arvalid[master]) && + !(s_accept && (s_selected[1] == 1'(master))) && + (s_wait_q[master] != 64'hffff_ffff_ffff_ffff)) + s_wait_d[master] = s_wait_q[master] + 64'd1; + end + end + for (genvar master = 0; master < 2; master++) begin : gen_master + assign s_write_addr[master] = { + masters[master].awaddr, + masters[master].awlen, + masters[master].awsize, + masters[master].awburst, + masters[master].awlock, + masters[master].awcache, + masters[master].awprot, + masters[master].awqos, + masters[master].awregion, + masters[master].awid, + masters[master].awuser + }; + assign s_read_addr[master] = { + masters[master].araddr, + masters[master].arlen, + masters[master].arsize, + masters[master].arburst, + masters[master].arlock, + masters[master].arcache, + masters[master].arprot, + masters[master].arqos, + masters[master].arregion, + masters[master].arid, + masters[master].aruser + }; + assign s_awvalid[master] = masters[master].awvalid; + assign s_arvalid[master] = masters[master].arvalid; + assign s_wdata[master] = masters[master].wdata; + assign s_wstrb[master] = masters[master].wstrb; + assign s_wlast[master] = masters[master].wlast; + assign s_wuser[master] = masters[master].wuser; + assign s_wvalid[master] = masters[master].wvalid; + assign s_bready[master] = masters[master].bready; + assign s_rready[master] = masters[master].rready; + assign masters[master].awready = s_accept && (s_selected == {1'(master), 1'b1}); + assign masters[master].arready = s_accept && (s_selected == {1'(master), 1'b0}); + assign masters[master].wready = (s_state_q == Response) && s_write_q && + (s_owner_q == 1'(master)) && s_target_wready[s_tgt_q]; + assign masters[master].bvalid = (s_state_q == Response) && s_write_q && + (s_owner_q == 1'(master)) && s_target_bvalid[s_tgt_q]; + assign masters[master].rvalid = (s_state_q == Response) && !s_write_q && + (s_owner_q == 1'(master)) && s_target_rvalid[s_tgt_q]; + assign masters[master].bid = s_target_bid[s_tgt_q]; + assign masters[master].bresp = s_target_bresp[s_tgt_q]; + assign masters[master].buser = s_target_buser[s_tgt_q]; + assign masters[master].rid = s_target_rid[s_tgt_q]; + assign masters[master].rdata = s_target_rdata[s_tgt_q]; + assign masters[master].rresp = s_target_rresp[s_tgt_q]; + assign masters[master].rlast = s_target_rlast[s_tgt_q]; + assign masters[master].ruser = s_target_ruser[s_tgt_q]; + end + for (genvar target = 0; target < 5; target++) begin : gen_target + assign targets[target].awaddr = s_addr_q.addr; + assign targets[target].awlen = s_addr_q.len; + assign targets[target].awsize = s_addr_q.size; + assign targets[target].awburst = s_addr_q.burst; + assign targets[target].awlock = s_addr_q.lock; + assign targets[target].awcache = s_addr_q.cache; + assign targets[target].awprot = s_addr_q.prot; + assign targets[target].awqos = s_addr_q.qos; + assign targets[target].awregion = s_addr_q.region; + assign targets[target].awid = s_addr_q.id; + assign targets[target].awuser = s_addr_q.user; + assign targets[target].awvalid = (s_state_q == Addr) && s_write_q && (s_tgt_q == 3'(target)); + assign targets[target].araddr = s_addr_q.addr; + assign targets[target].arlen = s_addr_q.len; + assign targets[target].arsize = s_addr_q.size; + assign targets[target].arburst = s_addr_q.burst; + assign targets[target].arlock = s_addr_q.lock; + assign targets[target].arcache = s_addr_q.cache; + assign targets[target].arprot = s_addr_q.prot; + assign targets[target].arqos = s_addr_q.qos; + assign targets[target].arregion = s_addr_q.region; + assign targets[target].arid = s_addr_q.id; + assign targets[target].aruser = s_addr_q.user; + assign targets[target].arvalid = (s_state_q == Addr) && !s_write_q && (s_tgt_q == 3'(target)); + assign targets[target].wdata = s_wdata[s_owner_q]; + assign targets[target].wstrb = s_wstrb[s_owner_q]; + assign targets[target].wlast = s_wlast[s_owner_q]; + assign targets[target].wuser = s_wuser[s_owner_q]; + assign targets[target].wvalid = (s_state_q == Response) && s_write_q && + (s_tgt_q == 3'(target)) && s_wvalid[s_owner_q]; + assign targets[target].bready = (s_state_q == Response) && s_write_q && + (s_tgt_q == 3'(target)) && s_bready[s_owner_q]; + assign targets[target].rready = (s_state_q == Response) && !s_write_q && + (s_tgt_q == 3'(target)) && s_rready[s_owner_q]; + assign s_target_awready[target] = targets[target].awready; + assign s_target_arready[target] = targets[target].arready; + assign s_target_wready[target] = targets[target].wready; + assign s_target_bvalid[target] = targets[target].bvalid; + assign s_target_bid[target] = targets[target].bid; + assign s_target_bresp[target] = targets[target].bresp; + assign s_target_buser[target] = targets[target].buser; + assign s_target_rvalid[target] = targets[target].rvalid; + assign s_target_rid[target] = targets[target].rid; + assign s_target_rresp[target] = targets[target].rresp; + assign s_target_rdata[target] = targets[target].rdata; + assign s_target_rlast[target] = targets[target].rlast; + assign s_target_ruser[target] = targets[target].ruser; + end + dffr #( + .DATA_WIDTH(2) + ) u_state_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_state_d), + .dat_o (s_state_bits_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_owner_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_owner_d), + .dat_o (s_owner_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_write_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_write_d), + .dat_o (s_write_q) + ); + dffr #( + .DATA_WIDTH(63) + ) u_addr_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_addr_d), + .dat_o (s_addr_q) + ); + dffr #( + .DATA_WIDTH(3) + ) u_target_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_tgt_d), + .dat_o (s_tgt_q) + ); + dffr #( + .DATA_WIDTH(128) + ) u_wait_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_wait_d), + .dat_o (s_wait_q) + ); +endmodule diff --git a/rtl/tiny/top/tiny_sysctrl.sv b/rtl/tiny/top/tiny_sysctrl.sv new file mode 100644 index 00000000..7a0ac57a --- /dev/null +++ b/rtl/tiny/top/tiny_sysctrl.sv @@ -0,0 +1,240 @@ +// Copyright (c) 2026 Yuchi Miao +// SPDX-License-Identifier: MulanPSL-2.0 +`include "sysctrl_define.svh" + +module tiny_sysctrl ( + input logic clk_i, + input logic rst_n_i, + apb4_if.slave apb4, + input logic fault_valid_i, + input logic [31:0] fault_addr_i, + input logic fault_write_i, + input logic fault_master_i, + input logic [ 1:0] fault_resp_i, + input logic [63:0] cpu_wait_i, + input logic [63:0] dma_wait_i, + input logic rtc_wake_i, + output logic perf_enable_o, + output logic perf_clear_o, + output logic test_done_o, + output logic test_pass_o, + output logic [ 7:0] test_code_o +); + logic [31:0] s_test_d, s_test_q; + logic [31:0] s_fault_addr_d, s_fault_addr_q; + logic [31:0] s_fault_count_d, s_fault_count_q; + logic [4:0] s_fault_stat_d, s_fault_stat_q; + logic s_fault_master_d, s_fault_master_q; + logic [1:0] s_fault_resp_d, s_fault_resp_q; + logic s_perf_en_d, s_perf_en_q; + logic s_wake_d, s_wake_q; + logic [63:0] s_cpu_snapshot_d, s_cpu_snapshot_q; + logic [63:0] s_dma_snapshot_d, s_dma_snapshot_q; + logic s_req, s_write, s_valid, s_writable, s_access_err; + logic s_ready_d, s_ready_q; + logic s_err_d, s_err_q; + logic [31:0] s_read_data; + logic [31:0] s_offset; + logic [31:0] s_rdata_d, s_rdata_q; + + assign s_offset = {20'd0, apb4.paddr[11:0]}; + assign s_req = apb4.psel && apb4.penable && !s_ready_q; + assign s_write = s_req && apb4.pwrite && !s_access_err; + assign s_access_err = (apb4.paddr[1:0] != 2'd0) || !s_valid || + (apb4.pwrite && (!s_writable || (apb4.pstrb != 4'hf))); + assign s_ready_d = s_req; + assign s_err_d = s_req && s_access_err; + assign s_rdata_d = s_req ? s_read_data : s_rdata_q; + assign apb4.pready = s_ready_q; + assign apb4.pslverr = s_err_q; + assign apb4.prdata = s_rdata_q; + assign perf_enable_o = s_perf_en_q; + assign perf_clear_o = s_write && (s_offset == `APB4_SYSCTRL__PERF_CTRL) && apb4.pwdata[1]; + assign test_done_o = s_test_q[31]; + assign test_pass_o = s_test_q[0]; + assign test_code_o = s_test_q[15:8]; + + always_comb begin + s_valid = 1'b1; + s_writable = 1'b0; + s_read_data = '0; + unique case (s_offset) + `APB4_SYSCTRL__CORESEL, `APB4_SYSCTRL__IPSEL: s_read_data = '0; + `APB4_SYSCTRL__USER_CORE_RESET: s_read_data = 32'hffff_ffff; + `APB4_SYSCTRL__USER_CORE_STATUS: s_read_data = 32'h0000_0200; + `APB4_SYSCTRL__FAULT_STATUS: begin + s_read_data = {27'd0, s_fault_stat_q}; + s_writable = 1'b1; + end + `APB4_SYSCTRL__FAULT_ADDR: s_read_data = s_fault_addr_q; + `APB4_SYSCTRL__FAULT_COUNT: s_read_data = s_fault_count_q; + `APB4_SYSCTRL__FAULT_MASTER: s_read_data = {31'd0, s_fault_master_q}; + `APB4_SYSCTRL__FAULT_DETAIL: s_read_data = {30'd0, s_fault_resp_q}; + `APB4_SYSCTRL__PERF_CTRL: begin + s_read_data = {31'd0, s_perf_en_q}; + s_writable = 1'b1; + end + `APB4_SYSCTRL__PERF_MGMT_WAIT_LO: s_read_data = s_cpu_snapshot_q[31:0]; + `APB4_SYSCTRL__PERF_MGMT_WAIT_HI: s_read_data = s_cpu_snapshot_q[63:32]; + `APB4_SYSCTRL__PERF_DMA_WAIT_LO: s_read_data = s_dma_snapshot_q[31:0]; + `APB4_SYSCTRL__PERF_DMA_WAIT_HI: s_read_data = s_dma_snapshot_q[63:32]; + `APB4_SYSCTRL__TEST_STATUS: begin + s_read_data = s_test_q; + s_writable = 1'b1; + end + `APB4_SYSCTRL__RTC_WAKE_STATUS: begin + s_read_data = {30'd0, s_wake_q, rtc_wake_i}; + s_writable = 1'b1; + end + default: s_valid = 1'b0; + endcase + end + always_comb begin + s_test_d = s_test_q; + s_fault_addr_d = s_fault_addr_q; + s_fault_count_d = s_fault_count_q; + s_fault_stat_d = s_fault_stat_q; + s_fault_master_d = s_fault_master_q; + s_fault_resp_d = s_fault_resp_q; + s_perf_en_d = s_perf_en_q; + s_wake_d = s_wake_q; + s_cpu_snapshot_d = s_cpu_snapshot_q; + s_dma_snapshot_d = s_dma_snapshot_q; + if (s_write) begin + unique case ({ + 20'd0, apb4.paddr[11:0] + }) + `APB4_SYSCTRL__FAULT_STATUS: if (apb4.pwdata[0]) s_fault_stat_d[0] = 1'b0; + `APB4_SYSCTRL__PERF_CTRL: begin + s_perf_en_d = apb4.pwdata[0]; + if (apb4.pwdata[1]) begin + s_cpu_snapshot_d = '0; + s_dma_snapshot_d = '0; + end else if (apb4.pwdata[2]) begin + s_cpu_snapshot_d = cpu_wait_i; + s_dma_snapshot_d = dma_wait_i; + end + end + `APB4_SYSCTRL__TEST_STATUS: + if (!s_test_q[31] && apb4.pwdata[31]) s_test_d = apb4.pwdata & 32'h8000_ff01; + `APB4_SYSCTRL__RTC_WAKE_STATUS: if (apb4.pwdata[1]) s_wake_d = 1'b0; + default: begin + end + endcase + end + if (rtc_wake_i) s_wake_d = 1'b1; + if (fault_valid_i) begin + if (s_fault_count_q != 32'hffff_ffff) s_fault_count_d = s_fault_count_q + 32'd1; + if (!s_fault_stat_d[0]) begin + s_fault_stat_d = {(fault_resp_i == 2'b11) ? 3'd1 : 3'd2, fault_write_i, 1'b1}; + s_fault_addr_d = fault_addr_i; + s_fault_master_d = fault_master_i; + s_fault_resp_d = fault_resp_i; + end + end + end + dffr #( + .DATA_WIDTH(32) + ) u_test_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_test_d), + .dat_o (s_test_q) + ); + dffr #( + .DATA_WIDTH(32) + ) u_fault_addr_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_fault_addr_d), + .dat_o (s_fault_addr_q) + ); + dffr #( + .DATA_WIDTH(32) + ) u_fault_count_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_fault_count_d), + .dat_o (s_fault_count_q) + ); + dffr #( + .DATA_WIDTH(5) + ) u_fault_status_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_fault_stat_d), + .dat_o (s_fault_stat_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_fault_master_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_fault_master_d), + .dat_o (s_fault_master_q) + ); + dffr #( + .DATA_WIDTH(2) + ) u_fault_resp_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_fault_resp_d), + .dat_o (s_fault_resp_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_perf_enable_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_perf_en_d), + .dat_o (s_perf_en_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_wake_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_wake_d), + .dat_o (s_wake_q) + ); + dffr #( + .DATA_WIDTH(64) + ) u_cpu_snapshot_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_cpu_snapshot_d), + .dat_o (s_cpu_snapshot_q) + ); + dffr #( + .DATA_WIDTH(64) + ) u_dma_snapshot_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_dma_snapshot_d), + .dat_o (s_dma_snapshot_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_ready_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_ready_d), + .dat_o (s_ready_q) + ); + dffr #( + .DATA_WIDTH(1) + ) u_error_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_err_d), + .dat_o (s_err_q) + ); + dffr #( + .DATA_WIDTH(32) + ) u_rdata_reg ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .dat_i (s_rdata_d), + .dat_o (s_rdata_q) + ); +endmodule diff --git a/scripts/check_embedded_c.py b/scripts/check_embedded_c.py index ab37fb25..2aa53276 100644 --- a/scripts/check_embedded_c.py +++ b/scripts/check_embedded_c.py @@ -66,7 +66,11 @@ def policy_issues(root: Path, path: Path, policy: dict[str, object]) -> list[str text = path.read_text(encoding="utf-8") issues: list[str] = [] - if TINY_TOKEN.search(text): + # Product names in comments/string literals are prose, not retired SDK + # identifiers. Legacy include paths are still checked against the raw text. + code = re.sub(r'/\*.*?\*/|//[^\n]*|"(?:\\.|[^"\\])*"|\'(?:\\.|[^\'\\])*\'', + " ", text, flags=re.DOTALL) + if TINY_TOKEN.search(code): issues.append("contains a retired tiny-prefixed identifier or label") if LEGACY_INCLUDE.search(text): issues.append("contains a retired legacy include path") diff --git a/scripts/check_format.py b/scripts/check_format.py index 647d22ca..bd85ce7a 100644 --- a/scripts/check_format.py +++ b/scripts/check_format.py @@ -17,6 +17,7 @@ SELF_OWNED_RTL_ROOTS = { ("rtl", "demo"), ("rtl", "ip"), ("rtl", "mini"), + ("rtl", "tiny"), ("rtl", "tech"), ("tests", "rtl"), } diff --git a/scripts/crypto_p0.py b/scripts/crypto_p0.py index b14b2b75..545234c5 100644 --- a/scripts/crypto_p0.py +++ b/scripts/crypto_p0.py @@ -193,7 +193,7 @@ def rtl(variant: Path, output: Path, jobs: int, selected: str | None = None) -> includes = [CRYPTO, COMMON, COMMON / "interface"] if top == "crypto_dma_p0_tb": generated = case / "memory_map" - execute(case, "memory-map", [sys.executable, str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + execute(case, "memory-map", [sys.executable, str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", str(generated), "--have-sram-if", "NO"]) includes += [generated / "rtl", COMMON / "stream", COMMON / "utils"] @@ -214,7 +214,7 @@ def rtl(variant: Path, output: Path, jobs: int, selected: str | None = None) -> fl.write_text("+define+SV_ASSRT_DISABLE\n" + "\n".join([*[f"+incdir+{p}" for p in includes], *map(str, sources)]) + "\n") converted = case / "test.v" - execute(case, "convert", [sys.executable, str(ROOT / "rtl/mini/script/convt_sv2v.py"), + execute(case, "convert", [sys.executable, str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(fl), "--output", str(converted)]) binary = case / "test.vvp" execute(case, "compile", ["iverilog", "-g2012", "-s", top, diff --git a/scripts/doctor.py b/scripts/doctor.py index 973bcff9..8e0c6961 100644 --- a/scripts/doctor.py +++ b/scripts/doctor.py @@ -23,6 +23,7 @@ def parse_args() -> argparse.Namespace: parser.add_argument("--synth", required=True) parser.add_argument("--sta", required=True) parser.add_argument("--pdk", required=True) + parser.add_argument("--soc", choices=("MINI", "TINY"), default="MINI") parser.add_argument("--have-sram-macro", choices=("YES", "NO"), default="NO") parser.add_argument("--formal", choices=("YES", "NO"), default="NO") parser.add_argument("--require-debug-tools", action="store_true") @@ -73,6 +74,9 @@ def main() -> int: tools.extend(("openocd", "riscv32-unknown-elf-gdb")) source_names = ["mpw", "hazard3", "cluster_common", "third_party_ip"] + if args.soc == "TINY": + from scripts.setup_tiny import TINY_SOURCES + source_names = [name for name in TINY_SOURCES if not name.startswith("pdk_")] pdk_names = { "IHP130": "pdk_ihp130", "ICS55": "pdk_ics55", diff --git a/scripts/generate_tiny.py b/scripts/generate_tiny.py new file mode 100644 index 00000000..6c908315 --- /dev/null +++ b/scripts/generate_tiny.py @@ -0,0 +1,160 @@ +#!/usr/bin/env python3 +"""Generate Tiny integration bindings and absolute source lists from owned maps.""" + +from __future__ import annotations + +import argparse +import json +import re +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +sys.path.insert(0, str(ROOT)) +from scripts.rtl.generate_memory_map import generate as generate_memory_map # noqa: E402 +from scripts.rtl.generate_pin_map import generate as generate_pin_map # noqa: E402 +from scripts.setup_helpers import atomic_write # noqa: E402 + +TINY = ROOT / "rtl/tiny" + + +def read_topology(path: Path, memory_map: Path) -> dict: + document = json.loads(path.read_text()) + regions = {r["symbol"] for r in json.loads(memory_map.read_text())["regions"]} + if document.get("schema_version") != 1 or document.get("dma_channels") != 4: + raise ValueError("Tiny requires topology schema 1 and four DMA channels") + if document.get("irq_vector_width") != 32 or document.get("external_irq_count") != 30: + raise ValueError("Tiny requires a 32-bit IRQ vector and 30 external inputs") + names: set[str] = set() + bits: set[int] = set() + for irq in document["interrupts"]: + if irq["name"] in names or irq["core_bit"] in bits: + raise ValueError("duplicate Tiny interrupt") + if not 0 <= irq["core_bit"] < 32: + raise ValueError("Tiny IRQ outside vector") + names.add(irq["name"]) + bits.add(irq["core_bit"]) + assigned: set[str] = set() + for target in document["apb_targets"]: + for region in target["regions"]: + if region not in regions or region in assigned: + raise ValueError(f"invalid or duplicate APB region {region}") + assigned.add(region) + if assigned != {r for r in regions if r.startswith("APB4_")}: + raise ValueError("Tiny topology must route every APB region") + if len(document["apb_targets"]) != 16: + raise ValueError("Tiny's fixed APB bridge requires sixteen targets") + target_names = [target["name"] for target in document["apb_targets"]] + if len(set(target_names)) != 16 or any(re.fullmatch(r"[a-z][a-z0-9_]*", name) is None + for name in target_names): + raise ValueError("Tiny APB target names must be unique identifiers") + if sorted(item["pin"] for item in document["gpio_alt_functions"]) != list(range(32)): + raise ValueError("Tiny GPIO map must contain all 32 pins exactly once") + return document + + +def generate_bindings(document: dict, output: Path) -> None: + comment = "// Generated by scripts/generate_tiny.py; do not edit.\n" + irq = [comment, "always_comb begin", " s_irq = '0;"] + header = ["#ifndef RETROSOC_GENERATED_IRQ_METADATA_H", + "#define RETROSOC_GENERATED_IRQ_METADATA_H", "#include ", + "#define RS_SOC_IRQ_VECTOR_WIDTH UINT32_C(32)", + "#define RS_SOC_EXTERNAL_IRQ_COUNT UINT32_C(30)", + f"#define RS_SOC_ALLOCATED_IRQ_COUNT UINT32_C({len(document['interrupts']) - 2})"] + for item in document["interrupts"]: + bit, name = item["core_bit"], item["name"].upper() + irq.append(f" s_irq[{bit}] = {item['signal']};") + header.append(f"#define RS_SOC_IRQ_{name} UINT32_C({bit})") + if bit >= 2: + header.append(f"#define RS_SOC_EXT_IRQ_{name} UINT32_C({bit - 2})") + irq.append("end\n") + header.append("#endif\n") + atomic_write(output / "rtl/tiny_irq.svh", "\n".join(irq)) + atomic_write(output / "include/retrosoc/generated/irq_metadata.h", "\n".join(header)) + atomic_write(output / "include/retrosoc/generated/user_extensions.h", + "#ifndef RETROSOC_GENERATED_USER_EXTENSIONS_H\n" + "#define RETROSOC_GENERATED_USER_EXTENSIONS_H\n" + "#define RS_SOC_USER_CORE_COUNT 0U\n#define RS_SOC_USER_IP_COUNT 0U\n" + "#define RS_SOC_HAS_USER_CORES 0U\n#define RS_SOC_HAS_USER_IP_MUX 0U\n#endif\n") + atomic_write(output / "include/retrosoc/generated/soc_features.h", + "#ifndef RETROSOC_GENERATED_SOC_FEATURES_H\n" + "#define RETROSOC_GENERATED_SOC_FEATURES_H\n" + "#define RS_SOC_TINY 1\n#define RS_SOC_HAS_PSRAM 0U\n" + "#define RS_SOC_DMA_CHANNELS 4U\n#define RS_SOC_ID 0x54494E59U\n#endif\n") + gpio = [comment] + for function in document["gpio_alt_functions"]: + pin = function["pin"] + for mode in ("alt0", "alt1"): + value = function[mode] + gpio.extend(f"assign {signal} = u_gpio_if.di_i[{pin}];" for signal in value["inputs"]) + gpio.extend((f"assign u_gpio_if.{mode}_do_i[{pin}] = {value['do']};", + f"assign u_gpio_if.{mode}_oe_i[{pin}] = {value['oe']};")) + atomic_write(output / "rtl/tiny_gpio.svh", "\n".join(gpio) + "\n") + ports, declarations, routes, decode = [], [comment], [comment], [comment] + for index, target in enumerate(document["apb_targets"]): + name = target["name"] + ports.append(f"apb4_if.master {name}") + declarations.append(f"apb4_if u_{name}_apb4_if (.pclk(clk_i), .presetn(s_rst_n));") + routes.append(f".{name}(u_{name}_apb4_if)") + decode.append(f"if ({' || '.join(f'`SOC_ADDR_IS_{r}(s_addr_q)' for r in target['regions'])}) " + f"s_select = {len(document['apb_targets'])}'b{1 << index:016b};") + atomic_write(output / "rtl/tiny_apb_ports.svh", ",\n".join(ports) + "\n") + atomic_write(output / "rtl/tiny_apb_interfaces.svh", "\n".join(declarations) + "\n") + atomic_write(output / "rtl/tiny_apb_connections.svh", ",\n".join(routes[1:]) + "\n") + atomic_write(output / "rtl/tiny_apb_decode.svh", "\n".join(decode) + "\n") + wiring = [comment] + for index, target in enumerate(document["apb_targets"]): + name = target["name"] + for field, value in {"paddr": "s_addr_q", "pwrite": "s_write_q", + "pwdata": "s_wdata_q", "pstrb": "s_wstrb_q", "pprot": "3'd0", + "psel": f"s_select[{index}] && s_access", + "penable": "s_enable"}.items(): + wiring.append(f"assign {name}.{field} = {value};") + wiring.extend((f"assign s_ready[{index}] = {name}.pready;", + f"assign s_error[{index}] = {name}.pslverr;", + f"assign s_rdata[{index}] = {name}.prdata;")) + atomic_write(output / "rtl/tiny_apb_wiring.svh", "\n".join(wiring) + "\n") + + +def generate_filelists(output: Path, generated: Path, defines: list[str]) -> None: + prefixes = {"top": TINY / "top", "dv": TINY / "dv", "ip": ROOT / "rtl/ip", + "tech": ROOT / "rtl/tech", "clusterip": ROOT / "rtl/managed/clusterip", + "hazard3": ROOT / "rtl/managed/hazard3/hdl", "physical": ROOT / "physical"} + templates = [*sorted((TINY / "filelist").glob("*.fl")), + ROOT / "rtl/filelist/pdk_ihp130.fl"] + for template in templates: + content = template.read_text() + for prefix, directory in prefixes.items(): + content = re.sub(rf"(? int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--output", type=Path) + parser.add_argument("--filelists", type=Path) + parser.add_argument("--define", action="append", default=[]) + parser.add_argument("--check", action="store_true") + args = parser.parse_args() + document = read_topology(TINY / "integration/soc_topology.json", + TINY / "address_map/memory_map.json") + if args.check: + return 0 + if args.output is None or args.filelists is None: + parser.error("--output and --filelists are required unless --check is used") + if any(not value.startswith("+define+") for value in args.define): + parser.error("--define requires a +define+ token") + output = args.output.resolve() + generate_memory_map(TINY / "address_map/memory_map.json", output / "memory_map", "YES", 128) + generate_pin_map(TINY / "pin_map/pin_map.json", output / "pin_map") + generate_bindings(document, output) + generate_filelists(args.filelists.resolve(), output, args.define) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/scripts/metrics.py b/scripts/metrics.py index cf9bf916..a17b61a4 100644 --- a/scripts/metrics.py +++ b/scripts/metrics.py @@ -17,7 +17,7 @@ from scripts.setup_helpers import atomic_write # noqa: E402 AREA_RE = re.compile(r"Chip area for top module[^:]*:\s*([0-9.eE+-]+)") -HIERARCHY_RE = re.compile(r"^\s*(\d+)\s+[0-9.eE+-]+\s+retrosoc_asic\s*$", re.MULTILINE) +HIERARCHY_RE = re.compile(r"^\s*(\d+)\s+[0-9.eE+-]+\s+retrosoc_(?:tiny_)?asic\s*$", re.MULTILINE) def collect(args: argparse.Namespace) -> int: @@ -35,10 +35,18 @@ def collect(args: argparse.Namespace) -> int: for binary in sorted((root / "sw").glob("*.bin")): metrics["firmware"][binary.name] = {"bytes": binary.stat().st_size} - area_json = synth_root / "rpt/retrosoc_asic_area.json" - area_report = synth_root / "rpt/retrosoc_asic_area.rpt" + manifest_path = root / "meta/manifest.json" + soc = "MINI" + if manifest_path.is_file(): + soc = json.loads(manifest_path.read_text())["configuration"].get("SOC", "MINI") + top = "retrosoc_tiny_asic" if soc == "TINY" else "retrosoc_asic" + area_json = synth_root / "rpt" / f"{top}_area.json" + area_report = synth_root / "rpt" / f"{top}_area.rpt" if area_json.is_file(): - design = json.loads(area_json.read_text(encoding="utf-8"))["design"] + # Yosys -t also prefixes tee report lines in some locked tool builds. + contents = re.sub(r"^\[\d+\.\d+\]\s?", "", area_json.read_text(encoding="utf-8"), + flags=re.MULTILINE) + design = json.loads(contents)["design"] metrics["synthesis"]["top_area"] = float(design["area"]) metrics["synthesis"]["top_cells"] = int(design["num_cells"]) elif area_report.is_file(): diff --git a/scripts/package.py b/scripts/package.py index 28a8b807..82f0b6c9 100644 --- a/scripts/package.py +++ b/scripts/package.py @@ -93,6 +93,8 @@ def main() -> int: manifest = json.loads(manifest_path.read_text(encoding="utf-8")) config = manifest["configuration"] lock = load_lock(args.lock) + soc = config.get("SOC", "MINI") + product_root = root / "rtl" / soc.lower() args.output_dir.parent.mkdir(parents=True, exist_ok=True) with tempfile.TemporaryDirectory( @@ -100,7 +102,9 @@ def main() -> int: ) as temp: staging = Path(temp) / "package" staging.mkdir() - timing_contract = Path(temp) / "commercial_timing_contract.tcl" + timing_contract = Path(temp) / ("tiny_core.sdc" if soc == "TINY" else "commercial_timing_contract.tcl") + timing_generator = (root / "physical/smoke/sta/opensta/generate_sdc.py" if soc == "TINY" + else root / "physical/commercial/scripts/generate_timing_contract.py") if config.get("MINI_MODE", "PRODUCT") == "MPW": dynamic_core_filelist = ( args.variant_root @@ -124,14 +128,11 @@ def main() -> int: subprocess.run( [ "python3", - str( - root - / "physical/commercial/scripts/generate_timing_contract.py" - ), + str(timing_generator), "--domains", - str(root / "rtl/mini/integration/clock_reset_domains.json"), + str(product_root / "integration/clock_reset_domains.json"), "--pin-map", - str(root / "rtl/mini/pin_map/pin_map.json"), + str(product_root / "pin_map/pin_map.json"), "--output", str(timing_contract), ], @@ -171,8 +172,16 @@ def main() -> int: "--archinfo-incdir", str(args.variant_root / "generated/archinfo"), "--metadata-file", - "contracts/commercial_timing_contract.tcl={0}".format(timing_contract), + f"contracts/{timing_contract.name}={timing_contract}", ] + if soc == "TINY": + if config.get("SYNTH") == "YOSYS": + recipe = config.get("SYNTH_RECIPE", "balanced") + folder = "yosys" if recipe == "balanced" else f"yosys-{recipe}" + source_dir = args.variant_root / "syn" / folder / "filelists" + else: + source_dir = args.variant_root / "sim" / config["SIMU"].lower() / "filelists" + command.extend(("--soc", "TINY", "--source-filelist-dir", str(source_dir))) for key, flag in ( ("HAVE_PLL", "--have-pll"), ("HAVE_SRAM_IF", "--have-sram-if"), diff --git a/scripts/regress.py b/scripts/regress.py index df161afe..92c8b4fc 100644 --- a/scripts/regress.py +++ b/scripts/regress.py @@ -70,7 +70,16 @@ PR_COMMANDS = ( ), ("configs/ci/ihp130.mk", ("STA=OPENSTA", "sta")), ) -RTL_COMMANDS = PR_COMMANDS[:6] +TINY_PR_COMMANDS = ( + ("configs/ci/ihp130-tiny.mk", RTL_LINT_VALUES), + ("configs/ci/ihp130-tiny.mk", ("APP=ci_smoke", "LINK_TYPE=ld2_all_sram", "SIMU=VERILATOR", "SOC_SIM_TIME=1800", "HAVE_CSR=YES", "HAVE_SVA=YES", "firmware", "sim")), + ("configs/ci/ihp130-tiny.mk", ("APP=ci_smoke", "SIMU=IVERILOG", "firmware", "sim")), + ("configs/ci/ihp130-tiny.mk", ("APP=ci_smoke", "SYNTH=YOSYS", "synth")), + ("configs/ci/ihp130-tiny.mk", ("APP=ci_smoke", "SIMU=IVERILOG", "netsim-boot")), + ("configs/ci/ihp130-tiny.mk", ("APP=ci_smoke", "STA=OPENSTA", "sta")), +) +RTL_COMMANDS = (*PR_COMMANDS[:6], *TINY_PR_COMMANDS[:3]) +PR_COMMANDS = (*PR_COMMANDS, *TINY_PR_COMMANDS) SMOKE_COMMANDS = ( ("configs/ci/ihp130.mk", RTL_LINT_VALUES), ("configs/ci/ihp130.mk", (CI_SMOKE_APP_VALUE, "firmware")), @@ -106,7 +115,7 @@ NIGHTLY_COMMANDS = ( *PR_COMMANDS, *NIGHTLY_EXTRA_COMMANDS, ) -PR_PROFILES = ("configs/ci/ihp130.mk",) +PR_PROFILES = ("configs/ci/ihp130.mk", "configs/ci/ihp130-tiny.mk") SMOKE_PROFILES: tuple[str, ...] = () NIGHTLY_PROFILES = PR_PROFILES @@ -161,7 +170,7 @@ def select_regression( if suite == "nightly-extra": if pdk is not None and pdk != "IHP130": raise ValueError("nightly-extra regression supports only --pdk IHP130") - return NIGHTLY_EXTRA_COMMANDS, NIGHTLY_PROFILES + return NIGHTLY_EXTRA_COMMANDS, ("configs/ci/ihp130.mk",) if pdk: if suite == "nightly": if pdk != "IHP130": @@ -259,6 +268,7 @@ def main() -> int: "--suite", choices=("smoke", "rtl", "pr", "nightly", "nightly-extra"), required=True ) parser.add_argument("--pdk", choices=tuple(PDK_PR_PROFILES), help="run one PDK matrix") + parser.add_argument("--soc", choices=("MINI", "TINY"), help="run one product only") parser.add_argument("--dry-run", action="store_true") parser.add_argument( "--netsim-boot-only", @@ -275,6 +285,17 @@ def main() -> int: commands, profiles = select_regression(args.suite, args.pdk) except ValueError as error: parser.error(str(error)) + if args.soc is not None: + tiny_profile = "configs/ci/ihp130-tiny.mk" + if args.soc == "TINY" and args.suite == "smoke": + commands, profiles = TINY_PR_COMMANDS[:2], (tiny_profile,) + else: + commands = tuple((profile, values) for profile, values in commands + if (profile == tiny_profile) == (args.soc == "TINY")) + profiles = tuple(profile for profile in profiles + if (profile == tiny_profile) == (args.soc == "TINY")) + if not commands: + parser.error(f"suite {args.suite} has no {args.soc} configuration for this PDK") if args.netsim_boot_only: commands = with_netsim_boot_only(commands) if args.behavioral_only: diff --git a/scripts/rtl/README.md b/scripts/rtl/README.md new file mode 100644 index 00000000..9325a82e --- /dev/null +++ b/scripts/rtl/README.md @@ -0,0 +1,10 @@ +# Shared RTL Flow Helpers + +These product-independent helpers parse filelists, convert SystemVerilog, +generate address/pad artifacts, and prepare simulation inputs. Both products +invoke them here directly, with Python imports through `scripts.rtl`. Product +inputs stay under their owning `rtl/` directory; outputs stay below +`build/`. + +Changes require focused generator tests, Ruff and Pytest, plus compilation of +each affected product. `generate_tiny.py` owns Tiny-only integration bindings. diff --git a/rtl/mini/script/comb.py b/scripts/rtl/comb.py similarity index 85% rename from rtl/mini/script/comb.py rename to scripts/rtl/comb.py index c4ec62ed..8de52f62 100644 --- a/rtl/mini/script/comb.py +++ b/scripts/rtl/comb.py @@ -3,9 +3,12 @@ from __future__ import annotations import argparse +import sys from pathlib import Path -from filelist import parse_filelists, write_filelist +ROOT = Path(__file__).resolve().parents[2] +sys.path.insert(0, str(ROOT)) +from scripts.rtl.filelist import parse_filelists, write_filelist # noqa: E402 DEFAULT_OUTPUT = Path(__file__).resolve().parent.parent / ".generated_fl" / "yosys.fl" diff --git a/rtl/mini/script/convt_sv2v.py b/scripts/rtl/convt_sv2v.py similarity index 89% rename from rtl/mini/script/convt_sv2v.py rename to scripts/rtl/convt_sv2v.py index 4d7160e6..df183201 100644 --- a/rtl/mini/script/convt_sv2v.py +++ b/scripts/rtl/convt_sv2v.py @@ -4,9 +4,12 @@ from __future__ import annotations import argparse import subprocess +import sys from pathlib import Path -from filelist import parse_filelists +ROOT = Path(__file__).resolve().parents[2] +sys.path.insert(0, str(ROOT)) +from scripts.rtl.filelist import parse_filelists # noqa: E402 def parse_args() -> argparse.Namespace: diff --git a/rtl/mini/script/filelist.py b/scripts/rtl/filelist.py similarity index 100% rename from rtl/mini/script/filelist.py rename to scripts/rtl/filelist.py diff --git a/rtl/mini/script/filelist_deps.py b/scripts/rtl/filelist_deps.py similarity index 91% rename from rtl/mini/script/filelist_deps.py rename to scripts/rtl/filelist_deps.py index dfb78d9a..f25a066c 100644 --- a/rtl/mini/script/filelist_deps.py +++ b/scripts/rtl/filelist_deps.py @@ -3,9 +3,12 @@ from __future__ import annotations import argparse +import sys from pathlib import Path -from filelist import atomic_write, parse_filelists +ROOT = Path(__file__).resolve().parents[2] +sys.path.insert(0, str(ROOT)) +from scripts.rtl.filelist import atomic_write, parse_filelists # noqa: E402 HEADER_SUFFIXES = {".h", ".vh", ".svh"} diff --git a/rtl/mini/address_map/generate_memory_map.py b/scripts/rtl/generate_memory_map.py similarity index 94% rename from rtl/mini/address_map/generate_memory_map.py rename to scripts/rtl/generate_memory_map.py index 5095a4f1..aef31204 100644 --- a/rtl/mini/address_map/generate_memory_map.py +++ b/scripts/rtl/generate_memory_map.py @@ -153,10 +153,10 @@ def join_or(expressions: list[str]) -> str: def render_rtl( - cpu_reset: int, regions: list[dict[str, Any]], sysctrl_registers: list[dict[str, Any]] + cpu_reset: int, regions: list[dict[str, Any]], sysctrl_registers: list[dict[str, Any]], legacy_rib: bool = True ) -> str: lines = [ - "// Generated by rtl/mini/address_map/generate_memory_map.py; do not edit.", + "// Generated by scripts/rtl/generate_memory_map.py; do not edit.", "`ifndef RETROSOC_GENERATED_MMAP_DEFINE_SVH", "`define RETROSOC_GENERATED_MMAP_DEFINE_SVH", "", @@ -189,7 +189,8 @@ def render_rtl( for region in regions if region["route"] in {"apb4_periph", "axi4"} ] - lines.append(f"`define SOC_ADDR_IS_RIB_LEGACY_TARGET(addr) ({join_or(legacy_rib_targets)})") + if legacy_rib: + lines.append(f"`define SOC_ADDR_IS_RIB_LEGACY_TARGET(addr) ({join_or(legacy_rib_targets)})") user_readable = [ f"`SOC_ADDR_IS_{region['symbol']}(addr)" for region in regions @@ -230,9 +231,10 @@ def render_c( regions: list[dict[str, Any]], sysctrl_registers: list[dict[str, Any]], have_sram_if: str, + capability_header: str | None = None, ) -> str: lines = [ - "/* Generated by rtl/mini/address_map/generate_memory_map.py; do not edit. */", + "/* Generated by scripts/rtl/generate_memory_map.py; do not edit. */", "#ifndef RETROSOC_GENERATED_MEMORY_MAP_H", "#define RETROSOC_GENERATED_MEMORY_MAP_H", "", @@ -260,13 +262,15 @@ def render_c( f"#define RS_SOC_SYSCTRL_{register['symbol']}_OFFSET {c_hex32(register['offset'])}" for register in sysctrl_registers ) + if capability_header is not None: + lines.append(f"#include <{capability_header}>") lines += ["", "#endif", ""] return "\n".join(lines) def render_linker(regions: list[dict[str, Any]]) -> str: lines = [ - "/* Generated by rtl/mini/address_map/generate_memory_map.py; do not edit. */", + "/* Generated by scripts/rtl/generate_memory_map.py; do not edit. */", "MEMORY", "{", ] @@ -301,12 +305,14 @@ def generate(map_path: Path, output_dir: Path, have_sram_if: str, sram_size_kib: cpu_reset, regions, sysctrl_registers = read_map(map_path, sram_size_kib) atomic_write( output_dir / "rtl" / "mmap_define.svh", - render_rtl(cpu_reset, regions, sysctrl_registers), + render_rtl(cpu_reset, regions, sysctrl_registers, + json.loads(map_path.read_text()).get("legacy_rib", True)), ) atomic_write(output_dir / "memory_map.fl", f"+incdir+{output_dir / 'rtl'}\n") atomic_write( output_dir / "include" / "retrosoc" / "generated" / "memory_map.h", - render_c(cpu_reset, regions, sysctrl_registers, have_sram_if), + render_c(cpu_reset, regions, sysctrl_registers, have_sram_if, + json.loads(map_path.read_text()).get("capability_header")), ) atomic_write(output_dir / "linker" / "memory_regions.ld", render_linker(regions)) diff --git a/rtl/mini/pin_map/generate_pin_map.py b/scripts/rtl/generate_pin_map.py similarity index 91% rename from rtl/mini/pin_map/generate_pin_map.py rename to scripts/rtl/generate_pin_map.py index 99156b06..57deee25 100644 --- a/rtl/mini/pin_map/generate_pin_map.py +++ b/scripts/rtl/generate_pin_map.py @@ -29,6 +29,7 @@ REQUIRED_PROFILES = {"fpga_mini", "tb", "verilator"} CONNECTION_RE = re.compile(r"(?:[A-Za-z_][A-Za-z0-9_]*)(?:\[[0-9]+\])?$") CONSTANT_RE = re.compile(r"[0-9]+'[bBdDhHoO][0-9a-fA-F_xXzZ]+$") IHP130_POWER_PAD_COUNTS = {"vdd": 24, "vss": 24, "iovdd": 16, "iovss": 16} +POWER_PAD_KINDS = tuple(IHP130_POWER_PAD_COUNTS) POWER_CONNECTIONS = "`RETROSOC_PAD_POWER_CONNECTIONS" @@ -173,9 +174,33 @@ def validate_connection(value: Any, field: str) -> str | None: raise ValueError(f"{field} must be a signal, bit-select, constant, or null") -def read_map(path: Path) -> tuple[list[Pad], dict[str, dict[str, str | None]]]: +def read_document(path: Path) -> dict[str, Any]: with path.open(encoding="utf-8") as source: - document = json.load(source) + return json.load(source) + + +def parse_power_pads(document: dict[str, Any]) -> dict[str, int]: + counts = document.get("power_pads") + if counts is None: + return dict(IHP130_POWER_PAD_COUNTS) + if not isinstance(counts, dict) or set(counts) != set(POWER_PAD_KINDS): + raise ValueError(f"power_pads must contain exactly {list(POWER_PAD_KINDS)}") + parsed: dict[str, int] = {} + for kind in POWER_PAD_KINDS: + value = counts[kind] + if not isinstance(value, int) or isinstance(value, bool) or value <= 0: + raise ValueError(f"power_pads.{kind} must be a positive integer") + parsed[kind] = value + return parsed + + +def read_power_pad_counts(path: Path) -> dict[str, int]: + return parse_power_pads(read_document(path)) + + +def read_map(path: Path) -> tuple[list[Pad], dict[str, dict[str, str | None]]]: + document = read_document(path) + parse_power_pads(document) if document.get("schema_version") != 1: raise ValueError("schema_version must be 1") groups = document.get("pads") @@ -221,7 +246,7 @@ def wrap_feature(pad: Pad, line: str) -> list[str]: def render_ports(pads: list[Pad]) -> str: lines = [ - "// Generated by rtl/mini/pin_map/generate_pin_map.py; do not edit.", + "// Generated by scripts/rtl/generate_pin_map.py; do not edit.", "`ifdef PDK_IHP130", "`ifdef USE_POWER_PINS", " inout wire IOVDD,", @@ -239,7 +264,7 @@ def render_ports(pads: list[Pad]) -> str: def render_core_ports(pads: list[Pad]) -> str: """Render the logical-chip port list without technology power pins.""" - lines = ["// Generated by rtl/mini/pin_map/generate_pin_map.py; do not edit."] + lines = ["// Generated by scripts/rtl/generate_pin_map.py; do not edit."] for index, pad in enumerate(pads): suffix = "," if index != len(pads) - 1 else "" lines.extend(wrap_feature(pad, f" {pad.direction} {pad.name}{suffix}")) @@ -299,9 +324,12 @@ def render_pad_instance(pad: Pad) -> str | None: return None -def render_pad_bindings(pads: list[Pad]) -> str: +def render_pad_bindings( + pads: list[Pad], power_counts: dict[str, int] | None = None +) -> str: + counts = IHP130_POWER_PAD_COUNTS if power_counts is None else power_counts lines = [ - "// Generated by rtl/mini/pin_map/generate_pin_map.py; do not edit.", + "// Generated by scripts/rtl/generate_pin_map.py; do not edit.", "`ifdef PDK_IHP130", "`ifdef USE_POWER_PINS", "`define RETROSOC_PAD_POWER_CONNECTIONS .iovdd(IOVDD), .iovss(IOVSS), .vdd(VDD), .vss(VSS),", @@ -311,7 +339,7 @@ def render_pad_bindings(pads: list[Pad]) -> str: " generate", ] cell_suffixes = {"vdd": "Vdd", "vss": "Vss", "iovdd": "IOVdd", "iovss": "IOVss"} - for kind, count in IHP130_POWER_PAD_COUNTS.items(): + for kind, count in counts.items(): lines.extend( [ f" for (genvar i = 0; i < {count}; i++) begin : {kind}_pads", @@ -395,7 +423,7 @@ def render_core_binding(pad: Pad) -> str | None: def render_core_bindings(pads: list[Pad]) -> str: - lines = ["// Generated by rtl/mini/pin_map/generate_pin_map.py; do not edit."] + lines = ["// Generated by scripts/rtl/generate_pin_map.py; do not edit."] for pad in pads: binding = render_core_binding(pad) if binding is not None: @@ -424,7 +452,7 @@ def ihp130_pad_instance(pad: Pad) -> str | None: def render_profile_bindings(pads: list[Pad], bindings: dict[str, str | None]) -> str: - lines = ["// Generated by rtl/mini/pin_map/generate_pin_map.py; do not edit."] + lines = ["// Generated by scripts/rtl/generate_pin_map.py; do not edit."] for index, pad in enumerate(pads): connection = bindings.get(pad.name) suffix = "," if index != len(pads) - 1 else "" @@ -435,9 +463,12 @@ def render_profile_bindings(pads: list[Pad], bindings: dict[str, str | None]) -> def generate(map_path: Path, output_dir: Path) -> None: pads, profiles = read_map(map_path) + power_counts = read_power_pad_counts(map_path) rtl_dir = output_dir / "rtl" atomic_write(rtl_dir / "retrosoc_asic_ports.svh", render_ports(pads)) - atomic_write(rtl_dir / "retrosoc_asic_pad_bindings.svh", render_pad_bindings(pads)) + atomic_write( + rtl_dir / "retrosoc_asic_pad_bindings.svh", render_pad_bindings(pads, power_counts) + ) atomic_write(rtl_dir / "retrosoc_core_ports.svh", render_core_ports(pads)) atomic_write(rtl_dir / "retrosoc_core_bindings.svh", render_core_bindings(pads)) for profile, bindings in profiles.items(): diff --git a/rtl/mini/script/prepare_norflash.py b/scripts/rtl/prepare_norflash.py similarity index 98% rename from rtl/mini/script/prepare_norflash.py rename to scripts/rtl/prepare_norflash.py index 5f42126e..536bbd4a 100644 --- a/rtl/mini/script/prepare_norflash.py +++ b/scripts/rtl/prepare_norflash.py @@ -9,7 +9,7 @@ from pathlib import Path SCRIPT_DIR = Path(__file__).resolve().parent MINI_DIR = SCRIPT_DIR.parent -ROOT_DIR = MINI_DIR.parent.parent +ROOT_DIR = SCRIPT_DIR.parents[1] DEFAULT_MODELS = ROOT_DIR / "rtl" / "managed" / "third_party" / "norflash" DEFAULT_FIRMWARE = ROOT_DIR / ".sw_build" / "retrosoc_fw.hex" diff --git a/scripts/run_apu_p5_corpus_rtl.py b/scripts/run_apu_p5_corpus_rtl.py index 03889e83..40720cbf 100644 --- a/scripts/run_apu_p5_corpus_rtl.py +++ b/scripts/run_apu_p5_corpus_rtl.py @@ -194,7 +194,7 @@ def _compile(build_dir: Path, bundle: Path) -> tuple[dict[str, Path], dict[str, conversion = _run_command( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", diff --git a/scripts/run_apu_p7_concurrent_rtl.py b/scripts/run_apu_p7_concurrent_rtl.py index f93bc999..e743f9ca 100644 --- a/scripts/run_apu_p7_concurrent_rtl.py +++ b/scripts/run_apu_p7_concurrent_rtl.py @@ -217,7 +217,7 @@ def _verification_sources() -> dict[str, str]: ROOT / "scripts/apu_codecs.py", ROOT / "scripts/apu_kws.py", ROOT / "scripts/apu_kws_convert.py", - ROOT / "rtl/mini/script/convt_sv2v.py", + ROOT / "scripts/rtl/convt_sv2v.py", Path(__file__).resolve(), ] return { @@ -346,7 +346,7 @@ def _compile(build_dir: Path) -> dict[str, Any]: conversion = _run_command( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", diff --git a/scripts/run_apu_p7_kws_rtl.py b/scripts/run_apu_p7_kws_rtl.py index e5e5d601..01004a4a 100644 --- a/scripts/run_apu_p7_kws_rtl.py +++ b/scripts/run_apu_p7_kws_rtl.py @@ -303,7 +303,7 @@ def _compile(build_dir: Path, simulator: str) -> dict[str, Any]: conversion = _run_command( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", diff --git a/scripts/run_c_tests.py b/scripts/run_c_tests.py index 2b049f6b..dcb18307 100644 --- a/scripts/run_c_tests.py +++ b/scripts/run_c_tests.py @@ -73,7 +73,7 @@ def main() -> int: subprocess.run( [ sys.executable, - str(root / "rtl/mini/address_map/generate_memory_map.py"), + str(root / "scripts/rtl/generate_memory_map.py"), "--map", str(root / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -131,6 +131,17 @@ def main() -> int: str(executable), *(str(root / source) for source in TEST_SOURCES), ] + tiny_object = temporary_root / "tiny_dma_math.o" + subprocess.run([ + compiler, "-std=c11", "-Wall", "-Wextra", "-Werror", "-DRS_SOC_TINY", + "-Drs_dma_config_validate=rs_tiny_dma_config_validate", + "-Drs_dma_tcd_validate=rs_tiny_dma_tcd_validate", + "-I", str(memory_map_root / "include"), + "-I", str(user_extensions_root / "include"), + "-I", str(root / "crt/include"), "-c", str(root / "crt/src/hal/dma_math.c"), + "-o", str(tiny_object), + ], check=True) + command.append(str(tiny_object)) subprocess.run(command, check=True) subprocess.run([str(executable)], check=True) return 0 diff --git a/scripts/setup_tiny.py b/scripts/setup_tiny.py new file mode 100644 index 00000000..57235911 --- /dev/null +++ b/scripts/setup_tiny.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 +"""Prepare only the locked inputs used by the Tiny MCU.""" + +from __future__ import annotations + +import argparse +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +sys.path.insert(0, str(ROOT)) +from scripts.dependency_lock import source # noqa: E402 +from scripts.setup_helpers import ensure_git_repo # noqa: E402 + +TINY_SOURCES = ( + "hazard3", "cluster_common", "cluster_archinfo", "cluster_pwm", + "cluster_rtc", "cluster_wdg", "pdk_ihp130", +) + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--update", action="store_true") + args = parser.parse_args() + for name in TINY_SOURCES: + dependency = source(name) + ensure_git_repo( + dependency["url"], ROOT / dependency["destination"], dependency["revision"], + recursive=dependency.get("recursive", False), update=args.update, + ) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tests/c/test_runtime.c b/tests/c/test_runtime.c index 70968b6c..0f92a5b0 100644 --- a/tests/c/test_runtime.c +++ b/tests/c/test_runtime.c @@ -739,6 +739,41 @@ static int test_gpio_helpers(void) { return 0; } +/* The runner compiles the same validator with Tiny's capability selection. */ +rs_status_t rs_tiny_dma_config_validate(uint32_t channel, const rs_dma_config_t *config); +rs_status_t rs_tiny_dma_tcd_validate(uint32_t channel, const rs_dma_tcd_t *tcd); + +static int test_tiny_dma_config_validation(void) { + rs_dma_config_t config = { + .kind = RS_DMA_KIND_MM_TO_MM, .request = RS_DMA_REQUEST_SOFTWARE, + .source = (uintptr_t)UINT32_C(0x30000000), + .destination = (uintptr_t)UINT32_C(0x30001000), .byte_count = 259U, + .width = RS_DMA_WIDTH_32, .source_increment = true, .destination_increment = true, + .burst_beats = 16U, + }; + static _Alignas(64) rs_dma_tcd_t descriptor; + if ((rs_tiny_dma_config_validate(3U, &config) != RS_OK) || + (rs_tiny_dma_config_validate(4U, &config) != RS_EINVAL)) { + return 1; + } + config.kind = RS_DMA_KIND_MM_TO_STREAM; + config.request = RS_DMA_REQUEST_I2S_TX; + config.byte_count = 256U; + if (rs_tiny_dma_config_validate(0U, &config) != RS_EINVAL) { + return 2; + } + descriptor.source = UINT32_C(0x30000000); + descriptor.byte_count = 256U; + descriptor.y_count = 1U; + descriptor.control = RS_DMA_TCD_VALID | RS_DMA_TCD_SRC_INC | + ((uint32_t)RS_DMA_KIND_MM_TO_STREAM << RS_DMA_TCD_KIND_SHIFT) | + ((uint32_t)RS_DMA_REQUEST_I2S_TX << RS_DMA_TCD_REQUEST_SHIFT); + if (rs_tiny_dma_tcd_validate(0U, &descriptor) != RS_ENOTSUP) { + return 3; + } + return 0; +} + static int test_dma_config_validation(void) { static rs_dma_tcd_t tcd __attribute__((aligned(64))); rs_dma_config_t config = { @@ -2703,6 +2738,7 @@ int main(void) { test_spisd_helpers(), test_gpio_helpers(), test_dma_config_validation(), + test_tiny_dma_config_validation(), test_opipsram_helpers(), test_user_ip_validation(), test_extension_validation(), diff --git a/tests/rtl/tiny_axi4_fabric_tb.sv b/tests/rtl/tiny_axi4_fabric_tb.sv new file mode 100644 index 00000000..58f0cff4 --- /dev/null +++ b/tests/rtl/tiny_axi4_fabric_tb.sv @@ -0,0 +1,277 @@ +`timescale 1ns / 1ps +module tiny_axi4_fabric_tb; + logic clk_i = 0; + logic rst_n_i = 0; + always #5 clk_i = !clk_i; + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) masters[2] ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + axi4_if #( + .ADDR_WIDTH(32), + .DATA_WIDTH(32), + .ID_WIDTH (1), + .USER_WIDTH(1) + ) targets[5] ( + .aclk (clk_i), + .aresetn(rst_n_i) + ); + logic fault_valid, fault_master, fault_write; + logic [31:0] fault_addr; + logic [ 1:0] fault_resp; + logic [63:0] cpu_wait, dma_wait; + integer faults = 0; + integer completions [2]; + integer target_requests[5]; + logic [1:0][31:0] awaddr; + logic [1:0][ 7:0] awlen; + logic [1:0][ 2:0] awsize; + logic [1:0][ 1:0] awburst; + logic [1:0][ 0:0] awlock; + logic [1:0][ 0:0] awid; + logic [1:0][ 0:0] awvalid; + logic [1:0][31:0] wdata; + logic [1:0][ 3:0] wstrb; + logic [1:0][ 0:0] wlast; + logic [1:0][ 0:0] wvalid; + logic [1:0][ 0:0] bready; + logic [1:0][31:0] araddr; + logic [1:0][ 7:0] arlen; + logic [1:0][ 2:0] arsize; + logic [1:0][ 1:0] arburst; + logic [1:0][ 0:0] arlock; + logic [1:0][ 0:0] arid; + logic [1:0][ 0:0] arvalid; + logic [1:0][ 0:0] rready; + logic [1:0][ 0:0] awready; + logic [1:0][ 0:0] arready; + logic [1:0][ 0:0] wready; + logic [1:0][ 0:0] bvalid; + logic [1:0][ 0:0] bid; + logic [1:0][ 1:0] bresp; + logic [1:0][ 0:0] rvalid; + logic [1:0][ 0:0] rid; + logic [1:0][ 0:0] rlast; + logic [1:0][31:0] rdata; + logic [1:0][ 1:0] rresp; + tiny_axi4_fabric u_dut ( + .clk_i (clk_i), + .rst_n_i (rst_n_i), + .perf_enable_i (1'b1), + .perf_clear_i (1'b0), + .masters (masters), + .targets (targets), + .fault_valid_o (fault_valid), + .fault_addr_o (fault_addr), + .fault_master_o(fault_master), + .fault_write_o (fault_write), + .fault_resp_o (fault_resp), + .cpu_wait_o (cpu_wait), + .dma_wait_o (dma_wait) + ); + always @(posedge clk_i) if (fault_valid) faults <= faults + 1; + for (genvar m = 0; m < 2; m++) begin : gen_master + assign masters[m].awaddr = awaddr[m]; + assign masters[m].awlen = awlen[m]; + assign masters[m].awsize = awsize[m]; + assign masters[m].awburst = awburst[m]; + assign masters[m].awlock = awlock[m]; + assign masters[m].awid = awid[m]; + assign masters[m].awvalid = awvalid[m]; + assign masters[m].wdata = wdata[m]; + assign masters[m].wstrb = wstrb[m]; + assign masters[m].wlast = wlast[m]; + assign masters[m].wvalid = wvalid[m]; + assign masters[m].bready = bready[m]; + assign masters[m].araddr = araddr[m]; + assign masters[m].arlen = arlen[m]; + assign masters[m].arsize = arsize[m]; + assign masters[m].arburst = arburst[m]; + assign masters[m].arlock = arlock[m]; + assign masters[m].arid = arid[m]; + assign masters[m].arvalid = arvalid[m]; + assign masters[m].rready = rready[m]; + assign awready[m] = masters[m].awready; + assign arready[m] = masters[m].arready; + assign wready[m] = masters[m].wready; + assign bvalid[m] = masters[m].bvalid; + assign bid[m] = masters[m].bid; + assign bresp[m] = masters[m].bresp; + assign rvalid[m] = masters[m].rvalid; + assign rid[m] = masters[m].rid; + assign rlast[m] = masters[m].rlast; + assign rdata[m] = masters[m].rdata; + assign rresp[m] = masters[m].rresp; + assign masters[m].awcache = '0; + assign masters[m].awprot = '0; + assign masters[m].awqos = '0; + assign masters[m].awregion = '0; + assign masters[m].awuser = '0; + assign masters[m].arcache = '0; + assign masters[m].arprot = '0; + assign masters[m].arqos = '0; + assign masters[m].arregion = '0; + assign masters[m].aruser = '0; + assign masters[m].wuser = '0; + end + for (genvar t = 0; t < 5; t++) begin : gen_target + // Deterministic terminal responder allows independent checks of routing, + // burst length and ID preservation without sharing the fabric decoder. + axi4_error_slave #( + .Response(t == 3 ? 2'b11 : (t == 4 ? 2'b10 : 2'b00)) + ) u_response ( + .clk_i (clk_i), + .rst_n_i(rst_n_i), + .axi4 (targets[t]) + ); + initial target_requests[t] = 0; + always @(posedge clk_i) begin + if ((targets[t].arvalid && targets[t].arready) || (targets[t].awvalid && targets[t].awready)) + target_requests[t] <= target_requests[t] + 1; + end + end + task automatic read_request(input int m, input logic [31:0] addr, input int beats, + input logic [2:0] size, input logic [1:0] burst, + input logic [1:0] expected); + logic [35:0] held; + @(negedge clk_i); + araddr[m] = addr; + arlen[m] = 8'(beats - 1); + arsize[m] = size; + arburst[m] = burst; + arid[m] = 1'(m); + arvalid[m] = 1; + do @(posedge clk_i); while (!arready[m]); + @(negedge clk_i); + arvalid[m] = 0; + for (int beat = 0; beat < beats; beat++) begin + do @(posedge clk_i); while (!rvalid[m]); + held = {rid[m], rlast[m], rresp[m], rdata[m]}; + repeat (3) begin + @(negedge clk_i); + if (!rvalid[m] || held != {rid[m], rlast[m], rresp[m], rdata[m]}) + $fatal(1, "read changed under backpressure"); + end + if (rresp[m] != expected || rid[m] != 1'(m) || rlast[m] != (beat == beats - 1)) + $fatal( + 1, + "read response/ID/length mismatch m=%0d addr=%x beat=%0d resp=%0d", + m, + addr, + beat, + rresp[m] + ); + rready[m] = 1; + @(posedge clk_i); + @(negedge clk_i); + rready[m] = 0; + end + completions[m]++; + endtask + task automatic write_request(input int m, input logic [31:0] addr, input int beats, + input logic [1:0] expected, input bit early_w); + @(negedge clk_i); + awaddr[m] = addr; + awlen[m] = 8'(beats - 1); + awsize[m] = 2; + awburst[m] = 1; + awid[m] = 1'(m); + wdata[m] = 32'h12345678; + wstrb[m] = 4'b0101; + wlast[m] = (beats == 1); + if (early_w) begin + wvalid[m] = 1; + repeat (4) begin + @(posedge clk_i); + if (wready[m]) $fatal(1, "W accepted before AW"); + end + @(negedge clk_i); + end + awvalid[m] = 1; + do @(posedge clk_i); while (!awready[m]); + @(negedge clk_i); + awvalid[m] = 0; + if (!early_w) repeat (5) @(negedge clk_i); + for (int beat = 0; beat < beats; beat++) begin + wvalid[m] = 1; + wlast[m] = (beat == beats - 1); + wdata[m] = 32'(beat); + do @(posedge clk_i); while (!wready[m]); + @(negedge clk_i); + wvalid[m] = 0; + repeat (2) @(negedge clk_i); + end + do @(posedge clk_i); while (!bvalid[m]); + repeat (3) begin + @(negedge clk_i); + if (!bvalid[m] || bresp[m] != expected || bid[m] != 1'(m)) + $fatal(1, "write response mismatch"); + end + bready[m] = 1; + @(posedge clk_i); + @(negedge clk_i); + bready[m] = 0; + completions[m]++; + endtask + initial begin + awaddr = '0; + awlen = '0; + awsize = '0; + awburst = '0; + awlock = '0; + awid = '0; + awvalid = '0; + wdata = '0; + wstrb = '0; + wlast = '0; + wvalid = '0; + bready = '0; + araddr = '0; + arlen = '0; + arsize = '0; + arburst = '0; + arlock = '0; + arid = '0; + arvalid = '0; + rready = '0; + completions[0] = 0; + completions[1] = 0; + repeat (5) @(negedge clk_i); + rst_n_i = 1; + fork + begin + write_request(0, 32'h30000000, 16, 0, 1); + read_request(0, 32'h30000000, 16, 2, 1, 0); + read_request(0, 32'h38000000, 4, 2, 1, 3); + read_request(0, 32'h30000ffc, 2, 2, 1, 2); + read_request(0, 32'h30000001, 1, 2, 1, 2); + read_request(0, 32'h10001000, 2, 2, 1, 2); + read_request(0, 32'h30000000, 4, 2, 2, 2); + end + begin + read_request(1, 32'h50000000, 4, 2, 1, 0); + write_request(1, 32'h10001000, 1, 0, 0); + write_request(1, 32'h38000000, 3, 3, 1); + read_request(1, 32'h10001000, 1, 2, 0, 0); + read_request(1, 32'h3001ffff, 1, 0, 1, 0); + read_request(1, 32'h30020000, 1, 2, 1, 3); + end + join + if (completions[0]!=7 || completions[1]!=6 || faults!=7 || + target_requests[0]!=3 || target_requests[1]!=1 || target_requests[2]!=2 || + target_requests[3]!=3 || target_requests[4]!=4 || cpu_wait==0 || dma_wait==0) + $fatal(1, "accounting/fairness mismatch faults=%0d", faults); + read_request(0, 32'h30000000, 1, 2, 1, 0); + $display("SIM_TEST_PASS Tiny fabric"); + $finish; + end + initial begin + repeat (20000) @(posedge clk_i); + $fatal(1, "SIM_TEST_TIMEOUT Tiny fabric"); + end +endmodule diff --git a/tests/rtl/tiny_sysctrl_tb.sv b/tests/rtl/tiny_sysctrl_tb.sv new file mode 100644 index 00000000..39433bdd --- /dev/null +++ b/tests/rtl/tiny_sysctrl_tb.sv @@ -0,0 +1,96 @@ +`timescale 1ns / 1ps +`include "sysctrl_define.svh" + +module tiny_sysctrl_tb; + logic clk_i = 0; + logic rst_n_i = 0; + always #5 clk_i = !clk_i; + apb4_if apb4 ( + .pclk (clk_i), + .presetn(rst_n_i) + ); + logic fault_valid = 0; + logic [31:0] fault_addr = 32'h38000000; + logic [63:0] cpu_wait = 64'h123456789abcdef0; + logic [63:0] dma_wait = 64'h1122334455667788; + logic wake = 0; + logic perf_enable, perf_clear, done, pass; + logic [ 7:0] code; + logic [31:0] value; + tiny_sysctrl u_dut ( + .clk_i (clk_i), + .rst_n_i (rst_n_i), + .apb4 (apb4), + .fault_valid_i (fault_valid), + .fault_addr_i (fault_addr), + .fault_write_i (1'b1), + .fault_master_i(1'b1), + .fault_resp_i (2'b11), + .cpu_wait_i (cpu_wait), + .dma_wait_i (dma_wait), + .rtc_wake_i (wake), + .perf_enable_o (perf_enable), + .perf_clear_o (perf_clear), + .test_done_o (done), + .test_pass_o (pass), + .test_code_o (code) + ); + `include "apb4_bfm.svh" + initial begin + apb4_idle(); + repeat (5) @(negedge clk_i); + rst_n_i = 1; + apb4_write(`APB4_SYSCTRL__HP_CTRL, 1, 4'hf, 1); + apb4_write(`APB4_SYSCTRL__PLL_CMD, 1, 4'hf, 1); + apb4_read(32'hfff, 1, value); + apb4_write(`APB4_SYSCTRL__TEST_STATUS, 32'h80001201, 4'h1, 1); + if (done) $fatal(1, "partial terminal write changed state"); + apb4_write(`APB4_SYSCTRL__TEST_STATUS, 32'h00001201, 4'hf, 0); + if (done) $fatal(1, "invalid terminal write changed state"); + apb4_write(`APB4_SYSCTRL__TEST_STATUS, 32'h80001201, 4'hf, 0); + apb4_write(`APB4_SYSCTRL__TEST_STATUS, 32'h80009900, 4'hf, 0); + if (!done || !pass || code != 8'h12) $fatal(1, "terminal status is not sticky"); + apb4_write(`APB4_SYSCTRL__PERF_CTRL, 5, 4'hf, 0); + cpu_wait = 0; + dma_wait = 0; + apb4_read(`APB4_SYSCTRL__PERF_MGMT_WAIT_LO, 0, value); + if (!perf_enable || value != 32'h9abcdef0) $fatal(1, "CPU snapshot changed"); + apb4_read(`APB4_SYSCTRL__PERF_DMA_WAIT_HI, 0, value); + if (value != 32'h11223344) $fatal(1, "DMA snapshot changed"); + @(negedge clk_i); + fault_valid = 1; + @(negedge clk_i); + fault_valid = 0; + fault_addr = 32'hffffffff; + @(negedge clk_i); + fault_valid = 1; + @(negedge clk_i); + fault_valid = 0; + apb4_read(`APB4_SYSCTRL__FAULT_ADDR, 0, value); + if (value != 32'h38000000) $fatal(1, "first fault overwritten"); + apb4_read(`APB4_SYSCTRL__FAULT_COUNT, 0, value); + if (value != 2) $fatal(1, "fault count mismatch"); + apb4_write(`APB4_SYSCTRL__FAULT_STATUS, 1, 4'hf, 0); + apb4_read(`APB4_SYSCTRL__FAULT_STATUS, 0, value); + if (value[0]) $fatal(1, "fault W1C failed"); + @(negedge clk_i); + wake = 1; + @(negedge clk_i); + wake = 0; + apb4_read(`APB4_SYSCTRL__RTC_WAKE_STATUS, 0, value); + if (value != 2) $fatal(1, "RTC sticky wake missing"); + apb4_write(`APB4_SYSCTRL__RTC_WAKE_STATUS, 2, 4'hf, 0); + apb4_read(`APB4_SYSCTRL__RTC_WAKE_STATUS, 0, value); + if (value != 0) $fatal(1, "RTC wake W1C failed"); + @(negedge clk_i); + rst_n_i = 0; + repeat (3) @(negedge clk_i); + if (done || perf_enable) $fatal(1, "reset failed"); + $display("SIM_TEST_PASS Tiny SYSCTRL"); + $finish; + end + initial begin + #100000; + $fatal(1, "SIM_TEST_TIMEOUT Tiny SYSCTRL"); + end +endmodule diff --git a/tests/test_apu.py b/tests/test_apu.py index 59e66f09..3706a8f8 100644 --- a/tests/test_apu.py +++ b/tests/test_apu.py @@ -121,7 +121,7 @@ def test_apu_p1_apb_register_shell(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -238,7 +238,7 @@ def test_apu_p1_integrated_irq_ownership_topology(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -530,7 +530,7 @@ last: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -658,7 +658,7 @@ done: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -747,7 +747,7 @@ def test_apu_p2_stream_router(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -801,7 +801,7 @@ def test_apu_p2_private_dma(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -846,7 +846,7 @@ def test_apu_p2_ring_scheduler_backend(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -904,7 +904,7 @@ def test_apu_p2_integrated_dma_ring_backend(tmp_path: Path) -> None: str(ROOT / "rtl/ip/peripheral/dma_axi4_master.sv"), str(multimedia / "apu_dma.sv"), str(multimedia / "apu_ring_scheduler.sv"), - str(ROOT / "rtl/mini/top/soc_common_cdc.sv"), + str(ROOT / "rtl/ip/util/soc_common_cdc.sv"), str(ROOT / "rtl/mini/top/axi4_async_bridge.sv"), str(ROOT / "rtl/mini/top/axi4_target_guard.sv"), str(ROOT / "rtl/mini/top/hp_axi4_mux3.sv"), @@ -919,7 +919,7 @@ def test_apu_p2_integrated_dma_ring_backend(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -972,7 +972,7 @@ def test_apu_p2_gateway_a_round_robin_fairness(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -1039,7 +1039,7 @@ def test_apu_p7_kws_engine_directed(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -1151,7 +1151,7 @@ def test_apu_p7_kws_sram_layout_and_isolation(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -1202,7 +1202,7 @@ def test_apu_p7_kws_job_lifecycle(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -1242,7 +1242,7 @@ def test_apu_p7_kws_loader_admission_and_abort(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_apu_codec_transport.py b/tests/test_apu_codec_transport.py index df30cf02..66332fe5 100644 --- a/tests/test_apu_codec_transport.py +++ b/tests/test_apu_codec_transport.py @@ -350,7 +350,7 @@ def test_p5_production_transport_matches_icarus_and_verilator(tmp_path: Path) -> subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", @@ -508,7 +508,7 @@ def test_p5_v2_4096_word_loader_store_and_sequencer(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", @@ -705,7 +705,7 @@ def test_p5_direct_wav_uses_product_loader_dma_sequencer_and_tx(tmp_path: Path) subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", diff --git a/tests/test_apu_kws_frontend.py b/tests/test_apu_kws_frontend.py index 0e09476e..371384c5 100644 --- a/tests/test_apu_kws_frontend.py +++ b/tests/test_apu_kws_frontend.py @@ -148,7 +148,7 @@ def _compile_dump_tb(build_dir: Path) -> dict[str, Path | None]: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", diff --git a/tests/test_apu_p8_contention.py b/tests/test_apu_p8_contention.py index 475a4136..39ba8039 100644 --- a/tests/test_apu_p8_contention.py +++ b/tests/test_apu_p8_contention.py @@ -41,7 +41,7 @@ def test_apu_p8_gateway_a_contention(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_apu_p8_quiesce_load.py b/tests/test_apu_p8_quiesce_load.py index 523572d7..f9c1a0f3 100644 --- a/tests/test_apu_p8_quiesce_load.py +++ b/tests/test_apu_p8_quiesce_load.py @@ -114,7 +114,7 @@ def test_apu_p8_quiesced_loader_admission(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_apu_p9_storage.py b/tests/test_apu_p9_storage.py index 87e642a1..531d25ca 100644 --- a/tests/test_apu_p9_storage.py +++ b/tests/test_apu_p9_storage.py @@ -67,7 +67,7 @@ def test_apu_p9_coefficient_store_and_proof_memo(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_apu_primitives.py b/tests/test_apu_primitives.py index 793f2f5a..7ef31499 100644 --- a/tests/test_apu_primitives.py +++ b/tests/test_apu_primitives.py @@ -1279,7 +1279,7 @@ def test_p4_production_primitives_icarus_and_verilator(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -1404,7 +1404,7 @@ def test_p4_loader_publishes_control_and_table_atomically(tmp_path: Path) -> Non subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -1457,7 +1457,7 @@ def test_p4_sequencer_kernel_pending_and_wait(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_axi4.py b/tests/test_axi4.py index 1a61c8ff..8a8f85f3 100644 --- a/tests/test_axi4.py +++ b/tests/test_axi4.py @@ -76,7 +76,7 @@ def test_axi4_async_bridge_transfers_and_warm_flushes(tmp_path: Path) -> None: str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv"), - str(ROOT / "rtl/mini/top/soc_common_cdc.sv"), + str(ROOT / "rtl/ip/util/soc_common_cdc.sv"), str(ROOT / "rtl/mini/top/axi4_async_bridge.sv"), str(ROOT / "tests/rtl/axi4_async_bridge_tb.sv"), "-Mdir", str(tmp_path / "obj"), "-o", str(output), @@ -187,7 +187,7 @@ def test_axi4_interconnect_classifies_decode_protocol_and_access_errors( subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -217,7 +217,7 @@ def test_axi4_interconnect_classifies_decode_protocol_and_access_errors( str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/stream/round_robin_arbiter.sv"), str(ROOT / "rtl/mini/top/axi4_interconnect.sv"), - str(ROOT / "rtl/mini/top/axi4_error_slave.sv"), + str(ROOT / "rtl/ip/interconnect/axi4_error_slave.sv"), str(ROOT / "tests/rtl/axi4_interconnect_tb.sv"), "-Mdir", str(tmp_path / "obj"), @@ -246,7 +246,7 @@ def test_axi4_data_crossbar_supports_cross_target_outstanding_and_acl(tmp_path: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", diff --git a/tests/test_axi4_hp_postfault.py b/tests/test_axi4_hp_postfault.py index cda280d3..97349bff 100644 --- a/tests/test_axi4_hp_postfault.py +++ b/tests/test_axi4_hp_postfault.py @@ -21,7 +21,7 @@ def test_axi4_interconnect_hp_postfault_visibility(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -51,7 +51,7 @@ def test_axi4_interconnect_hp_postfault_visibility(tmp_path: Path) -> None: str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/stream/round_robin_arbiter.sv"), str(ROOT / "rtl/mini/top/axi4_interconnect.sv"), - str(ROOT / "rtl/mini/top/axi4_error_slave.sv"), + str(ROOT / "rtl/ip/interconnect/axi4_error_slave.sv"), str(ROOT / "tests/rtl/axi4_interconnect_hp_postfault_tb.sv"), "-Mdir", str(tmp_path / "obj"), diff --git a/tests/test_clint.py b/tests/test_clint.py index 5cd22e33..f7721a07 100644 --- a/tests/test_clint.py +++ b/tests/test_clint.py @@ -49,7 +49,7 @@ def test_clint_standard_map_multi_hart_and_timebase(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_crypto.py b/tests/test_crypto.py index 6b5385af..e35389c7 100644 --- a/tests/test_crypto.py +++ b/tests/test_crypto.py @@ -124,7 +124,7 @@ def test_crypto_apb_register_path(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_dma.py b/tests/test_dma.py index 0c19cd0b..49db77df 100644 --- a/tests/test_dma.py +++ b/tests/test_dma.py @@ -21,7 +21,7 @@ def test_dma_reports_native_axi4_errors_bursts_and_streams(tmp_path: Path) -> No subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -61,7 +61,7 @@ def test_dma_reports_native_axi4_errors_bursts_and_streams(tmp_path: Path) -> No subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -88,7 +88,7 @@ def test_dma_apb_registers_and_irq(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -130,7 +130,7 @@ def test_dma_apb_registers_and_irq(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -157,7 +157,7 @@ def test_dma_crypto_stream_endpoints(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -195,7 +195,7 @@ def test_dma_crypto_stream_endpoints(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_dvp.py b/tests/test_dvp.py index f910b0c9..9123a7df 100644 --- a/tests/test_dvp.py +++ b/tests/test_dvp.py @@ -54,7 +54,7 @@ def test_dvp_capture_framing(tmp_path: Path) -> None: source_list.write_text("\n".join([*defines, *source, ""]), encoding="utf-8") converted = tmp_path / "dvp.v" subprocess.run( - [sys.executable, str(ROOT / "rtl/mini/script/convt_sv2v.py"), "-f", str(source_list), "--output", str(converted)], + [sys.executable, str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", str(converted)], check=True, ) simulation = tmp_path / "dvp_tb" diff --git a/tests/test_ga2d.py b/tests/test_ga2d.py index 427d1c94..ce261b16 100644 --- a/tests/test_ga2d.py +++ b/tests/test_ga2d.py @@ -26,7 +26,7 @@ def _generate_memory_map(tmp_path: Path) -> Path: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -122,7 +122,7 @@ def _run_iverilog_test( subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_ga2d_platform.py b/tests/test_ga2d_platform.py index 56b84257..7854314c 100644 --- a/tests/test_ga2d_platform.py +++ b/tests/test_ga2d_platform.py @@ -111,7 +111,7 @@ def test_ga2d_p5_preserves_p2_bridge_prefix_lifecycle_and_recovery(tmp_path: Pat subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -156,8 +156,8 @@ def test_ga2d_p5_preserves_p2_bridge_prefix_lifecycle_and_recovery(tmp_path: Pat str(common / "cdc/cdc_rst_ctrlr.sv"), str(common / "cdc/cdc_2phase.sv"), str(common / "clkrst/rst_sync.sv"), - str(top / "soc_common_cdc.sv"), - str(top / "axi4_connector.sv"), + str(ROOT / "rtl/ip/util/soc_common_cdc.sv"), + str(ROOT / "rtl/ip/interconnect/axi4_connector.sv"), str(top / "axi4_master_idle.sv"), str(top / "axi4_async_bridge.sv"), str(top / "axi4_address_gate.sv"), @@ -166,7 +166,7 @@ def test_ga2d_p5_preserves_p2_bridge_prefix_lifecycle_and_recovery(tmp_path: Pat str(top / "axi4_data_crossbar.sv"), str(top / "axi4_target_guard.sv"), str(top / "fabric_monitor.sv"), - str(top / "axi4_error_slave.sv"), + str(ROOT / "rtl/ip/interconnect/axi4_error_slave.sv"), str(top / "axi4_downsizer_64to32.sv"), str(top / "hp_axi4_mux3.sv"), str(top / "soc_data_plane.sv"), diff --git a/tests/test_gpio.py b/tests/test_gpio.py index 8f9e1b91..65a5fa6d 100644 --- a/tests/test_gpio.py +++ b/tests/test_gpio.py @@ -47,7 +47,7 @@ def test_gpio_register_pad_interrupt_and_filter_contract(tmp_path: Path) -> None subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_hp_mailbox.py b/tests/test_hp_mailbox.py index 89304742..953757a9 100644 --- a/tests/test_hp_mailbox.py +++ b/tests/test_hp_mailbox.py @@ -39,7 +39,7 @@ def test_hp_mailbox_registers_and_doorbells(tmp_path: Path) -> None: ) converted = tmp_path / "hp_mailbox_tb.v" subprocess.run( - [sys.executable, str(ROOT / "rtl/mini/script/convt_sv2v.py"), "-f", str(filelist), + [sys.executable, str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", str(converted)], check=True, ) diff --git a/tests/test_i2c.py b/tests/test_i2c.py index f69b6ae9..96df868c 100644 --- a/tests/test_i2c.py +++ b/tests/test_i2c.py @@ -48,7 +48,7 @@ def test_i2c_controller_and_recovery_contract(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_i2s.py b/tests/test_i2s.py index 129c0174..854ca05b 100644 --- a/tests/test_i2s.py +++ b/tests/test_i2s.py @@ -58,7 +58,7 @@ def test_i2s_controller_abi_and_clocking(tmp_path: Path) -> None: source_list.write_text("\n".join([*defines, *source, ""]), encoding="utf-8") converted = tmp_path / "i2s.v" subprocess.run( - [sys.executable, str(ROOT / "rtl/mini/script/convt_sv2v.py"), "-f", str(source_list), "--output", str(converted)], + [sys.executable, str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", str(converted)], check=True, ) simulation = tmp_path / "i2s_tb" diff --git a/tests/test_jpeg.py b/tests/test_jpeg.py index 148991c0..f58c9ea6 100644 --- a/tests/test_jpeg.py +++ b/tests/test_jpeg.py @@ -182,7 +182,7 @@ def test_jpeg_apb_register_path(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -226,7 +226,7 @@ def test_jpeg_2d_axi_dma(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -302,7 +302,7 @@ def test_jpeg_apb_ring_descriptor_path(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -410,7 +410,7 @@ def test_jpeg_byte_unpacker_and_bit_reader(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -590,7 +590,7 @@ def test_jpeg_mcu_reconstructor(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -640,7 +640,7 @@ def test_jpeg_mcu_builder(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -754,7 +754,7 @@ def test_jpeg_byte_joiner(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -847,7 +847,7 @@ def test_jpeg_encode_core_complete_file(tmp_path: Path) -> None: ) converted = tmp_path / "jpeg_encode_core_tb.v" subprocess.run( - [sys.executable, str(ROOT / "rtl/mini/script/convt_sv2v.py"), "-f", str(source_list), + [sys.executable, str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", str(converted)], check=True, ) @@ -943,7 +943,7 @@ def test_jpeg_decode_core_complete_file(tmp_path: Path) -> None: ) converted = tmp_path / "jpeg_decode_core_tb.v" subprocess.run( - [sys.executable, str(ROOT / "rtl/mini/script/convt_sv2v.py"), "-f", str(source_list), + [sys.executable, str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", str(converted)], check=True, ) diff --git a/tests/test_librelane_flow.py b/tests/test_librelane_flow.py index 4c48877d..521dfcd5 100644 --- a/tests/test_librelane_flow.py +++ b/tests/test_librelane_flow.py @@ -12,7 +12,7 @@ from types import SimpleNamespace ROOT = Path(__file__).resolve().parents[1] PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json" DOMAINS = ROOT / "rtl/mini/integration/clock_reset_domains.json" -FLOW_ROOT = ROOT / "physical/librelane" +FLOW_ROOT = ROOT / "physical/librelane/mini" def load_module(name: str, path: Path): @@ -83,11 +83,11 @@ def test_chip_config_places_every_signal_and_power_pad_once(tmp_path: Path) -> N assert config["EXTRA_EXCLUDED_CELLS"] == ["sg13g2_IOPad*"] assert config["VDD_NETS"] == ["VDD"] assert config["GND_NETS"] == ["VSS"] - assert config["PAD_CFG"].endswith("physical/librelane/pad_cfg.tcl") + assert config["PAD_CFG"].endswith("physical/librelane/mini/pad_cfg.tcl") assert config["PDN_ENABLE_PINS"] is True assert config["ERROR_ON_PDN_VIOLATIONS"] is True assert config["STA_EXTRA_CORNER_TCL_FILE"].endswith( - "physical/librelane/sta_report_limit.tcl" + "physical/librelane/mini/sta_report_limit.tcl" ) assert set(config["MACROS"]) == { "RM_IHPSG13_1P_4096x16_c3_bm_bist", @@ -200,7 +200,7 @@ def test_librelane_flow_exposes_core_and_chip_targets() -> None: assert "--skip OpenROAD.STAMidPNR" in makefile assert "--librelane-safe" in makefile assert "librelane-all" not in makefile - assert "include physical/librelane/Makefile" in top_makefile + assert "include physical/librelane/mini/Makefile" in top_makefile ihp_filelist = (ROOT / "rtl/filelist/pdk_ihp130.fl").read_text(encoding="utf-8") assert ihp_filelist.index("sg13g2_udp.v") < ihp_filelist.index("sg13g2_stdcell.v") assert lock["sources"]["pdk_ihp130"]["revision"] == ("970a7688e7dcce2a6172797df9ef47bde2f60f9f") @@ -209,7 +209,7 @@ def test_librelane_flow_exposes_core_and_chip_targets() -> None: def test_bondpad_lef_matches_the_generated_master_contract() -> None: - lef = (FLOW_ROOT / "bondpad/bondpad_70x70.lef").read_text(encoding="utf-8") + lef = (ROOT / "physical/librelane/bondpad/bondpad_70x70.lef").read_text(encoding="utf-8") assert "MACRO bondpad_70x70" in lef assert "CLASS COVER" in lef diff --git a/tests/test_librelane_tiny_flow.py b/tests/test_librelane_tiny_flow.py new file mode 100644 index 00000000..fd2da88f --- /dev/null +++ b/tests/test_librelane_tiny_flow.py @@ -0,0 +1,175 @@ +"""Tests for the Tiny IHP130 LibreLane chip flow.""" + +from __future__ import annotations + +import importlib.util +import re +from pathlib import Path +from types import SimpleNamespace + + +ROOT = Path(__file__).resolve().parents[1] +PIN_MAP = ROOT / "rtl/tiny/pin_map/pin_map.json" +DOMAINS = ROOT / "rtl/tiny/integration/clock_reset_domains.json" +FLOW_ROOT = ROOT / "physical/librelane/tiny" +BONDPAD_LEF = ROOT / "physical/librelane/bondpad/bondpad_70x70.lef" + + +def load_module(name: str, path: Path): + spec = importlib.util.spec_from_file_location(name, path) + assert spec is not None and spec.loader is not None + module = importlib.util.module_from_spec(spec) + spec.loader.exec_module(module) + return module + + +def chip_arguments(tmp_path: Path) -> SimpleNamespace: + return SimpleNamespace( + pin_map=PIN_MAP, + rtl=tmp_path / "retrosoc_tiny_asic_sources.sv", + sdc=tmp_path / "retrosoc_tiny_chip.sdc", + pdn=FLOW_ROOT / "pdn_cfg.tcl", + bondpad_gds=tmp_path / "bondpad_70x70.gds", + bondpad_lef=BONDPAD_LEF, + sram_vh=FLOW_ROOT / "sram_blackboxes.vh", + ext_clk_hz=24_000_000, + have_sram_macro=True, + sram_size_kib=128, + output=tmp_path / "config.json", + ) + + +def test_chip_config_places_every_signal_and_power_pad_once(tmp_path: Path) -> None: + module = load_module( + "retrosoc_tiny_librelane_config", FLOW_ROOT / "scripts/generate_chip_config.py" + ) + config = module.build_config(chip_arguments(tmp_path)) + sides = {name: config[f"PAD_{name.upper()}"] for name in module.SIDE_ORDER} + placed = [instance for side in module.SIDE_ORDER for instance in sides[side]] + + assert len(placed) == 84 + assert len(placed) == len(set(placed)) + assert {side: len(instances) for side, instances in sides.items()} == { + "south": 19, + "east": 24, + "north": 17, + "west": 24, + } + assert sum(item.startswith("vdd_pads[") for item in placed) == 8 + assert sum(item.startswith("vss_pads[") for item in placed) == 8 + assert sum(item.startswith("iovdd_pads[") for item in placed) == 8 + assert sum(item.startswith("iovss_pads[") for item in placed) == 8 + assert "u_extclk_i_pad.u_sg13g2_IOPadIn" in sides["south"] + assert "u_jtag_tck_i_pad.u_sg13g2_IOPadIn" in sides["south"] + assert "u_uart0_tx_o_pad.u_sg13g2_IOPadOut4mA" in sides["south"] + assert "u_xpi_sck_o_pad.u_sg13g2_IOPadOut4mA" in sides["north"] + assert "u_gpio_0_io_pad.u_sg13g2_IOPadInOut4mA" in sides["east"] + assert "u_gpio_15_io_pad.u_sg13g2_IOPadInOut4mA" in sides["east"] + assert "u_gpio_16_io_pad.u_sg13g2_IOPadInOut4mA" in sides["west"] + assert "u_gpio_31_io_pad.u_sg13g2_IOPadInOut4mA" in sides["west"] + assert config["meta"] == {"version": 3, "flow": "Chip"} + assert config["DESIGN_NAME"] == "retrosoc_tiny_asic" + assert config["DIE_AREA"] == [0, 0, 4700, 4700] + assert config["CORE_AREA"] == [365, 365, 4335, 4335] + assert config["CLOCK_PORT"] == ["extclk_i_pad", "jtag_tck_i_pad"] + assert config["CLOCK_PERIOD"] == 1_000_000_000 / 24_000_000 + assert config["PL_TARGET_DENSITY_PCT"] == 45 + assert config["USE_SLANG"] is True + assert config["SLANG_ARGUMENTS"] == ["--keep-hierarchy"] + assert config["SYNTH_HIERARCHY_MODE"] == "deferred_flatten" + assert config["SYNTH_KEEP_HIERARCHY_MODULES"] == [ + "sg13g2_IOPadVdd", + "sg13g2_IOPadVss", + "sg13g2_IOPadIOVdd", + "sg13g2_IOPadIOVss", + ] + assert config["RUN_CTS"] is False + assert config["ERROR_ON_SYNTH_CHECKS"] is False + assert config["EXTRA_EXCLUDED_CELLS"] == ["sg13g2_IOPad*"] + assert config["VDD_NETS"] == ["VDD"] + assert config["GND_NETS"] == ["VSS"] + assert config["PAD_CFG"].endswith("physical/librelane/tiny/pad_cfg.tcl") + assert config["PDN_ENABLE_PINS"] is True + assert config["ERROR_ON_PDN_VIOLATIONS"] is True + assert config["STA_EXTRA_CORNER_TCL_FILE"].endswith( + "physical/librelane/tiny/sta_report_limit.tcl" + ) + assert config["PAD_BONDPAD_NAME"] == "bondpad_70x70" + assert set(config["MACROS"]) == {"RM_IHPSG13_1P_1024x32_c2_bm_bist"} + + +def test_chip_config_covers_every_onchip_sram_bank(tmp_path: Path) -> None: + module = load_module( + "retrosoc_tiny_librelane_sram_config", FLOW_ROOT / "scripts/generate_chip_config.py" + ) + config = module.build_config(chip_arguments(tmp_path)) + + macro = config["MACROS"]["RM_IHPSG13_1P_1024x32_c2_bm_bist"] + assert len(macro["instances"]) == 32 + assert ( + "u_soc.u_sram.gen_memory.gen_bank[0].u_ram.u_mem" in macro["instances"] + ) + assert ( + "u_soc.u_sram.gen_memory.gen_bank[31].u_ram.u_mem" in macro["instances"] + ) + for instance in macro["instances"].values(): + x, y = instance["location"] + assert 365 <= x <= 4335 + assert 365 <= y <= 4335 + assert instance["orientation"] == "N" + assert len(config["PDN_MACRO_CONNECTIONS"]) == 64 + assert any( + "gen_bank.*0.*\\.u_ram" in connection + for connection in config["PDN_MACRO_CONNECTIONS"] + ) + blackboxes = (FLOW_ROOT / "sram_blackboxes.vh").read_text(encoding="utf-8") + assert "module RM_IHPSG13_1P_1024x32_c2_bm_bist" in blackboxes + assert "RM_IHPSG13_1P_4096x16_c3_bm_bist" not in blackboxes + + +def test_chip_sdc_is_pad_aware_and_does_not_false_path_all_io() -> None: + module = load_module( + "retrosoc_tiny_librelane_sdc", FLOW_ROOT / "scripts/generate_sdc.py" + ) + arguments = SimpleNamespace( + domains=DOMAINS, + pin_map=PIN_MAP, + ext_clk_hz=24_000_000, + ) + sdc = module.render(arguments) + + assert "u_extclk_i_pad.u_sg13g2_IOPadIn/p2c" in sdc + assert "u_jtag_tck_i_pad.u_sg13g2_IOPadIn/p2c" in sdc + assert "u_clock_buffer.u_sg13g2_buf_1/X" in sdc + assert "create_clock -name clk_external -period 41.6666666667" in sdc + assert "create_clock -name clk_jtag -period 100" in sdc + assert "create_generated_clock -name clk_system" in sdc + assert "set_clock_groups -name retrosoc_async -asynchronous" in sdc + assert "-group [get_clocks {clk_external clk_system}]" in sdc + assert "-group [get_clocks {clk_jtag}]" in sdc + assert "set_input_delay -max" in sdc + assert "set_output_delay -max" in sdc + assert "set_false_path -from $reset_ext_rst_n_i_pad" in sdc + assert "set_false_path -from $reset_jtag_trst_n_i_pad" in sdc + assert "set_false_path -from [all_inputs]" not in sdc + assert "set_false_path -to [all_outputs]" not in sdc + + +def test_tiny_flow_exposes_chip_target_only() -> None: + makefile = (FLOW_ROOT / "Makefile").read_text(encoding="utf-8") + top_makefile = (ROOT / "Makefile").read_text(encoding="utf-8") + + assert "librelane-chip:" in makefile + assert "librelane-core:" not in makefile + assert "--soc TINY" in makefile + assert "--source-filelist-dir" in makefile + assert re.search(r"ifeq \(\$\(SOC\),TINY\)\ninclude physical/librelane/tiny/Makefile", top_makefile) + assert "include physical/librelane/mini/Makefile" in top_makefile + doctor = (FLOW_ROOT / "scripts/doctor.py").read_text(encoding="utf-8") + assert "EXPECTED_SIGNAL_PADS = 52" in doctor + pad_cfg = (FLOW_ROOT / "pad_cfg.tcl").read_text(encoding="utf-8") + assert "vdd sg13g2_IOPadVdd 8" in pad_cfg + assert "iovss sg13g2_IOPadIOVss 8" in pad_cfg + pdn = (FLOW_ROOT / "pdn_cfg.tcl").read_text(encoding="utf-8") + assert "RM_IHPSG13_1P_1024x32_c2_bm_bist" in pdn + assert "RM_IHPSG13_1P_4096x16_c3_bm_bist" not in pdn diff --git a/tests/test_lp_irq.py b/tests/test_lp_irq.py index cc376e73..e3a1c7bf 100644 --- a/tests/test_lp_irq.py +++ b/tests/test_lp_irq.py @@ -115,14 +115,14 @@ int main(void) { def test_phase1_wrapper_and_backend_contracts() -> None: wrapper = (ROOT / "rtl/mini/top/core_wrapper.sv").read_text(encoding="utf-8") - management = (ROOT / "rtl/mini/top/mgmt_core_wrapper.sv").read_text(encoding="utf-8") + management = (ROOT / "rtl/ip/core/mgmt_core_wrapper.sv").read_text(encoding="utf-8") top = (ROOT / "rtl/mini/top/retrosoc.sv").read_text(encoding="utf-8") handler = (ROOT / "crt/src/core/system_irq_handler.c").read_text(encoding="utf-8") csr = (ROOT / "crt/include/retrosoc/arch/riscv/system_csr.h").read_text(encoding="utf-8") firmware = (ROOT / "app/apps/ci_smoke/main.c").read_text(encoding="utf-8") assert "parameter int ExternalIrqCount = 30" in wrapper - assert "parameter int ExternalIrqCount = 30" in management + assert re.search(r"parameter int ExternalIrqCount\s*= 30", management) assert ".NUM_IRQS (ExternalIrqCount)" in management assert ".IRQ_INPUT_BYPASS ({ExternalIrqCount{1'b0}})" in management assert "localparam int ManagementExternalIrqCount = `SOC_IRQ_VECTOR_WIDTH - 2" in top diff --git a/tests/test_memory_map.py b/tests/test_memory_map.py index 83213e5b..1688eaf7 100644 --- a/tests/test_memory_map.py +++ b/tests/test_memory_map.py @@ -11,7 +11,7 @@ from pathlib import Path ROOT = Path(__file__).resolve().parents[1] -GENERATOR = ROOT / "rtl/mini/address_map/generate_memory_map.py" +GENERATOR = ROOT / "scripts/rtl/generate_memory_map.py" MEMORY_MAP = ROOT / "rtl/mini/address_map/memory_map.json" USER_EXTENSIONS = ROOT / "rtl/mini/integration/user_extensions.json" USER_GENERATOR = ROOT / "rtl/mini/integration/generate_user_extensions.py" @@ -242,7 +242,7 @@ def test_bus_fault_responder_handles_reserved_and_unmapped_addresses(tmp_path: P subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -320,7 +320,7 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -349,7 +349,7 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(unsupported_list), "--output", diff --git a/tests/test_mgmt_core_spec.py b/tests/test_mgmt_core_spec.py index 692a61ca..823b1937 100644 --- a/tests/test_mgmt_core_spec.py +++ b/tests/test_mgmt_core_spec.py @@ -1,14 +1,15 @@ """Keep the boot display aligned with the fixed Hazard3 management-core integration.""" +import re from pathlib import Path ROOT = Path(__file__).resolve().parents[1] BOOTER = ROOT / "crt/src/service/booter.c" -SOFTWARE_MAKE = ROOT / "rtl/mini/mk/software.mk" -MGMT_CORE = ROOT / "rtl/mini/top/mgmt_core_wrapper.sv" -MGMT_DEBUG = ROOT / "rtl/mini/top/mgmt_debug_wrapper.sv" -AHBL_TO_AXI4 = ROOT / "rtl/mini/top/ahbl2axi4.sv" +SOFTWARE_MAKE = ROOT / "rtl/mk/software.mk" +MGMT_CORE = ROOT / "rtl/ip/core/mgmt_core_wrapper.sv" +MGMT_DEBUG = ROOT / "rtl/ip/core/mgmt_debug_wrapper.sv" +AHBL_TO_AXI4 = ROOT / "rtl/ip/interconnect/ahbl2axi4.sv" VEXII_CONFIG = ROOT / "scripts/vexiiriscv/GenerateRetroSocHp.scala" @@ -41,7 +42,7 @@ def test_booter_prints_the_fixed_hazard3_specification() -> None: assert "exact execute-address hardware breakpoints" not in booter for parameter in ( - ".EXTENSION_A (1)", + ".EXTENSION_A (EnableAtomics)", ".EXTENSION_C (1)", ".EXTENSION_M (1)", ".EXTENSION_ZBA (1)", @@ -57,12 +58,13 @@ def test_booter_prints_the_fixed_hazard3_specification() -> None: ".U_MODE (0)", ".PMP_REGIONS (0)", ".BREAKPOINT_TRIGGERS(2)", - "parameter int ExternalIrqCount = 30", ".NUM_IRQS (ExternalIrqCount)", ".IRQ_PRIORITY_BITS (2)", ): assert parameter in management_core + assert re.search(r"parameter int ExternalIrqCount\s*= 30", management_core) + assert re.search(r"parameter bit EnableAtomics\s*= 1'b1", management_core) assert ".HAVE_SBA(0)" in management_debug assert "ahbl.htrans == AHBL_TRANS_NSEQ" in ahbl_to_axi4 assert "axi4.awlen = 8'd0;" in ahbl_to_axi4 diff --git a/tests/test_mgmt_debug.py b/tests/test_mgmt_debug.py index 8c122f47..fbe9539d 100644 --- a/tests/test_mgmt_debug.py +++ b/tests/test_mgmt_debug.py @@ -20,7 +20,7 @@ def test_management_debug_reset_waits_for_the_ahbl_bridge(tmp_path: Path) -> Non sources = ( ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv", ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv", - ROOT / "rtl/mini/top/mgmt_debug_reset.sv", + ROOT / "rtl/ip/core/mgmt_debug_reset.sv", ROOT / "tests/rtl/mgmt_debug_reset_tb.sv", ) subprocess.run( diff --git a/tests/test_npu_rtl_compute.py b/tests/test_npu_rtl_compute.py index 929d2892..4b28a102 100644 --- a/tests/test_npu_rtl_compute.py +++ b/tests/test_npu_rtl_compute.py @@ -76,7 +76,7 @@ def _run_icarus( subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_npu_rtl_memory.py b/tests/test_npu_rtl_memory.py index 276abcb7..65da0a23 100644 --- a/tests/test_npu_rtl_memory.py +++ b/tests/test_npu_rtl_memory.py @@ -62,7 +62,7 @@ def _build_iverilog( subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", diff --git a/tests/test_npu_rtl_p3.py b/tests/test_npu_rtl_p3.py index c6fcd714..fbb2c1e6 100644 --- a/tests/test_npu_rtl_p3.py +++ b/tests/test_npu_rtl_p3.py @@ -137,7 +137,7 @@ def _build_iverilog(tools: dict[str, str], tmp_path: Path, name: str, top: str, subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", diff --git a/tests/test_npu_rtl_shell.py b/tests/test_npu_rtl_shell.py index 51bea20d..212916cf 100644 --- a/tests/test_npu_rtl_shell.py +++ b/tests/test_npu_rtl_shell.py @@ -77,7 +77,7 @@ def _build_iverilog(tools: dict[str, str], tmp_path: Path, name: str, top: str, subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", diff --git a/tests/test_onchip_ram.py b/tests/test_onchip_ram.py index 34924e41..d57cef75 100644 --- a/tests/test_onchip_ram.py +++ b/tests/test_onchip_ram.py @@ -27,7 +27,7 @@ def test_onchip_ram_axi4_capacity_protocol_and_performance( subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -55,6 +55,7 @@ def test_onchip_ram_axi4_capacity_protocol_and_performance( "+define+SV_ASSRT_DISABLE", "-I" + str(generated / "rtl"), "-I" + str(ROOT / "rtl/mini/top"), + "-I" + str(ROOT / "rtl/ip/memory"), "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"), "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"), str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"), @@ -63,8 +64,8 @@ def test_onchip_ram_axi4_capacity_protocol_and_performance( str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/tech/ram.sv"), str(ROOT / "rtl/tech/tc_sram.sv"), - str(ROOT / "rtl/mini/top/onchip_ram_reg.sv"), - str(ROOT / "rtl/mini/top/onchip_ram.sv"), + str(ROOT / "rtl/ip/memory/onchip_ram_reg.sv"), + str(ROOT / "rtl/ip/memory/onchip_ram.sv"), str(ROOT / "tests/rtl/onchip_ram_tb.sv"), "-Mdir", str(tmp_path / "obj"), @@ -96,7 +97,7 @@ def test_onchip_ram_native_axi64_width_ids_and_lanes( subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -124,6 +125,7 @@ def test_onchip_ram_native_axi64_width_ids_and_lanes( "+define+SV_ASSRT_DISABLE", "-I" + str(generated / "rtl"), "-I" + str(ROOT / "rtl/mini/top"), + "-I" + str(ROOT / "rtl/ip/memory"), "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"), "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"), str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"), @@ -132,8 +134,8 @@ def test_onchip_ram_native_axi64_width_ids_and_lanes( str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/tech/ram.sv"), str(ROOT / "rtl/tech/tc_sram.sv"), - str(ROOT / "rtl/mini/top/onchip_ram_reg.sv"), - str(ROOT / "rtl/mini/top/onchip_ram.sv"), + str(ROOT / "rtl/ip/memory/onchip_ram_reg.sv"), + str(ROOT / "rtl/ip/memory/onchip_ram.sv"), str(ROOT / "tests/rtl/onchip_ram64_tb.sv"), "-Mdir", str(tmp_path / "obj64"), @@ -162,7 +164,7 @@ def test_absent_onchip_ram_reports_capability_and_decode_errors(tmp_path: Path) subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -186,6 +188,7 @@ def test_absent_onchip_ram_reports_capability_and_decode_errors(tmp_path: Path) "+define+SV_ASSRT_DISABLE", "-I" + str(generated / "rtl"), "-I" + str(ROOT / "rtl/mini/top"), + "-I" + str(ROOT / "rtl/ip/memory"), "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"), "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"), str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"), @@ -194,8 +197,8 @@ def test_absent_onchip_ram_reports_capability_and_decode_errors(tmp_path: Path) str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/tech/ram.sv"), str(ROOT / "rtl/tech/tc_sram.sv"), - str(ROOT / "rtl/mini/top/onchip_ram_reg.sv"), - str(ROOT / "rtl/mini/top/onchip_ram.sv"), + str(ROOT / "rtl/ip/memory/onchip_ram_reg.sv"), + str(ROOT / "rtl/ip/memory/onchip_ram.sv"), str(ROOT / "tests/rtl/onchip_ram_absent_tb.sv"), "-Mdir", str(tmp_path / "obj-absent"), @@ -425,7 +428,7 @@ def test_native_axi4_burst_reaches_peak_and_removes_bridge_overhead(tmp_path: Pa subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -452,6 +455,7 @@ def test_native_axi4_burst_reaches_peak_and_removes_bridge_overhead(tmp_path: Pa "+define+SV_ASSRT_DISABLE", "-I" + str(generated / "rtl"), "-I" + str(ROOT / "rtl/mini/top"), + "-I" + str(ROOT / "rtl/ip/memory"), "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl"), "-I" + str(ROOT / "rtl/managed/clusterip/common/rtl/interface"), str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"), @@ -464,8 +468,8 @@ def test_native_axi4_burst_reaches_peak_and_removes_bridge_overhead(tmp_path: Pa str(ROOT / "rtl/managed/clusterip/common/rtl/tech/ram.sv"), str(ROOT / "rtl/tech/tc_sram.sv"), str(ROOT / "rtl/mini/top/axi42ram.sv"), - str(ROOT / "rtl/mini/top/onchip_ram_reg.sv"), - str(ROOT / "rtl/mini/top/onchip_ram.sv"), + str(ROOT / "rtl/ip/memory/onchip_ram_reg.sv"), + str(ROOT / "rtl/ip/memory/onchip_ram.sv"), str(ROOT / "tests/rtl/onchip_ram_perf_tb.sv"), "-Mdir", str(tmp_path / "obj-perf"), diff --git a/tests/test_onchip_sram_register_parity.py b/tests/test_onchip_sram_register_parity.py index 63d59d52..561c4f49 100644 --- a/tests/test_onchip_sram_register_parity.py +++ b/tests/test_onchip_sram_register_parity.py @@ -7,7 +7,7 @@ from pathlib import Path ROOT = Path(__file__).resolve().parents[1] -RTL_DEFINE = ROOT / "rtl/mini/top/onchip_ram_define.svh" +RTL_DEFINE = ROOT / "rtl/ip/memory/onchip_ram_define.svh" C_HEADER = ROOT / "crt/include/retrosoc/hal/onchip_sram_regs.h" diff --git a/tests/test_pin_map.py b/tests/test_pin_map.py index a3833d4b..95bc7594 100644 --- a/tests/test_pin_map.py +++ b/tests/test_pin_map.py @@ -11,7 +11,7 @@ from pathlib import Path ROOT = Path(__file__).resolve().parents[1] -GENERATOR = ROOT / "rtl/mini/pin_map/generate_pin_map.py" +GENERATOR = ROOT / "scripts/rtl/generate_pin_map.py" PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json" FPGA_TOP = ROOT / "fpga/mini/retrosoc_top.sv" FPGA_XDC = ROOT / "fpga/mini/starrysky_v2.xdc" @@ -183,6 +183,52 @@ def test_pin_map_requires_explicit_bidirectional_peripheral_signals(tmp_path: Pa assert "requires input, output, and output_enable" in result.stderr +def test_pin_map_tiny_power_pads_override(tmp_path: Path) -> None: + subprocess.run( + [ + sys.executable, + str(GENERATOR), + "--map", + str(ROOT / "rtl/tiny/pin_map/pin_map.json"), + "--output-dir", + str(tmp_path), + ], + check=True, + ) + pads = (tmp_path / "rtl/retrosoc_asic_pad_bindings.svh").read_text(encoding="utf-8") + + assert "for (genvar i = 0; i < 8; i++) begin : vdd_pads" in pads + assert "for (genvar i = 0; i < 8; i++) begin : vss_pads" in pads + assert "for (genvar i = 0; i < 8; i++) begin : iovdd_pads" in pads + assert "for (genvar i = 0; i < 8; i++) begin : iovss_pads" in pads + assert "i < 24" not in pads + assert "i < 16" not in pads + + +def test_pin_map_rejects_incomplete_power_pads(tmp_path: Path) -> None: + document = json.loads(PIN_MAP.read_text(encoding="utf-8")) + document["power_pads"] = {"vdd": 24, "vss": 24, "iovdd": 16} + invalid_map = tmp_path / "incomplete-power-pads.json" + invalid_map.write_text(json.dumps(document), encoding="utf-8") + + result = validate(invalid_map) + + assert result.returncode != 0 + assert "power_pads" in result.stderr + + +def test_pin_map_rejects_non_positive_power_pads(tmp_path: Path) -> None: + document = json.loads(PIN_MAP.read_text(encoding="utf-8")) + document["power_pads"] = {"vdd": 0, "vss": 24, "iovdd": 16, "iovss": 16} + invalid_map = tmp_path / "non-positive-power-pads.json" + invalid_map.write_text(json.dumps(document), encoding="utf-8") + + result = validate(invalid_map) + + assert result.returncode != 0 + assert "power_pads.vdd" in result.stderr + + def test_fpga_constraints_reference_declared_top_ports() -> None: top_ports = set( re.findall( @@ -213,7 +259,7 @@ def test_apb4_interface_bridge(tmp_path: Path) -> None: [ str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv"), str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv"), - str(ROOT / "rtl/mini/top/apb4_if_bridge.sv"), + str(ROOT / "rtl/ip/interconnect/apb4_if_bridge.sv"), str(ROOT / "tests/rtl/apb4_if_bridge_tb.sv"), "", ] @@ -224,7 +270,7 @@ def test_apb4_interface_bridge(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_plic.py b/tests/test_plic.py index 9ff20fdf..a923e9cd 100644 --- a/tests/test_plic.py +++ b/tests/test_plic.py @@ -38,7 +38,7 @@ def test_plic_priority_claim_and_completion(tmp_path: Path) -> None: ) converted = tmp_path / "plic_tb.v" subprocess.run( - [sys.executable, str(ROOT / "rtl/mini/script/convt_sv2v.py"), "-f", str(filelist), + [sys.executable, str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(filelist), "--output", str(converted)], check=True, ) diff --git a/tests/test_psram.py b/tests/test_psram.py index f7d7c872..4f2d8aad 100644 --- a/tests/test_psram.py +++ b/tests/test_psram.py @@ -22,7 +22,7 @@ def test_psram_controller_data_integrity_and_fault_isolation(tmp_path: Path) -> subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", diff --git a/tests/test_publication_implementation.py b/tests/test_publication_implementation.py index a0db6561..82b285bb 100644 --- a/tests/test_publication_implementation.py +++ b/tests/test_publication_implementation.py @@ -143,3 +143,13 @@ def test_real_tool_dry_run_never_invokes_gdb_and_is_not_device_pass(tmp_path, mo assert result["passed"] is True and result["executed"] is False assert ir.programming_result(result) == "Script generated; device not programmed" assert "XPI_FLASH_PROGRAM_PASS" in args.gdb_script.read_text() + + +def test_lp_boolean_feature_defaults_preserve_mini_atomics(): + text = """ + module mgmt_core_wrapper #(parameter bit EnableAtomics = 1'b1) (); + hazard3_cpu_1port #(.EXTENSION_A(EnableAtomics), .NUM_IRQS(ExternalIrqCount)) + u_hazard3_cpu_1port (); + endmodule + """ + assert ir.lp_parameters(text) == {"EXTENSION_A": "1", "NUM_IRQS": "ExternalIrqCount"} diff --git a/tests/test_publication_registers.py b/tests/test_publication_registers.py index 7f857e34..6fd0a27e 100644 --- a/tests/test_publication_registers.py +++ b/tests/test_publication_registers.py @@ -95,6 +95,9 @@ def test_reset_disagreement_and_field_overflow_are_rejected(reference): def test_constant_reader_does_not_execute_source_text(): assert number("8'(DEPTH / 2)", {"DEPTH": 16}) == 8 + assert number("4'(MaxBurstBeats)", {"MaxBurstBeats": 16}) == 0 + assert number("(EnableStreams ? 3'd3 : 3'd0)", {"EnableStreams": 1}) == 3 + assert number("(EnableStreams ? 3'd3 : 3'd0)", {"EnableStreams": 0}) == 0 assert number("(DEPTH > 4) ? 32'd4 : DEPTH - 1", {"DEPTH": 16}) == 4 assert number("(32'd1 << 0) |\n (32'd1 << 8)") == 0x101 with pytest.raises(ValueError): diff --git a/tests/test_publication_software.py b/tests/test_publication_software.py index a8f420f0..5fad7a17 100644 --- a/tests/test_publication_software.py +++ b/tests/test_publication_software.py @@ -61,7 +61,7 @@ def test_function_extraction_rejects_unsupported_definitions(source): @pytest.mark.parametrize("relative,old,new", [ - ("rtl/mini/mk/software.mk", "CRT_SRCS := $(APP_CRT_SRCS)", "CRT_SRCS += $(APP_CRT_SRCS)"), + ("rtl/mk/software.mk", "CRT_SRCS := $(APP_CRT_SRCS)", "CRT_SRCS += $(APP_CRT_SRCS)"), ("crt/arch/riscv/startup.S", "beqz t1, PSRAM_READY_WAIT", "beqz t1, main_start"), ("crt/arch/riscv/startup.S", "call _premain_init", "call other_premain"), ("crt/arch/riscv/system_irq.S", "SAVE_CSR_CONTEXT\n", "SAVE_CHANGED_CONTEXT\n"), diff --git a/tests/test_publication_tiny.py b/tests/test_publication_tiny.py new file mode 100644 index 00000000..81597ee3 --- /dev/null +++ b/tests/test_publication_tiny.py @@ -0,0 +1,179 @@ +"""Tiny publication is parameter-bound, complete and isolated from Mini inputs.""" +from __future__ import annotations + +import copy +import json +from pathlib import Path +import shutil + +import pytest + +from publications import tiny_reference as tiny +from publications.register_reference import parse_definitions + +ROOT = Path(__file__).resolve().parents[1] + + +@pytest.fixture(scope="module") +def data(): + return tiny.collect(tiny.read(ROOT / tiny.BOOK / "tiny.json"), check_snapshot=False) + + +def test_tiny_configuration_and_inventory_are_derived(data): + assert (data["facts"]["hardware_isa"], data["facts"]["firmware_isa"]) == ("RV32IMC", "RV32IM") + assert data["facts"]["sram"] == {"CapacityKiB": 128, "DataWidth": 32, "IdWidth": 1} + assert data["facts"]["dma"]["NumChannels"] == 4 + assert data["facts"]["dma"]["RequestMask"] == 0x7F9 + assert data["facts"]["dma"]["EnableStreams"] == 0 + assert len(data["catalog"]) == 14 and len(data["regions"]) == 20 and len(data["pads"]) == 52 + assert len(data["interrupts"]) == 14 and len(data["gpio"]) == 32 + assert not any(p.startswith("rtl/mini/") for p in data["source_paths"]) + assert "mpw" not in {s["destination"].split("/")[-1] for s in data["managed_sources"]} + + +def test_tiny_collection_does_not_open_mini_files(monkeypatch): + original = Path.read_text + def read(path, *args, **kwargs): + name = path.as_posix() + if "/rtl/mini/" in name or ("/publications/datasheets/" in name and "/tiny/" not in name): + raise AssertionError("Tiny opened a Mini product input: " + name) + return original(path, *args, **kwargs) + monkeypatch.setattr(Path, "read_text", read) + tiny.collect(tiny.read(ROOT / tiny.BOOK / "tiny.json"), check_snapshot=False) + + +def test_common_register_default_remains_mini_compatible(): + paths = ["rtl/ip/serial/apb4_uart_define.svh"] + assert parse_definitions(paths, {}) == parse_definitions(paths, {}, "rtl/mini/address_map/memory_map.json") + _, constants = parse_definitions(paths, {}, tiny.MAP) + assert "SOC_SYSCTRL_TEST_STATUS_OFFSET" in constants + + +@pytest.fixture +def source_tree(tmp_path): + sources = [tiny.TOP, tiny.ARCHINFO, tiny.SYSCTRL, "rtl/ip/core/mgmt_core_wrapper.sv", "configs/ci/ihp130-tiny.mk", + tiny.MAP, tiny.TOPOLOGY, (tiny.BOOK / "source-contract.json").as_posix()] + for relative in sources: + target = tmp_path / relative + target.parent.mkdir(parents=True, exist_ok=True) + shutil.copyfile(ROOT / relative, target) + return tmp_path + + +@pytest.mark.parametrize("path,before,after", [ + (tiny.TOP, ".CapacityKiB(128)", ".CapacityKiB(32)"), + (tiny.TOP, ".DataWidth (32)", ".DataWidth (64)"), + (tiny.TOP, ".NumChannels (4)", ".NumChannels (8)"), + (tiny.TOP, ".EnableStreams(1'b0)", ".EnableStreams(1'b1)"), + (tiny.TOP, ".EnableAtomics (1'b0)", ".EnableAtomics (1'b1)"), + ("configs/ci/ihp130-tiny.mk", "ISA := RV32IM", "ISA := RV32IMC"), + (tiny.ARCHINFO, "32'h5449_4e59", "32'h4d49_4e49"), + (tiny.SYSCTRL, "!s_test_q[31] && apb4.pwdata[31]", "s_test_q[31] && apb4.pwdata[31]"), +]) +def test_changed_hardware_or_isa_cannot_retain_publication_claim(source_tree, path, before, after): + file = source_tree / path + text = file.read_text(encoding="utf-8") + assert before in text + file.write_text(text.replace(before, after, 1), encoding="utf-8") + with pytest.raises(ValueError): + tiny.facts(source_tree) + + +@pytest.mark.parametrize("change", ["irq_missing", "irq_number", "region_address", "region_missing"]) +def test_missing_or_wrong_maps_fail(source_tree, change): + path = source_tree / (tiny.TOPOLOGY if change.startswith("irq") else tiny.MAP) + document = tiny.read(path) + if change == "irq_missing": + document["interrupts"].pop() + elif change == "irq_number": + document["interrupts"][-1]["core_bit"] = 27 + elif change == "region_address": + next(r for r in document["regions"] if r["symbol"] == "SRAM")["base"] = "0x31000000" + else: + document["regions"].pop() + path.write_text(json.dumps(document), encoding="utf-8") + with pytest.raises(ValueError): + tiny.validate_maps(source_tree, tiny.facts(source_tree)) + + +def test_tiny_sysctrl_and_discovery_do_not_inherit_mini_controls(data): + control = data["registers"]["sysctrl"]["registers"] + assert {r["name"] for r in control} == tiny.SUPPORTED_SYSCTRL + assert not any(r["name"] in {"HP_CTRL", "PLL_CFG", "DEBUG_SELECT"} for r in control) + test = next(r for r in control if r["name"] == "TEST_STATUS") + assert [(f["name"], f["lsb"], f["msb"]) for f in test["fields"] if f["name"] != "Reserved"] == [ + ("PASS", 0, 0), ("CODE", 8, 15), ("VALID", 31, 31)] + info = data["registers"]["archinfo"]["registers"] + assert next(r for r in info if r["name"] == "SOC_ID")["reset"] == "0x54494E59" + assert next(r for r in info if r["name"] == "SRAM_BYTES")["reset"] == "0x00020000" + assert data["registers"]["dma"]["groups"][1]["count"] == 4 + + +def test_tcd_layout_is_complete_and_bounded(data): + assert len(data["tcd"]) == 17 + assert sum(f["bytes"] for f in data["tcd"]) == 64 + assert data["tcd"][-1]["offset"] == 60 + + +def test_local_capabilities_keep_fabric_and_encoding_restrictions(data): + capability = next(r for r in data["registers"]["dma"]["registers"] if r["name"] == "CAPABILITY") + assert capability["reset"] == "0x00200401" + burst = next(f for f in capability["fields"] if f["name"] == "MAX_BURST_FIELD") + assert (burst["lsb"], burst["msb"], burst["reset"]) == (24, 27, "0x0") + assert "encoding limitation" in burst["description"] + sram = next(r for r in data["registers"]["sram"]["registers"] if r["name"] == "CAPABILITY") + assert "rejects WRAP" in next(f for f in sram["fields"] if f["name"] == "WRAP")["description"] + + +@pytest.mark.parametrize("key,value", [("document_id", "RS-MINI-DS"), ("profile", "configs/ci/ihp130.mk"), ("status", "RELEASE")]) +def test_wrong_product_configuration_cannot_enter_tiny_pipeline(key, value): + config = tiny.read(ROOT / tiny.BOOK / "tiny.json") + config[key] = value + with pytest.raises(ValueError, match="configuration"): + tiny.validate_configuration(config) + + +def test_existing_mini_output_is_never_overwritten(tmp_path, monkeypatch): + from publications import build_tiny_datasheet as builder + folder = tmp_path / "build/mini-existing" + folder.mkdir(parents=True) + manifest = folder / "manifest.json" + manifest.write_text('{"document":{"document_id":"RS-MINI-DS"}}') + before = manifest.read_bytes() + monkeypatch.setattr(builder, "ROOT", tmp_path) + with pytest.raises(ValueError, match="another product"): + builder.validate_output(folder, {"document_id": "RS-TINY-DS"}) + assert manifest.read_bytes() == before + + +@pytest.mark.parametrize("change", ["missing", "offset"]) +def test_register_inventory_cannot_silently_drop_or_move_a_definition(data, change): + refs = copy.deepcopy(data["registers"]) + if change == "missing": + refs["uart"]["registers"].pop() + else: + refs["uart"]["registers"][0]["offset"] += 4 + with pytest.raises(ValueError, match="register inventory"): + tiny.validate_register_inventory(refs, tiny.read(ROOT / tiny.BOOK / "register-contract.json")) + + +@pytest.mark.parametrize("change", ["missing", "duplicate"]) +def test_pdf_must_render_each_extracted_register_once(data, change): + from publications.build_tiny_datasheet import validate_rendered_registers + items = [dict(kind="tiny-register", family=family, key=r["key"], page=1) + for family, value in data["registers"].items() for r in value["registers"]] + assert validate_rendered_registers(data, items) == 337 + if change == "missing": + items.pop() + else: + items.append(items[0]) + with pytest.raises(ValueError, match="omitted or duplicated"): + validate_rendered_registers(data, items) + + +@pytest.mark.parametrize("key,value", [("status", "qualified"), ("current_commit_reports", [{"passed": True}])]) +def test_unmatched_qualification_claim_is_rejected(data, key, value): + evidence = copy.deepcopy(data["evidence"]) + evidence[key] = value + with pytest.raises(ValueError, match="qualification"): + tiny.validate_evidence(evidence) diff --git a/tests/test_publications.py b/tests/test_publications.py index 642862f6..7daccef4 100644 --- a/tests/test_publications.py +++ b/tests/test_publications.py @@ -57,7 +57,7 @@ def test_profile_rejects_make_evaluation_and_duplicate_assignment(tmp_path): def test_reviewed_profile_resolves_sram_instead_of_using_decoder_maximum(): config = ds.read_json(ds.CONFIG) profile = ds.profile_values(ROOT / config["profile"]) - generator = ds.load_generator("test_datasheet_memory", "rtl/mini/address_map/generate_memory_map.py") + generator = ds.load_generator("test_datasheet_memory", "scripts/rtl/generate_memory_map.py") _, regions, _ = generator.read_map(ROOT / ds.MAP, int(profile["SRAM_SIZE_KIB"])) sram = next(r for r in regions if r["symbol"] == "SRAM") assert sram["size"] == 32768 diff --git a/tests/test_rib.py b/tests/test_rib.py index 815dbeaf..d6d01c56 100644 --- a/tests/test_rib.py +++ b/tests/test_rib.py @@ -21,7 +21,7 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -58,7 +58,7 @@ def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -103,7 +103,7 @@ def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_rib2apb.py b/tests/test_rib2apb.py index eb1ca1a6..3821c3e1 100644 --- a/tests/test_rib2apb.py +++ b/tests/test_rib2apb.py @@ -23,7 +23,7 @@ def test_rib2apb_preserves_apb_and_rib_handshakes(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -71,7 +71,7 @@ def test_rib2apb_preserves_apb_and_rib_handshakes(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_rtl_style.py b/tests/test_rtl_style.py index e8fd0e4c..d0a3ce51 100644 --- a/tests/test_rtl_style.py +++ b/tests/test_rtl_style.py @@ -259,7 +259,7 @@ def test_owned_style_audit_matches_current_inventory() -> None: } actual_paths = { str(path.relative_to(ROOT)) - for root in (ROOT / "rtl/ip", ROOT / "rtl/mini/top") + for root in (ROOT / "rtl/ip", ROOT / "rtl/mini/top", ROOT / "rtl/tiny/top") for path in root.rglob("*") if path.is_file() and path.suffix in {".sv", ".svh"} } diff --git a/tests/test_script_tools.py b/tests/test_script_tools.py index e188fcb3..e40bcd8a 100644 --- a/tests/test_script_tools.py +++ b/tests/test_script_tools.py @@ -18,16 +18,12 @@ import pytest ROOT = Path(__file__).resolve().parents[1] -FILELIST_SCRIPT_DIR = ROOT / "rtl/mini/script" -FORMAL_SCRIPT_DIR = ROOT / "rtl/mini/formal" sys.path.insert(0, str(ROOT)) -sys.path.insert(0, str(FILELIST_SCRIPT_DIR)) -sys.path.insert(0, str(FORMAL_SCRIPT_DIR)) -from filelist import atomic_write, parse_filelists, write_filelist # noqa: E402 -from generate_filelist import generate_all # noqa: E402 -from generate_formal_filelist import generate as generate_formal_filelist # noqa: E402 -from generate_sby_config import render as render_sby_config # noqa: E402 +from scripts.rtl.filelist import atomic_write, parse_filelists, write_filelist # noqa: E402 +from rtl.mini.script.generate_filelist import generate_all # noqa: E402 +from rtl.mini.formal.generate_formal_filelist import generate as generate_formal_filelist # noqa: E402 +from rtl.mini.formal.generate_sby_config import render as render_sby_config # noqa: E402 from scripts.bitwuzla_smt2 import translate_arguments # noqa: E402 from scripts.analyze_warnings import normalize # noqa: E402 from scripts.check_c_warnings import self_owned_warnings # noqa: E402 @@ -870,7 +866,7 @@ def test_prepare_norflash_and_missing_firmware(tmp_path: Path) -> None: firmware = tmp_path / "firmware.hex" firmware.write_text("00\n", encoding="utf-8") sim_dir = tmp_path / "sim" - script = ROOT / "rtl/mini/script/prepare_norflash.py" + script = ROOT / "scripts/rtl/prepare_norflash.py" run( sys.executable, @@ -1043,7 +1039,7 @@ def test_make_dry_run_and_validation_do_not_write_filelists(tmp_path: Path) -> N line.startswith("MGMT_CPU_CLK_HZ") and line.rstrip().endswith("72000000") for line in mpw_config.splitlines() ) - software_makefile = (ROOT / "rtl/mini/mk/software.mk").read_text(encoding="utf-8") + software_makefile = (ROOT / "rtl/mk/software.mk").read_text(encoding="utf-8") assert "-DRS_CPU_CLOCK_HZ=$(MGMT_CPU_CLK_HZ)U" in software_makefile removed_debug = subprocess.run( @@ -1278,13 +1274,16 @@ def test_verilator_simulations_use_uniform_timeout() -> None: assert "--assert --Wall" in verilator_source regression_commands = (*SMOKE_COMMANDS, *PR_COMMANDS, *NIGHTLY_COMMANDS) - for _, values in regression_commands: + for profile, values in regression_commands: if "SIMU=VERILATOR" in values: simulation_timeout = [value for value in values if value.startswith("SOC_SIM_TIME=")] if "APP=ci_smoke" in values and "sim" in values: assert simulation_timeout == ["SOC_SIM_TIME=1800"] assert "LINK_TYPE=ld2_all_sram" in values - assert "VERILATOR_SIM_ARGS=--fast-flash" in values + if profile == "configs/ci/ihp130-tiny.mk": + assert not any(value.startswith("VERILATOR_SIM_ARGS=") for value in values) + else: + assert "VERILATOR_SIM_ARGS=--fast-flash" in values assert "HAVE_CSR=YES" in values elif "coremark-report" in values: assert simulation_timeout == ["SOC_SIM_TIME=7200"] @@ -1320,7 +1319,7 @@ def test_systemverilog_testbench_starts_in_reset_with_known_clocks() -> None: def test_management_core_is_fixed_to_hazard3_with_debug() -> None: - wrapper = (ROOT / "rtl/mini/top/mgmt_core_wrapper.sv").read_text(encoding="utf-8") + wrapper = (ROOT / "rtl/ip/core/mgmt_core_wrapper.sv").read_text(encoding="utf-8") makefile = (ROOT / "Makefile").read_text(encoding="utf-8") assert "CORE has been removed" in makefile @@ -1328,7 +1327,8 @@ def test_management_core_is_fixed_to_hazard3_with_debug() -> None: assert "CORE_$(CORE)" not in makefile assert "`ifdef CORE_" not in wrapper assert "`ifdef HAVE_DEBUG" not in wrapper - assert "ahbl2axi4 u_ahbl2axi4" in wrapper + assert re.search(r"ahbl2axi4\s*(?:#\([\s\S]*?\)\s*)?u_ahbl2axi4", wrapper) + assert re.search(r"TwoCycleBusErrors\s*=\s*1'b0", wrapper) assert ".RESET_VECTOR (`SOC_CPU_RESET_ADDR)" in wrapper assert ".DEBUG_SUPPORT (1)" in wrapper @@ -1336,8 +1336,8 @@ def test_management_core_is_fixed_to_hazard3_with_debug() -> None: def test_hazard3_debug_flow_is_locked_and_uses_remote_bitbang() -> None: lock = load_lock(ROOT / "dependencies/dependencies.lock.json") makefile = (ROOT / "Makefile").read_text(encoding="utf-8") - wrapper = (ROOT / "rtl/mini/top/mgmt_core_wrapper.sv").read_text(encoding="utf-8") - debug_wrapper = (ROOT / "rtl/mini/top/mgmt_debug_wrapper.sv").read_text(encoding="utf-8") + wrapper = (ROOT / "rtl/ip/core/mgmt_core_wrapper.sv").read_text(encoding="utf-8") + debug_wrapper = (ROOT / "rtl/ip/core/mgmt_debug_wrapper.sv").read_text(encoding="utf-8") verilator_makefile = (ROOT / "rtl/mini/mk/verilator.mk").read_text(encoding="utf-8") driver = (ROOT / "scripts/run_debug_session.py").read_text(encoding="utf-8") openocd = (ROOT / "rtl/mini/dv/verilator/openocd/retrosoc_hazard3.cfg").read_text( @@ -1466,7 +1466,7 @@ def test_rtl_regression_excludes_synthesis_and_timing() -> None: commands, profiles = select_regression("rtl", "IHP130") assert commands == RTL_COMMANDS - assert profiles == ("configs/ci/ihp130.mk",) + assert profiles == ("configs/ci/ihp130.mk", "configs/ci/ihp130-tiny.mk") values = [value for _, command_values in commands for value in command_values] assert "sim" in values assert "sim-asm" in values @@ -1535,7 +1535,7 @@ def test_hosted_regression_keeps_tools_but_skips_synthesis_execution() -> None: def test_hosted_smoke_formal_check_is_doctor_only() -> None: workflow = (ROOT / ".github/workflows/_regression.yml").read_text(encoding="utf-8") smoke = (ROOT / ".github/workflows/regression-smoke.yml").read_text(encoding="utf-8") - software_makefile = (ROOT / "rtl/mini/mk/software.mk").read_text(encoding="utf-8") + software_makefile = (ROOT / "rtl/mk/software.mk").read_text(encoding="utf-8") assert "timeout_minutes: 60" in smoke assert "formal_checks: true" in smoke @@ -1586,7 +1586,7 @@ def test_nightly_regression_runs_optional_yosys_recipes() -> None: commands, profiles = select_regression("nightly", "IHP130") assert commands == NIGHTLY_COMMANDS - assert profiles == ("configs/ci/ihp130.mk",) + assert profiles == ("configs/ci/ihp130.mk", "configs/ci/ihp130-tiny.mk") assert ( "configs/ci/ihp130.mk", ("SYNTH=YOSYS", "SYNTH_RECIPE=area", "synth"), diff --git a/tests/test_sdio.py b/tests/test_sdio.py index a8a6cac6..ccc1843f 100644 --- a/tests/test_sdio.py +++ b/tests/test_sdio.py @@ -8,7 +8,7 @@ from pathlib import Path ROOT = Path(__file__).resolve().parents[1] -CONVERTER = ROOT / "rtl/mini/script/convt_sv2v.py" +CONVERTER = ROOT / "scripts/rtl/convt_sv2v.py" BUILD = ROOT / "build/test-sdio" SDIO_FULL_SOURCES = [ diff --git a/tests/test_sdram.py b/tests/test_sdram.py index 0e2e47ff..3168bcdf 100644 --- a/tests/test_sdram.py +++ b/tests/test_sdram.py @@ -15,7 +15,7 @@ def _write_memory_map(generated: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -72,7 +72,7 @@ def test_sdram_controller_preserves_full_and_masked_writes(tmp_path: Path) -> No subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -103,7 +103,7 @@ def test_sdram_controller_preserves_data_with_micron_timing_model(tmp_path: Path subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_soc_topology.py b/tests/test_soc_topology.py index edeac8b1..b82c86d7 100644 --- a/tests/test_soc_topology.py +++ b/tests/test_soc_topology.py @@ -13,7 +13,7 @@ ROOT = Path(__file__).resolve().parents[1] TOPOLOGY = ROOT / "rtl/mini/integration/soc_topology.json" GENERATOR = ROOT / "rtl/mini/integration/generate_soc_topology.py" MEMORY_MAP = ROOT / "rtl/mini/address_map/memory_map.json" -MEMORY_MAP_GENERATOR = ROOT / "rtl/mini/address_map/generate_memory_map.py" +MEMORY_MAP_GENERATOR = ROOT / "scripts/rtl/generate_memory_map.py" def generate(output_dir: Path) -> None: @@ -574,7 +574,7 @@ def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Pa subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_spisd.py b/tests/test_spisd.py index 6d0ae275..f9cd7092 100644 --- a/tests/test_spisd.py +++ b/tests/test_spisd.py @@ -8,7 +8,7 @@ from pathlib import Path ROOT = Path(__file__).resolve().parents[1] -CONVERTER = ROOT / "rtl/mini/script/convt_sv2v.py" +CONVERTER = ROOT / "scripts/rtl/convt_sv2v.py" BUILD = ROOT / "build/test-spisd" COMMON_REGISTER = "rtl/managed/clusterip/common/rtl/utils/register.sv" INCDIRS = [ diff --git a/tests/test_sysctrl.py b/tests/test_sysctrl.py index a9e34c84..f5b41b83 100644 --- a/tests/test_sysctrl.py +++ b/tests/test_sysctrl.py @@ -40,7 +40,7 @@ def test_sysctrl_registers_lifecycle_faults_and_wake(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -78,7 +78,7 @@ def test_sysctrl_registers_lifecycle_faults_and_wake(tmp_path: Path) -> None: str(common / "cdc/cdc_sync.sv"), str(common / "clkrst/rst_sync.sv"), str(common / "cdc/cdc_rst_ctrlr.sv"), - str(TOP / "soc_common_cdc.sv"), + str(ROOT / "rtl/ip/util/soc_common_cdc.sv"), str(TOP / "data_plane_fault_cdc.sv"), str(PERIPHERAL / "pll_ctrl_if.sv"), str(PERIPHERAL / "clock_ctrl_if.sv"), @@ -97,7 +97,7 @@ def test_sysctrl_registers_lifecycle_faults_and_wake(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_timer.py b/tests/test_timer.py index 7b7f366b..39c31848 100644 --- a/tests/test_timer.py +++ b/tests/test_timer.py @@ -43,7 +43,7 @@ def test_timer_modes_interrupts_and_errors(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_tiny.py b/tests/test_tiny.py new file mode 100644 index 00000000..7c633fb7 --- /dev/null +++ b/tests/test_tiny.py @@ -0,0 +1,170 @@ +"""Tiny product isolation, generated ABI and native bus acceptance.""" + +from __future__ import annotations + +import json +import os +import shutil +import subprocess +from pathlib import Path + +import pytest + +from scripts.generate_tiny import generate_bindings, generate_filelists, read_topology +from scripts.rtl.filelist import parse_filelists +from scripts.rtl.generate_memory_map import generate as generate_memory_map + +ROOT = Path(__file__).resolve().parents[1] +TINY = ROOT / "rtl/tiny" +COMMON = ROOT / "rtl/managed/clusterip/common/rtl" + + +def run(command: list[str], **kwargs) -> subprocess.CompletedProcess: + result = subprocess.run(command, text=True, capture_output=True, **kwargs) + assert result.returncode == 0, result.stdout + result.stderr + return result + + +def test_tiny_sources_and_abi_are_independent(tmp_path: Path) -> None: + output = tmp_path / "generated" + filelists = tmp_path / "filelists" + document = read_topology(TINY / "integration/soc_topology.json", + TINY / "address_map/memory_map.json") + generate_bindings(document, output) + generate_filelists(filelists, output, ["+define+RETROSOC_SOC__TINY"]) + generate_memory_map(TINY / "address_map/memory_map.json", output / "memory_map", "YES", 128) + resolved = parse_filelists(filelists / name for name in + ("commonip.fl", "clusterip.fl", "core_hazard3.fl", "ip.fl", "top.fl")) + for source in resolved.files: + assert "/rtl/mini/" not in str(source) + assert not any(token in source.name.lower() for token in ("rib", "vexii", "radio")) + rtl = (output / "memory_map/rtl/mmap_define.svh").read_text() + sdk = (output / "memory_map/include/retrosoc/generated/memory_map.h").read_text() + assert "RIB" not in rtl + assert "SOC_ADDR_SRAM_END 32'h3001FFFF" in rtl + assert "RS_SOC_SRAM_SIZE UINT32_C(0x00020000)" in sdk + assert "RS_SOC_PSRAM_BASE" not in sdk + irq = (output / "include/retrosoc/generated/irq_metadata.h").read_text() + assert "RS_SOC_EXTERNAL_IRQ_COUNT UINT32_C(30)" in irq + assert "RS_SOC_EXT_IRQ_UART1 UINT32_C(24)" in irq + assert "RS_SOC_EXT_IRQ_DMA UINT32_C(18)" in irq + assert "RS_SOC_EXT_IRQ_NPU" not in irq + # A consumer of public SDK headers must see Tiny capabilities without + # reconstructing the firmware build's private preprocessor command line. + if shutil.which("cc"): + probe = tmp_path / "consumer.c" + probe.write_text('#include \n' + '_Static_assert(RS_DMA_CHANNEL_COUNT == 4, "wrong product");\n') + run(["cc", "-std=c11", "-Werror", "-I" + str(ROOT / "crt/include"), + "-I" + str(output / "memory_map/include"), "-I" + str(output / "include"), + "-c", str(probe), "-o", str(tmp_path / "consumer.o")]) + + +def test_tiny_topology_rejects_duplicate_irqs_and_missing_routes(tmp_path: Path) -> None: + source = json.loads((TINY / "integration/soc_topology.json").read_text()) + path = tmp_path / "invalid.json" + source["interrupts"][1]["core_bit"] = source["interrupts"][0]["core_bit"] + path.write_text(json.dumps(source)) + with pytest.raises(ValueError, match="duplicate"): + read_topology(path, TINY / "address_map/memory_map.json") + source = json.loads((TINY / "integration/soc_topology.json").read_text()) + source["apb_targets"].pop() + path.write_text(json.dumps(source)) + with pytest.raises(ValueError, match="every APB"): + read_topology(path, TINY / "address_map/memory_map.json") + + +@pytest.mark.parametrize("override", ["HAVE_HP=YES", "PDK=GF180", "MINI_MODE=PRODUCT", + "LINK_TYPE=ld2_psram", "APP=hp_boot", "HAVE_PLL=YES"]) +def test_tiny_rejects_incompatible_profiles(override: str) -> None: + result = subprocess.run( + ["make", "CONFIG=configs/ci/ihp130-tiny.mk", override, "config"], + cwd=ROOT, text=True, capture_output=True, + ) + assert result.returncode != 0 + assert "TINY" in result.stderr + + +@pytest.mark.parametrize("simulator", ["verilator", "iverilog"]) +@pytest.mark.parametrize("block", ["fabric", "sysctrl"]) +def test_tiny_protocol_contracts(tmp_path: Path, simulator: str, block: str) -> None: + if not shutil.which(simulator) or not (COMMON / "interface/axi4_if.sv").exists(): + pytest.skip("locked RTL/tool dependency unavailable") + generated = tmp_path / "map" + generate_memory_map(TINY / "address_map/memory_map.json", generated, "YES", 128) + top = "tiny_axi4_fabric_tb" if block == "fabric" else "tiny_sysctrl_tb" + sources = [COMMON / "utils/register.sv"] + if block == "fabric": + sources += [COMMON / "interface/axi4_if.sv", COMMON / "stream/round_robin_arbiter.sv", + ROOT / "rtl/ip/interconnect/axi4_error_slave.sv", TINY / "top/tiny_axi4_fabric.sv"] + else: + sources += [COMMON / "interface/apb4_if.sv", TINY / "top/tiny_sysctrl.sv"] + sources.append(ROOT / "tests/rtl" / f"{top}.sv") + includes = [f"-I{p}" for p in (COMMON, COMMON / "interface", generated / "rtl", + ROOT / "rtl/ip/peripheral", ROOT / "tests/rtl")] + output = tmp_path / "sim" + if simulator == "verilator": + cache = tmp_path / "cache" + cache.mkdir() + run([simulator, "--binary", "--timing", "--assert", "-Wno-fatal", + "-DSV_ASSRT_DISABLE", "--top-module", top, + *includes, *(str(p) for p in sources), "--Mdir", str(tmp_path / "obj"), + "-o", str(output)], + env={**os.environ, "CCACHE_DIR": str(cache), "CCACHE_TEMPDIR": str(cache)}) + command = [str(output)] + else: + if not shutil.which("sv2v"): + pytest.skip("sv2v unavailable") + converted = tmp_path / "converted.v" + conversion = run(["sv2v", "-DSV_ASSRT_DISABLE", *includes, *(str(p) for p in sources)]) + converted.write_text(conversion.stdout) + run([simulator, "-g2012", "-s", top, "-o", str(output), str(converted)]) + command = ["vvp", str(output)] + result = run(command, timeout=60) + assert ("SIM_TEST_PASS Tiny fabric" if block == "fabric" else "SIM_TEST_PASS Tiny SYSCTRL") in result.stdout + assert not any(marker in result.stdout for marker in ("SIM_TEST_FAIL", "FATAL", "%Error")) + + +def test_tiny_product_prose_does_not_restore_legacy_sdk_names(tmp_path: Path) -> None: + from scripts.check_embedded_c import load_policy, policy_issues + + path = tmp_path / "crt/probe.c" + path.parent.mkdir() + policy = load_policy(ROOT) + path.write_text('/* Tiny product */\nconst char *rs_name = "Tiny MCU";\n') + assert policy_issues(tmp_path, path, policy) == [] + path.write_text('void tiny_uart_init(void);\n') + assert any("retired tiny" in issue for issue in policy_issues(tmp_path, path, policy)) + path.write_text('#include \n') + assert any("legacy include" in issue for issue in policy_issues(tmp_path, path, policy)) + + +def test_tiny_metrics_use_product_top_and_timestamped_yosys_report(tmp_path: Path) -> None: + import argparse + from scripts.metrics import collect + + (tmp_path / "meta").mkdir() + (tmp_path / "meta/manifest.json").write_text('{"configuration": {"SOC": "TINY"}}') + report = tmp_path / "syn/yosys/rpt" + report.mkdir(parents=True) + (report / "retrosoc_tiny_asic_area.json").write_text( + '[00001.250000] {"design": {"area": 123.5, "num_cells": 42}}\n') + output = tmp_path / "meta/metrics.json" + assert collect(argparse.Namespace(variant_root=tmp_path, synth_root=None, sta_root=None, + recipe="balanced", output=output)) == 0 + data = json.loads(output.read_text()) + assert data["synthesis"]["top_area"] == 123.5 + assert data["synthesis"]["top_cells"] == 42 + + +def test_tiny_regression_does_not_require_mini_sources() -> None: + import sys + + result = run([sys.executable, str(ROOT / "scripts/regress.py"), "--root", str(ROOT), + "--suite", "pr", "--pdk", "IHP130", "--soc", "TINY", "--dry-run"]) + commands = result.stdout.splitlines() + assert commands + assert all("CONFIG=configs/ci/ihp130-tiny.mk" in line for line in commands) + assert any("SYNTH=YOSYS synth" in line for line in commands) + assert any("netsim-boot" in line for line in commands) + assert any("STA=OPENSTA sta" in line for line in commands) diff --git a/tests/test_uart.py b/tests/test_uart.py index ed9e132a..22c1be61 100644 --- a/tests/test_uart.py +++ b/tests/test_uart.py @@ -52,7 +52,7 @@ def test_uart_register_fifo_loopback_flow_control_and_errors(tmp_path: Path) -> subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_usb2.py b/tests/test_usb2.py index f9b94306..df264677 100644 --- a/tests/test_usb2.py +++ b/tests/test_usb2.py @@ -9,7 +9,7 @@ from pathlib import Path ROOT = Path(__file__).resolve().parents[1] BUILD = ROOT / "build/test-usb2" -CONVERTER = ROOT / "rtl/mini/script/convt_sv2v.py" +CONVERTER = ROOT / "scripts/rtl/convt_sv2v.py" def test_usb2_drain_stream_has_registered_ready_cut() -> None: diff --git a/tests/test_ws2812.py b/tests/test_ws2812.py index a60bc57a..fa95162d 100644 --- a/tests/test_ws2812.py +++ b/tests/test_ws2812.py @@ -45,7 +45,7 @@ def test_ws2812_register_waveform_streaming_and_errors(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", @@ -72,7 +72,7 @@ def test_ws2812_accepts_dma_fixed_destination_backpressure(tmp_path: Path) -> No subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/address_map/generate_memory_map.py"), + str(ROOT / "scripts/rtl/generate_memory_map.py"), "--map", str(ROOT / "rtl/mini/address_map/memory_map.json"), "--output-dir", @@ -121,7 +121,7 @@ def test_ws2812_accepts_dma_fixed_destination_backpressure(tmp_path: Path) -> No subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output", diff --git a/tests/test_xpi_io.py b/tests/test_xpi_io.py index 1a8a2144..9d182a2f 100644 --- a/tests/test_xpi_io.py +++ b/tests/test_xpi_io.py @@ -39,7 +39,7 @@ def test_xpi_releases_data_pads_while_receiving(tmp_path: Path) -> None: subprocess.run( [ sys.executable, - str(ROOT / "rtl/mini/script/convt_sv2v.py"), + str(ROOT / "scripts/rtl/convt_sv2v.py"), "-f", str(source_list), "--output",