From a6ef598aa2d501635b59b8c3479d82c48078f460 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 6 Feb 2025 15:40:15 +0800 Subject: [PATCH] feat: chg flash addr to cust spi flash ctrl --- crt/sections.lds | 2 +- rtl/ip/axil_ip_wrapper.v | 2 +- rtl/ip/cust/axil2apb/apb_master.v | 10 +++++++--- rtl/ip/cust/axil2apb/axi_apb_bridge.v | 6 ------ rtl/retrosoc.v | 4 ++-- rtl/retrosoc_tb.v | 16 ++++++++-------- 6 files changed, 19 insertions(+), 21 deletions(-) diff --git a/crt/sections.lds b/crt/sections.lds index c6b39acc..6995c0cf 100644 --- a/crt/sections.lds +++ b/crt/sections.lds @@ -1,7 +1,7 @@ MEMORY { - FLASH (rx) : ORIGIN = 0x00100000, LENGTH = 0x1000000 /* entire flash, 16 MiB */ + FLASH (rx) : ORIGIN = 0x30000000, LENGTH = 0x1000000 /* entire flash, 16 MiB */ /*FLASH (rx) : ORIGIN = 0x00100000, LENGTH = 0x400000 entire flash, 4 MiB*/ RAM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x10000 /* 64KB */ } diff --git a/rtl/ip/axil_ip_wrapper.v b/rtl/ip/axil_ip_wrapper.v index f192c021..276173ef 100644 --- a/rtl/ip/axil_ip_wrapper.v +++ b/rtl/ip/axil_ip_wrapper.v @@ -215,7 +215,7 @@ module axil_ip_wrapper ( .c_apb_num_slaves(APB_SLAVES_NUM), .memory_regions1 (MEM_REGIONS1), .memory_regions2 (MEM_REGIONS2), - .timeout_val (1), + .timeout_val (32'hFFFF_FFFF), .APB_Protocol (4) ) u_axi_apb_bridge ( .s_axi_clk (clk_i), diff --git a/rtl/ip/cust/axil2apb/apb_master.v b/rtl/ip/cust/axil2apb/apb_master.v index e5191c85..072e9624 100644 --- a/rtl/ip/cust/axil2apb/apb_master.v +++ b/rtl/ip/cust/axil2apb/apb_master.v @@ -27,6 +27,10 @@ module apb_master #( reg [1:0] state; + // for select ongoing slave + wire s_filter_pready = |(SSEL & PREADY); + // PREADY & SSEL + // 0111 & 1000 = 0000 always @(posedge PCLK) begin if (!PRESETn) state <= Idle; if (state == Idle) begin @@ -34,9 +38,9 @@ module apb_master #( else state <= Idle; end else if (state == Setup) state <= Access; else if (state == Access) begin - if (PREADY && STREQ) state <= Setup; - else if (PREADY && ~STREQ) state <= Idle; - else if (~PREADY) state <= Access; + if (s_filter_pready && STREQ) state <= Setup; + else if (s_filter_pready && ~STREQ) state <= Idle; + else if (~s_filter_pready) state <= Access; else state <= Idle; end else state <= Idle; diff --git a/rtl/ip/cust/axil2apb/axi_apb_bridge.v b/rtl/ip/cust/axil2apb/axi_apb_bridge.v index 40c29219..a8eacbb9 100644 --- a/rtl/ip/cust/axil2apb/axi_apb_bridge.v +++ b/rtl/ip/cust/axil2apb/axi_apb_bridge.v @@ -1,9 +1,3 @@ -/* -`include "apb_master.v" -`include "address_decoder.v" -`include "read_data_mux.v" -`include "flop.v" -*/ module axi_apb_bridge #( parameter c_apb_num_slaves = 1, diff --git a/rtl/retrosoc.v b/rtl/retrosoc.v index d3321259..b919ea61 100644 --- a/rtl/retrosoc.v +++ b/rtl/retrosoc.v @@ -35,8 +35,8 @@ module retrosoc #( parameter integer MEM_WORDS = 16384, parameter [31:0] STACKADDR = (4 * MEM_WORDS), // end of memory - // parameter [31:0] PROGADDR_RESET = 32'h3000_0000, // flash - parameter [31:0] PROGADDR_RESET = 32'h0010_0000, // flash + parameter [31:0] PROGADDR_RESET = 32'h3000_0000, // flash + // parameter [31:0] PROGADDR_RESET = 32'h0010_0000, // flash parameter PSRAM_NUM = 4 ) ( input clk_i, diff --git a/rtl/retrosoc_tb.v b/rtl/retrosoc_tb.v index 3235e249..0b665f29 100644 --- a/rtl/retrosoc_tb.v +++ b/rtl/retrosoc_tb.v @@ -132,14 +132,14 @@ module retrosoc_tb; // .Vpp_W_DQ2() // ); - spiflash u_spiflash ( - .csb(s_flash_csb), - .clk(s_flash_clk), - .io0(s_flash_io0), // MOSI - .io1(s_flash_io1), // MISO - .io2(s_flash_io2), - .io3(s_flash_io3) - ); + // spiflash u_spiflash ( + // .csb(s_flash_csb), + // .clk(s_flash_clk), + // .io0(s_flash_io0), // MOSI + // .io1(s_flash_io1), // MISO + // .io2(s_flash_io2), + // .io3(s_flash_io3) + // ); N25Qxxx u_N25Qxxx ( .C_ (s_cust_spfs_clk_o),