From bd423766abb6f12c85242d275bf6a48b73dba338 Mon Sep 17 00:00:00 2001
From: maksyuki <maksyuki@126.com>
Date: Fri, 31 Jan 2025 01:14:08 +0800
Subject: [PATCH] feat: add xtal pad into the tech module

---
 tech/tc_clk.v  |  2 +-
 tech/tc_io.v   | 12 +++++++++++-
 tech/tc_sram.v | 48 ++++++++++++++++++++++++------------------------
 3 files changed, 36 insertions(+), 26 deletions(-)

diff --git a/tech/tc_clk.v b/tech/tc_clk.v
index 5ad2cc2d..4aad7425 100644
--- a/tech/tc_clk.v
+++ b/tech/tc_clk.v
@@ -81,4 +81,4 @@ module ihp_clk_gating #(
   assign clk_o = clk_i;
   //   end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/tech/tc_io.v b/tech/tc_io.v
index 3d8e0cb3..1e417f68 100644
--- a/tech/tc_io.v
+++ b/tech/tc_io.v
@@ -1,3 +1,13 @@
+module ihp_io_xtl_pad (
+    input  xi_pad,
+    output xo_pad,
+    input  en,
+    output clk
+);
+
+  assign clk = en ? xi_pad : 1'b0;
+endmodule
+
 module ihp_io_tri_pad (
     inout  pad,
     input  c2p,
@@ -13,4 +23,4 @@ module ihp_io_tri_pad (
       .p2c   (p2c)
   );
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/tech/tc_sram.v b/tech/tc_sram.v
index b8c61956..afb7f211 100644
--- a/tech/tc_sram.v
+++ b/tech/tc_sram.v
@@ -53,27 +53,27 @@ module tc_sram_1024x32 (
 endmodule
 
 // 4KB
-module SPRAM1024X16 (
-    input             clk_i,
-    input             cs_i,
-    input      [ 9:0] addr_i,
-    input      [15:0] data_i,
-    input      [ 3:0] mask_i,
-    input             wren_i,
-    output reg [15:0] data_o
-);
-  reg [15:0] mem[0:1023];
-  always @(posedge clk_i) begin
-    if (cs_i) begin
-      if (!wren_i) begin
-        data_o <= mem[addr_i];
-      end else begin
-        if (mask_i[0]) mem[addr_i][7:0] <= data_i[7:0];
-        if (mask_i[1]) mem[addr_i][15:8] <= data_i[15:8];
-        if (mask_i[2]) mem[addr_i][23:16] <= data_i[23:16];
-        if (mask_i[3]) mem[addr_i][31:24] <= data_i[31:24];
-        data_o <= 32'bx;
-      end
-    end
-  end
-endmodule
+// module SPRAM1024X16 (
+//     input             clk_i,
+//     input             cs_i,
+//     input      [ 9:0] addr_i,
+//     input      [15:0] data_i,
+//     input      [ 3:0] mask_i,
+//     input             wren_i,
+//     output reg [15:0] data_o
+// );
+//   reg [15:0] mem[0:1023];
+//   always @(posedge clk_i) begin
+//     if (cs_i) begin
+//       if (!wren_i) begin
+//         data_o <= mem[addr_i];
+//       end else begin
+//         if (mask_i[0]) mem[addr_i][7:0] <= data_i[7:0];
+//         if (mask_i[1]) mem[addr_i][15:8] <= data_i[15:8];
+//         if (mask_i[2]) mem[addr_i][23:16] <= data_i[23:16];
+//         if (mask_i[3]) mem[addr_i][31:24] <= data_i[31:24];
+//         data_o <= 32'bx;
+//       end
+//     end
+//   end
+// endmodule