diff --git a/app/network/userip/userip.mk b/app/network/userip/userip.mk
index 1551aad3..1c013aae 100644
--- a/app/network/userip/userip.mk
+++ b/app/network/userip/userip.mk
@@ -1,2 +1,2 @@
 APP_SRCS     += $(ROOT_PATH)/app/network/userip/src/user_ip_demo.c
-APP_INC_DIRS += $(ROOT_PATH)/app/network/userip/include
+APP_INC_DIRS += $(ROOT_PATH)/app/network/userip/include
\ No newline at end of file
diff --git a/rtl/mini/mk/software.mk b/rtl/mini/mk/software.mk
index da161d23..62e576c7 100644
--- a/rtl/mini/mk/software.mk
+++ b/rtl/mini/mk/software.mk
@@ -213,4 +213,4 @@ firmware: $(FIRMWARE_ELF)
 
 firmware asm: | manifest
 
-.PHONY: FORCE_VERSION
+.PHONY: FORCE_VERSION
\ No newline at end of file
diff --git a/rtl/mini/top/rcu.sv b/rtl/mini/top/rcu.sv
index 06d90e64..0d97ab51 100644
--- a/rtl/mini/top/rcu.sv
+++ b/rtl/mini/top/rcu.sv
@@ -22,6 +22,7 @@ module rcu #(
            pll_ctrl_if.rcu pll_ctrl,
     output logic           sys_clk_o,
     output logic           sys_rst_n_o,
+    output logic           aud_clk_o,
     output logic           aud_rst_n_o,
     output logic           sys_clkdiv4_o,
     output logic           timebase_tick_o
@@ -190,6 +191,7 @@ module rcu #(
   );
 
   assign sys_rst_n_o          = s_sys_rst_n_sync;
+  assign aud_clk_o            = s_aud_clk_buf;
   assign aud_rst_n_o          = s_aud_rst_n_sync;
   assign sys_clkdiv4_o        = s_sys_clkdiv4_q;
   assign s_sys_reset_source_n = ext_rst_n_i && !wdg_reset_req_i;
diff --git a/rtl/mini/top/retrosoc_asic.sv b/rtl/mini/top/retrosoc_asic.sv
index 82da2aed..a28bb43f 100644
--- a/rtl/mini/top/retrosoc_asic.sv
+++ b/rtl/mini/top/retrosoc_asic.sv
@@ -58,6 +58,7 @@ module retrosoc_asic (
 );
   logic s_ext_clk;
   logic s_aud_clk;
+  logic s_aud_clk_buf;
   logic s_sys_clkdiv4;
   logic s_timebase_tick;
 `ifdef HAVE_PLL
@@ -105,6 +106,7 @@ rcu #(
       .pll_ctrl       (u_pll_ctrl_if),
       .sys_clk_o      (s_sys_clk),
       .sys_rst_n_o    (s_sys_rst_n),
+      .aud_clk_o      (s_aud_clk_buf),
       .aud_rst_n_o    (s_aud_rst_n),
       .sys_clkdiv4_o  (s_sys_clkdiv4),
       .timebase_tick_o(s_timebase_tick)
@@ -120,7 +122,7 @@ rcu #(
   retrosoc u_retrosoc (
       .clk_i          (s_sys_clk),
       .rst_n_i        (s_sys_rst_n),
-      .clk_aud_i      (s_aud_clk),
+      .clk_aud_i      (s_aud_clk_buf),
       .rst_aud_n_i    (s_aud_rst_n),
       .clkdiv4_i      (s_sys_clkdiv4),
       .timebase_tick_i(s_timebase_tick),
diff --git a/tests/rtl/pll_ctrl_tb.sv b/tests/rtl/pll_ctrl_tb.sv
index 65f1091a..9161df9c 100644
--- a/tests/rtl/pll_ctrl_tb.sv
+++ b/tests/rtl/pll_ctrl_tb.sv
@@ -12,6 +12,7 @@ module pll_ctrl_tb;
   logic        fault_reserved_i = 1'b0;
   logic        sys_clk_o;
   logic        sys_rst_n_o;
+  logic        aud_clk_o;
   logic        aud_rst_n_o;
   logic        sys_clkdiv4_o;
   apb4_if apb4 (
@@ -39,6 +40,7 @@ module pll_ctrl_tb;
       .pll_ctrl       (pll_ctrl),
       .sys_clk_o      (sys_clk_o),
       .sys_rst_n_o    (sys_rst_n_o),
+      .aud_clk_o      (aud_clk_o),
       .aud_rst_n_o    (aud_rst_n_o),
       .sys_clkdiv4_o  (sys_clkdiv4_o),
       .timebase_tick_o()
@@ -128,6 +130,18 @@ module pll_ctrl_tb;
     sysctrl.rtc_wake_i      = 1'b0;
     #100;
     rst_n_i = 1'b1;
+    repeat (2) begin
+      @(posedge aud_clk_i);
+      #1;
+      if (aud_clk_o !== 1'b1) begin
+        $fatal(1, "buffered audio clock did not follow a rising edge");
+      end
+      @(negedge aud_clk_i);
+      #1;
+      if (aud_clk_o !== 1'b0) begin
+        $fatal(1, "buffered audio clock did not follow a falling edge");
+      end
+    end
     wait (aud_rst_n_o);
     repeat (12) @(posedge sys_clk_o);
 
diff --git a/tests/test_sta_constraints.py b/tests/test_sta_constraints.py
index dbd4d183..59cc153a 100644
--- a/tests/test_sta_constraints.py
+++ b/tests/test_sta_constraints.py
@@ -5,6 +5,7 @@ from __future__ import annotations
 import hashlib
 import io
 import json
+import re
 import subprocess
 import sys
 import tarfile
@@ -16,6 +17,8 @@ DOMAINS = ROOT / "rtl/mini/integration/clock_reset_domains.json"
 PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json"
 GENERATOR = ROOT / "physical/smoke/sta/opensta/generate_sdc.py"
 OPENSTA_MAKEFILE = ROOT / "physical/smoke/sta/opensta/opensta.mk"
+RCU = ROOT / "rtl/mini/top/rcu.sv"
+RETROSOC_ASIC = ROOT / "rtl/mini/top/retrosoc_asic.sv"
 GF180_GENERATOR = ROOT / "physical/pdk/generate_gf180_liberty.py"
 ICS55_PREPARER = ROOT / "physical/pdk/prepare_ics55_liberty.py"
 ICS55_SIM_MODEL_PREPARER = ROOT / "physical/pdk/prepare_ics55_sim_model.py"
@@ -59,6 +62,17 @@ def test_core_sdc_covers_current_clock_domains(tmp_path: Path) -> None:
     assert "set_false_path -from $reset_ext_rst_n_i_pad" in sdc
 
 
+def test_audio_sdc_root_drives_the_functional_audio_domain() -> None:
+    rcu = RCU.read_text(encoding="utf-8")
+    asic = RETROSOC_ASIC.read_text(encoding="utf-8")
+
+    assert re.search(r"\boutput\s+logic\s+aud_clk_o\b", rcu) is not None
+    assert re.search(r"\bassign\s+aud_clk_o\s*=\s*s_aud_clk_buf\s*;", rcu) is not None
+    assert re.search(r"\.aud_clk_o\s*\(s_aud_clk_buf\)", asic) is not None
+    assert re.search(r"\.clk_aud_i\s*\(s_aud_clk_buf\)", asic) is not None
+    assert re.search(r"\.clk_aud_i\s*\(s_aud_clk\)", asic) is None
+
+
 def test_opensta_invocation_exits_after_a_tcl_error() -> None:
     makefile = OPENSTA_MAKEFILE.read_text(encoding="utf-8")