diff --git a/crt/include/retrosoc/core/soc.h b/crt/include/retrosoc/core/soc.h
index 8692658c..94cd4448 100644
--- a/crt/include/retrosoc/core/soc.h
+++ b/crt/include/retrosoc/core/soc.h
@@ -148,8 +148,6 @@
 #define RS_SOC_SYSCTRL_REG32(offset) RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, (offset))
 #define reg_sysctrl_coresel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x00))
 #define reg_sysctrl_ipsel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x04))
-#define reg_sysctrl_i2csel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x08))
-#define reg_sysctrl_qspicsel RS_SOC_REG32(RS_SOC_NMI_SYSCTRL_BASE, UINT32_C(0x0C))
 /* Status: bit 0 pending (W1C), bit 1 write, bits 3:2 reason (1 unmapped, 2 reserved). */
 #define reg_sysctrl_bus_fault_status RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_STATUS_OFFSET)
 #define reg_sysctrl_bus_fault_addr RS_SOC_SYSCTRL_REG32(RS_SOC_SYSCTRL_FAULT_ADDR_OFFSET)
diff --git a/rtl/ip/native/peripheral/sysctrl.sv b/rtl/ip/native/peripheral/sysctrl.sv
index 02617fc8..729b8113 100644
--- a/rtl/ip/native/peripheral/sysctrl.sv
+++ b/rtl/ip/native/peripheral/sysctrl.sv
@@ -14,8 +14,6 @@
 // verilog_format: off
 `define NATV_SYSCTRL_CORESEL 8'h00 // RO
 `define NATV_SYSCTRL_IPSEL   8'h04 // WR/RD
-`define NATV_SYSCTRL_I2CSEL  8'h08 // WR/RD
-`define NATV_SYSCTRL_QSPISEL 8'h0C // WR/RD
 `define NATV_SYSCTRL_FAULT_STATUS `SOC_SYSCTRL_FAULT_STATUS_OFFSET // W1C/RD
 `define NATV_SYSCTRL_FAULT_ADDR   `SOC_SYSCTRL_FAULT_ADDR_OFFSET   // RD
 `define NATV_SYSCTRL_FAULT_COUNT  `SOC_SYSCTRL_FAULT_COUNT_OFFSET  // RD
@@ -29,10 +27,8 @@
 interface sysctrl_if ();
   logic [`USER_CORESEL_WIDTH-1:0] core_sel_i;
   logic [  `USER_IPSEL_WIDTH-1:0] ip_sel_o;
-  logic                           i2c_sel_o;
-  logic                           qspi_sel_o;
 
-  modport dut(input core_sel_i, output ip_sel_o, output i2c_sel_o, output qspi_sel_o);
+  modport dut(input core_sel_i, output ip_sel_o);
 endinterface
 
 module nmi_sysctrl (
@@ -56,10 +52,6 @@ module nmi_sysctrl (
   logic [`USER_CORESEL_WIDTH-1:0] s_sysctrl_coresel_d, s_sysctrl_coresel_q;
   logic s_sysctrl_ipsel_en;
   logic [`USER_IPSEL_WIDTH-1:0] s_sysctrl_ipsel_d, s_sysctrl_ipsel_q;
-  logic s_sysctrl_i2csel_en;
-  logic s_sysctrl_i2csel_d, s_sysctrl_i2csel_q;
-  logic s_sysctrl_qspisel_en;
-  logic s_sysctrl_qspisel_d, s_sysctrl_qspisel_q;
   logic s_fault_status_clear;
   logic s_fault_pending_d, s_fault_pending_q;
   logic s_fault_write_d, s_fault_write_q;
@@ -72,9 +64,7 @@ module nmi_sysctrl (
   assign nmi.ready           = s_nmi_ready_q;
   assign nmi.rdata           = s_nmi_rdata_q;
 
-  assign sysctrl.ip_sel_o    = s_sysctrl_ipsel_q;
-  assign sysctrl.i2c_sel_o   = s_sysctrl_i2csel_q;
-  assign sysctrl.qspi_sel_o  = s_sysctrl_qspisel_q;
+  assign sysctrl.ip_sel_o = s_sysctrl_ipsel_q;
 
   assign s_sysctrl_coresel_d = sysctrl.core_sel_i;
   dffr #(`USER_CORESEL_WIDTH) u_sysctrl_coresel_dffr (
@@ -94,26 +84,6 @@ module nmi_sysctrl (
       s_sysctrl_ipsel_q
   );
 
-  assign s_sysctrl_i2csel_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SYSCTRL_I2CSEL;
-  assign s_sysctrl_i2csel_d  = nmi.wdata[0];
-  dffer #(1) u_sysctrl_i2csel_dffer (
-      clk_i,
-      rst_n_i,
-      s_sysctrl_i2csel_en,
-      s_sysctrl_i2csel_d,
-      s_sysctrl_i2csel_q
-  );
-
-  assign s_sysctrl_qspisel_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SYSCTRL_QSPISEL;
-  assign s_sysctrl_qspisel_d  = nmi.wdata[0];
-  dffer #(1) u_sysctrl_qspisel_dffer (
-      clk_i,
-      rst_n_i,
-      s_sysctrl_qspisel_en,
-      s_sysctrl_qspisel_d,
-      s_sysctrl_qspisel_q
-  );
-
   assign s_fault_status_clear = s_nmi_wr_hdshk &&
                                 nmi.addr[7:0] == `NATV_SYSCTRL_FAULT_STATUS &&
                                 nmi.wstrb[0] && nmi.wdata[0];
@@ -182,8 +152,6 @@ module nmi_sysctrl (
       // verilog_format: off
       `NATV_SYSCTRL_CORESEL: s_nmi_rdata_d = {{(32 - `USER_CORESEL_WIDTH) {1'b0}}, s_sysctrl_coresel_q};
       `NATV_SYSCTRL_IPSEL:   s_nmi_rdata_d = {{(32 - `USER_IPSEL_WIDTH) {1'b0}}, s_sysctrl_ipsel_q};
-      `NATV_SYSCTRL_I2CSEL:  s_nmi_rdata_d = {31'd0, s_sysctrl_i2csel_q};
-      `NATV_SYSCTRL_QSPISEL: s_nmi_rdata_d = {31'd0, s_sysctrl_qspisel_q};
       `NATV_SYSCTRL_FAULT_STATUS: s_nmi_rdata_d = {28'd0, s_fault_reason_q, s_fault_write_q, s_fault_pending_q};
       `NATV_SYSCTRL_FAULT_ADDR:   s_nmi_rdata_d = s_fault_addr_q;
       `NATV_SYSCTRL_FAULT_COUNT:  s_nmi_rdata_d = s_fault_count_q;
diff --git a/tests/test_memory_map.py b/tests/test_memory_map.py
index dc256cc5..9d34d778 100644
--- a/tests/test_memory_map.py
+++ b/tests/test_memory_map.py
@@ -177,3 +177,20 @@ def test_sysctrl_fault_registers_record_and_clear_pending(tmp_path: Path) -> Non
     )
     result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
     assert "sysctrl fault registers test passed" in result.stdout
+
+
+def test_sysctrl_does_not_expose_unused_i2c_or_qspi_select_registers() -> None:
+    rtl = (ROOT / "rtl/ip/native/peripheral/sysctrl.sv").read_text(encoding="utf-8")
+    header = (ROOT / "crt/include/retrosoc/core/soc.h").read_text(encoding="utf-8")
+
+    for symbol in (
+        "NATV_SYSCTRL_I2CSEL",
+        "NATV_SYSCTRL_QSPISEL",
+        "i2c_sel_o",
+        "qspi_sel_o",
+        "s_sysctrl_i2csel",
+        "s_sysctrl_qspisel",
+    ):
+        assert symbol not in rtl
+    assert "reg_sysctrl_i2csel" not in header
+    assert "reg_sysctrl_qspicsel" not in header