From fdc26d4c16a8ae57b377d942185f3edbc15701e2 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 1 Feb 2025 16:46:08 +0800 Subject: [PATCH] feat: reassign all mmio ip addrs --- rtl/firmware.c | 56 +++++++++++++++++++++------------------- rtl/firmware.h | 69 ++++++++++++++++++++++++++++---------------------- 2 files changed, 69 insertions(+), 56 deletions(-) diff --git a/rtl/firmware.c b/rtl/firmware.c index 971b456f..008e4762 100644 --- a/rtl/firmware.c +++ b/rtl/firmware.c @@ -581,39 +581,43 @@ void print_reg(char *info, uint32_t val, int digits) void ip_counter_timer_test() { print("[IP] counter timer test\n"); - print_reg("[TIM VALUE] ", reg_timer_value, 8); - print_reg("[TIM CONFIG] ", reg_timer_config, 8); + print_reg("[TIM0 VALUE] ", reg_timer0_value, 8); + print_reg("[TIM0 CONFIG] ", reg_timer0_config, 8); + print_reg("[TIM1 VALUE] ", reg_timer1_value, 8); + print_reg("[TIM1 CONFIG] ", reg_timer1_config, 8); - reg_timer_value = (uint32_t)0xffffffff; - // reg_timer_config = 1; - // reg_timer_config = 2; - // reg_timer_config = 4; // One-shot mode, where the counter triggers an interrupt when it reaches the value of reg_timer_data - reg_timer_config = 8; // 1000, timer enable, continuous mode, count down, irq disable - // reg_timer_config = 15; + reg_timer0_value = (uint32_t)0xffffffff; + reg_timer0_config = (uint32_t)0x0001; // irq disable, count down, continuous mode, timer enable - print_reg("[TIM VALUE] ", reg_timer_value, 8); - print_reg("[TIM CONFIG] ", reg_timer_config, 8); + reg_timer1_value = (uint32_t)0x0000ffff; + reg_timer1_config = (uint32_t)0x0101; // irq disable, count up, continuous mode, timer enable + + print_reg("[TIM0 VALUE] ", reg_timer0_value, 8); + print_reg("[TIM0 CONFIG] ", reg_timer0_config, 8); + print_reg("[TIM1 VALUE] ", reg_timer1_value, 8); + print_reg("[TIM1 CONFIG] ", reg_timer1_config, 8); for (int i = 0; i < 10; ++i) { - print_reg("[TIM DATA] ", reg_timer_data, 8); + print_reg("[TIM0 DATA] ", reg_timer0_data, 8); + print_reg("[TIM1 DATA] ", reg_timer1_data, 8); } } void ip_gpio_test() { print("[IP] gpio test\n"); - reg_gpio_pub = 0x5a5a; // NOT(pullup) - reg_gpio_enb = 0xa5a5; // NOT(output enable) - reg_gpio_data = 0xffff; - reg_gpio_data = 0x0000; - for (int i = 0; i < 10; ++i) - { - print("[GPIO] "); - print_hex(reg_gpio_data, 7); - print("\n"); - } + print_reg("[GPIO ENB] ", reg_gpio_enb, 8); + reg_gpio_enb = (uint32_t)0x0000; + print_reg("[GPIO ENB] ", reg_gpio_enb, 8); + + print_reg("[GPIO DATA] ", reg_gpio_data, 8); + reg_gpio_data = (uint32_t)0xffff; + print_reg("[GPIO DATA] ", reg_gpio_data, 8); + + reg_gpio_data = (uint32_t)0x0000; + print_reg("[GPIO DATA] ", reg_gpio_data, 8); } void i2c_init(unsigned int pre) @@ -687,14 +691,14 @@ void main() // print("\n"); // cmd_read_flash_id(); // cmd_read_flash_regs(); - cmd_print_spi_state(); + // cmd_print_spi_state(); - ip_counter_timer_test(); - // ip_gpio_test(); + // ip_counter_timer_test(); + ip_gpio_test(); ip_i2c_test(); - cmd_benchmark(true, 0); + // cmd_benchmark(true, 0); // cmd_benchmark_all(); - cmd_memtest(); + // cmd_memtest(); cmd_echo(); while (1) ; diff --git a/rtl/firmware.h b/rtl/firmware.h index afa61654..ad30ad9f 100644 --- a/rtl/firmware.h +++ b/rtl/firmware.h @@ -4,45 +4,54 @@ #include #include -// memory map definitions +// memory map io definitions #define reg_spictrl (*(volatile uint32_t*)0x02000000) -#define reg_uart_clkdiv (*(volatile uint32_t*)0x03000078) -#define reg_uart_data (*(volatile uint32_t*)0x0300007c) -// NOTE: "config" subsumes "control" and "prescale" fields. -#define reg_i2c_config (*(volatile uint32_t*)0x030000d4) -#define reg_i2c_control (*(volatile uint16_t*)0x030000d6) -#define reg_i2c_prescale (*(volatile uint16_t*)0x030000d4) -// NOTE: "status" and "command" are the same byte (one read, one write) -#define reg_i2c_status (*(volatile uint32_t*)0x030000d8) -#define reg_i2c_command (*(volatile uint32_t*)0x030000d8) -#define reg_i2c_data (*(volatile uint32_t*)0x030000dc) - -#define reg_timer_config (*(volatile uint32_t*)0x030000f4) -#define reg_timer_value (*(volatile uint32_t*)0x030000f8) -#define reg_timer_data (*(volatile uint32_t*)0x030000fc) - -#define reg_spi_config (*(volatile uint32_t*)0x030000b8) -#define reg_spi_data (*(volatile uint32_t*)0x030000bc) #define reg_gpio_data (*(volatile uint32_t*)0x03000000) #define reg_gpio_enb (*(volatile uint32_t*)0x03000004) #define reg_gpio_pub (*(volatile uint32_t*)0x03000008) #define reg_gpio_pdb (*(volatile uint32_t*)0x0300000c) -#define reg_spi_commconfig (*(volatile uint32_t*)0x03000080) -#define reg_spi_enables (*(volatile uint32_t*)0x03000084) -#define reg_spi_pll_config (*(volatile uint32_t*)0x03000088) -#define reg_spi_mfgr_id (*(volatile uint32_t*)0x0300008c) -#define reg_spi_prod_id (*(volatile uint32_t*)0x03000090) -#define reg_spi_mask_rev (*(volatile uint32_t*)0x03000094) -#define reg_spi_pll_bypass (*(volatile uint32_t*)0x03000098) +#define reg_uart_clkdiv (*(volatile uint32_t*)0x03000010) +#define reg_uart_data (*(volatile uint32_t*)0x03000014) -#define reg_xtal_out_dest (*(volatile uint32_t*)0x030000a0) -#define reg_pll_out_dest (*(volatile uint32_t*)0x030000a4) -#define reg_trap_out_dest (*(volatile uint32_t*)0x030000a8) +#define reg_spi_commconfig (*(volatile uint32_t*)0x03000018) +#define reg_spi_enables (*(volatile uint32_t*)0x0300001c) +#define reg_spi_pll_config (*(volatile uint32_t*)0x03000020) +#define reg_spi_mfgr_id (*(volatile uint32_t*)0x03000024) +#define reg_spi_prod_id (*(volatile uint32_t*)0x03000028) +#define reg_spi_mask_rev (*(volatile uint32_t*)0x0300002c) +#define reg_spi_pll_bypass (*(volatile uint32_t*)0x03000030) -#define reg_irq7_source (*(volatile uint32_t*)0x030000b0) -#define reg_irq8_source (*(volatile uint32_t*)0x030000b4) +#define reg_xtal_out_dest (*(volatile uint32_t*)0x03000034) +#define reg_pll_out_dest (*(volatile uint32_t*)0x03000038) +#define reg_trap_out_dest (*(volatile uint32_t*)0x0300003c) +#define reg_irq7_source (*(volatile uint32_t*)0x03000040) +#define reg_irq8_source (*(volatile uint32_t*)0x03000044) + +#define reg_spi_config (*(volatile uint32_t*)0x03000048) +#define reg_spi_data (*(volatile uint32_t*)0x0300004c) + +// NOTE: "config" subsumes "control" and "prescale" fields. +#define reg_i2c_config (*(volatile uint32_t*)0x03000050) +#define reg_i2c_prescale (*(volatile uint16_t*)0x03000050) +#define reg_i2c_control (*(volatile uint16_t*)0x03000052) +// NOTE: "status" and "command" are the same byte (one read, one write) +#define reg_i2c_status (*(volatile uint32_t*)0x03000054) +#define reg_i2c_command (*(volatile uint32_t*)0x03000054) +#define reg_i2c_data (*(volatile uint32_t*)0x03000058) + +#define reg_timer0_config (*(volatile uint32_t*)0x0300005c) +#define reg_timer0_value (*(volatile uint32_t*)0x03000060) +#define reg_timer0_data (*(volatile uint32_t*)0x03000064) + +#define reg_timer1_config (*(volatile uint32_t*)0x03000068) +#define reg_timer1_value (*(volatile uint32_t*)0x0300006c) +#define reg_timer1_data (*(volatile uint32_t*)0x03000070) + +// archinfo +// rng +// // command register bits // bit 7 = start