From fe5f447c2f5dff95ba2f3ff91ea54528fcf4eacc Mon Sep 17 00:00:00 2001 From: maksyuki Date: Fri, 31 Jan 2025 01:15:00 +0800 Subject: [PATCH] feat: add new verilogs --- syn/yosys/scripts/yosys_synthesis.tcl | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/syn/yosys/scripts/yosys_synthesis.tcl b/syn/yosys/scripts/yosys_synthesis.tcl index 48aa8fa7..e891bbef 100644 --- a/syn/yosys/scripts/yosys_synthesis.tcl +++ b/syn/yosys/scripts/yosys_synthesis.tcl @@ -28,13 +28,32 @@ source $script_dir/init_tech.tcl # --compat-mode --keep-hierarchy \ # --allow-use-before-declare --ignore-unknown-modules +# IP := ./ip/spram_model.v \ + # ./ip/spimemio.v \ + # ./ip/simpleuart.v \ + # ./ip/i2c_master_bit_ctrl.v \ + # ./ip/i2c_master_byte_ctrl.v \ + # ./ip/simple_i2c_master.v \ + # ./ip/simple_spi_master.v \ + # ./ip/counter_timer.v \ + # ./ip/spi_slave.v \ + # ./ip/ravenna_spi.v + yosys read_verilog ../../tech/tc_io.v yosys read_verilog ../../tech/tc_clk.v yosys read_verilog ../../tech/tc_sram.v -yosys read_verilog ../../rtl/spram_model.v +# yosys read_verilog -I../../rtl/ip +yosys read_verilog ../../rtl/ip/spram_model.v +yosys read_verilog ../../rtl/ip/spimemio.v +yosys read_verilog ../../rtl/ip/simpleuart.v +yosys read_verilog ../../rtl/ip/i2c_master_bit_ctrl.v +yosys read_verilog ../../rtl/ip/i2c_master_byte_ctrl.v +yosys read_verilog ../../rtl/ip/simple_i2c_master.v +yosys read_verilog ../../rtl/ip/simple_spi_master.v +yosys read_verilog ../../rtl/ip/counter_timer.v +yosys read_verilog ../../rtl/ip/spi_slave.v +yosys read_verilog ../../rtl/ip/ravenna_spi.v yosys read_verilog ../../rtl/picorv32.v -yosys read_verilog ../../rtl/spimemio.v -yosys read_verilog ../../rtl/simpleuart.v yosys read_verilog ../../rtl/retrosoc.v yosys read_verilog ../../rtl/retrosoc_asic.v