MyProjetct/uvm_timer
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Your Name 40eb03c0ef Update test_basic_random
2025-09-25 12:08:43 +07:00
common @ 2ccfbc4290
Add common folder for RTL
2025-09-24 20:59:52 +07:00
doc
Init for uvm apb timer project
2025-09-23 21:04:43 +07:00
driver
Init for uvm apb timer project
2025-09-23 21:04:43 +07:00
rtl
Init for uvm apb timer project
2025-09-23 21:04:43 +07:00
sim
Add common folder for RTL
2025-09-24 20:59:52 +07:00
tb
Update test_basic_random
2025-09-25 12:08:43 +07:00
.gitignore
Update Makefile for local env
2025-09-23 21:10:14 +07:00
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SystemVerilog 86.2%
C 7.3%
Makefile 6.5%