feat: refactor RTL modules and utilities for improved consistency and error handling

- Updated license headers to use SPDX format across all RTL files.
- Enhanced error checking in various modules (e.g., tech_ram, tech_regfile, bin2gray, gray2bin, lfsr) to validate parameters and prevent invalid configurations.
- Refactored FIFO implementation to simplify pointer management and ensure proper handling of push/pop operations.
- Introduced new scripts for checking formatting and license headers, ensuring compliance with project standards.
- Added style guidelines to maintain consistent coding practices across the RTL codebase.
- Updated testbench files to include license headers and maintain compatibility with legacy structures.

dv/README.md

@@ -0,0 +1,10 @@
+# Verification
+
+Each `dv/unit/*_tb.sv` testbench is self-checking and finishes with a non-zero
+exit through `$fatal` on failure. Run the portable regression with
+`make test-iverilog`; run the independent simulator implementation with
+`make test-verilator`.
+
+Protocol models under `rtl/model` and `rtl/verif` are compatibility utilities,
+not part of the synthesis source list. New tests must not rely on a simulator
+vendor library.