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maksyuki
3b6a925a51
- Created documentation for , , , and modules, detailing their functionality, parameters, and usage examples. - Implemented a script to ensure required headings and content are present in documentation files. - Developed to generate and update documentation pages from SystemVerilog declarations, ensuring consistency and completeness.
1.2 KiB
1.2 KiB
apb4_master_model
| Property | Value |
|---|---|
| Kind | module |
| RTL source | rtl/model/apb4_master_model.sv |
| Availability | Simulation/verification model |
Summary
Simulation APB4 master model.
Functional Behavior
Simulation APB4 master model. It models the protocol action for simulation and is not a synthesizable protocol endpoint.
Suitable Applications
Use in a SystemVerilog testbench or directed protocol smoke test.
Parameters
This unit has no configurable parameters.
Interface Definition
module apb4_master_model (
apb4_if.master apb4
);
Integration and Use
Include the required interface/configuration definitions and do not include this model in a silicon file list.
apb4_master_model u_apb4_master_model (
);
Dependencies and Verification
The linked RTL source is the implementation authority and contains local assertions for unsupported
parameter combinations. See docs/design.md for repository-wide CDC, reset,
stream, and storage contracts, and docs/verification.md for the
verification matrix.