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1.9 KiB
1.9 KiB
dffsr
| Property | Value |
|---|---|
| Kind | module |
| RTL source | rtl/utils/register.sv |
| Availability | Synthesizable RTL |
Summary
D flip-flop with synchronous reset.
Functional Behavior
D flip-flop with synchronous reset. Its exact parameters and ports are reproduced below from the implementation declaration.
Suitable Applications
Use as a small reusable datapath, state, coding, delay, or verification primitive.
Parameters
The declaration below is canonical; retain the RTL-enforced parameter range.
| Parameter | Declaration |
|---|---|
DATA_WIDTH |
parameter int DATA_WIDTH = 1 |
Interface Definition
module dffsr #(
parameter int DATA_WIDTH = 1
) (
input logic clk_i,
input logic rst_n_i,
input logic [DATA_WIDTH-1:0] dat_i,
output logic [DATA_WIDTH-1:0] dat_o
);
Port Summary
| Signal | Direction | Declaration |
|---|---|---|
clk_i |
input |
input logic clk_i |
rst_n_i |
input |
input logic rst_n_i |
dat_i |
input |
input logic [DATA_WIDTH-1:0] dat_i |
dat_o |
output |
output logic [DATA_WIDTH-1:0] dat_o |
Integration and Use
Keep parameter values within RTL assertions and add required clocking, reset, or CDC protection at the caller boundary.
dffsr #(
.DATA_WIDTH(DATA_WIDTH)
) u_dffsr (
.clk_i(clk_i),
.rst_n_i(rst_n_i),
.dat_i(dat_i),
.dat_o(dat_o)
);
Dependencies and Verification
The linked RTL source is the implementation authority and contains local assertions for unsupported
parameter combinations. See docs/design.md for repository-wide CDC, reset,
stream, and storage contracts, and docs/verification.md for the
verification matrix.