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24 lines
868 B
Systemverilog
24 lines
868 B
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// common is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module xchecker #(
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parameter DATA_WIDTH = 1
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) (
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input logic clk_i,
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input logic [DATA_WIDTH-1:0] dat_i
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);
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XCHECKER :
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assert property (@(posedge clk_i) ((^(dat_i)) !== 1'bx))
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else
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$fatal("\n [error]: detected x value here which can lead to the x state propagation problem\n");
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endmodule
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