mirror of
https://github.com/retroSoC/common.git
synced 2026-11-04 22:32:37 +00:00
maksyuki
a542f1ee57
- Added geometry validation for BIT_WIDTH, WORD_DEPTH, and ADDR_WIDTH in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to ensure proper configurations. - Implemented address range checks in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to prevent out-of-bounds access. - Improved error messages for unsupported access types in regfield module, including validation for DATA_WIDTH. - Added DATA_WIDTH validation in spill_register module to ensure positive values. - Refactored APB4AXI4Master and APB4Master classes to streamline constructor definitions and improve readability. - Enhanced AXI4Master class with additional burst address calculations and legality checks for read/write operations. - Updated read/write tasks in AXI4Master to include error handling for response mismatches and illegal burst conditions. - Simplified the filtering of reference data in rd_check task of AXI4Master to improve clarity and maintainability. - Cleaned up the TestBase class constructor for consistency and clarity.
276 lines
8.8 KiB
Systemverilog
276 lines
8.8 KiB
Systemverilog
// Copyright 2018-2019 ETH Zurich and University of Bologna.
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//
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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// SPDX-License-Identifier: SHL-0.51
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//
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// Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
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// Florian Zaruba <zarubaf@iis.ee.ethz.ch>
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//
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// -- Adaptable modifications are redistributed under compatible License --
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//
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// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// common is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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// verilog_format: off
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(* no_ungroup *)
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(* no_boundary_optimization *)
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// verilog_format: on
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module cdc_fifo #(
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parameter int DATA_WIDTH = 32,
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parameter int BUFFER_DEPTH = 8,
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parameter int SYNC_STAGES = 2
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) (
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input logic src_clk_i,
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input logic src_rst_n_i,
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input logic [DATA_WIDTH-1:0] src_data_i,
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input logic src_valid_i,
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output logic src_ready_o,
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input logic dst_clk_i,
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input logic dst_rst_n_i,
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output logic [DATA_WIDTH-1:0] dst_data_o,
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output logic dst_valid_o,
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input logic dst_ready_i
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);
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localparam int LOG_BUFFER_DEPTH = (BUFFER_DEPTH > 1) ? $clog2(BUFFER_DEPTH) : 1;
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logic [BUFFER_DEPTH-1:0][DATA_WIDTH-1:0] s_int_mem;
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logic [LOG_BUFFER_DEPTH:0] s_wr_ptr_gray, s_rd_ptr_gray;
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logic s_link_rst_n;
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logic s_src_rst_n;
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logic s_dst_rst_n;
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logic s_src_ready;
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logic s_dst_valid;
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initial begin
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if (DATA_WIDTH < 1 || BUFFER_DEPTH < 2 || (BUFFER_DEPTH & (BUFFER_DEPTH - 1)) != 0) begin
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$fatal(1, "cdc_fifo: BUFFER_DEPTH must be a power of two and at least two");
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end
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if (SYNC_STAGES < 2) begin
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$fatal(1, "cdc_fifo: SYNC_STAGES must be at least two");
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end
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end
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// Gray pointers lose their common history after a unilateral reset. Flush
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// both sides instead of allowing a stale pointer to expose old data.
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assign s_link_rst_n = src_rst_n_i && dst_rst_n_i;
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cdc_reset_barrier #(
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.STAGES(SYNC_STAGES)
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) u_reset_barrier (
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.clk_a_i (src_clk_i),
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.clk_b_i (dst_clk_i),
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.rst_n_i (s_link_rst_n),
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.release_i(1'b1),
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.rst_a_n_o(s_src_rst_n),
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.rst_b_n_o(s_dst_rst_n)
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);
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assign src_ready_o = s_src_rst_n && s_src_ready;
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assign dst_valid_o = s_dst_rst_n && s_dst_valid;
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cdc_fifo_src #(DATA_WIDTH, BUFFER_DEPTH, SYNC_STAGES) u_cdc_fifo_src (
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.clk_i (src_clk_i),
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.rst_n_i (s_src_rst_n),
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.data_i (src_data_i),
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.valid_i (src_valid_i),
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.ready_o (s_src_ready),
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(* async *) .async_data_o (s_int_mem),
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(* async *) .async_wr_ptr_o(s_wr_ptr_gray),
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(* async *) .async_rd_ptr_i(s_rd_ptr_gray)
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);
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cdc_fifo_dst #(DATA_WIDTH, BUFFER_DEPTH, SYNC_STAGES) u_cdc_fifo_dst (
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.clk_i (dst_clk_i),
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.rst_n_i (s_dst_rst_n),
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.data_o (dst_data_o),
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.valid_o (s_dst_valid),
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.ready_i (dst_ready_i),
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(* async *) .async_data_i (s_int_mem),
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(* async *) .async_wr_ptr_i(s_wr_ptr_gray),
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(* async *) .async_rd_ptr_o(s_rd_ptr_gray)
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);
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endmodule
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// verilog_format: off
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(* no_ungroup *)
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(* no_boundary_optimization *)
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// verilog_format: on
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module cdc_fifo_src #(
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parameter int DATA_WIDTH = 32,
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parameter int BUFFER_DEPTH = 8,
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parameter int SYNC_STAGES = 2,
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parameter int LOG_BUFFER_DEPTH = (BUFFER_DEPTH > 1) ? $clog2(BUFFER_DEPTH) : 1
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic [ DATA_WIDTH-1:0] data_i,
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input logic valid_i,
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output logic ready_o,
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output logic [ BUFFER_DEPTH-1:0][DATA_WIDTH-1:0] async_data_o,
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output logic [LOG_BUFFER_DEPTH:0] async_wr_ptr_o,
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input logic [LOG_BUFFER_DEPTH:0] async_rd_ptr_i
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);
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localparam int PTR_WIDTH = LOG_BUFFER_DEPTH + 1;
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localparam logic [PTR_WIDTH-1:0] PTR_FULL = (1 << LOG_BUFFER_DEPTH);
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logic [BUFFER_DEPTH-1:0][DATA_WIDTH-1:0] s_data;
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logic [PTR_WIDTH-1:0] s_wr_ptr_gray_d, s_wr_ptr_gray_q;
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logic [PTR_WIDTH-1:0] s_wr_ptr_bin, s_wr_ptr_bin_nxt;
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logic [PTR_WIDTH-1:0] s_rd_ptr_gray, s_rd_ptr_bin;
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logic s_hdshk;
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assign s_hdshk = valid_i & ready_o;
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assign ready_o = (s_wr_ptr_bin ^ s_rd_ptr_bin) != PTR_FULL;
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assign async_data_o = s_data;
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assign async_wr_ptr_o = s_wr_ptr_gray_q;
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for (genvar i = 0; i < BUFFER_DEPTH; i++) begin : CDC_FIFO_SRC_DATA
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localparam logic [LOG_BUFFER_DEPTH-1:0] DATA_INDEX = i;
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dffer #(DATA_WIDTH) u_data_dffer (
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clk_i,
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rst_n_i,
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s_hdshk && (s_wr_ptr_bin[LOG_BUFFER_DEPTH-1:0] == DATA_INDEX),
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data_i,
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s_data[i]
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);
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end
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// rd
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cdc_sync #(
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.STAGE (SYNC_STAGES),
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.DATA_WIDTH(PTR_WIDTH)
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) u_rd_ptr_sync (
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clk_i,
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rst_n_i,
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async_rd_ptr_i,
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s_rd_ptr_gray
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);
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gray2bin #(PTR_WIDTH) u_rd_ptr_g2b (
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s_rd_ptr_gray,
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s_rd_ptr_bin
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);
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// wr
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gray2bin #(PTR_WIDTH) u_wr_ptr_g2b (
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s_wr_ptr_gray_q,
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s_wr_ptr_bin
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);
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assign s_wr_ptr_bin_nxt = s_wr_ptr_bin + 1'b1;
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bin2gray #(
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.DATA_WIDTH(PTR_WIDTH)
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) u_wr_ptr_b2g (
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.bin_i (s_wr_ptr_bin_nxt),
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.gray_o(s_wr_ptr_gray_d)
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);
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dffer #(PTR_WIDTH) u_wr_ptr_gray_dffer (
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clk_i,
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rst_n_i,
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s_hdshk,
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s_wr_ptr_gray_d,
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s_wr_ptr_gray_q
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);
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endmodule
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// verilog_format: off
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(* no_ungroup *)
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(* no_boundary_optimization *)
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// verilog_format: on
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module cdc_fifo_dst #(
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parameter int DATA_WIDTH = 32,
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parameter int BUFFER_DEPTH = 8,
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parameter int SYNC_STAGES = 2,
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parameter int LOG_BUFFER_DEPTH = (BUFFER_DEPTH > 1) ? $clog2(BUFFER_DEPTH) : 1
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) (
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input logic clk_i,
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input logic rst_n_i,
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output logic [ DATA_WIDTH-1:0] data_o,
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output logic valid_o,
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input logic ready_i,
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input logic [ BUFFER_DEPTH-1:0][DATA_WIDTH-1:0] async_data_i,
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input logic [LOG_BUFFER_DEPTH:0] async_wr_ptr_i,
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output logic [LOG_BUFFER_DEPTH:0] async_rd_ptr_o
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);
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localparam int PTR_WIDTH = LOG_BUFFER_DEPTH + 1;
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localparam logic [PTR_WIDTH-1:0] PTR_EMPTY = '0;
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logic [DATA_WIDTH-1:0] s_data;
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logic [PTR_WIDTH-1:0] s_rd_ptr_gray_q, s_rd_ptr_gray_d;
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logic [PTR_WIDTH-1:0] s_rd_ptr_bin, s_rd_ptr_bin_nxt;
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logic [PTR_WIDTH-1:0] s_wr_ptr_gray, s_wr_ptr_bin;
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logic s_hdshk, s_valid, s_ready;
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assign s_hdshk = s_valid & s_ready;
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assign s_data = async_data_i[s_rd_ptr_bin[LOG_BUFFER_DEPTH-1:0]];
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assign s_valid = (s_wr_ptr_bin ^ s_rd_ptr_bin) != PTR_EMPTY;
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assign async_rd_ptr_o = s_rd_ptr_gray_q;
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// wr
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cdc_sync #(
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.STAGE (SYNC_STAGES),
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.DATA_WIDTH(PTR_WIDTH)
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) u_wr_ptr_sync (
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clk_i,
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rst_n_i,
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async_wr_ptr_i,
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s_wr_ptr_gray
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);
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gray2bin #(PTR_WIDTH) u_wr_ptr_g2b (
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s_wr_ptr_gray,
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s_wr_ptr_bin
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);
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// rd
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gray2bin #(PTR_WIDTH) u_rd_ptr_g2b (
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s_rd_ptr_gray_q,
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s_rd_ptr_bin
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);
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assign s_rd_ptr_bin_nxt = s_rd_ptr_bin + 1'b1;
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bin2gray #(
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.DATA_WIDTH(PTR_WIDTH)
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) u_rd_ptr_b2g (
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.bin_i (s_rd_ptr_bin_nxt),
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.gray_o(s_rd_ptr_gray_d)
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);
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dffer #(PTR_WIDTH) u_rd_ptr_gray_dffer (
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clk_i,
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rst_n_i,
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s_hdshk,
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s_rd_ptr_gray_d,
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s_rd_ptr_gray_q
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);
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spill_register #(DATA_WIDTH) u_spill_register (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.flush_i(1'b0),
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.valid_i(s_valid),
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.ready_o(s_ready),
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.data_i (s_data),
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.valid_o(valid_o),
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.ready_i(ready_i),
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.data_o (data_o)
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);
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endmodule
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