mirror of
https://github.com/retroSoC/common.git
synced 2026-11-04 22:32:37 +00:00
maksyuki
a542f1ee57
- Added geometry validation for BIT_WIDTH, WORD_DEPTH, and ADDR_WIDTH in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to ensure proper configurations. - Implemented address range checks in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to prevent out-of-bounds access. - Improved error messages for unsupported access types in regfield module, including validation for DATA_WIDTH. - Added DATA_WIDTH validation in spill_register module to ensure positive values. - Refactored APB4AXI4Master and APB4Master classes to streamline constructor definitions and improve readability. - Enhanced AXI4Master class with additional burst address calculations and legality checks for read/write operations. - Updated read/write tasks in AXI4Master to include error handling for response mismatches and illegal burst conditions. - Simplified the filtering of reference data in rd_check task of AXI4Master to improve clarity and maintainability. - Cleaned up the TestBase class constructor for consistency and clarity.
60 lines
1.4 KiB
Systemverilog
60 lines
1.4 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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// Reset assertion is asynchronous; release is independently synchronized into
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// each clock domain. release_i must remain high until both outputs are high.
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module cdc_reset_barrier #(
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parameter int STAGES = 3
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) (
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input logic clk_a_i,
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input logic clk_b_i,
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input logic rst_n_i,
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input logic release_i,
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output logic rst_a_n_o,
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output logic rst_b_n_o
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);
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logic s_release_a;
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logic s_release_b;
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logic s_reset_a_n;
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logic s_reset_b_n;
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initial begin
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if (STAGES < 2) begin
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$fatal(1, "cdc_reset_barrier: STAGES must be at least two");
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end
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end
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cdc_sync #(
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.STAGE(STAGES)
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) u_release_a (
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.clk_i (clk_a_i),
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.rst_n_i(rst_n_i),
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.dat_i (release_i),
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.dat_o (s_release_a)
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);
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cdc_sync #(
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.STAGE(STAGES)
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) u_release_b (
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.clk_i (clk_b_i),
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.rst_n_i(rst_n_i),
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.dat_i (release_i),
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.dat_o (s_release_b)
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);
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rst_sync #(
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.STAGE(STAGES)
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) u_reset_a (
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.clk_i (clk_a_i),
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.rst_n_i(rst_n_i),
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.rst_n_o(s_reset_a_n)
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);
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rst_sync #(
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.STAGE(STAGES)
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) u_reset_b (
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.clk_i (clk_b_i),
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.rst_n_i(rst_n_i),
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.rst_n_o(s_reset_b_n)
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);
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assign rst_a_n_o = s_reset_a_n && s_release_a;
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assign rst_b_n_o = s_reset_b_n && s_release_b;
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endmodule
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