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21 lines
806 B
Systemverilog
21 lines
806 B
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// common is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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interface ram_if ();
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logic [14:0] addr;
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logic [31:0] wdata;
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logic [ 3:0] wstrb;
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logic [31:0] rdata;
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modport slave(input addr, input wdata, input wstrb, output rdata);
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modport master(output addr, output wdata, output wstrb, input rdata);
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endinterface
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