mirror of
https://github.com/retroSoC/common.git
synced 2026-11-04 22:32:37 +00:00
maksyuki
d4de33c291
- Updated license headers to use SPDX format across all RTL files. - Enhanced error checking in various modules (e.g., tech_ram, tech_regfile, bin2gray, gray2bin, lfsr) to validate parameters and prevent invalid configurations. - Refactored FIFO implementation to simplify pointer management and ensure proper handling of push/pop operations. - Introduced new scripts for checking formatting and license headers, ensuring compliance with project standards. - Added style guidelines to maintain consistent coding practices across the RTL codebase. - Updated testbench files to include license headers and maintain compatibility with legacy structures.
24 lines
833 B
Systemverilog
24 lines
833 B
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
|
|
// common is licensed under Mulan PSL v2.
|
|
// You can use this software according to the terms and conditions of the Mulan PSL v2.
|
|
// You may obtain a copy of Mulan PSL v2 at:
|
|
// http://license.coscl.org.cn/MulanPSL2
|
|
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
|
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
|
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
|
// See the Mulan PSL v2 for more details.
|
|
|
|
module bin2gray #(
|
|
parameter int DATA_WIDTH = 1
|
|
) (
|
|
input logic [DATA_WIDTH-1:0] bin_i,
|
|
output logic [DATA_WIDTH-1:0] gray_o
|
|
);
|
|
|
|
initial begin
|
|
if (DATA_WIDTH < 1) $fatal(1, "bin2gray: DATA_WIDTH must be positive");
|
|
end
|
|
|
|
assign gray_o = bin_i ^ (bin_i >> 1);
|
|
endmodule
|