mirror of
https://github.com/retroSoC/psram.git
synced 2026-11-04 14:22:43 +00:00
58 lines
1.5 KiB
Makefile
58 lines
1.5 KiB
Makefile
NOVAS := /eda/tools/snps/verdi/R-2020.12/share/PLI/VCS/LINUX64
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EXTRA := -P ${NOVAS}/novas.tab ${NOVAS}/pli.a
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VERDI_TOOL := verdi
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SIM_TOOL := vcs
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SIM_OPTIONS := -full64 -debug_acc+all +v2k -sverilog -timescale=1ns/1ps \
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${EXTRA} \
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+error+500\
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+define+SVA_OFF\
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-work DEFAULT\
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+vcs+flush+all \
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+lint=TFIPC-L \
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+define+S50 \
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-kdb \
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SRC_FILE ?=
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SRC_FILE += ../rtl/psram_core.sv
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SRC_FILE += ../rtl/psram_axi4_slv_fsm.sv
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SRC_FILE += ../rtl/axi4_psram.sv
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SRC_FILE += ../model/APM_APS51208N-OB_Xccela_PSRAM_model_v1.5_encrypt.vp_vcs
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SRC_FILE += ../tb/psram_test.sv
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SRC_FILE += ../tb/test_top.sv
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SRC_FILE += ../tb/axi4_psram_tb.sv
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SIM_INC ?=
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SIM_INC += +incdir+../rtl/
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SIM_INC += +incdir+../../common/rtl/
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SIM_INC += +incdir+../../common/rtl/cdc
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SIM_INC += +incdir+../../common/rtl/tech
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SIM_INC += +incdir+../../common/rtl/clkrst
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SIM_INC += +incdir+../../common/rtl/verif
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SIM_INC += +incdir+../../common/rtl/interface
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SIM_APP ?= axi4_psram
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SIM_TOP := $(SIM_APP)_tb
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WAVE_CFG ?= # WAVE_ON
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RUN_ARGS ?=
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RUN_ARGS += +${WAVE_CFG}
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RUN_ARGS += +WAVE_NAME=$(SIM_TOP).fsdb
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comp:
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@mkdir -p build
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cd build && (${SIM_TOOL} ${SIM_OPTIONS} -top $(SIM_TOP) -l compile.log $(SRC_FILE) $(SIM_INC))
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run: comp
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cd build && ./simv -l run.log ${RUN_ARGS}
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wave:
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${VERDI_TOOL} -ssf build/$(SIM_TOP).fsdb &
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clean:
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rm -rf build
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rm -rf verdiLog
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rm -rf novas.*
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.PHONY: wave clean
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