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feat: enhance AXI4 and RIBP interfaces with burst support and address generation

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- Added burst handling to the AXI42RAM and AXI42RIBP modules, including support for fixed, increment, and wrap burst types.
- Introduced address generation logic for read and write operations based on burst parameters.
- Updated the AXI4 interconnect to validate burst types and lengths, ensuring compatibility with the AXI4 protocol.
- Modified the SDRAM controller and testbench to accommodate the new burst handling features.
- Enhanced test cases to verify the correct behavior of burst transactions and address patterns.
- Adjusted memory map and topology tests to reflect changes in the SDRAM size and interface connections.
This commit is contained in:
maksyuki committed 2026-08-13 22:37:01 +08:00
1 parent 2aacaf7507
commit 0077546d6b
27 files changed
+707 -360
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tests/test_sdram.py
+12 -2
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@@ -35,9 +35,14 @@ def test_sdram_controller_preserves_full_and_masked_writes(tmp_path: Path) -> No
[
"+define+SV_ASSRT_DISABLE",
f"+incdir+{generated / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl/interface'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_addr_gen.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/mini/top/axi42ribp_burst.sv"),
str(ROOT / "rtl/mini/top/ribp_arbiter2.sv"),
str(ROOT / "rtl/ip/memory/sdram.sv"),
str(ROOT / "rtl/ip/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/memory/sdram_reg.sv"),
@@ -95,10 +100,15 @@ def test_sdram_controller_preserves_data_with_micron_timing_model(tmp_path: Path
"+define+SV_ASSRT_DISABLE",
"+define+SDRAM_TIMING_MODEL",
f"+incdir+{generated / 'rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl/interface'}",
f"+incdir+{ROOT / 'rtl/managed/third_party/model/sdram'}",
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_addr_gen.sv"),
str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
str(ROOT / "rtl/mini/top/axi42ribp_burst.sv"),
str(ROOT / "rtl/mini/top/ribp_arbiter2.sv"),
str(ROOT / "rtl/ip/memory/sdram.sv"),
str(ROOT / "rtl/ip/memory/sdram_clkgen.sv"),
str(ROOT / "rtl/ip/memory/sdram_reg.sv"),