feat: enhance AXI4 and RIBP interfaces with burst support and address generation

- Added burst handling to the AXI42RAM and AXI42RIBP modules, including support for fixed, increment, and wrap burst types.
- Introduced address generation logic for read and write operations based on burst parameters.
- Updated the AXI4 interconnect to validate burst types and lengths, ensuring compatibility with the AXI4 protocol.
- Modified the SDRAM controller and testbench to accommodate the new burst handling features.
- Enhanced test cases to verify the correct behavior of burst transactions and address patterns.
- Adjusted memory map and topology tests to reflect changes in the SDRAM size and interface connections.

tests/test_sta_constraints.py

@@ -52,7 +52,7 @@ def test_core_sdc_covers_current_clock_domains(tmp_path: Path) -> None:
     assert "get_pins -quiet" in sdc
     assert "get_ports -quiet" in sdc
     assert "set clk_jtag_port [require_ports \"clock jtag\" {jtag_tck_i_pad}]" in sdc
-    assert "u_retrosoc.u_ip_ribp_wrapper.u_rib_dvp.u_dvp_pclk_clk_buf/clk_o" in sdc
+    assert "u_retrosoc.u_ip_ribp_wrapper.u_axi4_dvp.u_dvp_pclk_clk_buf/clk_o" in sdc
     assert "-group [get_clocks {clk_external clk_system}]" in sdc
     assert "set_clock_transition 0.1 [get_clocks {clk_dvp}]" in sdc
     assert "set_input_transition" not in sdc