mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
feat: add UART V2 support with formal verification and test cases
- Updated filelist to include new UART source files. - Enhanced formal file generation script to support UART target. - Introduced formal verification module and properties for UART. - Modified makefiles to include UART in formal targets and source files. - Added UART-related source files to software build. - Updated top-level wrapper to integrate UART DMA signals. - Implemented UART testbench for comprehensive testing of functionality. - Created Python test script for UART V2 register, FIFO, and interrupt tests. - Added UART helper functions in C test runtime. - Updated DMA error testbench to handle UART signals. - Ensured WS2812 DMA testbench accommodates UART signals.
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@@ -7,6 +7,7 @@
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#include <retrosoc/hal/lcd.h>
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#include <retrosoc/hal/spisd.h>
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#include <retrosoc/hal/timer.h>
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#include <retrosoc/hal/uart.h>
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#include <retrosoc/hal/ws2812.h>
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#include <retrosoc/lib/printf.h>
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#include <retrosoc/lib/stdlib.h>
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@@ -190,6 +191,26 @@ static int test_timer_helpers(void) {
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return 0;
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}
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static int test_uart_helpers(void) {
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rs_uart_timing_t timing;
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if ((rs_uart_timing_calculate(72000000U, 921600U, &timing) != RS_OK) ||
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(timing.baud_integer != 78U) || (timing.baud_fraction != 32U)) {
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return 1;
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}
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if ((rs_uart_timing_calculate(16000000U, 1000000U, &timing) != RS_OK) ||
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(timing.baud_integer != 16U) || (timing.baud_fraction != 0U)) {
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return 2;
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}
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if ((rs_uart_timing_calculate(0U, 115200U, &timing) != RS_EINVAL) ||
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(rs_uart_timing_calculate(72000000U, 0U, &timing) != RS_EINVAL) ||
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(rs_uart_timing_calculate(1000000U, 1000000U, &timing) != RS_EINVAL) ||
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(rs_uart_timing_calculate(72000000U, 115200U, NULL) != RS_EINVAL)) {
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return 3;
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}
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return 0;
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}
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static int test_gpio_helpers(void) {
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rs_gpio_filter_timing_t timing;
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@@ -252,7 +273,8 @@ int main(void) {
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const int results[] = {
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test_string_helpers(), test_formatter(), test_compiler_helpers(),
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test_wait_helper(), test_ws2812_helpers(), test_timer_helpers(),
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test_gpio_helpers(), test_wav_parser(), test_video_parser(),
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test_uart_helpers(), test_gpio_helpers(), test_wav_parser(),
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test_video_parser(),
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};
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for (size_t index = 0U; index < (sizeof(results) / sizeof(results[0])); ++index) {
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@@ -143,6 +143,8 @@ module dma_error_tb;
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hw_trg.i2s_rx_proc = 1'b0;
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hw_trg.qspi_tx_proc = 1'b0;
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hw_trg.qspi_rx_proc = 1'b0;
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hw_trg.uart_tx_proc = 1'b0;
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hw_trg.uart_rx_proc = 1'b0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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@@ -0,0 +1,176 @@
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`timescale 1ns / 1ps
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`include "ribp_uart_define.svh"
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module uart_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic dma_tx_stall;
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logic dma_rx_stall;
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ribp_if ribp ();
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uart_if uart ();
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always #5 clk_i = ~clk_i;
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ribp_uart u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(dma_tx_stall),
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.dma_rx_stall_o(dma_rx_stall),
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.ribp (ribp),
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.uart (uart)
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);
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task automatic ribp_write(input logic [31:0] address, input logic [31:0] data,
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input logic [3:0] strobe, input logic expected_error);
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begin
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@(negedge clk_i);
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ribp.addr = address;
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ribp.wdata = data;
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ribp.wstrb = strobe;
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ribp.valid = 1'b1;
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while (!ribp.ready) begin
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@(posedge clk_i);
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#1;
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end
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if (ribp.resp_err !== expected_error) begin
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$fatal(1, "UART write %h error=%b expected=%b", address, ribp.resp_err, expected_error);
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end
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@(negedge clk_i);
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ribp.valid = 1'b0;
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ribp.wstrb = '0;
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end
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endtask
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task automatic ribp_read(input logic [31:0] address, input logic expected_error,
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output logic [31:0] data);
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begin
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@(negedge clk_i);
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ribp.addr = address;
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ribp.wdata = '0;
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ribp.wstrb = '0;
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ribp.valid = 1'b1;
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while (!ribp.ready) begin
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@(posedge clk_i);
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#1;
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end
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if (ribp.resp_err !== expected_error) begin
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$fatal(1, "UART read %h error=%b expected=%b", address, ribp.resp_err, expected_error);
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end
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data = ribp.rdata;
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@(negedge clk_i);
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ribp.valid = 1'b0;
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end
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endtask
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task automatic write_ok(input logic [31:0] address, input logic [31:0] data);
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begin
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ribp_write(address, data, 4'hF, 1'b0);
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end
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endtask
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task automatic configure_uart(input logic [4:0] line_control, input logic [3:0] control);
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begin
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write_ok(`RIBP_UART_CTRL, 0);
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repeat (4) @(posedge clk_i);
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write_ok(`RIBP_UART_FIFO_CTRL, 3);
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write_ok(`RIBP_UART_BAUD_INT, 16);
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write_ok(`RIBP_UART_BAUD_FRAC, 0);
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write_ok(`RIBP_UART_LINE_CTRL, line_control);
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write_ok(`RIBP_UART_CTRL, control);
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end
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endtask
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task automatic send_external_8n1(input logic [7:0] data, input logic bad_stop);
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integer bit_index;
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begin
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uart.rx_i = 1'b0;
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repeat (16) @(posedge clk_i);
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for (bit_index = 0; bit_index < 8; bit_index = bit_index + 1) begin
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uart.rx_i = data[bit_index];
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repeat (16) @(posedge clk_i);
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end
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uart.rx_i = !bad_stop;
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repeat (16) @(posedge clk_i);
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uart.rx_i = 1'b1;
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repeat (24) @(posedge clk_i);
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end
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endtask
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initial begin
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logic [31:0] value;
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integer index;
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ribp.valid = 1'b0;
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ribp.addr = '0;
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ribp.wdata = '0;
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ribp.wstrb = '0;
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uart.rx_i = 1'b1;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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repeat (4) @(posedge clk_i);
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ribp_read(`RIBP_UART_IP_VERSION, 1'b0, value);
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if (value != 32'h0002_0000) $fatal(1, "UART IP version mismatch");
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ribp_read(`RIBP_UART_CAPABILITY, 1'b0, value);
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if (value != 32'h00FF_4040) $fatal(1, "UART capability mismatch");
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ribp_read(32'h0000_0002, 1'b1, value);
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ribp_read(`RIBP_UART_RXDATA, 1'b1, value);
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configure_uart(5'd3, 4'b0111);
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write_ok(`RIBP_UART_TXDATA, 8'hA5);
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repeat (220) @(posedge clk_i);
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ribp_read(`RIBP_UART_RXDATA, 1'b0, value);
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if (value[11:0] != 12'h0A5) $fatal(1, "UART 8N1 loopback mismatch: %h", value);
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configure_uart(5'd3, 4'b0001);
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write_ok(`RIBP_UART_TXDATA, 8'h5A);
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repeat (24) @(posedge clk_i);
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ribp_read(`RIBP_UART_STATUS, 1'b0, value);
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if (!value[`UART_STATUS_TX_BUSY]) $fatal(1, "UART TX did not start before disable");
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write_ok(`RIBP_UART_CTRL, 0);
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repeat (180) @(posedge clk_i);
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ribp_read(`RIBP_UART_STATUS, 1'b0, value);
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if (value[`UART_STATUS_TX_BUSY] || !value[`UART_STATUS_TX_EMPTY]) begin
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$fatal(1, "UART TX did not finish its active frame after disable: %h", value);
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end
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write_ok(`RIBP_UART_INTR_ENABLE, 6'h3F);
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write_ok(`RIBP_UART_INTR_TEST, 6'h20);
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ribp_read(`RIBP_UART_INTR_STATUS, 1'b0, value);
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if (!value[`UART_INTR_BREAK] || !uart.irq_o) $fatal(1, "UART interrupt test failed");
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write_ok(`RIBP_UART_INTR_STATE, 6'h3F);
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configure_uart(5'd3, 4'b0010);
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fork
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send_external_8n1(8'h3C, 1'b1);
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join
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ribp_read(`RIBP_UART_RXDATA, 1'b0, value);
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if ((value[7:0] != 8'h3C) || !value[`UART_RXDATA_FRAME_ERROR]) begin
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$fatal(1, "UART frame error was not retained: %h", value);
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end
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write_ok(`RIBP_UART_CTRL, 0);
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repeat (4) @(posedge clk_i);
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write_ok(`RIBP_UART_FIFO_CTRL, 3);
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for (index = 0; index < 64; index = index + 1) begin
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write_ok(`RIBP_UART_TXDATA, index);
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end
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ribp_write(`RIBP_UART_TXDATA, 32'h55, 4'hF, 1'b1);
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ribp_read(`RIBP_UART_FIFO_LEVEL, 1'b0, value);
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if (value[6:0] != 7'd64) $fatal(1, "UART TX FIFO depth mismatch: %h", value);
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write_ok(`RIBP_UART_FIFO_CTRL, 3);
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write_ok(`RIBP_UART_DMA_CTRL, 3);
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if (!dma_tx_stall || !dma_rx_stall) $fatal(1, "Disabled UART asserted a DMA request");
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$display("UART V2 register, FIFO, loopback, error, interrupt, and DMA test passed");
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$finish;
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end
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initial begin
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repeat (20000) @(posedge clk_i);
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$fatal(1, "UART test timeout");
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end
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endmodule
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@@ -217,6 +217,8 @@ module ws2812_dma_tb;
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hw_trg.i2s_rx_proc = 1'b0;
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hw_trg.qspi_tx_proc = 1'b0;
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hw_trg.qspi_rx_proc = 1'b0;
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hw_trg.uart_tx_proc = 1'b0;
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hw_trg.uart_rx_proc = 1'b0;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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@@ -0,0 +1,66 @@
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"""UART V2 register, FIFO, framing, interrupt, and DMA request tests."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_uart_v2_register_fifo_loopback_and_errors(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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serial = ROOT / "rtl/ip/ribp/serial"
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cluster_uart = ROOT / "rtl/managed/clusterip/uart/rtl"
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source_list = tmp_path / "uart.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{common}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'utils'}",
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f"+incdir+{serial}",
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str(common / "interface/ribp_if.sv"),
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str(common / "utils/register.sv"),
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str(common / "utils/fifo.sv"),
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str(cluster_uart / "uart_if.sv"),
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str(serial / "uart_baudgen.sv"),
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str(serial / "ribp_uart_tx.sv"),
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str(serial / "ribp_uart_rx.sv"),
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str(serial / "uart_core.sv"),
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str(serial / "uart_reg.sv"),
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str(serial / "ribp_uart.sv"),
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str(ROOT / "tests/rtl/uart_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "uart_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "uart_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "uart_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "UART V2 register, FIFO, loopback, error, interrupt, and DMA test passed" in result.stdout
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