docs: record the OpenC906 SRAM macro swap and its evidence

Move the chapter 3 memory swap from deferred to simulation-validated in
docs/ip/hp-platform.md (mechanism, define gating, and the stacking table)
and docs/hp-rv64-validation.md (macro-mode boot TB and SoC macro-sim
evidence, with the remaining synthesis/netlist/STA/LEC gates called out).
Extend the override inventories in rtl/README.md and scripts/README.md to
cover the eight aq_spsram_* wrappers. The chapter 3 ICG replacement and
physical qualification stay explicitly deferred.

scripts/README.md

@@ -130,7 +130,9 @@ source used by Mini product profiles and verifies the checked-out revision;
 the vendored checkout is never modified. `generate_openc906.py` resolves the
 upstream `C906_RTL_FACTORY/gen_rtl` filelists from that checkout, substitutes
 the reviewed overrides from `rtl/mini/ip_overrides/` (the hart-1
-`aq_sysio_kid.v` and the strong-order MMIO-window `sysmap.h`, each pinned to
+`aq_sysio_kid.v`, the strong-order MMIO-window `sysmap.h`, and the eight
+`aq_spsram_*.v` SRAM wrappers whose IHP130 macro path is gated on
+`PDK_IHP130`+`HAVE_SRAM_MACRO` without `PDK_BEHAV`, each pinned to
 the upstream file's SHA-256 so a locked-revision move forces review), and
 emits the single compilation unit `openc906_combined.v` below `build/`;
 generated RTL is never tracked.