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feat: add SPI-SD RTL tests and enhance interconnect testbench
- Increased the number of masters in the AXI4 interconnect testbench from 5 to 6. - Added new testbench for SPI-SD clock functionality (spisd_clock_tb). - Introduced testbench for SPI-SD command engine (spisd_command_tb). - Created testbench for SPI-SD CRC calculation (spisd_crc_tb). - Implemented testbench for SPI-SD data handling (spisd_data_tb). - Developed wrapper testbench for SPI-SD with APB and training checks (spisd_wrapper_tb). - Added Python test suite for SPI-SD RTL regressions (test_spisd.py). - Created a test for verifying register parity between RTL and C header definitions (test_spisd_register_parity.py).
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@@ -579,6 +579,63 @@ static int test_sdio_helpers(void) {
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return 0;
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}
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static int test_spisd_helpers(void) {
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rs_spisd_clock_t clock;
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rs_spisd_card_info_t info = {0};
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rs_spisd_descriptor_t descriptor;
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uint8_t csd_v2[16] = {0};
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uint8_t csd_v1[16] = {0};
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uint32_t argument;
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if ((rs_spisd_clock_calculate(72000000U, 400000U, &clock) != RS_OK) ||
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(clock.half_period != 90U) || (clock.actual_hz != 400000U) ||
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(rs_spisd_clock_calculate(72000000U, 36000000U, &clock) != RS_OK) ||
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(clock.half_period != 1U) || (clock.actual_hz != 36000000U)) {
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return 1;
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}
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if ((rs_spisd_clock_calculate(0U, 400000U, &clock) != RS_EINVAL) ||
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(rs_spisd_clock_calculate(72000000U, 36000001U, &clock) != RS_EINVAL) ||
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(rs_spisd_clock_calculate(72000000U, 400000U, NULL) != RS_EINVAL)) {
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return 2;
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}
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if ((rs_spisd_card_address(RS_SPISD_CARD_SDSC, 2U, &argument) != RS_OK) ||
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(argument != 1024U) ||
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(rs_spisd_card_address(RS_SPISD_CARD_SDHC, 2U, &argument) != RS_OK) || (argument != 2U) ||
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(rs_spisd_card_address((rs_spisd_card_type_t)2U, 0U, &argument) != RS_EINVAL)) {
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return 3;
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}
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csd_v2[0] = UINT8_C(0x40);
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csd_v2[8] = UINT8_C(0x03);
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csd_v2[9] = UINT8_C(0xFF);
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if ((rs_spisd_parse_csd(csd_v2, &info) != RS_OK) || !info.high_capacity ||
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(info.card_type != RS_SPISD_CARD_SDHC) || (info.capacity_blocks != UINT32_C(0x00100000))) {
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return 4;
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}
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csd_v1[5] = UINT8_C(9);
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csd_v1[7] = UINT8_C(0xFF);
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csd_v1[8] = UINT8_C(0xC0);
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csd_v1[9] = UINT8_C(0x03);
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csd_v1[10] = UINT8_C(0x80);
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if ((rs_spisd_parse_csd(csd_v1, &info) != RS_OK) || info.high_capacity ||
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(info.card_type != RS_SPISD_CARD_SDSC) || (info.capacity_blocks != UINT32_C(0x00080000))) {
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return 5;
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}
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if ((rs_spisd_descriptor_prepare(&descriptor, (uintptr_t)UINT32_C(0x40000000), 64U,
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(uintptr_t)0U, true, true) != RS_OK) ||
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(rs_spisd_descriptor_validate(&descriptor) != RS_OK) ||
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(rs_spisd_descriptor_publish(&descriptor) != RS_OK) ||
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((descriptor.control_status & RS_SPISD_DESC_OWN) == 0U)) {
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return 6;
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}
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if ((rs_spisd_descriptor_prepare(&descriptor, (uintptr_t)UINT32_C(0x40000002), 64U,
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(uintptr_t)0U, true, false) != RS_EINVAL) ||
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(rs_spisd_descriptor_prepare(&descriptor, (uintptr_t)UINT32_C(0x40000000), 64U,
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(uintptr_t)UINT32_C(0x40000FF0), false, false) != RS_EINVAL)) {
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return 7;
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}
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return 0;
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}
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static int test_gpio_helpers(void) {
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rs_gpio_filter_timing_t timing;
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@@ -710,15 +767,13 @@ static int test_video_parser(void) {
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int main(void) {
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const int results[] = {
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test_string_helpers(), test_formatter(),
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test_compiler_helpers(), test_wait_helper(),
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test_ws2812_helpers(), test_timer_helpers(),
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test_psram_helpers(), test_sdram_helpers(),
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test_uart_helpers(), test_i2s_helpers(),
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test_i2c_helpers(), test_sdio_helpers(),
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test_gpio_helpers(), test_dma_config_validation(),
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test_opipsram_helpers(), test_ps2_decoders(),
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test_wav_parser(), test_video_parser(),
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test_string_helpers(), test_formatter(), test_compiler_helpers(),
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test_wait_helper(), test_ws2812_helpers(), test_timer_helpers(),
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test_psram_helpers(), test_sdram_helpers(), test_uart_helpers(),
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test_i2s_helpers(), test_i2c_helpers(), test_sdio_helpers(),
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test_spisd_helpers(), test_gpio_helpers(), test_dma_config_validation(),
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test_opipsram_helpers(), test_ps2_decoders(), test_wav_parser(),
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test_video_parser(),
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};
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for (size_t index = 0U; index < (sizeof(results) / sizeof(results[0])); ++index) {
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