feat: refactor NMI interface and enhance performance logging

- Updated NMI interface references from  to  in multiple files for consistency.
- Added a new script  to convert UART performance records into structured JSON format.
- Enhanced the README documentation to include details about the new performance log parser.
- Implemented tests for the new performance log parser to ensure correct functionality.
- Added new test cases for DMA error handling and SDRAM data integrity to improve coverage.
- Updated existing test cases to accommodate changes in the NMI interface and added performance metrics.
- Refactored bus fault testbench to include fault code checks and improved error handling.
- Adjusted memory map generation and pin mapping tests to reflect recent changes in RTL structure.

tests/test_sta_constraints.py

@@ -202,6 +202,12 @@ def test_ics55_sim_model_preparer_patches_every_h7cr_muxi2_variant(tmp_path: Pat
 
     assert first.returncode == 0, first.stderr
     prepared = output.read_text(encoding="utf-8")
+    assert prepared.startswith(
+        "/* verilator lint_off DECLFILENAME */\n/* verilator lint_off SPECIFYIGN */\n"
+    )
+    assert prepared.endswith(
+        "/* verilator lint_on SPECIFYIGN */\n/* verilator lint_on DECLFILENAME */\n"
+    )
     assert prepared.count("wire muxi2_y;") == len(cells)
     assert prepared.count("udp_mux2 u0(muxi2_y, A, B, S0);") == len(cells)
     assert "not      u1(Y, Y);" not in prepared