feat: update CoreMark configurations and clock settings for improved simulation accuracy

Makefile

@@ -50,6 +50,7 @@ JTAG_IDCODE              ?= DEADBEEF
 EXT_CLK_HZ               ?= 72000000
 AUD_CLK_HZ               ?= 18432000
 CLINT_TIMEBASE_HZ        ?= 1000000
+MGMT_CPU_CLK_HZ          := $(if $(filter PRODUCT,$(MINI_MODE)),24000000,$(EXT_CLK_HZ))
 WAVE                     ?= NO
 FORMAL                   ?= NO
 VCS_USE_LSF              ?= YES
@@ -97,8 +98,8 @@ JOBS               ?= $(shell count=$$(nproc 2>/dev/null || printf '1'); \
 else printf '%s' "$$count"; fi)
 LOCAL_RTL_FILES    ?=
 CONFIG_KEY_VARS    := SOC MINI_MODE PDK HAVE_PLL HAVE_SRAM_IF HAVE_SRAM_MACRO SRAM_SIZE_KIB PDK_BEHAV HAVE_SVA \
-                   HAVE_HP HP_CONFIG BUILD_RELEASE JTAG_IDCODE EXT_CLK_HZ AUD_CLK_HZ CLINT_TIMEBASE_HZ ISA HAVE_CSR APP LINK_TYPE \
+                   HAVE_HP HP_CONFIG BUILD_RELEASE JTAG_IDCODE EXT_CLK_HZ AUD_CLK_HZ CLINT_TIMEBASE_HZ MGMT_CPU_CLK_HZ \
-                   COREMARK_MODE RTL_TOP FIRMWARE_NAME
+                   ISA HAVE_CSR APP LINK_TYPE COREMARK_MODE RTL_TOP FIRMWARE_NAME
 VARIANT_ID         := $(strip $(shell $(VCS_SHELL_PYTHON) $(ROOT_PATH)/scripts/config_key.py \
     --lock $(LOCK_FILE) --profile $(PROFILE_NAME) --timestamp $(BUILD_TIMESTAMP) \
     $(foreach var,$(CONFIG_KEY_VARS),--value $(var)=$($(var))) | tail -n 1))
@@ -439,7 +440,7 @@ config:
 	  PDK_BEHAV '$(PDK_BEHAV)' HAVE_SVA '$(HAVE_SVA)' \
 	  HAVE_HP '$(HAVE_HP)' HP_CONFIG '$(HP_CONFIG)' BUILD_RELEASE '$(BUILD_RELEASE)' \
 	  JTAG_IDCODE '$(JTAG_IDCODE)' EXT_CLK_HZ '$(EXT_CLK_HZ)' AUD_CLK_HZ '$(AUD_CLK_HZ)' \
-	  CLINT_TIMEBASE_HZ '$(CLINT_TIMEBASE_HZ)' \
+	  CLINT_TIMEBASE_HZ '$(CLINT_TIMEBASE_HZ)' MGMT_CPU_CLK_HZ '$(MGMT_CPU_CLK_HZ)' \
 	  ISA '$(ISA)' HAVE_CSR '$(HAVE_CSR)' APP '$(APP)' \
 	  LINK_TYPE '$(LINK_TYPE)' COREMARK_MODE '$(COREMARK_MODE)'
 

README.md

@@ -238,7 +238,7 @@ make CONFIG=configs/ci/ihp130.mk SIMU=IVERILOG \
 | Icarus netlist simulation after synthesis | `make CONFIG=configs/ci/ihp130.mk SIMU=IVERILOG netsim` |
 | OpenSTA core timing analysis after synthesis | `make CONFIG=configs/ci/ihp130.mk STA=OPENSTA sta` |
 | Strict Verilator RTL lint | `make CONFIG=configs/ci/ihp130.mk SIMU=VERILATOR HAVE_SVA=YES check-rtl-lint` |
-| Hazard3 CoreMark quick report | `make CONFIG=configs/benchmark/ihp130-hazard3-coremark.mk SIMU=VERILATOR coremark-report` |
+| Hazard3 CoreMark quick report | `make CONFIG=configs/benchmark/ihp130-hazard3-coremark.mk SIMU=VERILATOR SOC_SIM_TIME=7200 coremark-report` |
 | Generate the untracked HP core RTL | `make CONFIG=configs/ci/ihp130-hp.mk vexii-generate` |
 | Build and package the HP Linux flash image | `make setup-hp-linux && make CONFIG=configs/ci/ihp130-hp.mk hp-bundle` |
 | IHP130 fast smoke suite | `make regress-smoke` |

app/README.md

@@ -56,7 +56,8 @@ make CONFIG=configs/ci/ihp130-shell.mk SIMU=VERILATOR firmware sim
 make CONFIG=configs/benchmark/ihp130-hazard3.mk SIMU=VERILATOR benchmark-report
 
 # IHP130/Hazard3 fixed-workload CoreMark; result is written to meta/coremark.json
-make CONFIG=configs/benchmark/ihp130-hazard3-coremark.mk SIMU=VERILATOR coremark-report
+make CONFIG=configs/benchmark/ihp130-hazard3-coremark.mk \
+  SIMU=VERILATOR SOC_SIM_TIME=7200 coremark-report
 
 # Hazard3 remote-bitbang, OpenOCD, and GDB acceptance flow
 make CONFIG=configs/ci/ihp130-debug.mk SIMU=VERILATOR debug-sim

app/apps/coremark/main.c

@@ -19,14 +19,13 @@ int main(void) {
     int result;
     uint32_t cycles;
 
-    if (rs_uart_init(CPU_FREQ * UINT32_C(1000000), UART_BPS) != RS_OK) {
+    if (rs_uart_init(RS_CPU_CLOCK_HZ, UART_BPS) != RS_OK) {
         rs_test_finish(RS_TEST_FAILED, 2U);
     }
     result = core_main();
     cycles = (uint32_t)get_time();
     printf("COREMARK_RESULT mode=%s qualified=%u memory=sram iterations=%u cycles=%u cpu_hz=%u\n",
-           RS_COREMARK_MODE, RS_COREMARK_QUALIFIED, (uint32_t)ITERATIONS, cycles,
+           RS_COREMARK_MODE, RS_COREMARK_QUALIFIED, (uint32_t)ITERATIONS, cycles, RS_CPU_CLOCK_HZ);
-           CPU_FREQ * UINT32_C(1000000));
     if ((result != 0) || (cycles == 0U)) {
         printf("COREMARK_FAIL result=%d\n", result);
         rs_test_finish(RS_TEST_FAILED, 1U);

app/benchmark/coremark/core_portme.c

@@ -20,6 +20,7 @@ Original Author: Shay Gal-on
 #include <stdint.h>
 
 #include <retrosoc/arch/riscv/system_base.h>
+#include <retrosoc/core/soc.h>
 
 #if VALIDATION_RUN
 volatile ee_s32 seed1_volatile = 0x3415;
@@ -55,7 +56,7 @@ static CORETIMETYPE barebones_clock(void) {
    does not occur. If there are issues with the return value overflowing,
    increase this value.
         */
-#define CLOCKS_PER_SEC             72000000
+#define CLOCKS_PER_SEC             RS_CPU_CLOCK_HZ
 #define GETMYTIME(_t)              (*_t = barebones_clock())
 #define MYTIMEDIFF(fin, ini)       ((fin) - (ini))
 #define TIMER_RES_DIVIDER          1

crt/include/retrosoc/core/soc.h

@@ -7,9 +7,12 @@
 #include <retrosoc/generated/memory_map.h>
 #include <retrosoc/generated/user_extensions.h>
 
-#define HW_CORE                    "Management Hazard3"
+#ifndef RS_CPU_CLOCK_HZ
+#define RS_CPU_CLOCK_HZ UINT32_C(72000000)
+#endif
 
-#define CPU_FREQ                   72     // unit: MHz
+#define HW_CORE                    "Management Hazard3"
+#define CPU_FREQ                   (RS_CPU_CLOCK_HZ / UINT32_C(1000000))
 #define UART_BPS                   921600 // unit: bps
 #define SPFS_MEM_START             RS_SOC_FLASH_BASE
 #define SPFS_MEM_OFFST             RS_SOC_FLASH_SIZE

crt/src/service/booter.c

@@ -254,7 +254,7 @@ void rs_app_info(void) {
     printf("  COMPILER:            %s\n", COMPILER_NAME);
     printf("  CFLAGS:              %s\n", COMPILER_CFLAGS);
     printf("  ISA:                 %s\n", COMPILER_ISA);
-    printf("  FREQ:                %dMHz\n\n", CPU_FREQ);
+    printf("  FREQ:                %uMHz\n\n", (unsigned int)CPU_FREQ);
 
     printf("Inst/Memory Address Range:\n");
     printf("  XPI NOR:             @[0x%08x-0x%08x] %3d MiB\n", SPFS_MEM_START,

docs/coremark.md

@@ -11,13 +11,15 @@ the UART, flash fetches, or a peripheral timer.
 The benchmark application emits a single machine-readable UART record:
 
 ```text
-COREMARK_RESULT mode=quick qualified=0 memory=sram iterations=4 cycles=<n> cpu_hz=72000000
+COREMARK_RESULT mode=quick qualified=0 memory=sram iterations=4 cycles=<n> cpu_hz=24000000
 ```
 
 `scripts/parse_coremark_log.py` converts the record to `meta/coremark.json`.
 `coremark_per_mhz` is calculated as `iterations * 1,000,000 / cycles` and is
 rounded to three decimal places. The result also requires `COREMARK_PASS` and
-the common `SIM_TEST_PASS` terminal software result.
+the common `SIM_TEST_PASS` terminal software result. The PRODUCT management
+core starts from REF24 at 24 MHz, and the firmware build derives `cpu_hz` and
+UART timing from that reset-clock contract.
 
 ## Quick Regression Measurement
 
@@ -25,14 +27,15 @@ Run the fixed four-iteration workload with Verilator:
 
 ```sh
 make CONFIG=configs/benchmark/ihp130-hazard3-coremark.mk \
-  SIMU=VERILATOR coremark-report
+  SIMU=VERILATOR SOC_SIM_TIME=7200 coremark-report
 ```
 
 The quick profile is included in the IHP130 nightly regression. It verifies
-the CoreMark CRCs, SRAM linker placement, machine cycle counting, report
+the pin-level XPI boot path, CoreMark CRCs, SRAM linker placement, machine
-parsing, and terminal test status. Its short fixed workload is reproducible
+cycle counting, report parsing, and terminal test status. Its short fixed
-for regression trending, but it is not an EEMBC-qualified CoreMark score and
+workload is reproducible for regression trending, but it is not an
-must not be used for public performance claims.
+EEMBC-qualified CoreMark score and must not be used for public performance
+claims.
 
 ## Standard Hardware Measurement
 

rtl/mini/mk/software.mk

@@ -45,6 +45,7 @@ DEF_VAL += -DCOMPILER_NAME='"$(CC)"'
 DEF_VAL += -DCOMPILER_CFLAGS='"$(GCC_FLAGS) $(SW_WARN_FLAGS)"'
 DEF_VAL += -DCOMPILER_ISA='"$(ISA_FLAGS)"'
 DEF_VAL += -DRS_SOC_MGMT_JTAG_IDCODE=0x$(JTAG_IDCODE)U
+DEF_VAL += -DRS_CPU_CLOCK_HZ=$(MGMT_CPU_CLK_HZ)U
 DEF_VAL += -DRS_CLINT_TIMEBASE_HZ=$(CLINT_TIMEBASE_HZ)U
 DEF_VAL += -DRS_RTC_CLOCK_HZ=$(AUD_CLK_HZ)U
 ifeq ($(HAVE_CSR),YES)

scripts/regress.py

@@ -83,11 +83,11 @@ SMOKE_COMMANDS = (
 NIGHTLY_EXTRA_COMMANDS = (
     (
         "configs/benchmark/ihp130-hazard3-coremark.mk",
-        # The quick-mode serial-flash boot plus benchmark needs ~33M emu cycles;
+        # Pin-level serial-flash boot plus the PRODUCT benchmark needs ~80M
-        # hosted runners reach only ~15k cycles/s, far below the 180s default.
+        # emulator steps; 7200s preserves XPI coverage with runner margin.
         (
             "SIMU=VERILATOR",
-            "SOC_SIM_TIME=3600",
+            "SOC_SIM_TIME=7200",
             "HAVE_SVA=YES",
             "coremark-report",
         ),

tests/test_performance_log.py

@@ -60,14 +60,14 @@ def test_parse_log_rejects_report_with_performance_failure() -> None:
 def test_parse_coremark_quick_report() -> None:
     report = parse_coremark_log(
         "COREMARK_RESULT mode=quick qualified=0 memory=sram iterations=4 cycles=2000 "
-        "cpu_hz=72000000\nCOREMARK_PASS\n"
+        "cpu_hz=24000000\nCOREMARK_PASS\n"
     )
 
     assert report["status"] == "passed"
     assert report["results"] == [
         {
             "coremark_per_mhz": "2000.000",
-            "cpu_hz": 72000000,
+            "cpu_hz": 24000000,
             "cycles": 2000,
             "iterations": 4,
             "memory": "sram",

tests/test_script_tools.py

@@ -882,6 +882,18 @@ def test_make_dry_run_and_validation_do_not_write_filelists(tmp_path: Path) -> N
         line.startswith("MGMT_CORE") and line.rstrip().endswith("HAZARD3")
         for line in default_core.splitlines()
     )
+    assert any(
+        line.startswith("MGMT_CPU_CLK_HZ") and line.rstrip().endswith("24000000")
+        for line in default_core.splitlines()
+    )
+
+    mpw_config = run("make", "CONFIG=configs/cluster/mini-mpw.mk", "config").stdout
+    assert any(
+        line.startswith("MGMT_CPU_CLK_HZ") and line.rstrip().endswith("72000000")
+        for line in mpw_config.splitlines()
+    )
+    software_makefile = (ROOT / "rtl/mini/mk/software.mk").read_text(encoding="utf-8")
+    assert "-DRS_CPU_CLOCK_HZ=$(MGMT_CPU_CLK_HZ)U" in software_makefile
 
     removed_debug = subprocess.run(
         ["make", "HAVE_DEBUG=NO", "config"],
@@ -1042,7 +1054,8 @@ def test_verilator_simulations_use_uniform_timeout() -> None:
                 assert "LINK_TYPE=ld2_all_sram" in values
                 assert "VERILATOR_SIM_ARGS=--fast-flash" in values
             elif "coremark-report" in values:
-                assert simulation_timeout == ["SOC_SIM_TIME=3600"]
+                assert simulation_timeout == ["SOC_SIM_TIME=7200"]
+                assert not any(value.startswith("VERILATOR_SIM_ARGS=") for value in values)
             else:
                 assert not simulation_timeout
             if "debug-sim" not in values:
@@ -1394,8 +1407,9 @@ def test_nightly_extra_regression_skips_pr_netsim() -> None:
     )
     assert (
         "+ make CONFIG=configs/benchmark/ihp130-hazard3-coremark.mk "
-        "SIMU=VERILATOR SOC_SIM_TIME=3600 HAVE_SVA=YES coremark-report" in extra.stdout
+        "SIMU=VERILATOR SOC_SIM_TIME=7200 HAVE_SVA=YES coremark-report" in extra.stdout
     )
+    assert "--fast-flash" not in extra.stdout
     assert "+ make CONFIG=configs/ci/ihp130.mk SYNTH=YOSYS SYNTH_RECIPE=area synth" in extra.stdout
     assert "+ make CONFIG=configs/ci/ihp130.mk STA=OPENSTA SYNTH_RECIPE=area sta" in extra.stdout
     assert "+ make CONFIG=configs/ci/ihp130.mk SYNTH_RECIPE=area metrics" in extra.stdout