refactor: remove HAVE_DEBUG feature and related code

- Eliminated the HAVE_DEBUG preprocessor directive and all associated code from the RTL and test files.
- Updated the Emulator class to remove JTAG-related debug signals and configurations.
- Adjusted the pin map and JSON configurations to exclude debug-related entries.
- Modified the management core wrapper to only support the HAZARD3 core, removing references to the PICORV32 core.
- Updated tests to reflect the removal of the HAVE_DEBUG feature, ensuring they no longer check for debug-related conditions.
- Cleaned up various scripts and makefiles to remove dependencies on the HAVE_DEBUG flag, streamlining the build process.

tests/rtl/sysctrl_fault_tb.sv

@@ -124,10 +124,10 @@ module sysctrl_fault_tb;
     if (read_data !== 32'd11) $fatal(1, "performance snapshot was not recorded");
 
     read_register(32'h1000_B020, read_data);
-    if (read_data !== 32'h0000_001F) $fatal(1, "user cores were not held in reset");
+    if (read_data !== 32'h0000_003F) $fatal(1, "user cores were not held in reset");
     write_register(32'h1000_B000, 32'h0000_0006);
     read_register(32'h1000_B024, read_data);
-    if ((read_data & 32'h0000_081F) !== 32'h0000_0800) begin
+    if ((read_data & 32'h0000_083F) !== 32'h0000_0800) begin
       $fatal(1, "out-of-range user core selection was accepted");
     end
     write_register(32'h1000_B024, 32'h0000_0800);

tests/test_pin_map.py

@@ -44,15 +44,9 @@ def test_pin_map_generates_asic_and_platform_bindings(tmp_path: Path) -> None:
 
     ports = (tmp_path / "rtl/retrosoc_asic_ports.svh").read_text(encoding="utf-8")
     pads = (tmp_path / "rtl/retrosoc_asic_pad_bindings.svh").read_text(encoding="utf-8")
-    fpga = (tmp_path / "rtl/retrosoc_asic_fpga_mini_bindings.svh").read_text(
-        encoding="utf-8"
-    )
-    testbench = (tmp_path / "rtl/retrosoc_asic_tb_bindings.svh").read_text(
-        encoding="utf-8"
-    )
-    verilator = (tmp_path / "rtl/retrosoc_asic_verilator_bindings.svh").read_text(
-        encoding="utf-8"
-    )
+    fpga = (tmp_path / "rtl/retrosoc_asic_fpga_mini_bindings.svh").read_text(encoding="utf-8")
+    testbench = (tmp_path / "rtl/retrosoc_asic_tb_bindings.svh").read_text(encoding="utf-8")
+    verilator = (tmp_path / "rtl/retrosoc_asic_verilator_bindings.svh").read_text(encoding="utf-8")
 
     assert "inout extclk_i_pad," in ports
     assert "input xi_i_pad," in ports
@@ -60,6 +54,8 @@ def test_pin_map_generates_asic_and_platform_bindings(tmp_path: Path) -> None:
     assert "inout jtag_tck_i_pad" in ports
     assert "inout jtag_trst_n_i_pad" in ports
     assert "output jtag_tdo_o_pad" in ports
+    assert "HAVE_DEBUG" not in ports
+    assert "HAVE_DEBUG" not in pads
     assert "u_gpio_31_io_pad" in pads
     assert "u_sdram_dq15_io_pad" in pads
     assert ".gpio_30_io_pad(gpio_io30)" in fpga
@@ -78,9 +74,7 @@ def test_pin_map_generates_asic_and_platform_bindings(tmp_path: Path) -> None:
 
 def test_pin_map_rejects_duplicate_pads(tmp_path: Path) -> None:
     document = json.loads(PIN_MAP.read_text(encoding="utf-8"))
-    document["pads"][0]["ports"].append(
-        {"name": "extclk_i_pad", "signal": "s_duplicate_clock"}
-    )
+    document["pads"][0]["ports"].append({"name": "extclk_i_pad", "signal": "s_duplicate_clock"})
     invalid_map = tmp_path / "duplicate.json"
     invalid_map.write_text(json.dumps(document), encoding="utf-8")
 
@@ -115,8 +109,18 @@ def test_pin_map_rejects_unknown_profile_pad(tmp_path: Path) -> None:
 
 
 def test_fpga_constraints_reference_declared_top_ports() -> None:
-    top_ports = set(re.findall(r"^\s*(?:input|output|inout)\s+([A-Za-z_][A-Za-z0-9_]*)", FPGA_TOP.read_text(encoding="utf-8"), re.MULTILINE))
-    xdc_ports = set(re.findall(r"\[get_ports\s+([A-Za-z_][A-Za-z0-9_]*)\]", FPGA_XDC.read_text(encoding="utf-8")))
+    top_ports = set(
+        re.findall(
+            r"^\s*(?:input|output|inout)\s+([A-Za-z_][A-Za-z0-9_]*)",
+            FPGA_TOP.read_text(encoding="utf-8"),
+            re.MULTILINE,
+        )
+    )
+    xdc_ports = set(
+        re.findall(
+            r"\[get_ports\s+([A-Za-z_][A-Za-z0-9_]*)\]", FPGA_XDC.read_text(encoding="utf-8")
+        )
+    )
 
     assert xdc_ports
     assert xdc_ports <= top_ports

tests/test_script_tools.py

@@ -118,7 +118,7 @@ def test_generate_all_is_stable_and_expands_paths(tmp_path: Path) -> None:
     assert str(ROOT / "rtl/managed/hazard3/hdl") in hazard3
     assert "rtl/managed/mpw/core/username3" not in hazard3
     assert (tmp_path / "core_hazard3.fl").is_file()
-    assert (tmp_path / "core_picorv32.fl").is_file()
+    assert not (tmp_path / "core_picorv32.fl").exists()
     assert {
         "pdk_gf180.fl",
         "pdk_ics55.fl",
@@ -138,13 +138,11 @@ def test_filelist_round_trips_verilog_define_values(tmp_path: Path) -> None:
     parsed = parse_filelists([tmp_path / "def.fl"])
     output = tmp_path / "round-trip.fl"
     write_filelist(output, parsed)
-    assert output.read_text(encoding="utf-8") == (
-        "+define+SOC_JTAG_IDCODE=32'hDEADBEEF\n"
-    )
+    assert output.read_text(encoding="utf-8") == ("+define+SOC_JTAG_IDCODE=32'hDEADBEEF\n")
     assert parse_filelists([output]) == parsed
 
 
-def test_source_export_selects_the_requested_management_core(tmp_path: Path) -> None:
+def test_source_export_uses_the_fixed_hazard3_management_core(tmp_path: Path) -> None:
     module_path = ROOT / "syn/tools/export_soc_sources.py"
     spec = importlib.util.spec_from_file_location("retrosoc_source_export", module_path)
     assert spec is not None and spec.loader is not None
@@ -156,44 +154,39 @@ def test_source_export_selects_the_requested_management_core(tmp_path: Path) ->
     dynamic_core.write_text("", encoding="utf-8")
     dynamic_ip.write_text("", encoding="utf-8")
 
-    for core, source_name in (
-        ("HAZARD3", "hazard3_cpu_1port.v"),
-        ("PICORV32", "picorv32_ver.v"),
-    ):
-        arguments = SimpleNamespace(
-            pdk="IHP130",
-            simu="IVERILOG",
-            core=core,
-            have_pll=False,
-            have_sram_if=False,
-            have_sram_macro=False,
-            have_sva=False,
-            have_debug="YES" if core == "HAZARD3" else "NO",
-            jtag_idcode="DEADBEEF",
-            dynamic_core_filelist=dynamic_core,
-            dynamic_ip_filelist=dynamic_ip,
-        )
-        generated_dir = tmp_path / core.lower()
-        user_extensions_dir = generated_dir / "user_extensions"
-        source_export.generate_all(generated_dir, source_export.build_defines(arguments))
-        source_export.generate_user_extensions(
-            ROOT / "rtl/mini/integration/user_extensions.json", user_extensions_dir
-        )
-        filelist = source_export.configured_filelist(
-            arguments, generated_dir, user_extensions_dir, require_files=False
-        )
+    arguments = SimpleNamespace(
+        pdk="IHP130",
+        simu="IVERILOG",
+        have_pll=False,
+        have_sram_if=False,
+        have_sram_macro=False,
+        have_sva=False,
+        jtag_idcode="DEADBEEF",
+        dynamic_core_filelist=dynamic_core,
+        dynamic_ip_filelist=dynamic_ip,
+    )
+    generated_dir = tmp_path / "hazard3"
+    user_extensions_dir = generated_dir / "user_extensions"
+    source_export.generate_all(generated_dir, source_export.build_defines(arguments))
+    source_export.generate_user_extensions(
+        ROOT / "rtl/mini/integration/user_extensions.json", user_extensions_dir
+    )
+    filelist = source_export.configured_filelist(
+        arguments, generated_dir, user_extensions_dir, require_files=False
+    )
 
-        assert f"+define+CORE_{core}" in filelist.defines
-        assert "+define+SOC_JTAG_IDCODE=-559038737" in filelist.defines
-        assert ("+define+HAVE_DEBUG" in filelist.defines) == (core == "HAZARD3")
-        assert any(path.name == source_name for path in filelist.files)
+    assert "+define+SOC_JTAG_IDCODE=-559038737" in filelist.defines
+    assert not any(item.startswith("+define+CORE_") for item in filelist.defines)
+    assert "+define+HAVE_DEBUG" not in filelist.defines
+    assert any(path.name == "hazard3_cpu_1port.v" for path in filelist.files)
 
 
-def test_package_forwards_manifest_management_core() -> None:
+def test_package_forwards_manifest_jtag_idcode() -> None:
     package_source = (ROOT / "scripts/package.py").read_text(encoding="utf-8")
 
-    assert '"--core"' in package_source
-    assert 'config.get("CORE", "HAZARD3")' in package_source
+    assert '"--jtag-idcode"' in package_source
+    assert 'config.get("JTAG_IDCODE", "DEADBEEF")' in package_source
+    assert '"--core"' not in package_source
 
 
 def test_formal_filelists_are_scoped_to_the_protocol_duts(tmp_path: Path) -> None:
@@ -508,20 +501,29 @@ def test_make_dry_run_and_validation_do_not_write_filelists() -> None:
     assert invalid.returncode != 0
     assert "Invalid SIMU='UNKNOWN'" in invalid.stderr
 
-    invalid_core = subprocess.run(
+    removed_core = subprocess.run(
         ["make", "CORE=alternate", "config"],
         cwd=ROOT,
         text=True,
         capture_output=True,
     )
-    assert invalid_core.returncode != 0
-    assert "Invalid CORE='alternate'" in invalid_core.stderr
+    assert removed_core.returncode != 0
+    assert "CORE has been removed" in removed_core.stderr
 
     default_core = run("make", "config").stdout
-    assert "CORE               HAZARD3" in default_core
+    assert any(
+        line.startswith("MGMT_CORE") and line.rstrip().endswith("HAZARD3")
+        for line in default_core.splitlines()
+    )
 
-    picorv32_core = run("make", "CORE=PICORV32", "config").stdout
-    assert "CORE               PICORV32" in picorv32_core
+    removed_debug = subprocess.run(
+        ["make", "HAVE_DEBUG=NO", "config"],
+        cwd=ROOT,
+        text=True,
+        capture_output=True,
+    )
+    assert removed_debug.returncode != 0
+    assert "HAVE_DEBUG has been removed" in removed_debug.stderr
 
     removed_ip = subprocess.run(
         ["make", "IP=MDD", "config"],
@@ -668,7 +670,8 @@ def test_verilator_simulations_use_uniform_timeout() -> None:
     for _, values in regression_commands:
         if "SIMU=VERILATOR" in values:
             assert not any(value.startswith("SOC_SIM_TIME=") for value in values)
-            assert "HAVE_SVA=YES" in values
+            if "debug-sim" not in values:
+                assert "HAVE_SVA=YES" in values
 
 
 def test_verilator_has_no_external_core_selection() -> None:
@@ -681,16 +684,18 @@ def test_verilator_has_no_external_core_selection() -> None:
     assert "core_sel_i" not in testbench
 
 
-def test_management_core_selection_is_limited_to_hazard3_and_picorv32() -> None:
+def test_management_core_is_fixed_to_hazard3_with_debug() -> None:
     wrapper = (ROOT / "rtl/mini/top/mgmt_core_wrapper.sv").read_text(encoding="utf-8")
     makefile = (ROOT / "Makefile").read_text(encoding="utf-8")
 
-    assert "VALID_CORE      := HAZARD3 PICORV32" in makefile
-    assert "DEF_LIST += +define+CORE_$(CORE)" in makefile
-    assert "`ifdef CORE_PICORV32" in wrapper
-    assert "`elsif CORE_HAZARD3" in wrapper
+    assert "CORE has been removed" in makefile
+    assert "HAVE_DEBUG has been removed" in makefile
+    assert "CORE_$(CORE)" not in makefile
+    assert "`ifdef CORE_" not in wrapper
+    assert "`ifdef HAVE_DEBUG" not in wrapper
     assert "ahbl2ribp u_ahbl2ribp" in wrapper
     assert ".RESET_VECTOR       (`SOC_CPU_RESET_ADDR)" in wrapper
+    assert ".DEBUG_SUPPORT      (1)" in wrapper
 
 
 def test_hazard3_debug_flow_is_locked_and_uses_remote_bitbang() -> None:
@@ -704,19 +709,22 @@ def test_hazard3_debug_flow_is_locked_and_uses_remote_bitbang() -> None:
         encoding="utf-8"
     )
 
-    assert "HAVE_DEBUG               ?= YES" in makefile
     assert "JTAG_IDCODE              ?= DEADBEEF" in makefile
     assert "if [ $$value -gt 2147483647 ]" in makefile
-    assert "HAVE_DEBUG=YES requires CORE=HAZARD3" in makefile
+    assert "HAVE_DEBUG               ?=" not in makefile
     assert ".MULDIV_UNROLL      (2)" in wrapper
     assert ".BRANCH_PREDICTOR   (1)" in wrapper
     assert ".BREAKPOINT_TRIGGERS(2)" in wrapper
     assert ".HAVE_SBA(0)" in debug_wrapper
     assert "mgmt_debug_reset u_mgmt_debug_reset" in debug_wrapper
     assert "--timeout $(SOC_SIM_TIME)" in verilator_makefile
+    assert "--require-debug-tools" in verilator_makefile
+    assert "HAVE_DEBUG" not in verilator_makefile
     assert "DEBUG_GDB_PASS" in driver
     assert "break *0x30000008" in driver
     assert "adapter driver remote_bitbang" in openocd
+    assert "catch {remote_bitbang port $jtag_port}" in openocd
+    assert "remote_bitbang_port $jtag_port" in openocd
     assert "-expected-id 0xdeadbeef" in openocd
     assert lock["toolchains"]["ubuntu-22.04"]["openocd"]["version"] == "0.12.0-1"
     assert any(profile == "configs/ci/ihp130-debug.mk" for profile, _ in PR_COMMANDS)

tests/test_user_extensions.py

@@ -47,18 +47,20 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
     core = (tmp_path / "rtl/user_core_bindings.svh").read_text(encoding="utf-8")
     ip = (tmp_path / "rtl/user_ip_bindings.svh").read_text(encoding="utf-8")
     filelist = (tmp_path / "user_extensions.fl").read_text(encoding="utf-8")
+    config = (tmp_path / "rtl/user_extensions_config.svh").read_text(encoding="utf-8")
 
-    assert core.count("rib_if u_user_") == 5
-    assert core.count("ribp_if u_user_") == 5
-    assert core.count("ribp2rib #(") == 5
-    assert core.count(".SYNC_RESET(1'b1)") == 2
+    assert core.count("rib_if u_user_") == 6
+    assert core.count("ribp_if u_user_") == 6
+    assert core.count("ribp2rib #(") == 6
+    assert core.count(".SYNC_RESET(1'b1)") == 3
     assert core.count(".SYNC_RESET(1'b0)") == 3
     assert "rib.cmd_valid = '0;" in core
     assert "5'd0: begin" in core
     assert "5'd4: begin" in core
-    assert "5'd5: begin" not in core
+    assert "5'd5: begin" in core
     assert "core_reset_i[0]" in core
     assert "mpw_c0 #(0)" in core
+    assert "mpw_c5 #(5)" in core
     assert "mpw_i1 #(1)" in ip
     assert "User core 0 uses the RIBP contract" in core
     assert ip.count("user_gpio_if #(`USER_GPIO_NUM)") == 2
@@ -66,6 +68,7 @@ def test_extensions_generate_isolated_scalar_bindings(tmp_path: Path) -> None:
     assert "8'd2: begin" in ip
     assert "u_user_2_apb_if.psel = apb.psel;" in ip
     assert filelist.startswith("+incdir+")
+    assert "`define USER_CORE_COUNT 6" in config
 
 
 def test_extensions_reject_noncontiguous_slots_and_invalid_modules(tmp_path: Path) -> None: