feat: update test support for verilator

.github/workflows/test.yml

@@ -9,20 +9,20 @@ on:
 jobs:
   build:
     runs-on: ubuntu-22.04
-    
+
     steps:
     - name: Checkout Repository
       uses: actions/checkout@v4
-      
+
     - name: Setup Environment
       run: python3 setup.py
-      
+
-    - name: Run Tests
+    - name: Compile Firmware
-      run: echo "No tests defined yet"
+      run: make CORE=MDD IP=MDD SIMU=VERILATOR HAVE_SRAM_IF=NO HAVE_SRAM_MACRO=NO HAVE_PLL=NO ISA=RV32IM EXEC_TYPE=ld2_psram firmware
-      
+
-    - name: Build Project
+    - name: Build and Run sim
-      run: echo "Build placeholder"
+      run: make CORE=MDD IP=MDD SIMU=VERILATOR HAVE_SRAM_IF=NO HAVE_SRAM_MACRO=NO HAVE_PLL=NO ISA=RV32IM EXEC_TYPE=ld2_psram sim
-      
+
     - name: Success Notification
       run: echo "Workflow completed successfully"
 

crt/src/main.c

@@ -9,11 +9,12 @@ uint32_t my_get_millis(void) {
 
 void main() {
     uart0_init(CPU_FREQ, UART_BPS);
-
+    app_info();
-    tinybooter();
+    while(1);
-    i2c0_init((uint8_t)(CPU_FREQ / 2 - 1));
+    // tinybooter();
-    qspi_dev_init();
+    // i2c0_init((uint8_t)(CPU_FREQ / 2 - 1));
-    lcd_init();
+    // qspi_dev_init();
+    // lcd_init();
 
     // lv_init();
     // tim1_init();

rtl/mini/Makefile

@@ -1,13 +1,19 @@
 $(info RTL_PATH: $(RTL_PATH))
 
 gen_mpw_code:
+	python3 $(RTL_PATH)/mpw/setup.py
 ifeq ($(IP), MDD)
 	@echo "[mpw] generating user ip ..."
 	python3 $(RTL_PATH)/mpw/ip.py
-	python3 $(RTL_PATH)/mpw/core.py $(SIMU)
 else
 	@echo "[mpw] skipping user ip generation"
 endif
+ifeq ($(CORE), MDD)
+	@echo "[mpw] generating core ..."
+	python3 $(RTL_PATH)/mpw/core.py $(SIMU)
+else
+	@echo "[mpw] skipping core generation"
+endif
 
 include $(RTL_PATH)/script/software.mk
 

rtl/mini/script/verilator.mk

@@ -64,7 +64,7 @@ comp: lint
 	$(MAKE) VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(SOC_COMPILE_HOME) -f V$(SOC_VSRC_TOP).mk -j$(nproc) > $(BUILD_DIR)/compile.log 2>&1
 
 sim: comp
-	$(BUILD_DIR)/emu -i .sw_build/retrosoc_fw.bin
+	$(BUILD_DIR)/emu -i .sw_build/retrosoc_fw.bin -t 360
 
 # $(BUILD_DIR)/emu -t $(SOC_SIM_TIME) -i $(RTL_PATH)/.sw_build/retrosoc_fw.bin
 # $(BUILD_DIR)/emu -i app/asm/hello-asm.bin

setup.py

@@ -205,7 +205,7 @@ def check_software_toolchain_installed():
         result = run_command("riscv32-unknown-elf-gcc --version", check=False)
         if result.returncode == 0:
             version = result.stdout.strip()
-            print(f"✓ riscv32-unknown-elf-gcc version: {version}")
+            print(f"✓ {version}")
             return True
         else:
             print("✗ riscv32-unknown-elf-gcc command exists but cannot get version info")
@@ -252,6 +252,8 @@ def main():
     print("Verilator Installation Check Script")
     print("=" * 60)
 
+    project_path = os.getcwd()
+
     # Check current system
     if not sys.platform.startswith('linux'):
         print("Error: This script only works on Linux systems")
@@ -326,5 +328,10 @@ def main():
 
     check_software_toolchain_installed()
 
+    # TODO: git clone mpw
+    os.chdir(project_path)
+    run_command("git clone https://github.com/retroSoC/mini-ver-mpw.git rtl/mini/mpw")
+    
+
 if __name__ == "__main__":
     main()