feat: add SPI extension documentation and integration details for Tiny SoC

- Introduced the separately approved SPI extension (2026-10-04) for the Tiny SoC, detailing the addition of SPI0 as a master-only controller with 8/16-bit capabilities.
- Updated documentation to reflect the SPI phases (SPI-P0 to SPI-P5) and their respective requirements, including DMA V2.2 pacing and fixed-MMIO requests.
- Specified GPIO assignments for SPI functionality, including the use of previously reserved Gen1 ALT routes.
- Clarified the integration boundaries and dependencies on existing R2 and PIO-lite phases, emphasizing the need for complete implementation before qualification.
- Documented the implications of SPI integration on existing GPIO and DMA channels, ensuring no additional resources are allocated without proper validation.
- Updated the verification ledgers to track pending evidence and implementation gaps for both SPI and PIO-lite extensions.

docs/axi4-stream.md

@@ -13,6 +13,12 @@ implemented or enabled on Mini by this document. The historical I2S/DVP rules
 below do not substitute for PIO-lite's packing, ownership or reset contract;
 the existing [Crypto](ip/crypto.md) streams retain their own framing rules.
 
+The separately frozen [Tiny SPI master](ip/spi.md) uses DMA V2.2 paced fixed
+MMIO requests16/17, not new AXI4-Stream ports. Its source-qualified admission,
+credits, R/B drain and exact serial-frame completion must not be substituted
+with stream VALID/TLAST rules. PIO14/15 and the stream-direction count remain
+unchanged by that SPI extension.
+
 ## Interface Contract
 
 All three links use `DATA_WIDTH=32`, one-bit ID, destination, and user fields,