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feat: enhance test coverage and update system control interfaces

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- Added  interface to  and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in  to reflect new domain names.
- Modified expected outputs in  to include new clock domains.
- Adjusted chip configuration assertions in  to account for additional power pads.
- Enhanced memory map tests in  with new definitions and includes.
- Updated pin mapping tests in  to include new reference clock pads.
- Improved script tools tests in  to ensure correct validation of extension bindings.
- Refined system control tests in  to include new clock control interface.
- Updated USB2 packet RAM tests in  to include new SRAM definitions.
- Enhanced user extensions tests in  to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
This commit is contained in:
maksyuki committed 2026-08-30 08:10:59 +08:00
1 parent 795b3a4b1d
commit 2b6819449c
131 files changed
+5983 -1790
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tests/rtl/axi4_address_gate_tb.sv
+134
View File
@@ -0,0 +1,134 @@
`timescale 1ns / 1ps
module axi4_address_gate_tb;
logic clk_i = 1'b0;
logic rst_n_i = 1'b0;
logic block_new_i = 1'b0;
logic idle_o;
axi4_if #(
.ADDR_WIDTH(32),
.DATA_WIDTH(32),
.ID_WIDTH (1),
.USER_WIDTH(1)
) source (
.aclk (clk_i),
.aresetn(rst_n_i)
);
axi4_if #(
.ADDR_WIDTH(32),
.DATA_WIDTH(32),
.ID_WIDTH (1),
.USER_WIDTH(1)
) sink (
.aclk (clk_i),
.aresetn(rst_n_i)
);
always #5 clk_i = ~clk_i;
axi4_address_gate u_dut (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.block_new_i(block_new_i),
.source (source),
.sink (sink),
.idle_o (idle_o)
);
initial begin
source.awid = '0;
source.awaddr = 32'h1000_1000;
source.awlen = '0;
source.awsize = 3'd2;
source.awburst = 2'd1;
source.awlock = 1'b0;
source.awcache = '0;
source.awprot = '0;
source.awqos = '0;
source.awregion = '0;
source.awuser = '0;
source.awvalid = 1'b0;
source.wdata = 32'hA5A5_5A5A;
source.wstrb = 4'hF;
source.wlast = 1'b1;
source.wuser = '0;
source.wvalid = 1'b0;
source.bready = 1'b1;
source.arid = '0;
source.araddr = 32'h1000_2000;
source.arlen = '0;
source.arsize = 3'd2;
source.arburst = 2'd1;
source.arlock = 1'b0;
source.arcache = '0;
source.arprot = '0;
source.arqos = '0;
source.arregion = '0;
source.aruser = '0;
source.arvalid = 1'b0;
source.rready = 1'b1;
sink.awready = 1'b1;
sink.wready = 1'b1;
sink.bid = '0;
sink.bresp = '0;
sink.buser = '0;
sink.bvalid = 1'b0;
sink.arready = 1'b1;
sink.rid = '0;
sink.rdata = 32'h1234_5678;
sink.rresp = '0;
sink.rlast = 1'b1;
sink.ruser = '0;
sink.rvalid = 1'b0;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
@(negedge clk_i);
if (!idle_o) $fatal(1, "gate did not reset idle");
block_new_i = 1'b1;
source.awvalid = 1'b1;
#1;
if (source.awready || sink.awvalid || idle_o) begin
$fatal(1, "blocked write address was accepted or reported idle");
end
block_new_i = 1'b0;
source.wvalid = 1'b1;
@(posedge clk_i);
@(negedge clk_i);
source.awvalid = 1'b0;
source.wvalid = 1'b0;
block_new_i = 1'b1;
if (idle_o) $fatal(1, "accepted write was not tracked");
sink.bvalid = 1'b1;
#1;
if (!source.bvalid) $fatal(1, "write response was blocked during quiesce");
@(posedge clk_i);
@(negedge clk_i);
sink.bvalid = 1'b0;
if (!idle_o) $fatal(1, "write completion did not restore idle");
block_new_i = 1'b0;
source.arvalid = 1'b1;
@(posedge clk_i);
@(negedge clk_i);
source.arvalid = 1'b0;
block_new_i = 1'b1;
if (idle_o) $fatal(1, "accepted read was not tracked");
sink.rvalid = 1'b1;
#1;
if (!source.rvalid || source.rdata != 32'h1234_5678) begin
$fatal(1, "read response was blocked during quiesce");
end
@(posedge clk_i);
@(negedge clk_i);
sink.rvalid = 1'b0;
if (!idle_o) $fatal(1, "read completion did not restore idle");
$display("AXI4 address gate quiesce test passed");
$finish;
end
endmodule
tests/rtl/pll_ctrl_tb.sv
+81 -36
View File
@@ -2,7 +2,7 @@
module pll_ctrl_tb;
logic ext_clk_i = 1'b0;
logic xtal_clk_i = 1'b0;
logic ref24_clk_i = 1'b0;
logic aud_clk_i = 1'b0;
logic rst_n_i = 1'b0;
logic wdg_reset_req_i = 1'b0;
@@ -12,64 +12,87 @@ module pll_ctrl_tb;
logic fault_reserved_i = 1'b0;
logic sys_clk_o;
logic sys_rst_n_o;
logic aon_clk_o;
logic aon_rst_n_o;
logic hp_clk_o;
logic hp_rst_n_o;
logic pclk_o;
logic pclk_rst_n_o;
logic mem_clk_o;
logic mem_rst_n_o;
logic aud_clk_o;
logic aud_rst_n_o;
logic sys_clkdiv4_o;
apb4_if apb4 (
.pclk (sys_clk_o),
.presetn(sys_rst_n_o)
.pclk (pclk_o),
.presetn(pclk_rst_n_o)
);
sysctrl_if sysctrl ();
pll_ctrl_if pll_ctrl ();
clock_ctrl_if clock_ctrl ();
logic [31:0] read_data;
time edge_start;
time edge_end;
always #7 ext_clk_i = ~ext_clk_i;
always #21 xtal_clk_i = ~xtal_clk_i;
always #21 ref24_clk_i = ~ref24_clk_i;
always #27 aud_clk_i = ~aud_clk_i;
rcu u_rcu (
.ext_clk_i (ext_clk_i),
.ref24_clk_i (ref24_clk_i),
.aud_clk_i (aud_clk_i),
.ext_rst_n_i (rst_n_i),
.wdg_reset_req_i(wdg_reset_req_i),
`ifdef HAVE_PLL
.xtal_clk_i (xtal_clk_i),
`endif
.hp_idle_i (1'b1),
.pclk_idle_i (1'b1),
.pll_ctrl (pll_ctrl),
.clock_ctrl (clock_ctrl),
.aon_clk_o (aon_clk_o),
.aon_rst_n_o (aon_rst_n_o),
.sys_clk_o (sys_clk_o),
.sys_rst_n_o (sys_rst_n_o),
.hp_clk_o (hp_clk_o),
.hp_rst_n_o (hp_rst_n_o),
.pclk_o (pclk_o),
.pclk_rst_n_o (pclk_rst_n_o),
.mem_clk_o (mem_clk_o),
.mem_rst_n_o (mem_rst_n_o),
.aud_clk_o (aud_clk_o),
.aud_rst_n_o (aud_rst_n_o),
.sys_clkdiv4_o (sys_clkdiv4_o),
.timebase_tick_o()
.timebase_tick_o(),
.hp_block_o (),
.pll_fault_o (),
.mem_pad_mode_o (),
.mem_pad_lock_o ()
);
apb4_sysctrl u_sysctrl (
.clk_i (sys_clk_o),
.rst_n_i (sys_rst_n_o),
.clk_i (pclk_o),
.rst_n_i (pclk_rst_n_o),
.fault_valid_i (fault_valid_i),
.fault_addr_i (fault_addr_i),
.fault_wstrb_i (fault_wstrb_i),
.fault_reserved_i(fault_reserved_i),
.apb4 (apb4),
.sysctrl (sysctrl),
.pll_ctrl (pll_ctrl)
.pll_ctrl (pll_ctrl),
.clock_ctrl (clock_ctrl)
);
task automatic read_register(input logic [31:0] address, output logic [31:0] data);
begin
@(negedge sys_clk_o);
@(negedge pclk_o);
apb4.paddr = address;
apb4.pwdata = '0;
apb4.pstrb = '0;
apb4.pwrite = 1'b0;
apb4.psel = 1'b1;
apb4.penable = 1'b0;
@(negedge sys_clk_o);
@(negedge pclk_o);
apb4.penable = 1'b1;
while (!apb4.pready) @(negedge sys_clk_o);
while (!apb4.pready) @(negedge pclk_o);
if (apb4.pslverr !== 1'b0) begin
$fatal(1, "read %h error=%b expected=%b", address, apb4.pslverr, 1'b0);
end
@@ -81,16 +104,16 @@ module pll_ctrl_tb;
task automatic write_register(input logic [31:0] address, input logic [31:0] data);
begin
@(negedge sys_clk_o);
@(negedge pclk_o);
apb4.paddr = address;
apb4.pwdata = data;
apb4.pstrb = 4'hF;
apb4.pwrite = 1'b1;
apb4.psel = 1'b1;
apb4.penable = 1'b0;
@(negedge sys_clk_o);
@(negedge pclk_o);
apb4.penable = 1'b1;
while (!apb4.pready) @(negedge sys_clk_o);
while (!apb4.pready) @(negedge pclk_o);
if (apb4.pslverr !== 1'b0) begin
$fatal(1, "write %h error=%b expected=%b", address, apb4.pslverr, 1'b0);
end
@@ -141,8 +164,12 @@ module pll_ctrl_tb;
sysctrl.perf_flash_wait_i = '0;
sysctrl.rtc_wake_i = 1'b0;
sysctrl.hp_present_i = 1'b0;
rst_n_i = 1'b1;
#10;
rst_n_i = 1'b0;
#100;
rst_n_i = 1'b1;
$display("pll_ctrl_tb: root reset released");
repeat (2) begin
@(posedge aud_clk_i);
#1;
@@ -155,23 +182,40 @@ module pll_ctrl_tb;
$fatal(1, "buffered audio clock did not follow a falling edge");
end
end
$display("pll_ctrl_tb: audio clock buffer passed");
wait (aud_rst_n_o);
repeat (12) @(posedge sys_clk_o);
$display("pll_ctrl_tb: audio reset released");
repeat (50) @(posedge ref24_clk_i);
$display("pll_ctrl_tb: lp_clk=%b lp_rst=%b pclk=%b pclk_rst=%b div=%b valid=%b", sys_clk_o,
sys_rst_n_o, pclk_o, pclk_rst_n_o,
u_rcu.u_clock_reset_subsystem.u_pclk_divider.s_div_q,
u_rcu.u_clock_reset_subsystem.s_pclk_cfg_valid);
wait (pclk_rst_n_o);
repeat (12) @(posedge pclk_o);
$display("pll_ctrl_tb: clock domains released");
wdg_reset_req_i = 1'b1;
#1;
if (sys_rst_n_o || !aud_rst_n_o) begin
$fatal(1, "watchdog reset did not isolate system and audio reset domains");
end
wdg_reset_req_i = 1'b0;
repeat (8) @(posedge sys_clk_o);
if (!sys_rst_n_o || !aud_rst_n_o) begin
$fatal(1, "watchdog system reset did not deassert synchronously");
if (!$test$plusargs("pll_lock_fail")) begin
wdg_reset_req_i = 1'b1;
#1;
if (aon_rst_n_o !== 1'b1 || sys_rst_n_o || hp_rst_n_o || pclk_rst_n_o || mem_rst_n_o ||
aud_rst_n_o) begin
$fatal(1, "watchdog reset did not preserve AON and reset controlled domains");
end
wdg_reset_req_i = 1'b0;
wait (pclk_rst_n_o && sys_rst_n_o && hp_rst_n_o && mem_rst_n_o && aud_rst_n_o);
if (!aon_rst_n_o) begin
$fatal(1, "watchdog reset disturbed AON reset");
end
$display("pll_ctrl_tb: watchdog reset recovery passed");
end
read_register(32'h1000_B01C, read_data);
`ifdef HAVE_PLL
if (read_data !== 32'h0000_0500) begin
if ($test$plusargs("pll_lock_fail")) begin
if ((read_data !== 32'h0000_0500) && (read_data !== 32'h0000_05A0)) begin
$fatal(1, "runtime PLL lock fault status mismatch: %h", read_data);
end
end else if (read_data !== 32'h0000_0500) begin
$fatal(1, "pll reset status is not the external safe clock");
end
`else
@@ -182,6 +226,7 @@ module pll_ctrl_tb;
write_register(32'h1000_B008, 32'd4);
write_register(32'h1000_B00C, 32'd1);
$display("pll_ctrl_tb: PLL request submitted");
wait_for_completion(read_data);
`ifdef HAVE_PLL
@@ -196,10 +241,10 @@ module pll_ctrl_tb;
if (read_data !== 32'h0000_060C) begin
$fatal(1, "pll configuration did not select the requested frequency");
end
repeat (4) @(posedge sys_clk_o);
@(posedge sys_clk_o);
repeat (4) @(posedge hp_clk_o);
@(posedge hp_clk_o);
edge_start = $time;
@(posedge sys_clk_o);
@(posedge hp_clk_o);
edge_end = $time;
if ((edge_end - edge_start) > 9) begin
$fatal(1, "pll behavioral output is slower than 120MHz");
@@ -211,13 +256,13 @@ module pll_ctrl_tb;
if (read_data !== 32'h0000_0608) begin
$fatal(1, "pll did not select the 24MHz profile");
end
repeat (4) @(posedge sys_clk_o);
@(posedge sys_clk_o);
repeat (4) @(posedge hp_clk_o);
@(posedge hp_clk_o);
edge_start = $time;
@(posedge sys_clk_o);
@(posedge hp_clk_o);
edge_end = $time;
if ((edge_end - edge_start) < 35) begin
$fatal(1, "pll behavioral output is faster than the 24MHz profile");
if ((edge_end - edge_start) < 12) begin
$fatal(1, "pll behavioral output is faster than the 72MHz profile");
end
$display("pll controller dynamic configuration test passed");
tests/rtl/rib2apb_tb.sv
+11 -1
View File
@@ -18,6 +18,8 @@ module rib2apb_tb;
apb4_pure_if wdg ();
apb4_pure_if crc ();
apb4_pure_if user_ip ();
apb4_pure_if ext_l ();
apb4_pure_if ext_h ();
always #5 clk_i = ~clk_i;
@@ -45,6 +47,12 @@ module rib2apb_tb;
assign user_ip.pready = 1'b0;
assign user_ip.prdata = '0;
assign user_ip.pslverr = 1'b0;
assign ext_l.pready = 1'b0;
assign ext_l.prdata = '0;
assign ext_l.pslverr = 1'b0;
assign ext_h.pready = 1'b0;
assign ext_h.prdata = '0;
assign ext_h.pslverr = 1'b0;
rib2apb u_rib2apb (
.clk_i (clk_i),
@@ -57,7 +65,9 @@ module rib2apb_tb;
.rtc (rtc),
.wdg (wdg),
.crc (crc),
.user_ip (user_ip)
.user_ip (user_ip),
.ext_l (ext_l),
.ext_h (ext_h)
);
task automatic send_command(input logic [31:0] address, input logic write,
tests/rtl/soc_irq_topology_tb.sv
+3 -1
View File
@@ -56,6 +56,8 @@ module soc_irq_topology_tb;
2: expect_irq(32'd1 << 13);
3: expect_irq(32'd1 << 14);
4: expect_irq(32'd1 << 16);
5: expect_irq(32'd1 << 27);
6: expect_irq(32'd1 << 28);
default: $fatal(1, "unexpected APB IRQ bit %0d", bit_index);
endcase
end
@@ -66,7 +68,7 @@ module soc_irq_topology_tb;
$fatal(1, "SDIO core IRQ bits are not low when sources are low: IRQ10=%b IRQ21=%b",
s_irq[10], s_irq[21]);
end
if ((s_irq[31:27] !== '0) || (s_irq[19:18] !== '0)) begin
if ((s_irq[31:29] !== '0) || (s_irq[19:18] !== '0)) begin
$fatal(1, "unallocated core IRQ bits are not low: %h", s_irq);
end
tests/rtl/sysctrl_tb.sv
+38 -17
View File
@@ -13,6 +13,7 @@ module sysctrl_tb;
);
sysctrl_if sysctrl ();
pll_ctrl_if pll_ctrl ();
clock_ctrl_if clock_ctrl ();
always #5 clk_i = ~clk_i;
@@ -25,7 +26,8 @@ module sysctrl_tb;
.fault_reserved_i(fault_reserved_i),
.apb4 (apb4),
.sysctrl (sysctrl),
.pll_ctrl (pll_ctrl)
.pll_ctrl (pll_ctrl),
.clock_ctrl (clock_ctrl)
);
task automatic read_register(input logic [31:0] address, output logic [31:0] data);
@@ -49,6 +51,28 @@ module sysctrl_tb;
end
endtask
task automatic write_register_error(input logic [31:0] address, input logic [31:0] data);
begin
@(negedge clk_i);
apb4.paddr = address;
apb4.pwdata = data;
apb4.pstrb = 4'hF;
apb4.pwrite = 1'b1;
apb4.psel = 1'b1;
apb4.penable = 1'b0;
@(negedge clk_i);
apb4.penable = 1'b1;
while (!apb4.pready) @(negedge clk_i);
if (apb4.pslverr !== 1'b1) begin
$fatal(1, "write %h error=%b expected=%b", address, apb4.pslverr, 1'b1);
end
apb4.psel = 1'b0;
apb4.penable = 1'b0;
apb4.pwrite = 1'b0;
apb4.pstrb = '0;
end
endtask
task automatic write_register(input logic [31:0] address, input logic [31:0] data);
begin
@(negedge clk_i);
@@ -102,6 +126,12 @@ module sysctrl_tb;
pll_ctrl.rsp_error_i = '0;
pll_ctrl.rsp_valid_i = 1'b0;
pll_ctrl.capable_i = 1'b0;
clock_ctrl.req_ready_i = 1'b1;
clock_ctrl.rsp_data_i = '0;
clock_ctrl.rsp_valid_i = 1'b0;
clock_ctrl.current_i = '0;
clock_ctrl.fault_i = '0;
clock_ctrl.memory_i = 32'h0000_0005;
repeat (2) @(posedge clk_i);
rst_n_i = 1'b1;
@@ -156,24 +186,15 @@ module sysctrl_tb;
if (read_data !== 32'd151) $fatal(1, "USB2 performance snapshot was not recorded");
read_register(32'h1000_B020, read_data);
if (read_data !== 32'h0000_000F) $fatal(1, "user cores were not held in reset");
write_register(32'h1000_B000, 32'h0000_0004);
if (read_data !== 32'hFFFF_FFFF) $fatal(1, "retired user cores were not held in reset");
read_register(32'h1000_B024, read_data);
if ((read_data & 32'h0000_083F) !== 32'h0000_0800) begin
$fatal(1, "out-of-range user core selection was accepted");
end
write_register(32'h1000_B024, 32'h0000_0800);
write_register(32'h1000_B000, 32'h0000_0001);
write_register(32'h1000_B020, 32'h0000_000D);
if (read_data !== 32'h0000_0200) $fatal(1, "retired user-core status was not idle");
write_register_error(32'h1000_B000, 32'h0000_0001);
write_register_error(32'h1000_B004, 32'h0000_0001);
write_register_error(32'h1000_B020, 32'hFFFF_FFFE);
write_register_error(32'h1000_B024, 32'h0000_0800);
read_register(32'h1000_B024, read_data);
if ((read_data & 32'h0000_0300) !== 32'h0000_0300 || (read_data & 32'h1F) != 1) begin
$fatal(1, "user core start state was not recorded");
end
write_register(32'h1000_B020, 32'h0000_000F);
read_register(32'h1000_B024, read_data);
if ((read_data & 32'h0000_0300) !== 32'h0000_0200) begin
$fatal(1, "user core stop state was not recorded");
end
if (read_data !== 32'h0000_0A00) $fatal(1, "retired user-core write fault was not sticky");
read_register(32'h1000_B084, read_data);
if (read_data !== 32'h0000_0000) begin