feat: enhance test coverage and update system control interfaces

- Added  interface to  and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in  to reflect new domain names.
- Modified expected outputs in  to include new clock domains.
- Adjusted chip configuration assertions in  to account for additional power pads.
- Enhanced memory map tests in  with new definitions and includes.
- Updated pin mapping tests in  to include new reference clock pads.
- Improved script tools tests in  to ensure correct validation of extension bindings.
- Refined system control tests in  to include new clock control interface.
- Updated USB2 packet RAM tests in  to include new SRAM definitions.
- Enhanced user extensions tests in  to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.

tests/test_librelane_flow.py

@@ -45,10 +45,10 @@ def test_chip_config_places_every_signal_and_power_pad_once(tmp_path: Path) -> N
     sides = {name: config[f"PAD_{name.upper()}"] for name in module.SIDE_ORDER}
     placed = [instance for side in module.SIDE_ORDER for instance in sides[side]]
 
-    assert len(placed) == 191
+    assert len(placed) == 192
     assert len(placed) == len(set(placed))
     assert {side: len(instances) for side, instances in sides.items()} == {
-        "south": 32,
+        "south": 33,
         "east": 52,
         "north": 48,
         "west": 59,
@@ -58,6 +58,7 @@ def test_chip_config_places_every_signal_and_power_pad_once(tmp_path: Path) -> N
     assert sum(item.startswith("iovdd_pads[") for item in placed) == 16
     assert sum(item.startswith("iovss_pads[") for item in placed) == 16
     assert "u_extclk_i_pad.u_sg13g2_IOPadIn" in sides["south"]
+    assert "u_ref24clk_i_pad.u_sg13g2_IOPadIn" in sides["south"]
     assert "u_gpio_31_io_pad.u_sg13g2_IOPadInOut4mA" in sides["east"]
     assert "u_sdram_dq15_io_pad.u_sg13g2_IOPadInOut4mA" in sides["west"]
     assert config["DIE_AREA"] == [0, 0, 8000, 8000]