feat: enhance test coverage and update system control interfaces

- Added  interface to  and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in  to reflect new domain names.
- Modified expected outputs in  to include new clock domains.
- Adjusted chip configuration assertions in  to account for additional power pads.
- Enhanced memory map tests in  with new definitions and includes.
- Updated pin mapping tests in  to include new reference clock pads.
- Improved script tools tests in  to ensure correct validation of extension bindings.
- Refined system control tests in  to include new clock control interface.
- Updated USB2 packet RAM tests in  to include new SRAM definitions.
- Enhanced user extensions tests in  to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.

tests/test_usb2.py

@@ -129,8 +129,9 @@ def test_usb2_packet_ram_ecc_with_ics55_macros() -> None:
         [
             "rtl/managed/clusterip/common/rtl/utils/register.sv",
             "rtl/managed/clusterip/common/rtl/base/ecc_secded.sv",
-            "tests/rtl/ics55_sram_4096x32_stub.sv",
-            "rtl/tech/tc_usb2_packet_ram.sv",
+                "tests/rtl/ics55_sram_4096x32_stub.sv",
+                "rtl/tech/tc_sram.sv",
+                "rtl/tech/tc_usb2_packet_ram.sv",
             "rtl/ip/usb/usb2_packet_ram.sv",
             "tests/rtl/usb2_packet_ram_tb.sv",
         ],