feat: refactor tests for mailbox and environment validation

- Updated mailbox purpose tests to reflect new write order and sequence handling.
- Added tests to ensure Linux-ready values match LP contract and constants match Linux helper.
- Introduced tests to verify that offset changes do not hide stale Linux helpers.
- Enhanced environment tests to report current locked launcher and runtime versions.
- Added checks for SBT launcher presence in environment labels.
- Improved full diagram tests to validate storage geometry and RSA vector configurations.
- Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries.
- Modified script tools tests to include Vexii generation validation and updated workflow assertions.

scripts/README.md

@@ -123,8 +123,9 @@ SRAM CoreMark quick report into `meta/coremark.json`; it requires one valid
 `COREMARK_RESULT` record and `COREMARK_PASS`. Both reports complement, rather
 than replace, the common `SIM_TEST_PASS` simulation verdict.
 
-`generate_vexiiriscv.py` verifies the locked VexiiRiscv revision and generates
-the fixed HP core below `build/`; generated RTL is never tracked.
+`generate_vexiiriscv.py` verifies the locked VexiiRiscv revision, rejects local
+source changes before and after generation, and generates the fixed HP core
+below `build/`; generated RTL is never tracked.
 `setup_hp_linux.py` installs the locked OpenSBI, Linux, and Buildroot revisions
 and can resume a checkout left without `HEAD` by an interrupted fetch.
 `build_hp_linux.py` builds the RV64 `lp64d` userspace/OpenSBI image set with the repo-owned

scripts/generate_vexiiriscv.py

@@ -46,14 +46,22 @@ def locked_revision(lock_path: Path) -> str:
     return source["revision"]
 
 
+def validate_locked_source(source: Path, expected: str) -> str:
+    actual = git_revision(source)
+    if actual != expected:
+        raise ValueError(f"VexiiRiscv revision mismatch: expected {expected}, found {actual}")
+    status = git_status(source)
+    if status:
+        raise ValueError("VexiiRiscv source has local changes:\n" + "\n".join(status))
+    return actual
+
+
 def generate(args: argparse.Namespace) -> None:
     root = args.root.resolve()
     source = args.source.resolve()
     output = args.output.resolve()
     expected = locked_revision(args.lock.resolve())
-    actual = git_revision(source)
-    if actual != expected:
-        raise ValueError(f"VexiiRiscv revision mismatch: expected {expected}, found {actual}")
+    actual = validate_locked_source(source, expected)
 
     scala_dir = root / "scripts" / "vexiiriscv"
     output.mkdir(parents=True, exist_ok=True)
@@ -81,6 +89,7 @@ def generate(args: argparse.Namespace) -> None:
     generated = output / "vexii_riscv_hp_generated.v"
     if not generated.is_file():
         raise FileNotFoundError(f"VexiiRiscv generator did not create {generated}")
+    validate_locked_source(source, expected)
 
     submodules = run(["git", "submodule", "status", "--recursive"], source).splitlines()
     manifest = {
@@ -91,7 +100,7 @@ def generate(args: argparse.Namespace) -> None:
         "physical_address_width": 32,
         "mmu": "sv39",
         "vexiiriscv_revision": actual,
-        "source_status": git_status(source),
+        "source_status": [],
         "submodules": submodules,
         "generator": str((scala_dir / "GenerateRetroSocHp.scala").relative_to(root)),
         "files": {generated.name: sha256(generated)},

scripts/regress.py

@@ -33,9 +33,9 @@ CI_SMOKE_SIM_VALUES = (
 CI_SMOKE_SDRAM_SIM_VALUES = (
     CI_SMOKE_APP_VALUE,
     "LINK_TYPE=ld2_sdram",
-    # Hosted Verilator executes the expanded GA2D acceptance workload more
+    # Hosted Verilator executes the expanded peripheral acceptance workload
     # slowly when LP code and accelerator traffic share the SDRAM target.
-    "SOC_SIM_TIME=1800",
+    "SOC_SIM_TIME=3600",
     *CI_SMOKE_VERILATOR_VALUES,
 )
 RTL_LINT_VALUES = ("SIMU=VERILATOR", "HAVE_SVA=YES", "rtl-lint")