feat: add DVP (Digital Video Processor) support and related formal verification

- Modified dma_core to accommodate a wider data width for FIFO operations.
- Updated filelists to include new DVP source files and formal verification files.
- Introduced formal verification modules for DVP functionality.
- Enhanced clock and reset domain configurations for DVP integration.
- Added DVP interrupt handling in the IRQ topology.
- Implemented a testbench for DVP to validate register access and frame processing.
- Updated software build scripts to include DVP-related source files.
- Adjusted the system topology to reflect the new DVP interrupt and IRQ mapping.

tests/rtl/dvp_tb.sv

@@ -0,0 +1,135 @@
+`timescale 1ns / 1ps
+
+module dvp_tb;
+  logic        clk_i = 1'b0;
+  logic        pclk_i = 1'b0;
+  logic        rst_n_i = 1'b0;
+  logic        href_i = 1'b0;
+  logic        vsync_i = 1'b0;
+  logic [ 7:0] dat_i = 8'd0;
+  logic [31:0] ribp_rdata;
+  logic        irq_o;
+  ribp_if ribp ();
+  axi4_stream_if #(
+      .DATA_WIDTH(32),
+      .ID_WIDTH  (1),
+      .DEST_WIDTH(1),
+      .USER_WIDTH(1)
+  ) axis (
+      .aclk   (clk_i),
+      .aresetn(rst_n_i)
+  );
+  dvp_if dvp ();
+
+  assign dvp.pclk_i  = pclk_i;
+  assign dvp.href_i  = href_i;
+  assign dvp.vsync_i = vsync_i;
+  assign dvp.dat_i   = dat_i;
+  assign axis.tready = 1'b1;
+  always #5 clk_i = ~clk_i;
+  always #10 pclk_i = ~pclk_i;
+
+  ribp_dvp u_dut (
+      .clk_i  (clk_i),
+      .rst_n_i(rst_n_i),
+      .ribp   (ribp),
+      .rx_axis(axis),
+      .dvp    (dvp),
+      .irq_o  (irq_o)
+  );
+
+  task automatic write(input logic [31:0] address, input logic [31:0] data);
+    begin
+      @(negedge clk_i);
+      ribp.valid = 1'b1;
+      ribp.addr  = address;
+      ribp.wdata = data;
+      ribp.wstrb = 4'hf;
+      do @(negedge clk_i); while (!ribp.ready);
+      if (ribp.resp_err) $fatal(1, "unexpected write error at %h", address);
+      ribp.valid = 1'b0;
+      ribp.wstrb = '0;
+    end
+  endtask
+
+  task automatic read(input logic [31:0] address, output logic [31:0] data);
+    begin
+      @(negedge clk_i);
+      ribp.valid = 1'b1;
+      ribp.addr  = address;
+      ribp.wdata = '0;
+      ribp.wstrb = '0;
+      do @(negedge clk_i); while (!ribp.ready);
+      data       = ribp.rdata;
+      ribp.valid = 1'b0;
+    end
+  endtask
+
+  task automatic frame(input int lines, input int pixels);
+    begin
+      vsync_i = 1'b1;
+      repeat (3) @(posedge pclk_i);
+      vsync_i = 1'b0;
+      repeat (2) @(posedge pclk_i);
+      for (int line = 0; line < lines; line++) begin
+        href_i = 1'b1;
+        for (int index = 0; index < pixels * 2; index++) begin
+          dat_i = index + line * 8;
+          @(posedge pclk_i);
+        end
+        href_i = 1'b0;
+        repeat (2) @(posedge pclk_i);
+      end
+      vsync_i = 1'b1;
+      repeat (3) @(posedge pclk_i);
+      vsync_i = 1'b0;
+    end
+  endtask
+
+  task automatic check_frame(input int lines, input int pixels, input int expected_beats);
+    begin
+      beats = 0;
+      frame(lines, pixels);
+      repeat (80) @(posedge clk_i);
+      if (beats != expected_beats)
+        $fatal(1, "unexpected AXI beat count=%0d expected=%0d", beats, expected_beats);
+    end
+  endtask
+
+  logic [31:0] value;
+  int          beats;
+  always @(posedge clk_i) begin
+    if (axis.tvalid && axis.tready) begin
+      beats = beats + 1;
+      if (beats == 1 && !axis.tuser[0]) $fatal(1, "SOF missing");
+      if ((beats == 2 || beats == 4) && !axis.tlast) $fatal(1, "EOL missing");
+    end
+  end
+  initial begin
+    ribp.valid = 1'b0;
+    ribp.addr  = '0;
+    ribp.wdata = '0;
+    ribp.wstrb = '0;
+    repeat (4) @(posedge clk_i);
+    rst_n_i = 1'b1;
+    read(32'h0000_00f8, value);
+    if (value != 32'h0002_0000) $fatal(1, "bad DVP version %h", value);
+    read(32'h0000_0100, value);
+    if (!ribp.resp_err) $fatal(1, "invalid DVP access was accepted");
+    write(32'h0000_0018, {16'd2, 16'd4});
+    write(32'h0000_000c, 32'd1);
+    write(32'h0000_0000, 32'd3);
+    repeat (50) @(posedge pclk_i);
+    check_frame(2, 4, 4);
+    read(32'h0000_0024, value);
+    if (value == 0)
+      $fatal(1, "frame count/beats invalid count=%h beats=%0d", value, beats);
+    write(32'h0000_0018, {16'd2, 16'd3});
+    check_frame(1, 3, 2);
+    write(32'h0000_0048, 32'h0000_0004);
+    read(32'h0000_003c, value);
+    if (ribp.resp_err) $fatal(1, "DVP interrupt read failed");
+    $display("RIBP DVP V2 capture test passed");
+    $finish;
+  end
+endmodule

tests/rtl/soc_irq_topology_tb.sv

@@ -33,7 +33,10 @@ module soc_irq_topology_tb;
     for (int bit_index = 10; bit_index < `SOC_IRQ_RIBP_WIDTH; bit_index++) begin
       s_ribp_irq            = '0;
       s_ribp_irq[bit_index] = 1'b1;
-      expect_irq(32'd1 << (bit_index + 7));
+      case (bit_index)
+        13:      expect_irq(32'd1 << 15);
+        default: expect_irq(32'd1 << (bit_index + 7));
+      endcase
     end
 
     for (int bit_index = 0; bit_index < `SOC_IRQ_APB_WIDTH; bit_index++) begin
@@ -52,8 +55,8 @@ module soc_irq_topology_tb;
 
     s_apb_irq = '0;
     expect_irq('0);
-    if (s_irq[10] !== 1'b0 || s_irq[15] !== 1'b0) begin
-      $fatal(1, "removed core IRQ bits are not low: IRQ10=%b IRQ15=%b", s_irq[10], s_irq[15]);
+    if (s_irq[10] !== 1'b0) begin
+      $fatal(1, "removed core IRQ bit is not low: IRQ10=%b", s_irq[10]);
     end
     if (s_irq[31:18] !== '0) begin
       $fatal(1, "unallocated core IRQ bits are not low: %h", s_irq[31:18]);

tests/test_dvp.py

@@ -0,0 +1,63 @@
+"""RIBP DVP V2 register, CDC, framing, and packing regression."""
+
+from __future__ import annotations
+
+import shutil
+import subprocess
+import sys
+from pathlib import Path
+
+
+ROOT = Path(__file__).resolve().parents[1]
+
+
+def test_dvp_capture_framing(tmp_path: Path) -> None:
+    iverilog = shutil.which("iverilog")
+    vvp = shutil.which("vvp")
+    if iverilog is None or vvp is None:
+        return
+    common = ROOT / "rtl/managed/clusterip/common/rtl"
+    ip = ROOT / "rtl/ip/ribp/multimedia"
+    defines = [
+        "+define+PDK_BEHAV",
+        "+define+SV_ASSRT_DISABLE",
+    ]
+    source = [
+        "+incdir+" + str(common),
+        "+incdir+" + str(common / "interface"),
+        "+incdir+" + str(common / "utils"),
+        "+incdir+" + str(common / "cdc"),
+        "+incdir+" + str(common / "clkrst"),
+        "+incdir+" + str(ip),
+        str(common / "interface/ribp_if.sv"),
+        str(common / "interface/axi4_stream_if.sv"),
+        str(common / "utils/register.sv"),
+        str(common / "utils/xchecker.sv"),
+        str(common / "utils/bin2gray.sv"),
+        str(common / "utils/gray2bin.sv"),
+        str(common / "utils/spill_register.sv"),
+        str(common / "cdc/cdc_sync.sv"),
+        str(common / "cdc/cdc_rst_ctrlr.sv"),
+        str(common / "cdc/async_reqack.sv"),
+        str(common / "cdc/cdc_fifo.sv"),
+        str(common / "cdc/cdc_2phase.sv"),
+        str(common / "cdc/cdc_warm_flush.sv"),
+        str(common / "utils/edge_det.sv"),
+        str(common / "clkrst/rst_sync.sv"),
+        str(ROOT / "rtl/tech/tc_clk.sv"),
+        str(ip / "dvp_core.sv"),
+        str(ip / "dvp_reg.sv"),
+        str(ip / "dvp.sv"),
+        str(ROOT / "tests/rtl/dvp_tb.sv"),
+    ]
+    source_list = tmp_path / "dvp.fl"
+    source_list.write_text("\n".join([*defines, *source, ""]), encoding="utf-8")
+    converted = tmp_path / "dvp.v"
+    subprocess.run(
+        [sys.executable, str(ROOT / "rtl/mini/script/convt_sv2v.py"), "-f", str(source_list), "--output", str(converted)],
+        check=True,
+    )
+    simulation = tmp_path / "dvp_tb"
+    subprocess.run([iverilog, "-g2012", "-s", "dvp_tb", "-o", str(simulation), str(converted)], check=True)
+    result = subprocess.run([vvp, str(simulation)], check=True, capture_output=True, text=True)
+    assert "RIBP DVP V2 capture test passed" in result.stdout

tests/test_soc_topology.py

@@ -113,20 +113,21 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert ".cfg_axi4(u_cfg_axi4_if)" in bus_fabric
     assert ".apb_axi4(u_apb_axi4_if)" in bus_fabric
     assert "`define SOC_IRQ_VECTOR_WIDTH 32" in irq_config
-    assert "`define SOC_USER_IRQ_MASK 32'h000E7BFC" in irq_config
-    assert "`define SOC_IRQ_RIBP_WIDTH 13" in irq_config
+    assert "`define SOC_USER_IRQ_MASK 32'h000EFBFC" in irq_config
+    assert "`define SOC_IRQ_RIBP_WIDTH 14" in irq_config
     assert "`define SOC_IRQ_APB_WIDTH 5" in irq_config
     assert "assign irq_o[0] = u_clint_if.software_irq_o[0];" in rib_irq
     assert "assign irq_o[10] = ws2812.irq_o;" in rib_irq
     assert "assign irq_o[11] = gpio.irq_o;" in rib_irq
     assert "assign irq_o[12] = i2c1.irq_o;" in rib_irq
+    assert "assign irq_o[13] = s_dvp_irq;" in rib_irq
     assert "assign irq_o[0] = pwm.irq_o;" in apb_irq
     assert "assign irq_o[4] = s_rng_irq;" in apb_irq
     assert "s_irq[10]" not in irq_wiring
-    assert "s_irq[15]" not in irq_wiring
+    assert "s_irq[15] = s_ribp_irq[13];" in irq_wiring
     assert "s_irq[16] = s_apb_irq[4];" in irq_wiring
     assert "irq_i[10] == 1'b0" in irq_sva
-    assert "irq_i[15] == 1'b0" in irq_sva
+    assert "irq_i[15] == ribp_irq_i[13]" in irq_sva
     assert "irq_i[31] == 1'b0" in irq_sva
     assert "bind retrosoc soc_irq_topology_sva" in irq_sva
     assert filelist.startswith("+incdir+")
@@ -164,6 +165,7 @@ def test_topology_preserves_default_irq_compatibility_mapping() -> None:
         ("ws2812", "ribp", 10, 17, "ws2812.irq_o"),
         ("gpio", "ribp", 11, 18, "gpio.irq_o"),
         ("i2c1", "ribp", 12, 19, "i2c1.irq_o"),
+        ("dvp", "ribp", 13, 15, "s_dvp_irq"),
     ]