feat: add CLINT peripheral support and related enhancements

- Updated the formal file list generator to include CLINT source files.
- Added CLINT timebase to the clock and reset domains configuration.
- Enhanced the SOC topology generation to include CLINT interrupts and their mappings.
- Introduced a new CLINT testbench to validate multi-hart and timebase functionality.
- Modified the software build configuration to define CLINT timebase frequency.
- Updated the RCU module to integrate CLINT timebase generation.
- Adjusted the IRQ configuration to reflect changes in CLINT interrupt signals.
- Added user-visible flags for interrupts in the topology configuration.
- Enhanced the clock reset domain checks to include CLINT timebase.
- Updated the memory map tests to validate CLINT peripheral integration.

scripts/check_clock_reset_domains.py

@@ -11,7 +11,13 @@ from typing import Any
 
 
 RESET_PRIMITIVES = {"rst_sync"}
-CDC_PRIMITIVES = {"async_fifo", "cdc_2phase", "cdc_sync", "hazard3_apb_async_bridge"}
+CDC_PRIMITIVES = {
+    "async_fifo",
+    "cdc_2phase",
+    "cdc_sync",
+    "edge_det",
+    "hazard3_apb_async_bridge",
+}
 IDENTIFIER_RE = re.compile(r"[A-Za-z_][A-Za-z0-9_]*$")
 HIERARCHICAL_PIN_RE = re.compile(
     r"[A-Za-z_][A-Za-z0-9_.]*(?:/[A-Za-z_][A-Za-z0-9_.]*)+$"