feat: add CLINT peripheral support and related enhancements

- Updated the formal file list generator to include CLINT source files.
- Added CLINT timebase to the clock and reset domains configuration.
- Enhanced the SOC topology generation to include CLINT interrupts and their mappings.
- Introduced a new CLINT testbench to validate multi-hart and timebase functionality.
- Modified the software build configuration to define CLINT timebase frequency.
- Updated the RCU module to integrate CLINT timebase generation.
- Adjusted the IRQ configuration to reflect changes in CLINT interrupt signals.
- Added user-visible flags for interrupts in the topology configuration.
- Enhanced the clock reset domain checks to include CLINT timebase.
- Updated the memory map tests to validate CLINT peripheral integration.

tests/test_clock_reset_domains.py

@@ -42,7 +42,14 @@ def test_clock_reset_domain_inventory_matches_the_rcu() -> None:
     assert {
         (crossing["name"], crossing["source"], crossing["destination"])
         for crossing in document["crossings"]
-    } >= {("jtag_dmi", "jtag", "system")}
+    } >= {
+        ("clint_timebase", "external", "system"),
+        ("jtag_dmi", "jtag", "system"),
+    }
+    clint = next(
+        crossing for crossing in document["crossings"] if crossing["name"] == "clint_timebase"
+    )
+    assert clint["primitive"] == "edge_det"
 
 
 def test_clock_reset_domain_inventory_rejects_unknown_domain_and_instance(tmp_path: Path) -> None: