feat: add CLINT peripheral support and related enhancements

- Updated the formal file list generator to include CLINT source files.
- Added CLINT timebase to the clock and reset domains configuration.
- Enhanced the SOC topology generation to include CLINT interrupts and their mappings.
- Introduced a new CLINT testbench to validate multi-hart and timebase functionality.
- Modified the software build configuration to define CLINT timebase frequency.
- Updated the RCU module to integrate CLINT timebase generation.
- Adjusted the IRQ configuration to reflect changes in CLINT interrupt signals.
- Added user-visible flags for interrupts in the topology configuration.
- Enhanced the clock reset domain checks to include CLINT timebase.
- Updated the memory map tests to validate CLINT peripheral integration.

tests/test_memory_map.py

@@ -227,7 +227,10 @@ def test_pll_controller_reconfigures_and_falls_back_to_the_safe_clock(tmp_path:
                 str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/cdc/cdc_2phase.sv"),
                 str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv"),
+                str(ROOT / "rtl/managed/clusterip/common/rtl/clkrst/counter.sv"),
+                str(ROOT / "rtl/managed/clusterip/common/rtl/utils/edge_det.sv"),
                 str(ROOT / "rtl/ip/ribp/peripheral/pll_ctrl_if.sv"),
+                str(ROOT / "rtl/ip/ribp/peripheral/clint_timebase.sv"),
                 str(ROOT / "rtl/ip/ribp/peripheral/sysctrl.sv"),
                 str(ROOT / "rtl/tech/tc_clk.sv"),
                 str(ROOT / "rtl/tech/tc_pll.sv"),