feat: add CLINT peripheral support and related enhancements

- Updated the formal file list generator to include CLINT source files.
- Added CLINT timebase to the clock and reset domains configuration.
- Enhanced the SOC topology generation to include CLINT interrupts and their mappings.
- Introduced a new CLINT testbench to validate multi-hart and timebase functionality.
- Modified the software build configuration to define CLINT timebase frequency.
- Updated the RCU module to integrate CLINT timebase generation.
- Adjusted the IRQ configuration to reflect changes in CLINT interrupt signals.
- Added user-visible flags for interrupts in the topology configuration.
- Enhanced the clock reset domain checks to include CLINT timebase.
- Updated the memory map tests to validate CLINT peripheral integration.

tests/test_soc_topology.py

@@ -97,9 +97,10 @@ def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -
     assert ".apb_rib(u_apb_rib_if)" in bus_fabric
     assert ".rib(u_rib_if)" in bus_fabric
     assert "`define SOC_IRQ_VECTOR_WIDTH 32" in irq_config
+    assert "`define SOC_USER_IRQ_MASK 32'h0003FFFC" in irq_config
     assert "`define SOC_IRQ_RIBP_WIDTH 11" in irq_config
     assert "`define SOC_IRQ_APB_WIDTH 7" in irq_config
-    assert "assign irq_o[0] = u_clint_if.sfr_irq_o;" in rib_irq
+    assert "assign irq_o[0] = u_clint_if.software_irq_o[0];" in rib_irq
     assert "assign irq_o[10] = ws2812.irq_o;" in rib_irq
     assert "assign irq_o[5] = u_tmr_if.irq_o;" in apb_irq
     assert "s_irq[16] = s_apb_irq[6];" in irq_wiring
@@ -122,8 +123,8 @@ def test_topology_preserves_default_irq_compatibility_mapping() -> None:
         for interrupt in document["interrupts"]
     ]
     assert mappings[:18] == [
-        ("clint_software", "ribp", 0, 0, "u_clint_if.sfr_irq_o"),
-        ("clint_timer", "ribp", 1, 1, "u_clint_if.tmr_irq_o"),
+        ("clint_software", "ribp", 0, 0, "u_clint_if.software_irq_o[0]"),
+        ("clint_timer", "ribp", 1, 1, "u_clint_if.timer_irq_o[0]"),
         ("uart0", "ribp", 2, 2, "uart.irq_o"),
         ("timer0", "ribp", 3, 3, "s_tim0_irq"),
         ("timer1", "ribp", 4, 4, "s_tim1_irq"),